CN114879809A - Low dropout linear voltage stabilizing circuit - Google Patents
Low dropout linear voltage stabilizing circuit Download PDFInfo
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- CN114879809A CN114879809A CN202210396146.7A CN202210396146A CN114879809A CN 114879809 A CN114879809 A CN 114879809A CN 202210396146 A CN202210396146 A CN 202210396146A CN 114879809 A CN114879809 A CN 114879809A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a low dropout linear voltage stabilizing circuit, which relates to the technical field of low dropout linear voltage stabilizing and comprises the following components: the input end of the first reference current source is connected with the power supply, and the output end of the first reference current source is connected with the reference circuit through a first switching tube so as to provide reference voltage; the drain electrode of the second switching tube is connected with the power supply, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the source electrode of the second switching tube is connected with the voltage-stabilizing output port; when the external disturbance current flowing outwards is applied to the voltage-stabilizing output port, the output voltage of the voltage-stabilizing output port is controlled to be kept stable relative to the reference voltage in a mode of controlling the first switching tube and the second switching tube; the feedback circuit is respectively connected with the reference circuit, the voltage-stabilizing output port and the ground; when the external part applies the interference current flowing inwards to the voltage-stabilizing output port, the feedback circuit is used for controlling the output voltage of the voltage-stabilizing output port to keep stable relative to the reference voltage. The beneficial effects are that the output bidirectional strong anti-interference performance is realized; the circuit area is small; the response speed of the circuit is high.
Description
Technical Field
The invention relates to the technical field of low dropout linear voltage regulation, in particular to a low dropout linear voltage regulation circuit.
Background
Ldo (low dropout regulator) refers to a low dropout regulator, which is an integrated circuit regulator that generally has very low inherent noise and a high power Supply Rejection ratio psrr (power Supply Rejection ratio) compared to conventional linear regulators. LDO is a low-consumption micro system-on-chip, and is widely used due to its many advantages.
However, the existing LDO circuit can only achieve unidirectional anti-interference capability, that is, when the load has interference of large input current, the circuit cannot stabilize the output voltage, that is, the LDO fails, and the anti-interference response speed is very slow.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a low dropout linear voltage stabilizing circuit, which comprises:
the input end of the first reference current source is connected with a power supply, and the output end of the first reference current source is connected with a reference circuit through a first switching tube so as to provide a reference voltage;
the drain electrode of the first switch tube is respectively connected with the output end of the first reference current source and the grid electrode of the first switch tube, and the source electrode of the first switch tube is connected with the reference circuit;
the drain electrode of the second switching tube is connected with the power supply, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the source electrode of the second switching tube is connected with a voltage-stabilizing output port;
when the external disturbance current flowing out is applied to the voltage-stabilizing output port, the output voltage of the voltage-stabilizing output port is controlled to be kept stable relative to the reference voltage in a mode of controlling the first switch tube and the second switch tube;
the feedback circuit is respectively connected with the reference circuit, the voltage-stabilizing output port and the ground;
when the external part applies the interference current flowing inwards to the voltage-stabilizing output port, the feedback circuit is used for controlling the output voltage of the voltage-stabilizing output port to keep stable relative to the reference voltage.
Preferably, the feedback circuit includes:
a source electrode of the third switching tube is connected with the voltage-stabilizing output port, and a grid electrode of the third switching tube is connected with the reference circuit;
a grid electrode of the fourth switching tube is connected with a drain electrode of the third switching tube, the drain electrode of the fourth switching tube is respectively connected with a source electrode of the third switching tube and the voltage-stabilizing output port, and the source electrode of the fourth switching tube is grounded;
one end of the first resistor is connected with the drain electrode of the third switching tube and the grid electrode of the fourth switching tube respectively, and the other end of the first resistor is grounded.
Preferably, the reference circuit includes:
a grid electrode of the fifth switching tube is respectively connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube;
one end of the second reference current source is connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube respectively, and the other end of the second reference current source is grounded;
one end of the second resistor is connected with the source electrode of the first switch tube and the source electrode of the fifth switch tube respectively, and the other end of the second resistor is grounded.
Preferably, the third switching tube and the fifth switching tube are PMOS tubes arranged in a mirror image manner, and the gate turn-on voltages of the third switching tube and the fifth switching tube are the same.
Preferably, the fourth switching tube is an NMOS tube.
Preferably, the reference current source further comprises a first capacitor, one end of the first capacitor is connected to the gate of the third switching tube, the gate of the fifth switching tube, the drain of the fifth switching tube, and one end of the second reference current source, respectively, and the other end of the first capacitor is grounded.
Preferably, the calculation formula of the reference voltage is as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein, V ref For representing said reference voltage, I ref1 For representing a first reference current value, I, supplied by said first reference current source ref2 For indicating a second reference current value, R, supplied by said second reference current source 2 For representing the resistance value of the second resistor.
Preferably, the current reference circuit further comprises a second capacitor, one end of the second capacitor is connected to the gate of the first switch tube, the gate of the second switch tube and the output end of the first reference current source, respectively, and the other end of the second capacitor is grounded.
Preferably, the first switch tube and the second switch tube are NMOS tubes arranged in a mirror image manner, and gate turn-on voltages of the first switch tube and the second switch tube are the same.
Preferably, the power supply further comprises a load current source, one end of the load current source is connected to the voltage-stabilizing output port, and the other end of the load current source is grounded.
The technical scheme has the following advantages or beneficial effects: the strong anti-interference performance of output two-way can be realized; the circuit area is small; aiming at the output change, the feedback voltage can change according to the square rate of the overdrive voltage of the switching tube, and the response speed of the circuit is greatly accelerated.
Drawings
FIG. 1 is a diagram illustrating a low dropout linear voltage regulator circuit according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of voltage waveforms at key points of a circuit when a circuit is disturbed according to a preferred embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. The present invention is not limited to the embodiment, and other embodiments may be included in the scope of the present invention as long as the gist of the present invention is satisfied.
In view of the above problems in the prior art, the preferred embodiment of the present invention provides a low dropout linear voltage regulator circuit, as shown in fig. 1, comprising:
the input end of the first reference current source Iref1, the input end of the first reference current source Iref1 is connected with a power supply VDD, the output end of the first reference current source Iref1 is connected with a reference circuit 1 through a first switch tube M1 to provide a reference voltage Vref;
the drain of the first switch tube M1 is connected to the output terminal of the first reference current source Iref1 and the gate of the first switch tube M1, respectively, and the source of the first switch tube M1 is connected to the reference circuit 1;
a second switching tube M2, a drain of the second switching tube M2 is connected to the power supply VDD, a gate of the second switching tube M2 is connected to a gate of the first switching tube M1, and a source of the second switching tube M2 is connected to a regulated output port 2;
when the external disturbance current flowing outwards is applied to the voltage-stabilizing output port 2, the output voltage of the voltage-stabilizing output port 2 is controlled to be kept stable relative to the reference voltage by controlling the first switching tube M1 and the second switching tube M2;
and the feedback circuit 3, the feedback circuit 3 is respectively connected with the reference circuit 1, the voltage-stabilizing output port 2 and the ground, and the feedback circuit 3 is used for controlling the output voltage of the voltage-stabilizing output port 2 to keep stable relative to the reference voltage when the interference current flowing inwards is externally applied to the voltage-stabilizing output port 2.
Specifically, in this embodiment, by using the low dropout linear regulator circuit according to the present technical solution, the circuit operates in a static state, i.e., operates normally, and when there is no external interference, the output voltage Vout of the regulated output port 2 is kept equal to the reference voltage Vref, so as to realize voltage regulation. Further, when the voltage-stabilizing output port 2 is subjected to strong external interference, for example, when a strong CMTI current exists, the current value of the CMTI current can reach 10mA, lasts for 20ns, and the direction of the current is random, the low-dropout linear voltage-stabilizing circuit still maintains a relatively stable output voltage Vout. In other words, no matter how the direction of the external interference current is, the low dropout linear voltage regulator circuit of the technical scheme can effectively control the output voltage Vout of the voltage-stabilizing output port 2 to keep stable relative to the reference voltage Vref, so that the output bidirectional strong anti-interference performance is realized.
In a preferred embodiment of the present invention, the feedback circuit 3 includes:
a third switching tube M3, wherein the source of the third switching tube M3 is connected with the voltage stabilization output port 2, and the gate of the third switching tube M3 is connected with the reference circuit 1;
a grid electrode of the fourth switching tube M4, a drain electrode of the fourth switching tube M4 is connected with a drain electrode of the third switching tube M3, drain electrodes of the fourth switching tube M4 are respectively connected with a source electrode of the third switching tube M3 and the voltage stabilization output port 2, and a source electrode of the fourth switching tube M4 is grounded;
one end of the first resistor R1, one end of the first resistor R1 is connected to the drain of the third switching tube M3 and the gate of the fourth switching tube M4, respectively, and the other end of the first resistor R1 is grounded.
In a preferred embodiment of the present invention, the reference circuit 1 includes:
the grid electrode of the fifth switching tube M5 and the grid electrode of the fifth switching tube M5 are respectively connected with the grid electrode of the third switching tube M3 and the drain electrode of the fifth switching tube M5;
one end of the second reference current source Iref2 is connected to the gate of the third switching tube M3 and the drain of the fifth switching tube M5, and the other end of the second reference current source Iref2 is grounded;
one end of a second resistor R2 and one end of a second resistor R2 are respectively connected with the source electrode of the first switch tube M1 and the source electrode of the fifth switch tube M5, and the other end of the second resistor R2 is grounded.
In a preferred embodiment of the present invention, the third switching transistor M3 and the fifth switching transistor M5 are PMOS transistors arranged in a mirror image, and the gate turn-on voltages of the third switching transistor M3 and the fifth switching transistor M5 are the same.
In the preferred embodiment of the present invention, the fourth switch transistor M4 is an NMOS transistor.
In the preferred embodiment of the present invention, the first capacitor C1 is further included, one end of the first capacitor C1 is respectively connected to the gate of the third switching tube M3, the gate of the fifth switching tube M5, the drain of the fifth switching tube M5, and one end of the second reference current source Iref2, and the other end of the first capacitor C1 is grounded.
In a preferred embodiment of the present invention, the calculation formula of the reference voltage is as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein, V ref For representing a reference voltage, I ref1 For indicating a first reference current value, I, supplied by a first reference current source Iref1 ref2 For indicating a second reference current value, R, provided by second reference current source Iref2 2 Which is used to represent the resistance value of the second resistor R2.
In the preferred embodiment of the present invention, the second capacitor C2 is further included, one end of the second capacitor C2 is respectively connected to the gate of the first switch transistor M1, the gate of the second switch transistor M2 and the output end of the first reference current source Iref1, and the other end of the second capacitor C2 is grounded.
In a preferred embodiment of the present invention, the first switch transistor M1 and the second switch transistor M2 are NMOS transistors with mirror image arrangement, and the gate turn-on voltages of the first switch transistor M1 and the second switch transistor M2 are the same.
In the preferred embodiment of the present invention, the present invention further comprises a load current source Iload, one end of the load current source Iload is connected to the regulated output port 2, and the other end of the load current source Iload is grounded.
Specifically, the low dropout linear voltage regulator circuit according to the present technical solution works in a static state, that is, works normally, and when there is no external interference, the first switching tube M1 and the fifth switching tube M5 are controlled to be turned on, and the first switching tube M1 and the fifth switching tube M5 both adopt a diode connection method with a short-circuited gate and drain, which is equivalent to a diode and has a small voltage drop, based on which, the first reference current source Iref1 and the second reference current source Iref2 generate the reference voltage Vref through the second resistor R2, and the calculation formula is as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein, V ref For representing a reference voltage, I ref1 For indicating a first reference current value, I, supplied by a first reference current source Iref1 ref2 For indicating a second reference current value, R, provided by second reference current source Iref2 2 Which is used to represent the resistance value of the second resistor R2.
Since the second switch transistor M2 and the first switch transistor M1 are the same two NMOS transistors arranged in a mirror image, the gate-source voltage of the second switch transistor M2 is the same as the gate-source voltage of the first switch transistor M1. Similarly, since the third switching transistor M3 and the fifth switching transistor M5 are two same PMOS transistors arranged in a mirror image manner, the gate-source voltage of the third switching transistor M3 is the same as the gate-source voltage of the fifth switching transistor M5, and therefore, when the low dropout linear voltage regulator circuit according to the present embodiment operates in a static state, the output voltage Vout of the regulated output port 2 is equal to the reference voltage Vref.
When the voltage-stabilizing output port 2 is strongly interfered by the outside, for example, in the application of a digital isolator, there is a strong CMTI current, the current of which can reach 10mA and last for 20ns, the current flows out, the second switching tube M2 and the first switching tube M1 are controlled to be turned on, the third switching tube M3 and the fourth switching tube M4 are turned off, and the node voltage Vnb1 is kept still due to the existence of the capacitor C2, according to the saturation region current formula of the NMOS transistor as shown below:
wherein i ds The source-drain current of the NMOS tube is represented, beta represents the transconductance coefficient of the NMOS tube, and V gs Representing the gate-source voltage, V, of the NMOS tube th Representing the threshold voltage, V, of the NMOS transistor ov Representing the overdrive voltage of the NMOS transistor.
A calculation formula of the change amount of the output voltage Vout of the voltage stabilization output port shown below can be obtained:
wherein, is Δ V out Indicates the amount of change, i, of the output voltage Vout ds2 Represents the source-drain current i of the NMOS tube when the current interference flowing out from the outside is applied ds Representing the source-drain current of the NMOS transistor in the quiescent state, and k representing the amount of change in the source-drain current of the NMOS transistor in the externally applied disturb, e.g. designing the overdrive voltage V of the NMOS transistor ov The change k of the source-drain current of the NMOS tube is (10.2-0.2)/0.2 is (50) when the source-drain current of the NMOS tube is 200uA and the interference current of CMTI interference is 10.2mA in static work; Δ Vout becomes 0.35V.
It can be seen that, by adopting the low dropout linear voltage regulator circuit of the technical scheme, the output voltage of Vout can be changed very little even if the output current is changed by 50 times.
When the regulated output port 2 is strongly disturbed from the outside, for example, a strong reverse CMTI current (second interference current) exists, the current can reach 10mA and lasts for 20ns, and the current flows inwards and is kept due to the existence of the capacitor C1The node voltage Vpb1 is at rest, when Vout quickly develops an upward voltage, based on the node voltage V as shown below fb (feedback voltage) calculation formula:
V fb ＝i dsp ·R 1 ＝0.5·R 1 ·β p ·(V gsp -V thp ) 2
wherein i dsp Represents the source-drain current, beta, flowing through the third switch tube M3 p The transconductance coefficient, V, of the third switching tube M3 gsp Represents the source-gate voltage, V, of the third switching tube M3 thp Indicating the threshold voltage of the third switching tube M3.
In the static state, V is preferably fb Set to 0.7Vth, where Vth is the threshold voltage of the fourth switching transistor M4, and at this time, the fourth switching transistor M4 is in the off state as long as the output voltage Vout varies by more than 4V ovp (overdrive voltage V of the third switching tube M3 ovp ，V ovp ＝V gsp -V thp ) Then i is dsp Current of is 16 times, resulting in V fb Becomes 11.2 Vth; at this time, the fourth switch M4 is turned on to quickly drain the interfering CMTI current through the fourth switch M4, thereby keeping the variation of the output voltage Vout small. It will be appreciated that V is as described above fb The value of (d) is not limited to 0.7Vth, and may be configured as required. It can be seen that the feedback voltage V is directed to the output variation fb Can be in accordance with an overdrive voltage V ovp (V ovp ＝V gsp -V thp ) The square rate of the circuit is changed, and the response speed of the circuit is greatly increased.
More specifically, when the feedback circuit adopts a PMOS transistor, if the feedback circuit adopts the same structure as the two NMOS transistors of the first switch transistor M1 and the second switch transistor M2, the output voltage will change greatly due to the fact that the PMOS transistor needs a larger area and the drain-source current ids of the PMOS transistor is small, and furthermore, if the feedback circuit adopts a large PMOS transistor, in order to keep the voltage of the node voltage Vpb1 constant, a large capacitor C1 needs to be configured, which also needs a large area; based on the problems of the PMOS transistor, the feedback circuit is formed by the third switching tube M3, the first resistor R1 and the fourth switching tube M4, and the PMOS transistor can be small in area, so that the low dropout linear voltage regulator circuit has a smaller circuit area compared with the existing low dropout linear voltage regulator circuit.
As shown in FIG. 2, the circuit of the present invention operates in a static state from t0 to t1, i.e. the load current Iload is I0 (its value may be small, for example 200uA), and when the time reaches t1, the load current Iload suddenly changes to Imax (its value may be large, for example 10mA) due to external disturbance, such as the overdrive voltage V of the NMOS transistor ov The voltage is 50mV, the source-drain current of the NMOS tube is 200uA in static operation, the first interference current of CMTI interference is 10.2mA, and the analysis shows that Vout changes downwards by 0.35V, the third switching tube M3 is closed, and the feedback voltage V is fb Rapidly changing to 0V, and when the time reaches t2, restoring the current to the normal condition; when the time reaches t3, the load current Iload suddenly changes to Imin due to the large current being injected into the regulated output port by external disturbance, such as the overdrive voltage V of the third switching tube M3 ovp Is 50mV, if the output voltage Vout increases by 0.2V, the feedback voltage V fb Rapidly increasing to 3V, and simultaneously rapidly opening the fourth switching tube M4; when the time reaches t4, the circuit returns to the static state, i.e. the feedback voltage V fb The output voltage Vout is restored to the normal value at 0.7 Vth.
It can be seen that no matter the direction of the external interference current, the low dropout linear voltage regulator circuit of the technical scheme can effectively control the output voltage Vout of the voltage-stabilizing output port 2 to keep stable relative to the reference voltage Vref, thereby realizing output bidirectional strong anti-interference.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A low dropout linear voltage regulator circuit, comprising:
the input end of the first reference current source is connected with a power supply, and the output end of the first reference current source is connected with a reference circuit through a first switching tube so as to provide a reference voltage;
the drain electrode of the first switch tube is respectively connected with the output end of the first reference current source and the grid electrode of the first switch tube, and the source electrode of the first switch tube is connected with the reference circuit;
the drain electrode of the second switching tube is connected with the power supply, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube, and the source electrode of the second switching tube is connected with a voltage-stabilizing output port;
when the external disturbance current flowing out is applied to the voltage-stabilizing output port, the output voltage of the voltage-stabilizing output port is controlled to be kept stable relative to the reference voltage in a mode of controlling the first switch tube and the second switch tube;
the feedback circuit is respectively connected with the reference circuit, the voltage-stabilizing output port and the ground;
when the external part applies the interference current flowing inwards to the voltage-stabilizing output port, the feedback circuit is used for controlling the output voltage of the voltage-stabilizing output port to keep stable relative to the reference voltage.
2. The low dropout linear voltage regulator circuit of claim 1, wherein said feedback circuit comprises:
a source electrode of the third switching tube is connected with the voltage-stabilizing output port, and a grid electrode of the third switching tube is connected with the reference circuit;
a grid electrode of the fourth switching tube is connected with a drain electrode of the third switching tube, the drain electrode of the fourth switching tube is respectively connected with a source electrode of the third switching tube and the voltage-stabilizing output port, and the source electrode of the fourth switching tube is grounded;
one end of the first resistor is connected with the drain electrode of the third switching tube and the grid electrode of the fourth switching tube respectively, and the other end of the first resistor is grounded.
3. The low dropout linear voltage regulator circuit of claim 2, wherein said reference circuit comprises:
a grid electrode of the fifth switching tube is respectively connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube;
one end of the second reference current source is connected with the grid electrode of the third switching tube and the drain electrode of the fifth switching tube respectively, and the other end of the second reference current source is grounded;
one end of the second resistor is connected with the source electrode of the first switch tube and the source electrode of the fifth switch tube respectively, and the other end of the second resistor is grounded.
4. The low dropout linear voltage regulator circuit of claim 3, wherein the third switching transistor and the fifth switching transistor are mirror PMOS transistors, and the gate turn-on voltages of the third switching transistor and the fifth switching transistor are the same.
5. The low dropout linear voltage regulator circuit of claim 4, wherein said fourth switching transistor is an NMOS transistor.
6. The low dropout linear voltage regulator circuit of claim 3, further comprising a first capacitor, wherein one end of the first capacitor is connected to the gate of the third switching transistor, the gate of the fifth switching transistor, the drain of the fifth switching transistor and one end of the second reference current source, respectively, and the other end of the first capacitor is grounded.
7. The low dropout linear voltage regulator circuit of claim 3, wherein said reference voltage is calculated as follows:
V ref ＝(I ref1 -I ref2 )*R 2
wherein, V ref For representing said reference voltage, I ref1 For representing a first reference current value, I, supplied by said first reference current source ref2 For indicating a second reference current value, R, supplied by said second reference current source 2 For representing the resistance value of the second resistor.
8. The low dropout linear voltage regulator circuit of claim 1, further comprising a second capacitor, wherein one end of the second capacitor is connected to the gate of the first switch transistor, the gate of the second switch transistor and the output terminal of the first reference current source, respectively, and the other end of the second capacitor is grounded.
9. The low dropout linear voltage regulator circuit of claim 1, wherein the first switch transistor and the second switch transistor are NMOS transistors arranged in a mirror image, and the gate turn-on voltages of the first switch transistor and the second switch transistor are the same.
10. The low dropout linear voltage regulator circuit of claim 1, further comprising a load current source, wherein one end of said load current source is connected to said regulated output port, and the other end of said load current source is connected to ground.
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| CN115657779A (en) * | 2022-12-08 | 2023-01-31 | 荣湃半导体（上海）有限公司 | Low dropout regulator for suppressing transient sudden change of power supply |
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