CN114868248A

CN114868248A - Three-dimensional memory device with separate source siding and method of fabricating the same

Info

Publication number: CN114868248A
Application number: CN202180006591.1A
Authority: CN
Inventors: 津美正三里; 矢田信介; 虫贺光昭; 西田昭夫; 小川裕之; 翁照男
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2020-11-18
Filing date: 2021-06-08
Publication date: 2022-08-05
Also published as: WO2022108624A1

Abstract

The invention discloses a three-dimensional memory device, comprising: an alternating stack of insulating layers and conductive layers, the alternating stack being located over at least one source layer; and a set of memory opening fill structures extending vertically through the alternating stack. Each memory opening fill structure may include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source side select gate electrodes may be laterally spaced apart by source select level dielectric isolation structures. Alternatively or additionally, the at least one source layer may comprise a plurality of source layers. The set of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level conductive layer.

Description

Three-dimensional memory device with separate source siding and method of fabricating the same

RELATED APPLICATIONS

The present application claims priority rights to U.S. non-provisional application No. 16/951,325 filed on

month

11, 18, 2020 and U.S. non-provisional application No. 16/951,354 filed on

month

11, 18, 2020; the entire contents of these applications are incorporated herein by reference.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional memory devices including separate source side select lines and/or separate source lines and methods of fabricating the same.

Background

Three-dimensional vertical NAND strings With one bit per Cell are disclosed in an article entitled "Novel Ultra High sensitivity Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM proc. (2001)33-36 by t.endoh et al.

Disclosure of Invention

According to still another aspect of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of insulating layers and conductive layers, the alternating stack being located over a plurality of source layers, wherein the alternating stack is located between a pair of backside trench-fill structures; sets of memory openings extending vertically through the alternating stack; and a set of memory opening fill structures, the set of memory opening fill structures located in the set of memory openings, wherein each of the memory opening fill structures comprises: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting a respective one of the plurality of source layers; and a respective drain region contacting a second end of the respective vertical semiconductor channel; wherein: the plurality of source layers are laterally spaced apart and electrically isolated from one another; and each group of memory opening fill structures contacts a respective one of the plurality of source layers.

According to another aspect of the present disclosure, a method of forming a three-dimensional memory device includes: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or subsequently replaced by conductive layers; forming a set of memory openings through the alternating stack; forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel; forming a source-level material layer by thinning the substrate, by removing the substrate, or by replacing the substrate with at least one conductive material layer; and forming a plurality of source layers by patterning the source-level material layer, wherein the plurality of source layers are laterally spaced apart and electrically isolated from each other, wherein each group of the memory opening fill structures contacts a respective one of the plurality of source layers.

According to an aspect of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of insulating layers and conductive layers over at least one source layer and between a pair of backside trench-fill structures; sets of memory openings extending vertically through the alternating stack; and a set of memory opening fill structures, the set of memory opening fill structures located in the set of memory openings, wherein each of the memory opening fill structures comprises: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting the at least one source layer; and a respective drain region contacting a second end of the respective vertical semiconductor channel; wherein the conductive layer comprises: word lines extending continuously laterally between and contacting each of the pair of back side trench-fill structures; and a plurality of source side select gate electrodes vertically between the at least one source layer and the word lines and horizontally between the pair of backside trench-fill structures, wherein the plurality of source side select gate electrodes are laterally spaced apart by a source select level dielectric isolation structure.

According to another aspect of the present disclosure, there is provided a method of forming a three-dimensional memory device, the method including: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or subsequently replaced by conductive layers; forming a set of memory openings through the alternating stack; forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures comprises a respective vertical stack of memory elements, a respective vertical semiconductor channel, and a respective drain region; forming a source-level material layer by thinning the substrate or by replacing the substrate with at least one conductive material layer, wherein each group of memory opening fill structures contacts a respective one of the plurality of source layers; and forming a plurality of source side select gate electrodes by forming source side trenches through the first subset of conductive layers before or after forming the source level material layers, wherein the source side trenches do not divide the second subset of conductive layers.

Drawings

Fig. 1A is a vertical cross-sectional view of a first exemplary structure after forming a first vertically alternating sequence of first insulating layers and first sacrificial material layers, according to a first embodiment of the present disclosure.

Fig. 1B illustrates, in plan view, a layout of semiconductor dies within the first exemplary structure of fig. 1A.

Fig. 2 is a vertical cross-sectional view of a first example structure after first stepped surface patterning and formation of first backward stepped dielectric material portions over a first vertically alternating sequence in accordance with an embodiment of the present disclosure.

Fig. 3A is a vertical cross-sectional view of a first example structure after forming a first layer memory opening and a first layer support opening, according to an embodiment of the disclosure.

FIG. 3B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in FIG. 3A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 3A.

Fig. 4 is a vertical cross-sectional view of a first example structure after forming an optional pedestal channel portion in each of a first layer memory opening and a first layer support opening, according to an embodiment of the present disclosure.

Fig. 5A is a vertical cross-sectional view of a first example structure after forming a first layer of sacrificial memory opening fill structures and a first layer of sacrificial support structures, according to an embodiment of the present disclosure.

Fig. 5B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 5A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 5A.

Fig. 6 is a vertical cross-sectional view of the first exemplary structure after forming a second vertically alternating sequence of second insulating layers and second sacrificial material layers, second layer backward stepped dielectric material portions, and a second insulating cap layer, according to an embodiment of the disclosure.

Fig. 7A is a vertical cross-sectional view of a first example structure after forming a second tier memory opening and a second tier support opening in accordance with an embodiment of the present disclosure.

Fig. 7B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 7A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 7A.

Fig. 7C illustrates a horizontal cross-sectional view of various configurations for disposing a second layer of reservoir openings, according to embodiments of the present disclosure.

Fig. 8 is a vertical cross-sectional view of a first example structure after forming an interlayer memory opening and an interlayer support opening, according to an embodiment of the present disclosure.

Fig. 9A-9H are sequential vertical cross-sectional views of an interlayer memory opening during formation of a memory opening fill structure, according to an embodiment of the present disclosure.

Fig. 10A is a vertical cross-sectional view of a first example structure after forming a reservoir opening filling structure and a main support pillar structure, according to an embodiment of the present disclosure.

Fig. 10B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 10A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 10A.

Fig. 11A is a vertical cross-sectional view of a first example structure after forming backside trenches and source regions, according to an embodiment of the present disclosure.

FIG. 11B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in FIG. 11A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 11A.

Fig. 11C illustrates, in plan view, a layout of semiconductor dies within the first exemplary structure of fig. 11A and 11B.

Fig. 12A is a vertical cross-sectional view of a first example structure after forming a backside recess, according to an embodiment of the present disclosure.

Fig. 12B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 12A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 12A.

Fig. 13A is a vertical cross-sectional view of a first example structure after replacing a sacrificial material layer with a conductive layer, according to an embodiment of the disclosure.

Fig. 13B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 13A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 13A.

Fig. 14A is a vertical cross-sectional view of a first example structure after forming backside insulating spacers and backside via structures, according to an embodiment of the disclosure.

Fig. 14B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 14A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 14A.

Fig. 14C illustrates, in plan view, a layout of semiconductor dies within the first exemplary structure of fig. 14A and 14B.

Fig. 15A is a vertical cross-sectional view of a first example structure after forming a drain contact via cavity and a word line contact via cavity, according to an embodiment of the present disclosure.

Fig. 15B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' in fig. 15A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 15A.

Fig. 16A is a vertical cross-sectional view of a first example structure after forming a bit line level metal interconnect structure, according to an embodiment of the present disclosure.

Fig. 16B is a top view of a region of the first exemplary structure of fig. 16A.

Fig. 16C and 16D show in plan view alternative word line layouts for the semiconductor die within the first exemplary structure of fig. 16A and 16B.

Fig. 17A is a vertical cross-sectional view of a logic die according to a first embodiment of the present disclosure.

Fig. 17B shows a layout of the logic die of fig. 17A in plan view.

Fig. 18A and 18B are vertical cross-sectional views of a first exemplary structure after bonding a semiconductor die to a logic die according to a first embodiment of the present disclosure.

Fig. 19A and 19B are vertical cross-sectional views of a first exemplary structure after thinning the backside of the semiconductor die according to a first embodiment of the present disclosure.

Fig. 20A and 20B are vertical cross-sectional views of a first example structure after forming a plurality of source layers according to a first embodiment of the present disclosure.

Fig. 21 is a vertical cross-sectional view of a first alternative configuration of the first example structure after forming a plurality of source layers according to the first embodiment of the present disclosure.

Fig. 22A-22D are vertical cross-sectional views of alternative configurations of a memory opening during formation of a memory opening fill structure, according to a second embodiment of the present disclosure.

Fig. 23 is a vertical cross-sectional view of a second exemplary structure after removal of the substrate, according to a second embodiment of the present disclosure.

Fig. 24A and 24B are vertical cross-sectional views of a memory opening fill structure during removal of a bottom portion of a memory film according to a second embodiment of the present disclosure.

Fig. 25A is a vertical cross-sectional view of a second example structure after forming a source-level material layer, according to a second embodiment of the present disclosure.

Fig. 25B is a vertical cross-sectional view of a memory opening fill structure within the second exemplary structure of fig. 25A.

Fig. 26A and 26B are vertical cross-sectional views of a second example structure after formation of a source layer, according to a second embodiment of the present disclosure.

Fig. 27 is a circuit schematic of the second exemplary structure of fig. 26A and 26B.

Fig. 28 is a vertical cross-sectional view of a third exemplary structure after forming source select level trenches, according to a third embodiment of the present disclosure.

Fig. 29 is a vertical cross-sectional view of a third exemplary structure after formation of a source select level dielectric isolation structure, according to a third embodiment of the present disclosure.

Fig. 30 is a vertical cross-sectional view of a third example structure after formation of a source layer according to a third embodiment of the present disclosure.

Fig. 31A is a circuit schematic of the third exemplary structure of fig. 30.

Fig. 31B is a schematic top view of a third exemplary structure.

Fig. 32 is a vertical cross-sectional view of a fourth example structure after formation of a source layer according to a fourth embodiment of the present disclosure.

Fig. 33 is a vertical cross-sectional view of a fourth exemplary structure after forming a source-side trench, according to a fourth embodiment of the present disclosure.

Fig. 34 is a vertical cross-sectional view of a first alternative configuration of a fourth example structure after forming source level dielectric isolation layers according to a fourth embodiment of the present disclosure.

Fig. 35 is a vertical cross-sectional view of a second alternative configuration of a fourth example structure after forming source level dielectric isolation layers according to a fourth embodiment of the present disclosure.

Fig. 36 is a circuit schematic of various configurations of the fourth exemplary structure of fig. 35.

Fig. 37 is a vertical cross-sectional view of an example structure for providing electrical connection to a source layer, according to an embodiment of the present disclosure.

Fig. 38 is a vertical cross-sectional view of another example structure for providing an electrical connection to a source layer, according to an embodiment of the present disclosure.

Fig. 39A is a vertical cross-sectional view of a fifth example structure after forming a memory opening fill structure, according to a fifth embodiment of the present disclosure.

FIG. 39B is a horizontal cross-sectional view of the fifth exemplary structure taken along horizontal plane B-B' of FIG. 39B.

Fig. 40A is a vertical cross-sectional view of a fifth example structure after formation of a drain select level dielectric isolation structure, according to a fifth embodiment of the present disclosure.

FIG. 40B is a horizontal cross-sectional view of the fifth exemplary structure taken along horizontal plane B-B' of FIG. 40A.

Fig. 41 is a vertical cross-sectional view of a fifth exemplary structure after removal of the substrate, according to a fifth embodiment of the present disclosure.

Fig. 42 is a vertical cross-sectional view of a region of the fifth exemplary structure of fig. 41 along a vertical plane a-a'.

Fig. 43 is a vertical cross-sectional view of a region of a fifth example structure after forming source select level trenches, according to a fifth embodiment of the present disclosure.

Fig. 44A is a vertical cross-sectional view of a region of a fifth example structure after formation of a source select level dielectric isolation structure, according to a fifth embodiment of the present disclosure.

Fig. 44B is a horizontal cross-sectional view taken along horizontal plane B-B' of the fifth exemplary structure of fig. 44A.

Fig. 45 is a vertical cross-sectional view of a fifth example structure after formation of a source layer, according to a fifth embodiment of the present disclosure.

Fig. 46 is a vertical cross-sectional view of a fifth example structure after dividing a source layer into a plurality of source layers, according to a fifth embodiment of the present disclosure.

Detailed Description

As described above, embodiments of the present disclosure relate to three-dimensional memory devices including separate source lines and/or separate source side select lines and methods of fabricating the same, various aspects of which are described in detail herein.

The figures are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated to be absent repetition of the element. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The term "at least one" element is intended to mean all possibilities including single element possibilities and multiple element possibilities.

The same reference numerals indicate the same elements or similar elements. Elements having the same reference number are assumed to have the same composition and the same function unless otherwise stated. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. Two or more elements are "separated" from each other if the elements are not in direct contact with each other or with each other. As used herein, a first element that is positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is "electrically connected" to a second element if there is a conductive path between the first element and the second element that is comprised of at least one conductive material. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range that is less than the range of an underlying or overlying structure. In addition, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above and/or below.

As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane including the first surface and the second surface. A substantially vertical plane is a plane that extends straight in a direction that deviates from vertical by an angle of less than 5 degrees. The vertical plane or substantially vertical plane is straight in the vertical direction or substantially vertical direction and may or may not include curvature in a direction perpendicular to the vertical direction or substantially vertical direction.

Generally, a semiconductor package (or "package") refers to a unitary semiconductor device that may be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "dies") bonded therein, such as by flip-chip bonding or another die-to-die bonding. A package or chip may include a single semiconductor die (or "die") or a plurality of semiconductor dies. The die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip having multiple dies is capable of executing as many external commands as the total number of planes therein at the same time. Each die includes one or more planes. The same concurrent operation may be performed in each plane within the same die, but there may be some limitations. Where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") which are the smallest units that can be erased by a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

Referring to fig. 1A and 1B, a first exemplary structure according to a first embodiment of the present disclosure is shown. The first exemplary structure includes a substrate 8 comprising a substrate semiconductor layer 9 at least at an upper portion thereof. In one embodiment, the substrate semiconductor layer 9 may be a layer of single crystal semiconductor material or a doped well in a semiconductor substrate, such as a silicon wafer. In another embodiment, the substrate 8 may include a substrate semiconductor layer (not shown) having semiconductor devices (not shown) thereon and a lower level dielectric material layer (not shown) embedded in and overlying the lower level metal interconnect structures (not shown). In this case, the substrate semiconductor layer 9 may be formed over a lower level dielectric material layer. The substrate semiconductor layer 9 may have a doping of a second conductivity type, which may be p-type or n-type, which is opposite to the first conductivity type used for doping the subsequently formed vertical semiconductor channel. The substrate semiconductor layer 9 may comprise a single crystal semiconductor material or a polycrystalline semiconductor material (such as polysilicon or a polycrystalline silicon germanium alloy).

As used herein, "semiconductor material" is meant to have a chemical composition of 1.0X 10 ^-6 S/cm to 1.010 ⁵ A material having an electrical conductivity in the range of S/cm. As used herein, "semiconductor material" refers to a material having a molecular weight of 1.0 x 10 in the absence of an electrical dopant therein ^-6 S/cm to 1.0X 10 ⁵ A material having an electrical conductivity in the range of S/cm and capable of being produced, when suitably doped with an electrical dopant, having a conductivity in the range of 1.0S/cm to 1.0X 10 ⁵ A doping material of conductivity in the range of S/cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to a valence band within the band structure, or an n-type dopant that adds electrons to a conduction band within the band structure. As used herein, "conductive material" means having a composition of greater than 1.0 x 10 ⁵ S/cm of conductivity. As used herein, "insulator material" or "dielectric material" is meant to have a thickness of less than 1.0 x 10 ^-6 S/cm of conductivity. As used herein, "heavily doped semiconductor material" refers to a material that is doped with an electrical dopant at a sufficiently high atomic concentration to become conductive (i.e., has a concentration of greater than 1.0 x 10) when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initial amorphous state) ⁵ Electrical conductivity of S/cm). The "doped semiconductor material" may be a heavily doped semiconductor material, or may be a material including a dopant provided at 1.0 × 10 ^-6 S/cm to 1.0X 10 ⁵ A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/cm. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped semiconductor material. The doped semiconductor material may be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metallic element therein. All conductivity measurements were performed under standard conditions.

A vertically alternating sequence of first and second layers of material is then formed. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. In the case where at least one further vertically alternating sequence of material layers is subsequently formed over the vertically alternating sequence of first and second material layers, the vertically alternating sequence is referred to herein as a first vertically alternating sequence. The first vertically alternating sequence of levels is referred to herein as a first level of levels, and the levels of the vertically alternating sequence to be subsequently formed directly above the first level of levels are referred to herein as a second level of levels, and so on.

The first vertically alternating sequence may include a first layer of insulating material 132 as a first layer of material and a first layer of sacrificial material 142 as a second layer of material. In one embodiment, each first layer insulating layer 132 may comprise a first insulating material, and each first layer sacrificial material layer 142 may comprise a first sacrificial material. A plurality of alternating first layer insulating layers 132 and first layer sacrificial material layers 142 are formed over the substrate semiconductor layer 9. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

The first vertically alternating sequence (132,142) can include a first layer of insulating layers 132 composed of a first material and a first layer of sacrificial material layers 142 composed of a second material that is different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

The second material of the first layer of sacrificial material 142 is a sacrificial material that can be removed selectively to the first material of the first layer of insulating layer 132. As used herein, the removal of a first material is "selective" for a "second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process for the first material relative to the second material.

The first layer of sacrificial material 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first layer of sacrificial material 142 may then be replaced with a conductive electrode, which may be used, for example, as a control gate electrode for a vertical NAND device. In one embodiment, the first layer of sacrificial material 142 may be a layer of material comprising silicon nitride.

In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first layer of sacrificial material 142 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20nm to 50nm, although lesser and greater thicknesses may be employed for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the pair of first insulating layer 132 and first sacrificial material layer 142 may be in the range of 2 to 1024, and typically in the range of 8 to 256, although more repetitions may be employed. In one embodiment, each first layer of sacrificial material layer 142 in the first vertically alternating sequence (132,142) may have a uniform thickness that is substantially constant within each respective first layer of sacrificial material layer 142. Each layer within the first vertically alternating sequence (132,142) can be a continuous layer of material without any openings therein. Thus, the first vertically alternating sequence (132,142) may comprise a vertically alternating sequence of successive insulating layers and successive layers of sacrificial material.

A first insulating cap layer 170 is then formed over the stack (132, 142). The first insulating cap layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating cap layer 170 comprises the same dielectric material as the first layer insulating layer 132. The thickness of the first insulating cap layer 170 may be in the range of 20nm to 300nm, although lesser and greater thicknesses may also be employed.

In general, the memory die may be formed using the substrate semiconductor layer 9 and the material layers thereon. The memory die may include multiple planes (P0-P7). The exemplary layout shown in fig. 1B includes eight planes (P0-P7) that can be operated independently within the memory die. Each plane (P0-P7) may include a respective three-dimensional memory array that contains multiple blocks when the memory die is completed. Each plane (P0-P7) may include a respective memory array region 100, a respective contact region 200, and a respective peripheral region 300. The gap region G may be disposed between an adjacent pair of planes (P0-P7). In one implementation, the gap regions G may extend laterally along a first horizontal direction (i.e., word line direction) hd1, and a pair of adjacent planes (P0 and P1; P2 and P3; P4 and P5; P6 and P7) adjacent along a second horizontal direction (e.g., bit line direction) hd2 may be laterally spaced apart by the gap regions G along a second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. According to aspects of the present disclosure, the width of each gap region G may be the same as the width of a corresponding backside trench subsequently formed between adjacent blocks in the same memory plane. In the illustrative example, the width of each gap region G may be in the range of 300nm to 3,000nm, although lesser and greater widths may also be employed. An adjacent pair of planes (P0 and P2; P4 and P6; P1 and P3; P5 and P7) adjacent along the first horizontal direction hd1 may be laterally spaced apart by a respective contact region 200.

Referring to fig. 2, the first insulating cap layer 170 and the first vertically alternating sequence (132,142) may be patterned to form a first stepped surface in the contact region 200. The contact region 200 may include respective first stepped regions in which first stepped surfaces are formed and second stepped regions in which additional stepped surfaces are subsequently formed in second layer structures (which are subsequently formed over the first layer structures) and/or additional layer structures. The first stepped surface may be formed, for example, by forming a masking layer having openings therein, etching cavities within the level of the first insulating cap layer 170, and iteratively expanding the etched regions, and vertically recessing the cavities by etching each first layer insulating layer 132 and first layer sacrificial material layer 142 pair positioned directly below the bottom surface of the etched cavity within the etched region. The first stepped surface extends continuously from a bottom-most layer within the first vertically alternating series (132,142) to a top-most layer within the first vertically alternating series (132, 142). The cavity overlying the first stepped surface is referred to herein as a first stepped cavity.

A dielectric material, such as silicate glass, may be deposited in the first stepped cavity. The dielectric material is then planarized to provide a planar surface in a horizontal plane including the top surface of the first insulating cap layer. The continuous remaining portion of dielectric material covering the first stepped surface and filling the first stepped cavity is referred to herein as a first backward stepped dielectric material portion 165, which comprises and may consist of a first silicate glass material. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to vertical distance from a top surface of a substrate on which the element is present. The first vertically alternating series (132,142) and the first retro-stepped dielectric material portion 165 collectively comprise a first layer structure that is an in-process structure that is subsequently modified.

An interlevel dielectric layer 180 may optionally be deposited over the first level structure (132,142,165,170). The interlayer dielectric layer 180 includes a dielectric material, such as a silicate glass material. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but lesser and greater thicknesses may also be employed. In one embodiment, the interlayer dielectric layer 180 may comprise a silicate glass that provides a greater etch rate in hydrofluoric acid than an undoped silicate glass. For example, the interlayer dielectric layer 180 may include borosilicate glass.

The combination of all material portions formed above the top surface of the substrate semiconductor layer 9 and below the interlayer dielectric layer 180 constitutes a first layer structure (132,142,165). The first layer structure (132,142,165) includes a first vertically alternating sequence of first layers of insulating layers 132 and first layers of sacrificial material 142 and a first backward stepped dielectric material portion 165 overlying and contacting a first stepped surface of the first vertically alternating sequence (132, 142). The first stepped surface extends continuously from a bottom-most layer within the first vertically alternating series (132,142) to a top-most layer within the first vertically alternating series (132,142) and contacts the vertical and horizontal bottom surfaces of the first rearwardly stepped dielectric material portion 165.

Referring to fig. 3A and 3B, a first layer memory opening 149 and a first layer support opening 119 may be formed. The positions of the steps S in the first vertically alternating sequence (132,142) are shown in dashed lines in FIG. 3B. The first layer memory openings 149 and the first layer support openings 119 extend through the first vertically alternating sequence (132,142) at least to the top surface of the substrate semiconductor layer 9. First-level memory openings 149 may be formed at locations in the memory array region 100 where a memory stack structure comprising a vertical stack of memory elements will subsequently be formed. The first layer support opening 119 may be formed in the contact region 200. The first layer support openings 119 may be formed in a first region of a first stepped surface where the first backward stepped dielectric material portion 165 contacts a first vertically alternating sequence (132,142), and in a second region of the contact region 200 where a second stepped surface of a second vertically alternating sequence is subsequently formed. The second region of contact regions 200 is located between the first region of word line contact regions and memory array region 100.

For example, a photolithographic material stack (not shown) including at least a photoresist layer may be formed over the first insulating cap layer 170 (and optional interlayer dielectric layer 180, if present), and the photolithographic material stack may be lithographically patterned to form an opening within the photolithographic material stack. The pattern in the stack of photolithographic material may be transferred through the first insulating cap layer 170 (and optional interlevel dielectric layer 180) and through the entire first vertically alternating sequence (132,142) by at least one anisotropic etch that employs the patterned stack of photolithographic material as an etch mask. The first insulating cap layer 170 (and optional interlevel dielectric layer 180) and portions of the first vertically alternating sequence (132,142) underlying the openings in the patterned stack of photolithographic material are etched to form first layer memory openings 149 and first layer support openings 119. In other words, the transfer of the pattern in the patterned stack of photolithographic material through the first insulating cap layer 170 and the first vertically alternating sequence (132,142) forms the first layer memory openings 149 and the first layer support openings 119.

In one embodiment, the chemical reactions of the anisotropic etching process used to etch through the material of the first vertically alternating sequence (132,142) may be alternated to optimize the etching of the first and second materials in the first vertically alternating sequence (132, 142). The anisotropic etch can be, for example, a series of reactive ion etches or a single etch (e.g., CF) ₄ /O ₂ /Ar etching). A first layer of memory openings 149 and sidewalls of support openings 119. Subsequently, the patterned stack of photolithographic material can be subsequently removed, for example by ashing.

Generally, the groups of first tier reservoir openings 149 may be formed through a first vertically alternating sequence (132, 142). Each group of first-level memory openings 149 may be formed within a rectangular region (e.g., a region of a memory block) extending laterally along a first horizontal direction (e.g., a word line direction) hd 1. Each group of first layer memory openings 149 may include multiple rows of first layer memory openings 149. The first-layer memory openings 149 of each row may extend laterally along the first horizontal direction hd 1. The rows of first-tier memory openings 149 may be laterally spaced from one another along a second horizontal direction (e.g., a bit line direction) hd 2.

Optionally, the portions of first layer memory openings 149 and first layer support openings 119 at the level of interlevel dielectric layer 180 may be laterally expanded by isotropic etching. For example, if the interlayer dielectric layer 180 comprises a dielectric material (such as borosilicate glass) having a greater etch rate than the first insulating layer 132 (which may comprise undoped silicate glass), an isotropic etch (such as a wet etch with HF) may be used to extend the lateral dimensions of the first layer memory opening at the level of the interlayer dielectric layer 180.

Referring to fig. 4, a base channel portion 11 may optionally be formed at the bottom of each of the first layer memory opening 149 and the first layer support opening 119. The pedestal channel portion 11 may be formed by a selective semiconductor deposition process that deposits a doped semiconductor material having a doping of the first conductivity type. If the pedestal channel portion 11 is formed, the top surface of the pedestal channel portion 11 may be formed at or above the horizontal plane including the top surface of the bottommost first layer of sacrificial material layer 142 and at or above the horizontal plane including the bottom surface of the first layer of sacrificial material layer 42 closest to the bottommost first layer of sacrificial material layer 142 (i.e., the second layer of sacrificial material layer 142 from the bottom).

Referring to fig. 5A and 5B, a first layer of sacrificial memory opening fill structures 148 may be formed in the first layer of memory openings 149 and a first layer of sacrificial support structures 118 may be formed in the first layer of support openings 119. For example, a layer of filler material including a filler material is deposited in the first layer of memory openings 149 and the first layer of support openings 119.

Referring to fig. 6, a second layer structure may be formed over the first layer structure (132,142,170,148,118). The second layer structure may comprise an additional vertically alternating sequence of insulating layers and sacrificial material layers, which may be sacrificial material layers. For example, a second vertically alternating sequence (232,242) of material layers may then be formed on the top surface of the first vertically alternating sequence (132, 142). The second stack (232,242) includes a plurality of alternating layers of a third material and a fourth material. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first layer of insulating layer 132, and the fourth material may be the same as the second material of the first layer of sacrificial material 142.

In one embodiment, the third material layer may be a second layer of insulating layers 232 and the fourth material layer may be a second layer of sacrificial material 242 providing a vertical spacing between each vertically adjacent pair of second layer insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively.

The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second layer sacrificial material layer 242 may be a sacrificial material that is selectively removable with respect to the third material of the second layer insulating layer 232. The second layer of sacrificial material 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second layer of sacrificial material 242 may then be replaced with a conductive electrode that may be used, for example, as a control gate electrode for a vertical NAND device.

In one embodiment, each second layer insulating layer 232 may comprise a second insulating material, and each second layer sacrificial material layer 242 may comprise a second sacrificial material. In this case, the second stack (232,242) may include a plurality of second insulating layers 232 and second sacrificial material layers 242 alternating. The third material of the second insulating layer 232 may be deposited, for example, by Chemical Vapor Deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that can be used for the second insulating layer 232 can be any material that can be used for the first insulating layer 132. The fourth material of the second layer of sacrificial material 242 is a sacrificial material that is selectively removable with respect to the third material of the second layer of insulating layer 232. The sacrificial material that may be used for the second layer of sacrificial material 242 may be any material that may be used for the first layer of sacrificial material 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

The thickness of the second-layer insulating layer 232 and the second-layer sacrificial material layer 242 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each second-layer insulating layer 232 and each second-layer sacrificial material layer 242. The number of repetitions of the pair of second insulating layer 232 and second sacrificial material layer 242 may be in the range of 2 to 1024, and typically in the range of 8 to 256, although more repetitions may be employed. In one embodiment, each second layer sacrificial material layer 242 in the second stack (232,242) may have a uniform thickness that is substantially constant within each respective second layer sacrificial material layer 242.

The second vertically alternating sequence (232,242) may be patterned to form a second stepped surface in a second stepped region within the contact region 200. The second stepped region is closer to the memory array region 100 than the first stepped region to the memory array region including the first stepped surface. The second stepped surface may be formed, for example, by forming a mask layer having openings therein, etching cavities within the topmost second layer sacrificial material layer 242 and the topmost second layer insulating layer 232, and iteratively expanding the etched regions, and vertically recessing the cavities by etching each pair of first layer insulating layer 132 and first layer sacrificial material layer 142 that is located directly below the bottom surface of the etched cavity within the etched regions. The second stepped surface extends continuously from a bottom-most layer in the second vertically alternating sequence (232,242) to a top-most layer in the first vertically alternating sequence (132, 142). The cavity overlying the second stepped surface is referred to herein as a first stepped cavity.

A dielectric material, such as silicon oxide, may be deposited over the second stepped surface. Portions of the dielectric material overlying the second vertically alternating sequence (232,242) may be removed by a planarization process, such as a Chemical Mechanical Planarization (CMP) process. The continuous remaining portion of dielectric material covering the second stepped surface and filling the second stepped cavity is referred to herein as a second backward stepped dielectric material portion 265. The second vertically alternating series (232,242) and the second backward stepped dielectric material portions 265 collectively constitute a second layer structure that is an in-process structure that is subsequently modified. The second stepped surface extends continuously from a bottom-most layer within the second vertically alternating sequence (232,242) to a top-most layer within the second vertically alternating sequence (232,242) and contacts the vertical and horizontal bottom surfaces of the second rearwardly stepped dielectric material portion 265.

A second insulating cap layer 270 may then be formed over the second vertically alternating sequence (232, 242). The second insulating cap layer 270 includes a dielectric material different from the material of the second layer of sacrificial material 242. In one embodiment, the second insulating cap layer 270 may include silicon oxide.

Optionally, a drain select level dielectric isolation structure 72 may be formed through a subset of layers in an upper portion of the second vertically alternating sequence (232, 242). The second layer of sacrificial material 242 cut by the drain select level dielectric isolation structures 72 corresponds to the level at which the drain select level conductive layers are subsequently formed. The drain select level dielectric isolation structure 72 comprises a dielectric material, such as silicon oxide.

In general, a subset of the layer of spacer material (such as the far-side subset of the second layer of sacrificial material layer 246 that is furthest from the substrate including the substrate semiconductor layer 9) may be divided by forming the drain select level trenches after forming the group of memory opening fill structures 58. The drain select level dielectric isolation structures 72 may be formed by depositing a dielectric material in the drain select level trenches. The drain select level dielectric isolation structures 72 may extend laterally along the first horizontal direction hd 1.

Referring to fig. 7A to 7C, the second-layer memory openings 249 and the second-layer support openings 219, which extend through the second-layer structure (232,242,270,265), are formed in the region covering the sacrificial memory opening filling portions 148. A photoresist layer may be applied over the second layer structure (232,242,270,265) and may be lithographically patterned to form the same pattern as the sacrificial memory opening fill portions 148 and the first layer sacrificial support structures 118, i.e., the pattern of the first layer memory openings 149 and the first layer support openings 119. An anisotropic etch may be performed to transfer the pattern of the lithographically patterned photoresist layer through the second layer structure (232,242,270,265). In one embodiment, the chemistry of the anisotropic etching process used to etch through the material of the second vertically alternating sequence (232,242) may be alternated to optimize the etching of the alternating material layers (232,242) in the second vertically alternating sequence. The anisotropic etch may be, for example, a series of reactive ion etches. For example, the patterned stack of photolithographic materials may be removed by ashing after the anisotropic etch process.

The top surface of the underlying sacrificial memory opening fill portions 148 may be physically exposed at the bottom of each second-layer memory opening 249. The top surface of the underlying first layer sacrificial support structures 118 may be physically exposed at the bottom of each second layer support opening 219.

Generally, the groups of second tier memory openings 249 can be formed through a second vertically alternating sequence (232, 242). Each group of the second-layer memory openings 249 may be formed within a rectangular region (e.g., a memory block region) extending laterally along the first horizontal direction hd 1. Each group of second layer memory openings 249 may include multiple rows of second layer memory openings 249. The second-layer memory openings 249 of each row may extend laterally along the first horizontal direction hd 1. The rows of second-layer memory openings 249 may be laterally spaced apart from one another along a second horizontal direction (e.g., bit line direction) hd 2. The number of rows within each group of second-layer memory openings 249 (e.g., in a memory string cell) depends on the total number of drain select level dielectric isolation structures 72 per group of second-layer memory openings 249. In one implementation, the drain select level dielectric isolation structures 72 are formed such that a region of each drain select level dielectric isolation structure 72 overlaps a row of second level memory openings 249. Fig. 7C shows an example where the total number of rows of drain select level dielectric isolation structures 72 within each memory block (i.e., within each group of second layer memory openings 249) is 1, 4, or 7, which results in a memory block having 8, 20, or 32 staggered rows of second layer memory openings 249, respectively. In these memory blocks, 2,5 or 8 drain-side select lines are formed in the drain select line level, respectively, which results in 2,5 or 8 memory string cells in each memory block, respectively. As can be seen in fig. 7C, the memory block size increases as the number of staggered rows of second layer memory openings 249 increases.

Referring to fig. 8, an etching process may be performed after the sacrificial memory opening filling portion 148 and the top surface of the first layer of sacrificial support structures 118 are physically exposed. The etch process removes the sacrificial memory opening fill portion 148 and the sacrificial material (e.g., C) of the first layer of sacrificial support structures 118 selective to the material of the second vertically alternating sequence (232,242) and the first vertically alternating sequence (132,142) ₄ F ₈ /O ₂ /Ar etching). The etching process may include an anisotropic etching process or an isotropic etching process.

Upon removal of the sacrificial memory opening fill portions 148, each vertically adjoining pair of second layer memory openings 249 and first layer memory openings 149 forms a continuous cavity extending through the first vertically alternating sequence (132,142) and the second vertically alternating sequence (232,242), which is referred to herein as an inter-layer memory opening 49 or memory opening 49. Likewise, upon removal of the first layer of sacrificial support structures 118, each vertically adjacent pair of second layer support openings 219 and first layer support openings 119 forms a continuous cavity extending through the first vertically alternating sequence (132,142) and the second vertically alternating sequence (232,242), referred to herein as an interlayer support opening 19 or a support opening 19. The top surface of the substrate semiconductor layer 9 may be physically exposed at the bottom of each memory opening and the bottom of each support opening. The positions of the steps S in the first (132,142) and second (232,242) vertically alternating sequences are shown in dashed lines.

Generally, at least one vertically alternating sequence of successive insulating layers and successive sacrificial material layers can be formed over a substrate. The reservoir openings 49 are formed through the at least one vertically alternating sequence.

Fig. 9A-9H provide sequential cross-sectional views of reservoir opening 49 or support opening 19 during formation of reservoir opening fill structure 58 or main support pillar structure 20. Although structural changes to the memory openings 49 are shown in fig. 9A-9H, it should be understood that the same structural changes occur in each of the memory openings 49 and the support openings 19 during the same set of processing steps.

Referring to fig. 9A, a memory opening 49 in the exemplary device structure of fig. 14 is shown. The memory opening 49 extends through the first layer structure and the second layer structure. Likewise, each support opening 19 extends through the first layer structure and the second layer structure. The pedestal channel portion 11 may or may not be present within each memory opening 49 and within each support opening 19. The cavity 49' exists in an unfilled portion of the memory opening 49 (or support opening) above the pedestal channel portion 11.

Referring to fig. 9B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element, such as nitrogen.

In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). Non-limiting examples of dielectric metal oxides include aluminum oxide (Al) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) Lanthanum oxide (LaO) ₂ ) Yttrium oxide (Y) ₂ O ₃ ) Tantalum oxide (Ta) ₂ O ₅ ) Silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof.

The dielectric metal oxide layer may be deposited, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Pulsed Laser Deposition (PLD), liquid source atomized chemical deposition, or combinations thereof. The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, although lesser and greater thicknesses may also be employed. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks stored charge from leaking to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include a plurality of dielectric metal oxide layers having different material compositions.

Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric silicon compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 may be formed by a conformal deposition method, such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof.

The thickness of the dielectric semiconductor compound may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be employed. Alternatively, the blocking dielectric layer 52 may be omitted, and the backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be formed later.

Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of charge trapping material including a dielectric charge trapping material (which may be silicon nitride, for example). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a layer of sacrificial material (142,242) within the lateral recesses. In one embodiment, charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layer (142,242) and the insulating layer (132,232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

In another embodiment, the sacrificial material layer (142,242) may be recessed laterally relative to the sidewalls of the insulating layer (132,232), and the charge storage layer 54 may be formed as a plurality of vertically spaced memory material portions using a combination of a deposition process and an anisotropic etching process. Although the present disclosure is described with an embodiment in which charge storage layer 54 is a single continuous layer, embodiments are expressly contemplated herein in which charge storage layer 54 is replaced by a plurality of vertically spaced apart portions of memory material (which may be portions of charge trapping material or electrically isolated portions of conductive material).

The charge storage layer 54 may be formed as a single charge storage layer of uniform composition, or may include a stack of a plurality of charge storage layers. The plurality of charge storage layers, if employed, may comprise a plurality of spaced apart floating gate material layers comprising conductive material (e.g., metals such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and/or semiconductor material (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or in addition, the charge storage layer 54 may include an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 may comprise conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage layer 54 may be formed, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of charge storage layer 54 may be in the range of 2nm to 20nm, but lesser and greater thicknesses may also be employed.

The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by fowler-nordheim tunneling induced charge transfer, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunnel dielectric layer 56 may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be employed.

Referring to fig. 9C, an optional first semiconductor channel layer 601 may be deposited by a conformal deposition process. The optional first semiconductor channel layer 601 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polysilicon. The first semiconductor channel layer 601 may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the first semiconductor channel layer 601 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be employed. A cavity 49' is formed in the volume of each reservoir opening 49 that is not filled with a deposited material layer (52,54,56, 601).

Referring to fig. 9D, the optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 are sequentially anisotropically etched using at least one anisotropic etching process. Portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 located above the top surface of the second insulating cap layer 270 may be removed by at least one anisotropic etching process. In addition, horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each cavity 49' may be removed to form an opening in the remaining portions thereof. Each of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 may be etched by a respective anisotropic etch process employing a respective etch chemistry, which may be the same or different for the various material layers.

Each remaining portion of the first semiconductor channel layer 601 may have a tubular configuration. The charge storage layer 54 may include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, charge storage layer 54 may be a charge storage layer in which each portion of the adjacent sacrificial material layer (142,242) constitutes a charge storage region.

The surface of the pedestal channel portion 11 (or the surface of the substrate semiconductor layer 9 in the case where the pedestal channel portion 11 is not employed) may be physically exposed below the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each cavity 49 'may be vertically recessed such that the recessed semiconductor surface below the cavity 49' is vertically offset from the topmost surface of the pedestal channel portion 11 (or semiconductor material layer 10 if pedestal channel portion 11 is not employed) by a recessed distance. A tunneling dielectric layer 56 is positioned over charge storage layer 54. A set of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 in memory opening 49 form a memory film 50 that includes a plurality of charge storage regions (e.g., embodied as charge storage layer 54) that are insulated from the surrounding material by blocking dielectric layer 52 and tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 may have vertically coincident sidewalls.

Referring to fig. 9E, the second semiconductor channel layer 602 may be deposited directly on the semiconductor surface of the pedestal channel portion 11 or on the semiconductor material layer 10 (if the pedestal channel portion 11 is omitted), and directly on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 includes amorphous silicon or polysilicon. The second semiconductor channel layer 602 may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the second semiconductor channel layer 602 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be employed. The second semiconductor channel layer 602 may partially fill the cavity 49' in each memory opening, or may completely fill the cavity in each memory opening.

The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

Referring to fig. 9F, in the event that the cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer 62L may be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L may be deposited by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD) or by a self-planarizing deposition process such as spin-coating.

Referring to fig. 9G, the horizontal portion of the dielectric core layer 62L may be removed, for example, by a recess etch from above the top surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62. In addition, the horizontal portion of the second semiconductor channel layer 602 located above the top surface of the second insulating cap layer 270 may be removed by a planarization process, which may employ recess etching or Chemical Mechanical Planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 may be positioned entirely within the memory opening 49 or entirely within the support opening 19.

Each contiguous pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 may collectively form a vertical semiconductor channel 60 through which current may flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds portions of the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 collectively comprise a memory film 50 that can store charge with macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and may be subsequently formed after the backside recess is formed. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a persistent memory device, such as a retention time in excess of 24 hours.

Referring to fig. 9H, the top surface of each dielectric core 62 may be further recessed into each memory opening, for example by recess etching to a depth between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. By doping the semiconductor materialA material is deposited in each recessed region over dielectric core 62 to form drain region 63. The drain region 63 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the drain region 63 may be 5.0 × 10 ¹⁸ /cm ³ To 2.0X 10 ²¹ /cm ³ Although lesser and greater dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from over the top surface of the second insulating cap layer 270, for example by Chemical Mechanical Planarization (CMP) or a recess etch, to form the drain region 63.

Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. Memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements embodied as part of charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of pedestal channel portion 11 (if present), memory stack structure 55, dielectric core 62, and drain region 63 within memory opening 49 constitutes a memory opening fill structure 58. Each combination of pedestal channel portion 11 (if present) within each support opening 19, memory film 50, vertical semiconductor channel 60, dielectric core 62, and drain region 63 fills the respective support opening 19 and constitutes a main support pillar structure 20.

The first level structure (132,142,170,165), the second level structure (232,242,270,265), the interlayer dielectric layer 180, the memory opening fill structures 58, and the main support pillar structures 20 collectively constitute a memory level assembly. Memory level components are formed over the substrate semiconductor layer 9 such that the substrate semiconductor layer 9 includes horizontal semiconductor channels electrically connected to the vertical semiconductor channels 60 within the memory stack structure 55.

Referring to fig. 10A and 10B, a first exemplary structure is shown after forming a reservoir opening filling structure 58 within each reservoir opening 49 and forming a main support post structure 20 within each support opening 19. Each memory opening fill structure 58 includes a respective vertical semiconductor channel 60.

Referring to fig. 11A-11C, a first contact level dielectric layer 280 may be formed over the memory level components. A first contact level dielectric layer 280 is formed at the contact level through which various contact via structures are subsequently formed to the drain region 63, and various conductive layers are formed in place of the sacrificial material layers (142,242) in subsequent processing steps.

Backside trenches 79 are then formed through the first contact level dielectric layer 280 and the memory level components. For example, a photoresist layer may be applied and photolithographically patterned on the first contact level dielectric layer 280 to form elongated openings extending along the first horizontal direction hd 1. An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the first contact level dielectric layer 280 and the memory level components to the top surface of the substrate semiconductor layer 9. The photoresist layer may then be removed, for example, by ashing.

The back side groove 79 extends in the first horizontal direction hd1, and thus is elongated in the first horizontal direction hd 1. The backside grooves 79 may be laterally spaced apart from each other along a second horizontal direction hd2 that may be perpendicular to the first horizontal direction hd 1. Backside trenches 79 may extend through memory array region (e.g., memory plane) 100 and contact region 200 within each plane (P0-P7).

In one embodiment, the backside grooves 79 may extend laterally along the first horizontal direction hd1 and be spaced laterally along the second horizontal direction hd 2. In one embodiment, the planes (P0-P7) may be arranged such that each even plane (P0, P2.P4, P6) is laterally spaced from a respective odd plane (P1, P3, P5, P7) by a respective backside trench 79, referred to herein as inter-array backside trenches 793. In general, the backside trenches 79 may include first backside trenches 791 extending laterally through respective ones of the even-numbered planes (P0, P2, P4, P6), second backside trenches 792 extending laterally through respective ones of the odd-numbered planes (P1, P3, P5, P7), and inter-array backside trenches 793 (shown in fig. 1B) formed within respective gap regions G. The first and second backside trenches (791,792) separate the memory blocks within each respective plane. Generally, the first backside trenches 791, the second backside trenches 792, and the inter-array backside trenches 793 may be formed simultaneously by forming a patterned etch mask layer (not shown) on the at least one vertically alternating sequence of continuous insulating layers (132,232) and continuous sacrificial material layers (142,242), and anisotropically etching the unmasked portions of the at least one vertically alternating sequence by performing an anisotropic etch process. In one embodiment, the patterned etch mask layer may be a patterned photoresist layer. In one embodiment, the first back side groove 791, the second back side groove 792, and the inter-array back side groove 793 may have the same width in the second horizontal direction hd 2. In one embodiment, the first backside trench 791, the second backside trench 792, and the inter-array backside trench 793 may be formed as a periodic one-dimensional array that repeats periodically along the second horizontal direction hd 2.

The portion of the continuous insulating layer (132,232) divided by the first backside trench 791 is referred to herein as a first insulating layer (132, 232). The portion of the continuous insulating layer (132,232) divided by the second backside trench 792 is referred to herein as the second insulating layer (132, 232). The portion of the continuous sacrificial material layer (142,242) divided by the first backside trench 791 is referred to herein as a first sacrificial material layer (142, 242). The portion of the continuous layer of sacrificial material (142,242) divided by the second backside trench 792 is referred to herein as the second layer of sacrificial material (142, 242).

Generally, the vertically alternating sequence of continuous insulating layers (132,232) and continuous sacrificial material layers (142,242) is divided into a first alternating stack of first insulating layers (132,232) and first sacrificial material layers (142,242) laterally spaced apart by first backside trenches 791, and a second alternating stack of second insulating layers (132,232) and second sacrificial material layers (142,242) laterally spaced apart by second backside trenches 792. The first and second alternating stacks are laterally spaced apart by the inter-array backside trenches 793. A first subset of the memory opening fill structures 58 extend vertically through a respective one of the first alternating stacks and a second subset of the memory opening fill structures 58 extend vertically through a respective one of the second alternating stacks.

A dopant having a second conductivity type opposite to the first conductivity type of the substrate semiconductor layer 9 may be implanted into a surface portion of the substrate semiconductor layer 9 to form a source region 61 below a bottom surface of each backside trench 79.

Referring to fig. 12A and 12B, an etchant that selectively etches the material of the first and second sacrificial material layers (142,242) with respect to the material of the first and second insulating layers (132,232), the first and second insulating cap layers (170,270), and the material of the outermost layers of the memory film 50 may be introduced into the backside trench 79, for example, using an isotropic etching process. A first backside recess 143 is formed in the volume from which the first layer of sacrificial material 142 is removed. A second backside recess 243 is formed in the volume from which the second layer of sacrificial material 242 is removed. In one embodiment, the first and second layers of sacrificial material (142,242) may comprise silicon nitride, and the material of the first and second layers of insulating layers (132,232) may be silicon oxide. In another embodiment, the first and second layers of sacrificial material (142,242) may comprise a semiconductor material such as germanium or a silicon-germanium alloy, and the material of the first and second layers of insulating layers (132,232) may be selected from silicon oxide and silicon nitride.

The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the first and second layers of sacrificial material (142,242) comprise silicon nitride, the etching process may be a wet etch process that immerses the first exemplary structure in a wet etch bath comprising phosphoric acid that etches silicon nitride selectively to silicon oxide, silicon, and various other materials employed in the art. Where the sacrificial material layer (142,242) comprises a semiconductor material, a wet etch process (which may employ a wet etchant such as KOH solution) or a dry etch process (which may include gaseous HCl) may be employed.

Each of the first and second backside recesses (143,243) may be a laterally extending cavity having a lateral dimension greater than a vertical extent of the cavity. In other words, a lateral dimension of each of the first and second backside recesses (143,243) may be greater than a height of the respective backside recess. A plurality of first backside recesses 143 can be formed in the volume from which the first layer of sacrificial material 142 material is removed. A plurality of second backside recesses 243 may be formed in the volume from which the second layer sacrificial material layer 242 material is removed. Each of the first and second backside recesses (143,243) may extend substantially parallel to a top surface of the substrate, which may be a top surface of the substrate semiconductor layer 9. The backside recess (143,243) may be vertically bounded by a top surface of an underlying insulating layer (132 or 232) and a bottom surface of an overlying insulating layer (132 or 232). In one implementation, each of the first backside recess and the second backside recess may have a uniform height throughout.

In one embodiment, after removing the first and second layers of sacrificial material (142,242), the sidewall surface of each pedestal channel portion 11 may be physically exposed at each bottommost first backside recess. In addition, the top surface of the substrate semiconductor layer 9 may be physically exposed at the bottom of each backside trench 79. An annular dielectric spacer 116 may be formed around each pedestal channel portion 11 by oxidizing the physically exposed peripheral portion of the pedestal channel portion 11. Further, a semiconductor oxide portion (not shown) may be formed from each physically exposed surface portion of the substrate semiconductor layer 9 while forming the annular dielectric spacer.

Referring to fig. 13A-13B, a backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses and backside trenches 79 and over the first contact level dielectric layer 280. A backside blocking dielectric layer may be deposited on the physically exposed portions of the outer surfaces of memory stack structure 55. The backside blocking dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. If employed, the backside blocking dielectric layer can be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1nm to 60nm, although lesser and greater thicknesses may also be employed.

At least one conductive material may be deposited in the plurality of backside recesses, on the sidewalls of the backside trenches 79, and over the first contact level dielectric layer 280. The at least one conductive material may comprise at least one metallic material, i.e. a conductive material comprising at least one metallic element.

A plurality of first layer conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second layer conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous layer of metallic material (not shown) may be formed on sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Thus, the first and second layers of sacrificial material (142,242) may be replaced with first and second layers of conductive material (146,246), respectively. Specifically, each first layer sacrificial material layer 142 may be replaced with an optional portion of a backside barrier dielectric layer and a first layer conductive layer 146, and each second layer sacrificial material layer 242 may be replaced with an optional portion of a backside barrier dielectric layer and a second layer conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with a continuous layer of metallic material.

The metallic material may be deposited by a conformal deposition method, which may be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. The metallic material may be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductively doped semiconductor material, a conductive metal-semiconductor alloy, such as a metal silicide, alloys thereof, and combinations or stacks thereof. Non-limiting exemplary metal materials that can be deposited in the backside recesses include tungsten, tungsten nitride, titanium nitride, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallic material may include a metal, such as tungsten and/or a metal nitride. In one embodiment, the metal material used to fill the backside recesses may be a combination of a titanium nitride layer and a tungsten fill material. In one embodiment, the metallic material may be deposited by chemical vapor deposition or atomic layer deposition.

The remaining conductive material may be removed from within backside trench 79. In particular, the deposited metallic material of the continuous metallic material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metallic material in the first backside recess constitutes a first layer of conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recesses constitutes a second layer conductive layer 246. Each conductive layer (146,246) may be a conductive line structure.

A subset of the second layer conductive layers 246 positioned at levels of the drain select level dielectric isolation structures 72 constitute drain select gate electrodes. A subset of the first layer conductive layer 146 at each level of the annular dielectric spacers (not shown) constitutes a source select gate electrode. A subset of the conductive layer (146,246) located between the drain select gate electrode and the source select gate electrode may be used as a combination of control gates and word lines located at the same level. The control gate electrode within each conductive layer (146,246) is a control gate electrode for a vertical memory device that includes memory stack structure 55.

Each of memory stack structures 55 includes a vertical stack of memory elements positioned at each level of a conductive layer (146,246). A subset of the conductive layers (146,246) may include word lines for memory elements. Memory level components are positioned above a substrate semiconductor layer 9. The memory hierarchy assembly includes at least one vertically alternating sequence (132,146,232,246) and a memory stack structure 55 extending vertically through the at least one vertically alternating sequence (132,146,232,246). Each alternating stack (132,146,232,246) includes alternating layers of a respective insulating layer (132,232) and a respective conductive layer (146,246). Each alternating stack (132,146,232,246) includes a stair-step region that includes a stair-step in which each underlying conductive layer (146,246) extends further along the first horizontal direction hd1 than any overlying conductive layer (146,246) within the memory-level component. Typically, first sacrificial material layer 142 and second sacrificial material layer 242 may be replaced with first conductive layer 146 and second conductive layer 246, respectively.

Referring to fig. 14A through 14C, a backside trench filling structure 76 may be formed in the remaining volume of each backside trench 79. In the embodiments shown in fig. 14A-14C and 42-44A, the backside trench-filling structure 76 is comprised of a dielectric separator. The dielectric isolation may be formed, for example, by depositing at least one dielectric material and removing excess portions of the deposited at least one dielectric material from above a horizontal plane including a top surface of the first contact level dielectric layer 280 by a planarization process, such as chemical mechanical planarization or recess etching.

In an alternative embodiment shown in fig. 18A-21, the backside trench-fill structure 76 includes a backside insulating spacer 74 and a conductive local interconnect (e.g., source contact) 75. The backside insulating spacers 74 may be formed by depositing a relatively thin dielectric layer in the backside trench 79, then performing an anisotropic sidewall spacer etch to remove horizontal portions of the dielectric layer and leave the backside insulating spacers 74 on the sidewalls of the backside trench 79. A conductive material (e.g., a metal, metal nitride, metal silicide, or heavily doped semiconductor) is then deposited on the backside insulating spacers 74 and planarized to the top surface of the first contact level dielectric layer 280 to form local interconnects 75.

The backside trench fill structure 76 provides electrical isolation in all lateral directions and extends laterally along the first horizontal direction hd 1. Thus, the backside trench-fill structure 76 is laterally elongated in the first horizontal direction hd 1. As used herein, a structure is "laterally elongated" if the maximum lateral dimension of the structure in a first horizontal direction is greater than the maximum lateral dimension of the structure in a second horizontal direction that is transverse to the first horizontal direction by at least a factor of 5.

The backside trench fill structures 76 may include a first backside trench fill structure 761 filling the first backside trench 791, a second backside trench fill structure 762 filling the second backside trench 792, and an inter-array backside trench fill structure 763 filling the inter-array backside trench 793. In general, the first backside trench fill structure 761, the second backside trench fill structure 762, and the inter-array backside trench fill structures 762 may be formed by simultaneously depositing at least a dielectric material and optionally a conductive material (such as a metallic material) within the first backside trench 791, the second backside trench 792, and the inter-array backside trench 793. Inter-array backside insulating material portions, such as backside insulating spacers 74, may be deposited directly on sidewalls of one of the first alternating stacks comprising a first plane of the first three-dimensional memory array and directly within each inter-array backside trench 793 on sidewalls of one of the second alternating stacks comprising a second plane of the second three-dimensional memory array.

Referring to fig. 15A and 15B, a second contact level dielectric layer 282 may optionally be formed over the first contact level dielectric layer 280. The second contact level dielectric layer 282 comprises a dielectric material, such as silicon oxide or silicon nitride. The thickness of the second contact level dielectric layer 282 may be in the range of 30nm to 300nm, although lesser and greater thicknesses may also be employed.

A photoresist layer (not shown) may be applied over the second contact level dielectric layer 282 and may be lithographically patterned to form openings at locations where various contact via structures are subsequently formed. The openings in the photoresist layer include wordline contact openings that cover horizontal surfaces of the first stepped surface and the second stepped surface in the contact region 200. Further, the opening in the photoresist layer includes a drain contact opening that covers a top surface of the memory stack structure 55.

A reactive ion etching process is performed to transfer the pattern of openings in the photoresist layer through the underlying dielectric material layer. A contact via cavity is formed through the lower dielectric material portion (282,280,270,265,165). The contact via cavity comprises a drain contact via cavity formed through the second contact-level dielectric layer 282, the first contact-level dielectric layer 280, and the second insulating cap layer 270 over the top surface of the drain region 63 within the memory stack structure 55. The top surface of drain region 63 is physically exposed at the bottom of the drain contact via cavity. The contact via cavities further include word line contact via cavities formed by an anisotropic etch process through the second contact level dielectric layer 282, the first contact level dielectric layer 280, the second insulating cap layer 270, and the second and first retro-stepped dielectric material portions (165, 265). Top surfaces (146,246) of the first and second conductive layers are physically exposed at a bottom region of the word line contact via cavity.

At least one conductive material may be deposited in the contact via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the second contact-level dielectric layer 282 by a planarization process, such as a recess etch or a Chemical Mechanical Planarization (CMP) process. Each remaining portion of the at least one conductive material in the word line contact via cavity constitutes a layer contact via structure 86 and each remaining portion of the at least one conductive material in the drain contact via cavity constitutes a drain contact via structure 88.

The first contact via structures 86 within the first subset of the contact via structures 86 extend vertically through the second rearwardly-stepped dielectric material portion 265 and the first rearwardly-stepped dielectric material portion 165 and contact a top surface of a respective one of the first level conductive layers 146. Second contact via structures 86 within the second subset of the layer contact via structures 86 extend vertically through the second backward-stepped dielectric material portion 265 and contact a top surface of a respective one of the second layer conductive layers 246.

Referring to fig. 16A-16D, at least one upper interconnect level dielectric layer 284 may be formed over the contact level dielectric layers (280, 282). Various upper interconnect-level metal structures may be formed in the at least one upper interconnect-level dielectric layer 284. For example, the various upper interconnect level metal structures may include line level metal interconnect structures (96, 98). The line-level metal interconnect structures (96,98) may include bit lines 98 contacting respective ones of the drain contact via structures 88 and extending along the second horizontal direction (e.g., bit line direction) hd2 and perpendicular to the first horizontal direction (e.g., word line direction) hd 1. Note that only two subsets of bit lines 98 are shown within each plane (P0-P7), and some of the bit lines 98 are schematically indicated as dashed lines between the two sets of bit lines 98 within each plane (P0-P7). Further, the line level metal interconnect structures (96,98) may include an upper metal line structure 96 that contacts a top surface of a respective one of the via structures 86 and/or another contact via structure (not shown) that extends vertically through the retro-stepped dielectric material portions (165,265) or other dielectric material portions (not shown). Additional metal interconnect structures (not shown) and additional layers of dielectric material (not shown) may be formed to provide electrical interconnections between various components of the three-dimensional memory device in the first exemplary structure.

In one embodiment shown in FIG. 16C, bit lines 98 include first bit lines 981 formed in even planes (P0.P2, P4, P6) and second bit lines 98 formed in odd planes (P1, P3, P5, P7). Generally, first and second bit lines 981,982 may be formed on a first alternating stack of first insulating layers (132,232) and first conductive layers (146,246) within each even-numbered plane (P0, P2, P4, P6), and on a second alternating stack of second insulating layers (132,232) and second conductive layers (146,246) within each odd-numbered plane (P1, P3, P5, P7). The first bit lines 981 are electrically connected to respective subsets of the first vertical semiconductor channels 60 within respective first three-dimensional memory arrays in respective ones of the even planes (P0, P2, P4, P6) and are electrically isolated from the second vertical semiconductor channels 60 within any other three-dimensional memory array. The second bit lines 982 are electrically connected to respective subsets of the second vertical semiconductor channels 60 within respective second three-dimensional memory arrays in respective ones of the odd-numbered planes (P1, P3, P5, P7) and are electrically isolated from the first vertical semiconductor channels 60 within any other three-dimensional memory array.

In an alternative embodiment, bit lines 98 may extend across even and odd planes, as shown in FIG. 16D. Each bit line 98 may be formed over an alternating stack of insulating layers (132,232) and conductive layers (146,246) in one even plane (P0, P2, P4, P6) and one odd plane (P1, P3, P5, P7). The bit lines 98 are electrically connected to the vertical semiconductor channels 60 in respective ones of the even planes (P0, P2, P4, P6) and in respective ones of the odd planes (P1, P3, P5, P7).

Referring to fig. 17A and 17B, a logic die 700 is shown, according to an embodiment of the present disclosure. Logic die 700 may include a logic die substrate 708 and peripheral circuitry 710 formed thereon. Logic die substrate 708 includes a logic die substrate semiconductor layer 709 at least at an upper portion thereof. Shallow trench isolation structures 720 may be formed in an upper portion of the logic die substrate semiconductor layer 709 to provide electrical isolation from other semiconductor devices. Peripheral circuitry 710 may include, for example, field effect transistors including respective transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, dielectric gate spacers 756, and a gate capping dielectric 758.

The logic die 700 may have multiple planar peripheral (i.e., driver or control) circuits (Q0-Q7), each of which may have the same area as the corresponding plane (P0-P7) of the semiconductor die shown in fig. 16C-16D. Logic die 700 may be one of a plurality of logic dies 700 disposed above a semiconductor wafer. Each planar peripheral circuit (Q0-Q7) of logic die 700 includes peripheral circuit 710 configured to operate a respective three-dimensional memory array within one of the planes (P0-P7) of the semiconductor die shown in fig. 16C-16D. In one embodiment, each planar peripheral circuit (Q0-Q7) of logic die 700 may include: a word line driver circuit 620 including word line switch transistors; a bit line driver circuit 630, including a sense amplifier; and miscellaneous peripheral circuitry 610 for operating the respective three-dimensional memory array in the respective plane in subsequent electrical connection therewith.

A layer of dielectric material, referred to herein as dielectric material layer 760, is formed over the semiconductor device. The dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and/or applies appropriate stress to underlying structures), an interconnect dielectric layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier layer) 766 overlying the interconnect dielectric layer 764, and a bond pad level dielectric layer 768.

The layer of dielectric material 760 serves as a matrix of metal interconnect structures 780 that provide electrical connections between the peripheral circuitry 710 and the logic side bond pads 798. Logic side bond pads 798 are embedded within bond pad level dielectric 768. Each layer of dielectric material within the interconnect dielectric layer 764 may comprise any of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides, such as aluminum oxide. In one embodiment, the interconnect dielectric layer 764 may comprise or consist essentially of a layer of dielectric material having a dielectric constant that does not exceed the dielectric constant of 3.9 for undoped silicate glass (silicon oxide). A metal interconnect structure 780 is formed within the dielectric layer stack of the lower-level dielectric material layer 760. Metal interconnect structure 780 may include various metal via structures 786 and various metal line structures 788.

In general, logic die 700 includes support circuitry configured to control the operation of memory die 900, which includes a three-dimensional memory array within the plane (P0-P7) of fig. 16A-16D. The logic side bond pads 798 may have a mirror image of the pattern of the memory side bond pads 998 shown in fig. 18A and 18B.

Referring to fig. 18A and 18B, a logic die 700 may be bonded to the memory die 900 of fig. 16A-16D. In fig. 18A, the substrate semiconductor layer 9 comprises a doped top portion of a semiconductor (e.g., silicon) substrate 8, such as a doped well in a silicon substrate. In fig. 18B, the substrate semiconductor layer 9 includes a buried source line (e.g., a heavily doped polysilicon layer) between the substrate (e.g., a silicon wafer) 8 and the first layer alternating stack (132,146).

For example, wafer-to-wafer bonding may be employed to bond a first wafer comprising multiple instances of the semiconductor die of fig. 16A-16D to a second wafer comprising multiple instances of logic die 700. The logic side bond pads 798 are bonded to respective ones of the memory side bond pads 998 by metal-to-metal bonds. Where bond pad level dielectric 768 and topmost dielectric layer 968 of memory die 900 comprise silicon oxide, oxide-to-oxide bonding may be used in addition to or instead of metal-to-metal bonding.

Typically, the logic side bond pads 798 may be bonded to respective ones of the memory side bond pads 998. Logic die 700 includes support circuitry (i.e., peripheral circuitry) configured to control the operation of the three-dimensional memory device within memory die 900. If the configuration of fig. 16C is used, the optional cut region CR shown in fig. 23 may be disposed at a bit line level between a first bit line 981 and a second bit line 982 of an adjacent pair of adjacent even and odd planes. Alternatively, if the configuration of fig. 16D is used, the cutting region is omitted and each bit line 98 extends continuously on adjacent odd and even planes, as shown in fig. 18A and 18B. The lateral spacing between adjacent pairs of planes using different sets of bit lines 98 may be the same as the width of the backside trench fill structures 76.

In general, bit lines 98 may directly contact a respective subset of drain contact via structures 88, or may be electrically connected to a respective subset of drain contact via structures 88 through additional connection via structures 188.

Typically, alternating stacks of insulating layers (132,232) and layers of spacer material, such as layers of sacrificial material (142,242), may be formed over the substrate. The layer of spacer material may be formed as a conductive layer (146,246), or may be subsequently replaced by such conductive layers. Groups of memory openings 49 may be formed through the alternating stacks (132, 232). Groups of memory opening fill structures 58 may be formed in the memory openings 49. Each of memory opening fill structures 58 includes a memory stack structure 55 that includes a respective vertical stack of memory elements, which may include a portion of memory film 50 at the level of conductive layer (146,246), and a respective vertical semiconductor channel 60. Each of the memory opening fill structures 58 can comprise a vertical NAND string containing a vertical stack of memory elements. An alternating stack of insulating layers (132) and conductive layers (146,246) can be formed over the substrate. The backside trench filling structure 76 may be formed through the alternate stacking { (132,146), (232,246) }. For each alternating stack of insulating layers (132,232) and conductive layers (146,246), a pair of backside trench-fill structures 76 can be formed through the alternating stack { (132,146), (232,246) }.

Referring to fig. 19A and 19B, the backside of the substrate 8 may be thinned, for example, by grinding, polishing, an anisotropic etching process, and/or an isotropic etching process. The thickness of the substrate semiconductor layer 9 after thinning (i.e., the doped well in fig. 19A or the buried source line in fig. 19B) may be in the range of 100nm to 6,000nm, but smaller and larger thicknesses may also be employed. In one embodiment shown in fig. 19A, the substrate semiconductor layer 9 may be a layer of single crystal semiconductor material, such as a single crystal silicon layer. In another embodiment shown in fig. 19B, the substrate semiconductor layer 9 may be a layer of polycrystalline semiconductor material, such as a doped polysilicon layer. The substrate semiconductor layer 9 constitutes a source-level material layer (e.g., a source line). In one embodiment, the source-level material layer may be doped with dopants of the second conductivity type by providing dopants of the second conductivity type, for example by ion implantation or gas phase diffusion. In an alternative embodiment, dopants of the second conductivity type may be implanted or diffused from the front side of the substrate semiconductor layer 9 before forming the first layer of alternating stacks of first insulating layers 132 and first sacrificial material layers 142. In another alternative implementation shown in fig. 19B, dopants of the second conductivity type may be provided in-situ during the buried source line growth.

Referring to fig. 20A and 20B, a photoresist layer may be applied over the backside of the substrate semiconductor layer 9 and may be lithographically patterned to form line-shaped openings extending laterally along the first horizontal direction hd 1. An anisotropic etching process may be performed to divide the substrate semiconductor layer 9 into a plurality of semiconductor material layers that serve as respective sets of source regions (or a combination of source regions and source lines) of the vertical semiconductor channels 60 located within the same region (e.g., a string cell region). The plurality of layers of semiconductor material is hereinafter referred to as source layer 9. The thinned substrate semiconductor layer 9 having the doping of the second conductivity type serves as a source-level material layer, and a plurality of source layers 9 are formed by patterning the thinned substrate semiconductor layer 9. A plurality of source-side trenches 21 are formed through the source-level material layer such that each adjacent pair of the plurality of source layers 9 is laterally spaced apart from each other by a respective one of the plurality of source-side trenches 21. The plurality of source layers 9 are laterally spaced apart and electrically isolated from each other. Each group of memory opening fill structures 58 contacts a respective one of the plurality of source layers 9. Each adjacent pair of the source layers 9 of the plurality of source layers 9 is laterally spaced apart from each other by a respective one of the plurality of source-side trenches 21. A dielectric material may be deposited in the source side trenches 21 and over the source layer 9 to form source level dielectric isolation structures 23 in the respective trenches 21.

Referring to fig. 21, a first alternative configuration of the first exemplary structure is shown after forming a plurality of source layers 9 (e.g., of the type shown in fig. 18A or the buried source line shown in fig. 18B). In a first alternative configuration, the plurality of source-side trenches 21 extend through the source-level material layers to form the source layer 9 and through at least one topmost conductive layer 146 below the source layer 9 to form a separate source-side select gate electrode (SGS) (i.e., source-side select gate line) 146S. Each patterned first layer conductive layer 146 within the first subset of conductive layers (146,246) may be divided into a plurality of source side select gate electrodes 146S by forming source side trenches 21. The source-side trenches 21 do not divide a second subset of the conductive layer that serves as word lines (i.e., word lines) (146W,246W) extending laterally between an adjacent pair of the backside trench-fill structures 76 in the word line direction hd 1. The source-side trenches 21 also do not divide the drain-side select gate electrode 246D separated by the drain select level dielectric isolation structure 72. A dielectric material may be deposited in the source side trenches 21 and over the source layer 9 to form source level dielectric isolation structures 23 in the respective trenches 21.

Fig. 22A-22D illustrate an alternative configuration of the memory opening 49 during formation of the memory opening fill structure 58 according to a second embodiment of the present disclosure.

Referring to fig. 22A, interlayer memory openings 49 (i.e., memory openings 49) or interlayer support openings 19 are shown in the processing step of fig. 8.

Referring to fig. 22B, a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 may be deposited in the interlayer memory opening 49 by performing the process steps of fig. 9B. The combination of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 constitute memory film 50.

Referring to fig. 23C, a semiconductor channel layer 60L may be deposited on the memory film 50. The semiconductor channel layer 60L may be deposited in the same manner as the first semiconductor channel layer 601 or the second semiconductor channel layer 602 described above, and may have the same material composition as the first semiconductor channel layer 601 and/or the second semiconductor channel layer 602. The thickness of the semiconductor channel layer 60L may be the same as the sum of the thicknesses of the first semiconductor channel layer 601 or the second semiconductor channel layer 602.

Referring to fig. 22D, the processing steps of fig. 9F, 9G, and 9H may be performed to form a dielectric core 62 and a drain region 63 within each memory opening fill structure 58. Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60.

Subsequently, the process steps of fig. 10-18 may be performed to form a second exemplary structure including a bonded assembly of the memory die 900 and the logic die 700 according to a second embodiment of the present disclosure. Each alternating stack of insulating layers (132,232) and conductive layers (146,246) may be laterally bounded by a pair of backside trench-fill structures 76.

Referring to fig. 23, an optional cut region CR between first bit line 981 and second bit line 982 shown in fig. 16C may exist in memory die 900 between adjacent planes P0 and P1. Alternatively, the cutting region CR may be omitted, and the continuous bit line 98 shown in fig. 16D and 20 may be provided instead.

Referring to fig. 23 and 24A, the substrate semiconductor layer 9 may be removed from the backside of the bonded assembly, for example, by grinding, polishing, an anisotropic etching process, or an isotropic etching process. For example, the substrate semiconductor layer 9 may be thinned from the back side, for example, by grinding, and an isotropic etching process or an anisotropic etching process may be performed to remove the remaining portion of the substrate semiconductor layer 9 selectively to the memory film 50. For example, the isotropic etching process may include a wet etching process using potassium hydroxide.

Referring to fig. 24B, a series of isotropic etching processes may be performed to etch the physically exposed portion (i.e., the bottom portion) of the storage film 50. The series of isotropic etch processes may be selected to sequentially etch the materials of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 selective to the material of vertical semiconductor channel 60, thereby exposing at least a bottom portion of vertical semiconductor channel 60.

Referring to fig. 25A and 25B, a layer of source-level material 109 may be deposited on the physically exposed end faces of the vertical semiconductor channels 60, which are referred to herein as proximal end faces. The source-level material layer 109 comprises at least one conductive material. In one implementation, the source level material layer 109 comprises a heavily doped semiconductor material, such as polysilicon. In another embodiment, the source-level material layer 109 may comprise a vertical stack of a heavily doped polycrystalline source semiconductor (e.g., polysilicon) layer 109A having a doping of the second conductivity type and a metal source layer 109B, such as a metal silicide (e.g., titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide) or a metal (e.g., tungsten, aluminum, molybdenum, copper, etc.).

Referring to fig. 26A and 26B, source-side trenches 21 may be formed through the source-level material layer 109. Each of the source-side trenches 21 may extend laterally along a first horizontal direction (i.e., word line direction) hd1, and may laterally divide the source-level material layer 109 into a plurality of source structures, referred to herein as source lines 109. A subset of the source-side trenches 21A extend to a proximal subset of the first conductive layer 146 that is proximate to the source layer 109. An optional second subset of the source-side trenches 21B extend vertically to the backside trench fill structure 76. A dielectric material may be deposited in the source side trenches 21 and over the source layer 9 to form source level dielectric isolation structures 23 in the respective trenches 21. Fig. 26A shows the configuration of the divided bit lines (981,982) of fig. 16C, and fig. 26B shows the configuration of the continuous bit line 98 of fig. 16D.

Referring to fig. 27, a circuit schematic of the second exemplary structure of fig. 26A and 26B is shown. For clarity, fig. 27 shows 16 staggered rows of devices, while fig. 26A and 26B show 24 staggered rows of devices. The source lines (SL1, SL2, SL3, SL4) may include the source layer 109 shown in fig. 26A and 26B or the source layer 9 shown in fig. 20A or 20B. By dividing a single source line into four source layers (e.g., source lines), smaller erase units EU having a smaller number of memory cells, including a Gate Induced Drain Leakage (GIDL) erase step, may be erased during the erase step, during which an erase voltage is applied to the respective source line (e.g., SL1 in fig. 27). Therefore, the size of the functional memory block (i.e., the erase unit EU) is reduced. This reduces the operating leakage current.

Referring collectively to the first and second example structures, a plurality of source layers (9 or 109) may be formed by patterning the source level material layer. The plurality of source layers (9 or 109) are laterally spaced apart and electrically isolated from each other, and each group of memory opening fill structures 58 may contact a respective one of the plurality of source layers (9 or 109). A plurality of source-side trenches 21 may be formed through the source-level material layer, wherein each adjacent pair of the plurality of source layers (9,109) are laterally spaced apart from each other by a respective one of the plurality of source-side trenches 21.

Referring to fig. 28, a third exemplary structure according to a third embodiment of the present disclosure is shown after removal of the substrate semiconductor layer 9 and after formation of the source selection level trenches 17. In this case, source select level trenches 17 may be formed through the first subset of conductive layers (i.e., the source side select gate electrode) 146S after removing the substrate 8 and before forming the at least one layer of conductive material that is subsequently used to form the source layer 109. Typically, a plurality of source side select gate electrodes (i.e., source select level conductive layers) 146S may be formed by forming source select level trenches 17 through the plurality of source side select gate electrodes 146S before or after forming the source level material layers. The source select level trenches 17 do not divide the word lines (146W,246W) or the drain side select gate electrodes 146D. Source select level trenches 17 are source side trenches that extend vertically through source side select gate electrodes 146S, which are a subset of the conductive layer (146,246). The source side select gate electrode 146S can activate or deactivate a respective string group of vertical semiconductor channels 60 of NAND strings, thereby selecting or deselecting a group of NAND strings within the three-dimensional memory array. While a split bit line 98 configuration is shown in fig. 28, it should be understood that the continuous bit line 98 configuration of fig. 16D or 26B may alternatively be used.

Referring to fig. 29, a dielectric material such as silicon oxide may be deposited in source select level trenches 17. Excess portions of the dielectric material may be removed by a planarization process from above a horizontal plane including a topmost one of the insulating layers, such as the nearest first level insulating layer 132. Source select level dielectric isolation structures 22 comprising remaining portions of dielectric material may be formed in source select level trenches 17.

Referring to fig. 30, the process steps of fig. 25A and 25B may be performed to form a source-level material layer 109, referred to herein as a proximal face, on the physically exposed end faces of the vertical semiconductor channels 60. The source-level material layer 109 comprises at least one conductive material. In one embodiment, the source-level material layers 109 may include a vertical stack of a polycrystalline source semiconductor layer 109A having a doping of the second conductivity type and a metal source layer 109B comprising a metal material. Typically, the source-level material layer 109 may be formed by replacing the substrate 8 with at least one layer of conductive material 109. In the third embodiment, the source-side trench 21 of fig. 26A and 26B may be present or omitted.

Referring to fig. 31A, a circuit schematic of the third exemplary structure of fig. 30 is shown. Four split source side select gate electrodes 146S1,146S2,146S3, and 146S4 are shown in fig. 31A. However, there may be two, three or more than four split source side select gate electrodes. The single source line SL may include the source layer 9 shown in fig. 20A or 20B or the source layer 109 shown in fig. 29. In this embodiment, the smaller erase units EU having a smaller number of memory cells can be erased during the erase step, during which the erase voltage is applied to the common source line SL. Therefore, the size of the functional memory block (i.e., the erase unit EU) is reduced. This reduces the operating leakage current.

Referring to fig. 31B, a schematic top view of a third exemplary structure is shown. A plurality of source side select gate electrodes 146S located at the same vertical level are laterally spaced apart from each other in the horizontal direction by source select level dielectric isolation structures 22. The plurality of source side select gate electrodes 146S are located between the at least one source layer (9,109) and the word lines (146w,246w) in the vertical direction.

Referring to fig. 32, a fourth exemplary structure according to a fourth embodiment of the present disclosure is shown, which may be the same as the second exemplary structure shown in fig. 25A and 25B. The structure may include the split bit lines (981,982) of FIG. 16C or the continuous bit line 98 of FIG. 16D.

Referring to fig. 33, source-side trenches 21 may be formed through source-level material layer 109 and through a first subset of conductive layers, such as a proximal subset of first-level conductive layers 146. The pattern of the source-side trench 21 may be the same as that of the source-side trench in the exemplary structure shown in fig. 26A and 26B. A plurality of source layers 109 are formed by patterning the source-level material layer 109. The plurality of source layers 109 may be laterally spaced apart from each other and may be electrically isolated. Each string of memory opening fill structures 58 contacts a respective one of the plurality of source layers 109.

Each patterned first layer conductive layer 146 within the first subset of conductive layers (146,246) may be divided into a plurality of source side select gate electrodes 146S by forming source side trenches 21. The source-side trenches do not divide the word lines (146W,246W) or the drain-side select gate electrodes 246D. A dielectric material may be deposited in the source side trenches 21 and over the source layer 109 to form source level dielectric isolation structures 23 in the respective trenches 21.

A first subset of the source-side trenches 21 extend into a respective one of the backside trench fill structures 76. A second subset of the source-side trenches 21 extends into a proximal subset of the one or more conductive layers 146 and divides them into a respective plurality of source-side select gate electrodes 146S.

Referring to fig. 34, a first alternative configuration of a fourth exemplary structure according to a fourth embodiment of the present disclosure is shown. A first alternative configuration of the fourth example structure may be derived from the fourth example structure of fig. 33 by depositing dielectric material in the source-side trenches 21 and over the source layer 109 to form the source level dielectric isolation layers 122 such that each portion of the layers 122 protruding down into a respective trench 21 comprises a combination of a source level isolation structure 23 and a source select level isolation structure 22.

Referring to fig. 35, a second alternative configuration of the fourth exemplary structure according to the fourth embodiment of the present disclosure may be derived from the third exemplary structure of fig. 30 by dividing the source level material layer 109 and dividing the source side select gate layer 146S in separate steps. For example, as shown in fig. 29, a source select level dielectric isolation structure 22 is first formed in the source side select gate layer 146S. A source-level material layer 109 is then deposited over the source select-level dielectric isolation structures 22 and the source-side select gate layer 146S, followed by forming source-side trenches 21 in the source-level material layer 109 using the method illustrated in fig. 26A and 26B to divide the layer 109 into the plurality of source layers 109. A dielectric material may be deposited in the source side trenches 21 and over the source layer 9 to form source level dielectric isolation structures 23 in the respective trenches 21.

Referring to fig. 36, circuit schematics of various configurations of the fourth exemplary structure of fig. 32-35 are shown. A plurality of split source lines (SL1, SL2, SL3, SL4) and a plurality of split source side select gate electrodes (146S1,146S2,146S3,146S4) may be formed between the pair of back side trench fill structures 76. Each block of vertical NAND strings can be activated or deactivated by the source layer (9,109), by the source side select gate electrode 146S, or by a combination of the source layer and the source side select gate electrode 146S.

Referring to fig. 37, an exemplary structure for providing an electrical connection to a source layer (9 or 109) is illustrated in accordance with an embodiment of the present disclosure. In particular, a backside metal interconnect structure 930, such as aluminum tape, may be employed to provide electrical connections between metal interconnect structure 980A (i.e., a subset of structures 980 described above) and each source layer (9 or 109). A subset of backside metal interconnect structures 930 may contact a backside surface of a respective one of the source layers (9 or 109).

Referring to fig. 38, another exemplary structure for providing an electrical connection to a source layer (9 or 109) is illustrated in accordance with an embodiment of the present disclosure. In this case, metal interconnect structure 980A may contact a frontside surface of a respective one of the source layers (9 or 109).

Referring to fig. 39A and 39B, a fifth exemplary structure according to a fifth embodiment of the present disclosure may be derived from the first exemplary structure of fig. 10A and 10B by modifying the pattern of the memory opening filling structure 58. In particular, the memory openings 49 and the memory opening fill structures 58 may be formed at spaced intervals such that all of the memory opening fill structures 58 remain active after the formation of the drain select level dielectric isolation structures 72. In contrast, in the first exemplary structure of fig. 10A and 10B, each fifth row of memory opening fill structures 58 acts as a dummy memory opening fill structure 58 as it is cut in half by a respective drain select level dielectric isolation structure 72.

Referring to fig. 40A and 40B, a drain select level dielectric isolation structure 72 may be formed through a distal subset of the second layer of sacrificial material 242 away from the substrate semiconductor layer 9. In this case, the drain select level dielectric isolation structure 72 may be formed between a pair of rows of memory opening fill structures 58 and may cut through an edge portion of each memory opening fill structure 58 in the pair of rows of memory opening fill structures 58. Each drain select level dielectric isolation structure 72 may extend laterally along the first horizontal direction hd 1.

Referring to fig. 41 and 42, the processing steps of fig. 11-19 and the processing steps of fig. 23 may be performed. In one implementation, each of the memory opening fill structures 58 may be formed using the processing steps of fig. 22A-22D. In this case, a series of isotropic etching processes may be employed to remove the proximal portion of the memory film 50 and physically expose the proximal portion of the vertical semiconductor channel 60.

Referring to fig. 43, a photoresist layer (not shown) may be applied on the physically exposed proximal surface of the alternating stack { (132,146), (232,246) }, and may be lithographically patterned to form a linear opening in the area overlying the drain select level dielectric isolation structure 72. An anisotropic etch process may be performed to etch through a first subset of the conductive layers, such as a proximal subset of the first layer conductive layer 146, to form the source side select gate electrode 146S. Source select level trenches 17 may be formed through a first subset of conductive layers into the source side select gate electrode 146S.

Referring to fig. 44A and 44B, source select level dielectric isolation structures 22 may be formed in source select level trenches 17 by depositing a dielectric material, such as silicon oxide, and by removing excess portions of the dielectric material from over the alternating stack of insulating layers (132,232) and conductive layers (146,246).

Referring to fig. 45, the process steps of fig. 32 may be performed to form source-level material layers 109, which may serve as a single source layer 109.

Referring to fig. 46, the process steps of fig. 35 may optionally be performed to divide the source-level material layer 109 into a plurality of source layers 109. A dielectric material may be deposited in the source side trenches 21 and over the source layer 109 to form source level dielectric isolation structures 23 in the respective trenches 21. Typically, a plurality of source layers 109 may be formed by patterning the source level material layers. The plurality of source layers 109 are laterally spaced apart and electrically isolated from one another. Each group of memory opening fill structures 58 contacts a respective one of the plurality of source layers 109.

With reference to all figures and in accordance with various embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers (132,232) and conductive layers (146,246) over the plurality of source layers (9,109), wherein the alternating stack is between a pair of backside trench-fill structures 76; a reservoir opening 49 extending vertically through the alternating stack { (132,146), (232,246) }; and groups of memory opening fill structures 58, the groups located in memory openings 49, wherein each of the memory opening fill structures 58 comprises a respective vertical stack of memory elements (which may comprise portions of charge storage layer 54 located at a level of word lines (146W, 246W)); a respective vertical semiconductor channel 60 having a first end contacting a respective one of the plurality of source layers (9, 109); and a respective drain region 63 contacting a second end of the respective vertical semiconductor channel 60; wherein: the plurality of source layers (9,109) being laterally spaced apart and electrically isolated from each other; and each group of memory opening fill structures 58 contacts a respective one of the plurality of source layers.

In one embodiment, the plurality of source layers 9 comprises a plurality of layers of single crystalline semiconductor material having the same crystallographic orientation. In one embodiment, each of the memory opening fill structures 58 includes a pedestal channel portion 11 comprising a single crystal semiconductor material having a doping of opposite conductivity type relative to the plurality of layers of single crystal semiconductor material and contacting a respective one of the plurality of layers of single crystal semiconductor material.

In one embodiment, the plurality of source layers 109 includes a plurality of polycrystalline source semiconductor layers 109A; and each of the memory opening fill structures 58 contacts a respective one of the plurality of polycrystalline source semiconductor layers 109A. In one embodiment, each of the plurality of source layers 109 comprises a respective stack of a source semiconductor layer 109A and a metal source layer 109B.

In one embodiment, the plurality of source layers (9,109) are laterally spaced apart from each other by respective source level dielectric isolation structures 23. In one embodiment, the conductive layer includes: word lines (146w,246w) extending laterally continuously between and contacting each of the pair of backside trench-fill structures 76; and a plurality of source side select gate electrodes 146S located between the plurality of source layers (9,109) and the word lines (146W,246W) in the vertical direction. The plurality of source side select gate electrodes 146S are laterally spaced apart by source select level dielectric isolation structures 23.

In one implementation, each of the source-level dielectric isolation structures 23 contacts a respective one of the source select-level isolation structures 22. In the configuration of fig. 21, each of the source-level dielectric isolation structures 23 has a sidewall that vertically coincides with a respective one of the source select-level isolation structures (i.e., a continuous straight sidewall with continuous taper or no taper in the vertical direction). In the configuration of fig. 35, there is a horizontal step between each of the source-level dielectric isolation structures 23 and a respective one of the source select-level isolation structures 22. In the configuration of fig. 34, a source horizontal isolation dielectric layer 120 contacts the backside of each of the plurality of source layers 109 and includes vertically downward protruding portions 122 that include both the source-level dielectric isolation structures 23 and the source select-level isolation structures 22.

In one embodiment, each of the plurality of source layers (9,109) contacts only one of the pair of backside trench fill structures 76 or does not contact any of the pair of backside trench fill structures 76. In one embodiment, each of the plurality of source side select gate electrodes 146S laterally surrounds a respective group of memory opening fill structures 58 and is laterally spaced apart from any other group of memory opening fill structures 58 of the group of memory opening fill structures 58.

In one embodiment, the three-dimensional memory device includes a bit line 98 and a drain contact via structure 88 that contacts the drain region 63. The conductive layer (146,246) includes a plurality of drain select level conductive layers 246D that are vertically between word lines (146w,246w) and bit lines 98 and laterally spaced apart by drain select level dielectric isolation structures 72. In one embodiment, each of the pair of backside trench fill structures 76 includes a dielectric structure or conductive local interconnect 75 surrounded by an insulating spacer 74, as shown in fig. 18A.

According to another aspect of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers (132,232) and conductive layers (146,246) over the at least one source layer (9,109) and between a pair of backside trench-fill structures 76; sets of reservoir openings 49 extending vertically through the alternating stack { (132,146), (232,246) }; and groups of memory opening fill structures 58, the groups located in groups of memory openings 49, wherein each of the memory opening fill structures 58 comprises a respective vertical stack of memory elements (which includes a portion of charge storage layer 54 located at a level of a word line (146W, 246W)); a respective vertical semiconductor channel 60 having a first end contacting the at least one source layer (9, 109); and a respective drain region 63 contacting a second end of the respective vertical semiconductor channel 60. The conductive layer (146,246) includes: word lines (146w,246w) extending laterally continuously between and contacting each of the pair of backside trench-fill structures 76; and a plurality of source side select gate electrodes 146S vertically between the at least one source layer (9,109) and the word lines (146W,246W), and horizontally between the pair of backside trench-fill structures 76, wherein the plurality of source side select gate electrodes 146S are laterally spaced apart by the source select level dielectric isolation structures 22.

In one embodiment, the vertical semiconductor channel 60 comprises a doped semiconductor material having a first conductivity type; and the at least one source layer (9,109) comprises a layer of semiconductor material having a doping of a second conductivity type opposite to the first conductivity type. In one embodiment, the at least one source layer (9,109) includes a continuous source layer contacting each of the first ends of each of the vertical semiconductor channels 60. In one implementation, each of the source select level dielectric isolation structures 22 includes a first horizontal surface contacting one of the insulating layers (132,232) and a second horizontal surface contacting the at least one source layer (9, 109).

In another embodiment, the at least one source layer (9,109) includes a plurality of source layers laterally spaced apart from one another. Each group of memory opening fill structures 58 of the group of memory opening fill structures 58 contacts a respective one of the plurality of source layers (9,109) and is electrically isolated from all other source layers (9,109) of the plurality of source layers (9, 109).

In one embodiment, the plurality of source layers (9,109) are laterally spaced apart from each other by respective source level dielectric isolation structures 23. In one implementation, each of the source-level dielectric isolation structures 23 contacts a respective one of the source select-level isolation structures 22. In the configuration of fig. 21, each of the source-level dielectric isolation structures 23 has a sidewall that vertically coincides with a respective one of the source select-level isolation structures (i.e., a continuous straight sidewall with continuous taper or no taper in the vertical direction). In the configuration of fig. 35, there is a horizontal step between each of the source-level dielectric isolation structures 23 and a respective one of the source select-level isolation structures 22. In the configuration of fig. 34, a source horizontal isolation dielectric layer 120 contacts the backside of each of the plurality of source layers 109 and includes vertically downward protruding portions 122 that include both the source-level dielectric isolation structures 23 and the source select-level isolation structures 22.

In one embodiment, each of the pair of backside trench fill structures 76 includes a dielectric structure or conductive local interconnect 75 surrounded by an insulating spacer 74, as shown in fig. 18A.

In one embodiment, the plurality of source layers 109 includes a plurality of polycrystalline semiconductor layers 109A. In one embodiment, each of the plurality of source layers (9,109) contacts only one of the pair of backside trench fill structures 76 or does not contact any of the pair of backside trench fill structures 76. In one embodiment, each of the plurality of source side select gate electrodes 146S laterally surrounds a respective group of memory opening fill structures 58 and is laterally spaced apart from any other group of memory opening fill structures 58 of the group of memory opening fill structures 58.

In one embodiment, the number of reprogramming steps is reduced by performing an erase operation on a smaller memory string rather than the entire memory block. This improves the programming speed. Further, the select/unselect operation is operated with higher accuracy on the string unit. The disturb memory cell area of the erase unit EU is reduced. Thus, unselected NAND string stress is reduced and cell degradation is improved.

While specific embodiments have been mentioned above, it should be understood that the disclosure is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the word "comprising" or "includes" contemplates all embodiments in which the word "consisting essentially of …" or the word "consisting of …" replaces the word "comprising" or "includes". Embodiments employing specific structures and/or configurations are shown in the present disclosure, it being understood that the present disclosure may be practiced in any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising:

an alternating stack of insulating layers and conductive layers over a plurality of source layers, wherein the alternating stack is between a pair of backside trench-fill structures;

a set of memory openings extending vertically through the alternating stack; and

a set of memory opening fill structures located in the set of memory openings, wherein each of the memory opening fill structures comprises: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting a respective one of the plurality of source layers; and a respective drain region contacting a second end of the respective vertical semiconductor channel,

wherein:

the plurality of source layers are laterally spaced apart and electrically isolated from one another; and is

Each group of memory opening fill structures contacts a respective one of the plurality of source layers.

2. The three-dimensional memory device of claim 1, wherein the plurality of source layers comprises a plurality of layers of single crystalline semiconductor material having a same crystallographic orientation.

3. The three-dimensional memory device of claim 2, wherein each of the memory opening fill structures comprises a pedestal channel portion comprising a single crystal semiconductor material having a doping of opposite conductivity type relative to the plurality of layers of single crystal semiconductor material and contacting a respective one of the plurality of layers of single crystal semiconductor material.

4. The three-dimensional memory device of claim 1, wherein:

the plurality of source layers comprises a plurality of polycrystalline source semiconductor layers; and is

Each of the memory opening fill structures contacts a respective one of the plurality of polycrystalline source semiconductor layers.

5. The three-dimensional memory device of claim 1, wherein each of the plurality of source layers comprises a respective stack of a source semiconductor layer and a metal source layer.

6. The three-dimensional memory device of claim 1, wherein the plurality of source layers are laterally spaced apart from each other by respective source-level dielectric isolation structures.

7. The three-dimensional memory device of claim 6, wherein the conductive layer comprises:

a word line extending continuously laterally between and contacting each of the pair of the backside trench fill structures; and

a plurality of source side select gate electrodes vertically between the plurality of source layers and the word line, wherein the plurality of source side select gate electrodes are laterally spaced apart by a source select level dielectric isolation structure.

8. The three-dimensional memory device of claim 7, wherein each of the source-level dielectric isolation structures contacts a respective one of the source selection-level isolation structures.

9. The three-dimensional memory device of claim 8, wherein each of the source-level dielectric isolation structures has a sidewall vertically coincident with the respective one of the source select-level isolation structures.

10. The three-dimensional memory device of claim 8, wherein there is a horizontal step between each of the source-level dielectric isolation structures and a respective one of the source-select-level isolation structures.

11. The three-dimensional memory device of claim 8, further comprising a source level isolation dielectric layer that contacts a backside of each of the plurality of source layers and comprises a vertically downward protruding portion comprising the source level dielectric isolation structure.

12. The three-dimensional memory device of claim 7, wherein:

each of the pair of backside trench fill structures comprises a dielectric structure or a conductive local interconnect surrounded by an insulating spacer;

each of the plurality of source layers contacts only one of the pair of the back side trench fill structures or does not contact any of the pair of the back side trench fill structures; and is

Each of the plurality of source side select gate electrodes laterally surrounds a respective group of memory opening fill structures and is laterally spaced apart from any other group of memory opening fill structures of the group of memory opening fill structures.

13. The three-dimensional memory device of claim 8, further comprising a bit line and a drain contact via structure contacting the drain region, wherein the conductive layer comprises a plurality of drain select level conductive layers vertically between the word line and the bit line and laterally spaced apart by a drain select level dielectric isolation structure.

14. A method of forming a three-dimensional memory device, the method comprising:

forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or subsequently replaced by conductive layers;

forming a set of memory openings through the alternating stack;

forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel;

forming a source-level material layer by thinning the substrate, by removing the substrate, or by replacing the substrate with at least one layer of conductive material; and

forming a plurality of source layers by patterning the source-level material layer, wherein the plurality of source layers are laterally spaced apart and electrically isolated from each other, and wherein each group of memory opening fill structures contacts a respective one of the plurality of source layers.

15. The method of claim 14, wherein the substrate comprises a semiconductor material and the source-level material layer is formed by thinning the substrate.

16. The method of claim 14, further comprising forming a buried source line between the substrate and the alternating stack, and the source-level material layer comprises the buried source line exposed after the step of removing the substrate.

17. The method of claim 14, wherein the source-level material layer is formed by replacing the substrate with the at least one layer of conductive material.

18. The method of claim 14, the method further comprising:

forming a plurality of source-side trenches through the source-level material layer, wherein each adjacent pair of the plurality of source layers is laterally spaced apart from each other by a respective one of the plurality of source-side trenches; and

a plurality of source-level dielectric isolation structures are formed in the respective source-side trenches.

19. The method of claim 18, further comprising forming a pair of backside trench fill structures through the alternating stack, wherein:

a first subset of the source-side trenches extending vertically into the pair of the backside trench-fill structures; and is

A second subset of the source-side trenches extends into a proximal subset of the conductive layers and divides each conductive layer within the proximal subset of the conductive layers into a respective plurality of source-side select gate electrodes.

20. The method of claim 18, further comprising forming a source select level dielectric isolation structure by depositing dielectric material in the plurality of source-side trenches.

21. A three-dimensional memory device, the three-dimensional memory device comprising:

an alternating stack of insulating layers and conductive layers over at least one source layer and between a pair of backside trench-fill structures;

a set of memory opening fill structures located in the set of memory openings, wherein each of the memory opening fill structures comprises: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting the at least one source layer; and a respective drain region contacting a second end of the respective vertical semiconductor channel;

wherein the conductive layer comprises:

a plurality of source side select gate electrodes vertically between the at least one source layer and the word line and horizontally between the pair of backside trench-fill structures, wherein the plurality of source side select gate electrodes are laterally spaced apart by a source select level dielectric isolation structure.

22. The three-dimensional memory device of claim 21, wherein:

the vertical semiconductor channel comprises a doped semiconductor material having a first conductivity type; and is

The at least one source layer includes a layer of semiconductor material having a doping of a second conductivity type opposite the first conductivity type.

23. The three-dimensional memory device of claim 21, wherein the at least one source layer comprises a continuous source layer contacting each of the first ends of each of the vertical semiconductor channels.

24. The three-dimensional memory device of claim 23, wherein each of the source select level dielectric isolation structures comprises a first horizontal surface that contacts one of the insulating layers and a second horizontal surface that contacts the at least one source layer.

25. The three-dimensional memory device of claim 21, wherein:

the at least one source layer comprises a plurality of source layers laterally spaced apart from one another; and is provided with

Each group of memory opening fill structures of the group of memory opening fill structures contacts a respective one of the plurality of source layers and is electrically isolated from all other source layers of the plurality of source layers.

26. The three-dimensional memory device of claim 25, wherein the plurality of source layers are laterally spaced apart from each other by respective source-level dielectric isolation structures.

27. The three-dimensional memory device of claim 26, wherein each of the source-level dielectric isolation structures contacts a respective one of the source selection-level isolation structures.

28. The three-dimensional memory device of claim 27, wherein each of the source-level dielectric isolation structures has a sidewall vertically coincident with the respective one of the source select-level isolation structures.

29. The three-dimensional memory device of claim 27, wherein there is a horizontal step between each of the source-level dielectric isolation structures and a respective one of the source-select-level isolation structures.

30. The three-dimensional memory device of claim 25, further comprising a source level isolation dielectric layer that contacts a backside of each of the plurality of source layers and comprises a vertically downward protruding portion comprising the source level dielectric isolation structure.

31. The three-dimensional memory device of claim 21, wherein each of the pair of backside trench fill structures comprises a dielectric structure or a conductive local interconnect surrounded by an insulating spacer.

32. The three-dimensional memory device of claim 21, wherein each of the plurality of source side select gate electrodes laterally surrounds a respective group of memory opening fill structures and is laterally spaced apart from any other group of memory opening fill structures of the group of memory opening fill structures.

33. The three-dimensional memory device of claim 21, wherein the plurality of source layers comprises a plurality of polycrystalline semiconductor layers.

34. A method of forming a three-dimensional memory device, the method comprising:

forming a set of memory openings through the alternating stack;

forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures comprises a respective vertical stack of memory elements, a respective vertical semiconductor channel, and a respective drain region;

forming a source-level material layer by thinning the substrate or by replacing the substrate with at least one layer of conductive material, wherein each group of memory opening fill structures contacts a respective one of the plurality of source layers; and

forming a plurality of source side select gate electrodes by forming source side trenches through a first subset of the conductive layer before or after forming the source level material layer, wherein the source side trenches do not divide a second subset of the conductive layer.

35. The method of claim 34, wherein:

the substrate comprises a semiconductor material;

forming the source-level material layer by thinning the substrate; and is

The source-side trench is formed through the source-level material layer.

36. The method of claim 34, wherein the source-level material layer is formed by replacing the substrate with the at least one layer of conductive material.

37. The method of claim 36, wherein the source-side trench is formed through the first subset of the conductive layer after removing the substrate and before forming the at least one layer of conductive material.

38. The method of claim 36, wherein the source-side trench is formed after and through the at least one layer of conductive material is formed.

39. The method of claim 34, further comprising forming a pair of backside trench fill structures through the alternating stack prior to forming the source-level material layer and prior to forming the source-side trench.

40. The method of claim 34, further comprising forming trenches through the source-level material layer to separate the source-level material layer into a plurality of source layers.