CN114866808A - High-performance video processing system and method and electronic equipment - Google Patents
High-performance video processing system and method and electronic equipment Download PDFInfo
- Publication number
- CN114866808A CN114866808A CN202210654473.8A CN202210654473A CN114866808A CN 114866808 A CN114866808 A CN 114866808A CN 202210654473 A CN202210654473 A CN 202210654473A CN 114866808 A CN114866808 A CN 114866808A
- Authority
- CN
- China
- Prior art keywords
- video
- video processing
- video data
- processing
- final
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs
- H04N21/23424—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs involving splicing one content stream with another content stream, e.g. for inserting or substituting an advertisement
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234336—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by media transcoding, e.g. video is transformed into a slideshow of still pictures or audio is converted into text
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/44016—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving splicing one content stream with another content stream, e.g. for substituting a video clip
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
Abstract
The invention provides a high-performance video processing system, comprising: the video processing core module is used for receiving initial video data and distributing the initial video data to a plurality of video processing blade node modules; the video processing blade node modules are used for receiving the initial video data transmitted by the video processing core module, analyzing and processing the initial video data and feeding back final video data obtained after analysis and processing to the video processing core module; and the system management module is used for controlling the video processing core module and the video processing blade node modules to carry out video processing task scheduling distribution. The method distributes the videos to the video processing blade node modules for respective processing in an array multi-core processing design mode, can rapidly process under the condition of processing a large amount of video data, has the advantage of high-performance video processing, and greatly improves the speed and efficiency of video processing.
Description
Technical Field
The present invention relates to the field of video processing technologies, and in particular, to a high-performance video processing system, method, and electronic device.
Background
With the increase of large-screen display users in recent years, large-scale system integration displays are also increasing. The traditional video processing system is far from meeting the requirements of users; with the advent of this big data age, timely processing of large amounts of video image data has become an urgent need.
At present, the processing of video images is mainly based on single-core processing, and when the demand of processing a large amount of video data is met, the processing becomes laborious and difficult to meet the demand of rapid development, and particularly in the current video data era, the demand of rapid processing of videos is higher and higher for some fields with frequent video distribution, such as live webcasts, video distribution platforms and the like.
Therefore, the current video processing technical means is difficult to meet the current video fast processing requirement, and a high-performance video fast processing technical means is urgently needed.
Disclosure of Invention
In order to overcome the problem that the conventional video processing technical means is difficult to meet the conventional video fast processing requirement, the invention provides a high-performance video processing system, a high-performance video processing method and electronic equipment.
In order to solve the technical problems, the invention provides a technical scheme as follows: a high performance video processing system comprising:
the video processing core module is used for receiving initial video data and distributing the initial video data to a plurality of video processing blade node modules;
the video processing blade node modules are used for receiving the initial video data transmitted by the video processing core module, analyzing and processing the initial video data, and feeding back final video data obtained after analysis and processing to the video processing core module so as to output the final video data through the video processing core module; and
and the system management module is used for controlling the video processing core module and the plurality of video processing blade node modules to carry out scheduling and distribution on the video processing tasks.
Preferably, the video processing core module comprises a first network switching unit and a first FPGA video processing unit;
the first network switching unit is used for receiving the initial video data, distributing the initial video data to a plurality of video processing blade node modules, receiving the final video data fed back after the processing of the video processing blade node modules, and outputting the final video data;
the first FPGA video processing unit is used for receiving a plurality of final video data from a plurality of video processing blade node modules received by the first network switching unit, processing the final video data by one or a combination of segmentation, cutting, superposition, scaling and splicing, and outputting the processed final video data through the first network switching unit.
Preferably, the video processing core module further comprises a first ARM video processing unit and a network transceiver;
the first ARM video processing unit is used for receiving the final video data processed by the first FPGA video processing unit and carrying out video coding on the final video data;
the network transceiver is used for performing signal conversion on the final video data subjected to video coding by the first ARM video processing unit and outputting the converted final video data through the first network switching unit.
Preferably, the first FPGA video processing unit is further configured to serialize the final video data of the plurality of video processing blade node modules into a single video signal.
Preferably, a single video processing blade node module comprises a second network switching unit and a plurality of second ARM video processing units;
the second network switching unit is used for receiving the initial video data transmitted by the video processing core module, distributing the initial video data to a plurality of second ARM video processing units for processing, and receiving the final video data obtained after the processing of the second ARM video processing units and feeding the final video data back to the video processing core module;
the second ARM video processing units are used for receiving the initial video data and processing the initial video data through one or more combinations of video decoding, video analysis and video format conversion to obtain final video data.
Preferably, the single video processing blade node module further includes a second FPGA video processing unit, where the second FPGA video processing unit is configured to receive the final video data of the plurality of second ARM video processing units, perform processing including one or a combination of segmentation, clipping, superposition, scaling, and splicing on the final video data, and feed back the processed final video data to the video processing core module.
Preferably, the second FPGA video processing unit is further configured to serialize the final video data of the second ARM video processing units into a path of video signal, and output the path of video signal to the video processing core module.
The invention also provides a high-performance video processing method, which comprises the following steps:
receiving initial video data, and distributing the initial video data to a plurality of video processing blade node modules;
distributing the initial video data distributed to a single video processing blade node module to a plurality of second ARM video processing units contained in the corresponding video processing blade node module to perform processing including one or a combination of video decoding, video analysis and video format conversion;
and serializing and outputting the final video data processed by the second ARM video processing unit.
Preferably, before serializing and outputting the final video data processed by the second ARM video processing unit, the method further includes:
and sending the final video data processed by the second ARM video processing unit to a first FPGA video processing unit for processing including one or more of segmentation, cutting, superposition, scaling and splicing, and serializing and outputting the processed final video data.
The invention also provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program which is set to execute the high-performance video processing method when running; the processor is arranged to perform the high performance video processing method of the above by means of the computer program.
Compared with the prior art, the high-performance video processing system, the method and the electronic equipment provided by the invention have the following advantages:
1. by means of the design of the array multi-core processing unit, videos are distributed to the video processing blade node modules to be processed respectively, processing can be performed rapidly under the condition of processing a large amount of video data, the advantages of high-performance video processing are achieved, and the speed and the efficiency of video processing are greatly improved.
2. The mode that video data are firstly distributed to the video processing blade node modules to be processed respectively and then are further processed in a centralized mode through the video processing core module is adopted, the high efficiency of parallel processing of the video data is achieved, serialization processing is carried out on the processed video data, multiple paths of video data can be processed simultaneously in a serial mode, the video processing efficiency is greatly improved, and effective technical support can be provided for big data video processing.
Drawings
Fig. 1 is a block diagram of a high-performance video processing system according to a first embodiment of the present invention.
Fig. 2 is a block diagram of a first structure of a video processing core module according to a first embodiment of the present invention.
Fig. 3 is a second structural block diagram of a video processing core module according to the first embodiment of the present invention.
Fig. 4 is a first structural block diagram of a video processing blade node module according to a first embodiment of the present invention.
Fig. 5 is a block diagram of a second structure of a video processing blade node module according to the first embodiment of the present invention.
Fig. 6 is a block diagram of an overall structure of a high-performance video processing system according to a first embodiment of the present invention.
Fig. 7 is a flowchart of a high-performance video processing method according to a second embodiment of the present invention.
Fig. 8 is a block diagram of an electronic device according to a third embodiment of the invention.
Description of reference numerals:
1. a video processing core module; 11. a first network switching unit; 12. a first FPGA video processing unit; 13. a first ARM video processing unit; 14. a network transceiver; 2. a video processing blade node module; 21. a second network switching unit; 22. a second ARM video processing unit; 23. a second FPGA video processing unit; 3. a system management module; 10. a memory; 20. a processor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
To solve the above technical problem, as shown in fig. 1, a first embodiment of the present invention provides a technical solution as follows: a high performance video processing system comprising:
the video processing core module 1 is used for receiving initial video data and distributing the initial video data to a plurality of video processing blade node modules;
the video processing blade node modules 2 are configured to receive the initial video data transmitted by the video processing core module 1, analyze the initial video data, and feed back final video data obtained after the analysis to the video processing core module 1, so as to output the final video data through the video processing core module 1; and
and the system management module 3 is used for controlling the video processing core module 1 and the video processing blade node modules 2 to perform video processing task scheduling and distribution.
It can be understood that, in the embodiment, the system management module 3 may be implemented by using a high-performance ARM processor when being specifically integrated, an embedded operating system is run on the system management module, an ethernet interface is provided for the outside, and a scheduling management function of a hardware system can be implemented by matching with control management platform software of a user. The video processing core module 1, the video processing blade node module 2 and other business unit modules in the whole video processing system are controlled by the system management module 3, real-time command transmission is carried out through an Ethernet communication interface, and a special control management channel (UART/SPI and the like) is used for realizing basic functions of business control, system configuration management, software upgrading, log alarm and the like, and meanwhile, video signals can be previewed. Specific and further functions may also be devised by a person skilled in the art according to practical needs, in combination with the prior art, and will not be further described herein.
It is understood that the processing of the video in this embodiment includes segmentation, cropping, overlaying, scaling, and splicing. Besides decoding and format conversion, those skilled in the art can perform setting and add other processing operations according to the actual video processing requirements, which are not further described herein.
In addition, it is understood that a person skilled in the art may add some common modules according to actual needs, such as a power module, a heat dissipation module, a backplane module, etc., which belong to conventional technical means and are not further described herein.
It can be understood that, in this embodiment, connection and communication between modules and the outside world can be performed through ethernet interfaces, where the ethernet interfaces include physical forms such as gigabit network interfaces and gigabit network interfaces, and further details are not further developed here.
Further, referring to fig. 2, in the present embodiment, the video processing core module 1 includes a first network switching unit 11 and a first FPGA video processing unit 12;
the first network switching unit 11 is configured to receive the initial video data, distribute the initial video data to a plurality of video processing blade node modules 2, receive the final video data fed back after being processed by the video processing blade node modules 2, and output the final video data;
the first FPGA video processing unit 12 is configured to receive a plurality of final video data from a plurality of video processing blade node modules 2 received by the first network switching unit 11, perform processing including one or a combination of segmentation, clipping, superposition, scaling, and splicing on the final video data, and output the processed final video data through the first network switching unit 11.
It can be understood that the first network switching unit 11 in this embodiment may be a high-performance network switch, and when data transfer switching is performed, data transfer switching may be performed in a two-layer non-blocking switching manner, and specific details are not limited, which is only an example of the preferred embodiment, and a person skilled in the art may also design according to actual needs.
Further, referring to fig. 3, in this embodiment, the video processing core module 1 further includes a first ARM video processing unit 13 and a network transceiver 14;
the first ARM video processing unit 13 is configured to receive the final video data processed by the first FPGA video processing unit 12, and perform video coding on the final video data;
the network transceiver 14 is configured to perform signal conversion on the final video data subjected to video coding by the first ARM video processing unit 13, and output the converted final video data through the first network switching unit 11.
It is understood that video coding includes H.264/H.265/MPGE, etc. standards, which are not limited and are not described herein.
Further, the first FPGA video processing unit 12 is further configured to serialize the final video data of the plurality of video processing blade node modules 2 into a path of video signal.
In addition, it can be understood that, in this embodiment, the first FPGA video processing unit 12 may also directly display the final video data locally for display and output, and those skilled in the art may design the video data according to actual needs.
Further, referring to fig. 4, in the present embodiment, a single video processing blade node module 2 includes a second network switching unit 21 and a plurality of second ARM video processing units 22;
the second network switching unit 21 is configured to receive the initial video data sent by the video processing core module 1, distribute the initial video data to a plurality of second ARM video processing units 22 for processing, and receive the final video data obtained after processing by the second ARM video processing units 22 and feed back the final video data to the video processing core module 1;
the second ARM video processing units 22 are configured to receive the initial video data, and perform processing including one or more combinations of video decoding, video analysis, and video format conversion on the initial video data to obtain the final video data.
It is understood that the second ARM video processing unit 22 in the present embodiment can be implemented by ARM video codec processor hardware modules, and the processor can be selected (including not only) from high-pass 865 processor, haisi Hi3559A processor, and other prior art processors, which are not further described herein.
Further, as shown in fig. 5, in this embodiment, a single video processing blade node module 2 further includes a second FPGA video processing unit 23, where the second FPGA video processing unit 23 is configured to receive the final video data of the plurality of second ARM video processing units 22, perform processing including one or more combinations of segmentation, cropping, superposition, scaling, and splicing on the final video data, and feed back the processed final video data to the video processing core module 1.
Further, the second FPGA video processing unit 23 is further configured to serialize the final video data of the second ARM video processing units 22 into a video signal, and output the video signal to the video processing core module 1.
It will be appreciated that in the preferred embodiment, after video data is distributed to a plurality of (for example, M) video processing blade node modules 2 for respective processing, the video data is distributed to a plurality of (for example, N) second ARM video processing units 22 for processing in a single video processing blade node module 2, and all the final video data finally returned to the first FPGA video processing unit 12 is equivalent to contain MxN video data, and the advantages of video data processing distribution and parallel re-serialization processing are highlighted.
Finally, as shown in fig. 6, which is a block diagram of an overall structure of a high-performance video processing system in a preferred embodiment provided in this embodiment, a person skilled in the art can understand the above description for each unit module in the figure, and the description is not repeated here.
Meanwhile, based on fig. 6, the high-performance video processing system in the embodiment can be divided into two following example situations when applied:
the first is the situation that only intelligent analysis, decoding or format conversion is performed on the initial video data, the flow of the initial video data mainly passes through the first network switching unit 11 to the second network switching unit 21, and is distributed to the second ARM video processing units 22 for intelligent analysis, decoding or format conversion processing, and the final video data obtained after processing is fed back to the first network switching unit 11 for output, so that the video processing flow can be completed.
The second is the situation that the initial video data is subjected to intelligent analysis, decoding or format conversion, and also subjected to video segmentation, cutting, scaling, splicing and other processing, the flow of the initial video data mainly passes through the first network switching unit 11 to the second network switching unit 21, is distributed to the second ARM video processing units 22 to be subjected to intelligent analysis, decoding or format conversion, then enters the second FPGA video processing unit 23 to be subjected to one or more combination processing of segmentation, cutting, overlapping, scaling and splicing, and a plurality of processed final video data uniformly enter the first FPGA video processing unit 12 to be subjected to one or more combination processing of segmentation, cutting, overlapping, scaling and splicing, and then are output.
A second embodiment of the present invention further provides a high-performance video processing method, please refer to fig. 7, which includes the following steps:
step S1: receiving initial video data, and distributing the initial video data to a plurality of video processing blade node modules;
step S2: distributing the initial video data distributed to a single video processing blade node module to a plurality of second ARM video processing units contained in the corresponding video processing blade node module to perform processing including one or a combination of video decoding, video analysis and video format conversion;
step S3: and serializing and outputting the final video data processed by the second ARM video processing unit 22.
It is to be understood that the video processing blade node module 2, the second ARM video processing unit 22, and the like described in the present embodiment can be understood by referring to the description in the foregoing embodiments, and the detailed functions and actions of the similar functional units are not repeated here.
Further, before serializing and outputting the final video data processed by the second ARM video processing unit 22, the method further includes:
and sending the final video data processed by the second ARM video processing unit 22 to the first FPGA video processing unit 12 for processing including one or more of segmentation, clipping, superposition, scaling and splicing, and serializing and outputting the processed final video data.
It can be understood that the method provided in this embodiment may be designed correspondingly with reference to the system data processing flow in the foregoing embodiment, and the description is not repeated here, and the flow between the video data may be completed according to the system in the foregoing embodiment.
In a third embodiment of the present invention, an electronic device is further provided, please refer to fig. 8, which includes a memory and a processor, wherein the memory stores a computer program, and the computer program is configured to execute the high performance video processing method in the second embodiment when running; the processor is arranged to execute the high performance video processing method in the second embodiment described above by means of the computer program.
Compared with the prior art, the high-performance video processing system, the method and the electronic equipment provided by the invention have the following advantages:
1. by means of the design of the array multi-core processing unit, videos are distributed to the video processing blade node modules to be processed respectively, processing can be performed rapidly under the condition of processing a large amount of video data, the advantages of high-performance video processing are achieved, and the speed and the efficiency of video processing are greatly improved.
2. The mode that video data are firstly distributed to the video processing blade node modules to be processed respectively and then are further processed in a centralized mode through the video processing core module is adopted, the high efficiency of parallel processing of the video data is achieved, serialization processing is carried out on the processed video data, multiple paths of video data can be processed simultaneously in a serial mode, the video processing efficiency is greatly improved, and effective technical support can be provided for big data video processing.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart.
Which when executed by a processor performs the above-described functions defined in the method of the present application. It should be noted that the computer memory described herein can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer memory may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof.
More specific examples of computer memory may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present application, a computer readable signal medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In this application, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present application may be implemented by software or hardware. The described units may also be provided in a processor, and may be described as: a processor comprises a video processing core module, a number of said video processing blade node modules 2 and a system management module 3. For example, the video processing blade node module 2 may also be described as a "module for receiving the initial video data transmitted by the video processing core module, performing analysis processing on the initial video data, and feeding back final video data obtained after the analysis processing to the video processing core module".
As another aspect, the present application also provides a computer memory, which may be included in the apparatus described in the above embodiments; or may be present separately and not assembled into the device. The computer memory carries one or more programs that, when executed by the apparatus, cause the apparatus to: receiving initial video data and distributing the initial video data to a plurality of video processing blade node modules 2; distributing the initial video data distributed to a single video processing blade node module 2 to a plurality of second ARM video processing units 22 corresponding to the video processing blade node module 2 to perform processing including one or a combination of video decoding, video analysis and video format conversion; and serializing and outputting the final video data processed by the second ARM video processing unit 22.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent alterations and improvements made within the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A high performance video processing system, comprising:
the video processing core module is used for receiving initial video data and distributing the initial video data to a plurality of video processing blade node modules;
the video processing blade node modules are used for receiving the initial video data transmitted by the video processing core module, analyzing and processing the initial video data, and feeding back final video data obtained after analysis and processing to the video processing core module so as to output the final video data through the video processing core module; and
and the system management module is used for controlling the video processing core module and the video processing blade node modules to carry out video processing task scheduling distribution.
2. The high performance video processing system of claim 1, wherein the video processing core module comprises a first network switching unit and a first FPGA video processing unit;
the first network switching unit is used for receiving the initial video data, distributing the initial video data to a plurality of video processing blade node modules, receiving the final video data fed back after being processed by the video processing blade node modules, and outputting the final video data;
the first FPGA video processing unit is used for receiving a plurality of final video data from a plurality of video processing blade node modules received by the first network switching unit, processing the final video data by one or a combination of segmentation, cutting, superposition, scaling and splicing, and outputting the processed final video data through the first network switching unit.
3. The high performance video processing system of claim 2 wherein the video processing core module further comprises a first ARM video processing unit and a network transceiver;
the first ARM video processing unit is used for receiving the final video data processed by the first FPGA video processing unit and carrying out video coding on the final video data;
the network transceiver is used for performing signal conversion on the final video data subjected to video coding by the first ARM video processing unit and outputting the converted final video data through the first network switching unit.
4. The high performance video processing system of claim 2 wherein said first FPGA video processing unit is further configured to serialize said final video data of said plurality of video processing blade node modules into a single video signal.
5. The high performance video processing system of claim 1 wherein a single one of said video processing blade node modules comprises a second network switching unit and a plurality of second ARM video processing units;
the second network switching unit is used for receiving the initial video data transmitted by the video processing core module, distributing the initial video data to a plurality of second ARM video processing units for processing, and receiving the final video data obtained after the processing of the second ARM video processing units and feeding the final video data back to the video processing core module;
the second ARM video processing units are used for receiving the initial video data and processing the initial video data through one or more combinations of video decoding, video analysis and video format conversion to obtain final video data.
6. The high performance video processing system of claim 5, wherein a single video processing blade node module further comprises a second FPGA video processing unit, said second FPGA video processing unit is configured to receive said final video data from a plurality of said second ARM video processing units, perform processing on said final video data including one or more of segmentation, cropping, overlaying, scaling, and splicing, and feed back said processed final video data to said video processing core module.
7. The high performance video processing system of claim 6, wherein the second FPGA video processing unit is further configured to serialize the final video data of the second ARM video processing units into a video signal, and output the video signal to the video processing core module.
8. A high performance video processing method, comprising the steps of:
receiving initial video data, and distributing the initial video data to a plurality of video processing blade node modules;
distributing the initial video data distributed to a single video processing blade node module to a plurality of second ARM video processing units contained in the corresponding video processing blade node module to perform processing including one or a combination of video decoding, video analysis and video format conversion;
and serializing and outputting the final video data processed by the second ARM video processing unit.
9. The method of high performance video processing as set forth in claim 8 wherein before serializing the final video data processed by said second ARM video processing unit, further comprising:
and sending the final video data processed by the second ARM video processing unit to a first FPGA video processing unit for processing including one or more of segmentation, cutting, superposition, scaling and splicing, and serializing and outputting the processed final video data.
10. An electronic device comprising a memory and a processor, characterized in that: the memory having stored therein a computer program arranged to perform, when running, the high performance video processing method of any of claims 8 to 9;
the processor is arranged to execute the high performance video processing method of any of the claims 8 to 9 by means of the computer program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210654473.8A CN114866808A (en) | 2022-06-10 | 2022-06-10 | High-performance video processing system and method and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210654473.8A CN114866808A (en) | 2022-06-10 | 2022-06-10 | High-performance video processing system and method and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114866808A true CN114866808A (en) | 2022-08-05 |
Family
ID=82623935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210654473.8A Pending CN114866808A (en) | 2022-06-10 | 2022-06-10 | High-performance video processing system and method and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114866808A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104780294A (en) * | 2015-04-21 | 2015-07-15 | 东方网力科技股份有限公司 | FPGA Soc parallel processing-based distributed large-data volume video processing system and method |
| US9204103B1 (en) * | 2011-12-30 | 2015-12-01 | Emc Corporation | Technique for parallel, distributed video processing |
| CN109951737A (en) * | 2019-02-26 | 2019-06-28 | 北京字节跳动网络技术有限公司 | Method for processing video frequency, device, electronic equipment and computer readable storage medium |
| CN111010541A (en) * | 2019-12-11 | 2020-04-14 | 重庆山淞信息技术有限公司 | Video processing module based on FPGA and compression processor |
| CN111163335A (en) * | 2019-12-31 | 2020-05-15 | 深圳市瑞讯云技术有限公司 | Video processing method and device for distributed server |
| CN113691812A (en) * | 2021-10-25 | 2021-11-23 | 广州朗国电子科技股份有限公司 | Hongmon system-based distributed video processing method, terminal and readable medium |
-
2022
- 2022-06-10 CN CN202210654473.8A patent/CN114866808A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9204103B1 (en) * | 2011-12-30 | 2015-12-01 | Emc Corporation | Technique for parallel, distributed video processing |
| CN104780294A (en) * | 2015-04-21 | 2015-07-15 | 东方网力科技股份有限公司 | FPGA Soc parallel processing-based distributed large-data volume video processing system and method |
| CN109951737A (en) * | 2019-02-26 | 2019-06-28 | 北京字节跳动网络技术有限公司 | Method for processing video frequency, device, electronic equipment and computer readable storage medium |
| CN111010541A (en) * | 2019-12-11 | 2020-04-14 | 重庆山淞信息技术有限公司 | Video processing module based on FPGA and compression processor |
| CN111163335A (en) * | 2019-12-31 | 2020-05-15 | 深圳市瑞讯云技术有限公司 | Video processing method and device for distributed server |
| CN113691812A (en) * | 2021-10-25 | 2021-11-23 | 广州朗国电子科技股份有限公司 | Hongmon system-based distributed video processing method, terminal and readable medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2019102064A (en) | Method and apparatus for processing task in smart device | |
| CN110769278A (en) | Distributed video transcoding method and system | |
| CN109145023A (en) | Method and apparatus for handling data | |
| CN114205230B (en) | Configuration method, system, medium and electronic equipment of cloud primary network element | |
| EP3934253A1 (en) | Method and apparatus for transcoding video, device, and medium | |
| CN111327692A (en) | Model training method and device and cluster system | |
| CN114866808A (en) | High-performance video processing system and method and electronic equipment | |
| CN111083408A (en) | Method, system and equipment for processing video storage service | |
| CN114301980A (en) | Method, device and system for scheduling container cluster and computer readable medium | |
| CN113792869A (en) | Video processing method and device based on neural network chip and electronic equipment | |
| CN111835558A (en) | Edge cloud platform multi-resource visual control method | |
| CN115988087B (en) | Service calling method and device based on bus, electronic equipment and storage medium | |
| CN116974654B (en) | Image data processing method and device, electronic equipment and storage medium | |
| CN215729726U (en) | 5G edge computing platform architecture | |
| CN112346700B (en) | Audio transmission method, device and computer readable storage medium | |
| CN111008074B (en) | File processing method, device, equipment and medium | |
| CN115378937B (en) | Distributed concurrency method, device, equipment and readable storage medium for tasks | |
| CN112671877B (en) | Data processing method and device | |
| US11902346B2 (en) | Method and apparatus for processing streaming media service, electronic device, and storage medium | |
| CN113132480B (en) | Data transmission method, device and system | |
| CN115543588A (en) | Electromagnetic perception task execution method, system and terminal based on script arrangement | |
| CN107291954B (en) | OC L parallel query method based on MapReduce | |
| CN117762590A (en) | Execution method, system and device of computing task and related equipment | |
| CN113923220A (en) | Computing system for realizing edge computing, data exchange and sharing and realizing method | |
| CN117407464A (en) | Cross-cluster database capacity expansion method and device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |