CN114866217A - Anti-power-consumption-attack SM4 encryption circuit based on digital true random number generator - Google Patents
Anti-power-consumption-attack SM4 encryption circuit based on digital true random number generator Download PDFInfo
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Abstract
The invention discloses a power consumption attack resistant SM4 encryption circuit based on a digital true random number generator, wherein a true random number generator module is added in an SM4 encryption circuit, and implantation of random variables is completed through a programming state machine, so that the power consumption track of the circuit is disturbed, and the purpose of resisting differential power consumption attack is achieved. The true random number generator is composed of an entropy source module based on clock jitter and circuit metastable state, a sampling module based on a D trigger and a post-processing module based on exclusive OR operation, and is realized by a pure digital circuit and convenient to transplant. The invention can realize the normal SM4 encryption function and has the capability of resisting differential power consumption attack.
Description
Technical Field
The invention relates to an SM4 encryption circuit, in particular to a power consumption attack resisting SM4 encryption circuit based on a digital true random number generator.
Background
The SM4 is a kind of block symmetric cryptographic algorithm, is independently developed and implemented by our country, is mainly used for authentication of wireless local area networks and other privacy basic devices, and can effectively guarantee confidentiality of data. Currently, the SM4 cryptographic algorithm can be implemented in both software and hardware. Compared with hardware implementation, the technology for implementing SM4 software is mature, but with the continuous improvement of the requirements of the industry and academia on encryption and decryption performance, most enterprises at home and abroad adopt FPGA-based hardware systems to implement the SM4 cryptographic algorithm, and the realization of the SM4 cryptographic algorithm by hardware has become a trend.
The risk of leakage is faced when the cryptographic algorithm is used for information encryption transmission. The bypass attack is a method for acquiring the secret information of the device by analyzing the bypass information generated by the cryptosystem during operation, and is classified into time attack, power consumption attack, electromagnetic radiation attack, fault attack and the like according to the type of the analyzed information. Among the many side-channel attacks, the power attack is the easiest to implement and most threatening, and is one of the most common attack means in cryptographic circuits, and the impact on the security of the cryptographic circuits is not insignificant.
At present, aiming at the difference of power consumption attack protection levels, the existing defense measures can be roughly divided into algorithm level protection and circuit level protection. The essence of algorithm level protection is a power consumption randomization strategy, which mainly comprises a random mask technology, a clock randomization technology, an instruction execution randomization technology and the like, and the basic principle is to destroy the correlation between power consumption information and a secret key and plaintext through randomization operation. And whatever randomization technique is adopted, the randomization needs to be completed by relying on a random number generator. The random number generator is used as a core component in the encryption circuit, the unpredictability generated by the random number generator plays a crucial role in guaranteeing the information security, and the quality of the random number determines the security degree of the encryption circuit.
Random number generators are generally classified into two types, namely true random number generators and pseudo random number generators. The random source (entropy source) of a true random number generator is generated by some special physical phenomena or circuit structure, such as metastable state, electromagnetic radiation, thermal noise, etc. The random sequences generated by them are truly unpredictable, with no regularity to follow, and such sequences are therefore referred to as true random numbers. Pseudo-random number generators generally use mathematical calculations or program settings to generate pseudo-random sequences, which are not truly random numbers, but rather have long periods and are still regularly repeatable. If the pseudo random number is applied to the field of data encryption, certain cracking risk exists, and the true random number cannot occur, so that the safety of an encryption circuit can be effectively ensured. At present, most of random numbers adopted in a cipher circuit are pseudo-random sequences generated by a pseudo-random number generator, and the randomness is not high, so that the circuit safety is low.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a digital true random number generator-based SM4 encryption circuit capable of enhancing the security of a cryptographic circuit and resisting power consumption attack.
The technical scheme is as follows: the invention discloses an SM4 encryption circuit for resisting power consumption attack, which comprises: the device comprises a digital true random number generator, a round transformation module, a key expansion module, a round counting module, an input/output selection module and a state control center module;
the digital true random number generator is connected with the state control center module and the input/output selection module and is used for generating random variables; the random variable is used as a control signal and input to the state control center module, and once the state control center module detects that the random variable is a specific value, the randomization operation is executed; the random variable is used as a control signal to be input into the input and output selection module, and the input and output selection module is controlled to randomly select the plaintext and the secret key to be output;
the round conversion module is connected with the state control center module, the input/output selection module, the key expansion module and the round counting module and is used for carrying out round conversion; the round conversion has 32 rounds, and each round generates a 128-bit intermediate value which is used as input data of the next round conversion; 4-bit 32-bit data output in the last round is subjected to reverse order transformation operation to obtain a ciphertext;
the key expansion module is connected with the state control center module, the input/output selection module, the round conversion module and the round counting module and used for performing key expansion, and the key expansion module generates 32 round keys for the round conversion through 32 rounds of expansion operation;
the round counting module counts the number of rounds of the key expansion and the round transformation, and ensures that 32 rounds of iterations of the key expansion and the round transformation are carried out;
the state control center module controls the running states of the digital true random number generator, the round transformation module, the key expansion module, the round counting module and the input/output selection module;
the input and output selection module completes input selection of each round of the key expansion module and the round transformation module according to control signals received from the state control center module and the digital true random number generator and counting signals k _ counter and r _ counter sent by the round counting module;
the plaintext and the secret key are both 128 bits.
Further, the digital true random number generator comprises an entropy source module based on circuit metastable state and clock jitter, a sampling module based on a D trigger and a post-processing module based on exclusive-or operation;
the input of the digital true random number generator is 4 clock signals, and the output is a 4-bit random sequence; the circuit metastable state-based entropy source consists of two exclusive-OR gates, 2-bit data is input, and 1-bit data is output to finish sampling through 3D triggers; the entropy source module based on clock jitter is composed of a 3-level ring oscillator, the input is also 2 bits, and the output 1-bit data is sampled through 1D trigger; and respectively connecting the two output 1-bit data with the input ends of two 4-bit shift registers, and performing XOR operation to obtain a 4-bit random sequence.
Further, the input of the round transformation module is 128-bit data, the output is 32-bit data, and the operation unit is a 32-bit word, and the round transformation module comprises a round key adding unit, a byte replacing unit, a linear left shifting unit and an exclusive or operation unit;
the input of each round of conversion is 128-bit data, which is divided into 4 32-bit words on average, and the lower 3 32-bit words and the round key are connected with the input end of the round key adding unit; the output end of the round key adding unit is connected with the input end of the byte replacing unit; the byte replacement unit consists of 4S boxes with 8-bit input and 8-bit output, and the output end of the byte replacement unit is connected with the input end of the linear left shift unit; the output end of the linear left shift is connected with the input end of the high 32-bit word and XOR operation unit of each round of conversion; the output end of the exclusive-or operation unit outputs a 32-bit intermediate value, and the intermediate value is cascaded with the lower 96-bit data of the previous round to form a 128-bit intermediate value of the next round of conversion.
Further, the key expansion module has 128 bits of input and 32 bits of output, and comprises seven exclusive ors XOR1, XOR2, XOR3, XOR4, XOR5, XOR6, XOR7, a byte replacement unit and a linear left shift unit;
the middle value of each round of key expansion is 128 bits, the key expansion is divided into 4 32-bit words on average, and 4 32-bit system parameters are respectively connected to the input ends of four XOR devices of XOR1, XOR2, XOR3 and XOR 4; wherein, the output ends of the XOR2, the XOR3 and the XOR4 are connected with the input end of the XOR 5; the output of XOR5 is connected with a 32-bit fixed parameter to the input of XOR 6; an output terminal of XOR6 is connected to an input terminal of the byte replacement unit; the output end of the byte replacement unit is connected with the input end of the linear left shift unit; the output end of the linear left shift unit is connected with the input end of the XOR 7; the output of the exclusive or XOR7 is a 32-bit round key.
Furthermore, the input of the round counting module is a 1-bit round counting enable signal, the output is two counting values of 6 bits, the counting values respectively represent the round numbers corresponding to the round conversion and the key expansion, and the round counting module is composed of two registers, two selectors and two adders.
Further, the input of the input/output selection module is 4 1-bit state signals, 2 6-bit data and 4 128-bit data, which respectively indicate encryption enable, round conversion end, key expansion end, encryption completion, key expansion round number, round conversion count, initial input key, key intermediate value of each round, initial input plaintext and round conversion intermediate value of each round, and output is 2 round conversion intermediate value data of 128 bits and 1-bit encryption end flag signal.
Further, the input of the state control center module is 1-bit encryption enabling signal and 1-bit self-defined signal representing random state, and the output is 5 1-bit signals respectively representing 5 states of key expansion enabling, key expansion proceeding, round conversion enabling, round conversion proceeding and round conversion finishing;
the state control center module is internally provided with 7 states which are respectively initial states S 0 A key expansion enabling state K _ en, a key expansion performing state K _ ing, a round transformation enabling state R _ en, a round transformation performing state R _ ing, a round transformation ending state R _ end and a random state rand;
the circuit defaults to the initial state S 0 After receiving the 1-bit encryption enabling signal, the state control center module raises the round key expansion enabling signal and then transfers to a key expansion state; after the key expansion is finished, the next state is transferred, and the round transformation enabling signal is pulled up; at the moment, inserting a random state rand, controlling by a random signal R _ R, if the random signal at the moment is detected to be a specific value, carrying out random round transformation operation by the circuit, otherwise, normally operating the circuit;
finishing a small round of encryption in the round of conversion state, entering a round of conversion ending state R _ end, and storing a round key and an intermediate value; and repeating the cycle for 32 times to finish the encryption of a group of plaintext data.
Compared with the prior art, the invention has the following remarkable effects:
1. the random variable is generated by the random number generator module and is used as a selection signal of the state machine, the correlation between the key and the power consumption is damaged so as to change the specific operation of the cryptographic circuit at a specific moment and obscure the power consumption information at an intermediate value moment, so that differential power consumption attack is resisted, and the safety of the circuit is enhanced;
2. the invention adopts the digital true random number generator to generate the random state, and compared with the traditional defense measure against power consumption attack, the invention can reduce the hardware resource expenditure of the circuit while ensuring the safety of the encryption circuit.
Drawings
FIG. 1 is a general block diagram of the present invention;
fig. 2 is a SM4 encryption flow diagram;
FIG. 3 is a diagram of an SM4 encryption round transformation circuit;
FIG. 4 is an overall structure view of the wheel changing S-box;
FIG. 5 is a block diagram of a wheel shift linear shift circuit;
fig. 6 is a diagram of an SM4 encryption key expansion circuit;
FIG. 7 is a diagram of a key expansion linear shift circuit;
fig. 8 is a flow diagram of SM4 encryption based on random state;
FIG. 9 is a circuit diagram of the digital true random number generator according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
SM4 is a 32-round iterative block cipher algorithm, each round of encryption is composed of two major parts, key expansion and round transformation function, wherein the round transformation includes nonlinear S-box byte substitution, exclusive-or operation and linear shift operation. The plaintext length and the key length of the algorithm are both 128 bits, and the unit of data processing is usually 8-bit bytes and 32-bit words. The encryption and decryption algorithms of SM4 are identical in structure, except that the key order used for decryption and the encryption are reversed.
The power consumption attack is realized based on the correlation between the power consumption generated by the cryptographic chip in the running process and the secret key and the plaintext. An attacker can deduce a correct key through a large number of power consumption curve samples and mathematical statistical analysis. The differential power attack DPA is a mainstream power attack method at present, has strong aggressivity and low implementation cost, and mainly comprises two steps: power consumption data acquisition and power consumption data analysis. The power consumption data acquisition means that an attacker acquires and records power consumption information in real time in a hardware or software mode when a cryptographic algorithm runs. The power consumption data analysis means that the collected power consumption data are subjected to statistical analysis, and a correct key is deduced according to effective information in the power consumption data. The DPA attack method based on the mean difference method is specifically divided into the following 4 steps:
(1) collecting actual power consumption curves
Firstly, M random plaintexts are selected and input into a cipher chip, and the generated power consumption curve sampling point data is recorded as P ═ P (P) 1 ,p 2 ,...,p M ) Wherein P is i (i 1, …, M) represents the i-th plaintext data to be encrypted, and the plaintext data P is obtained i The corresponding power consumption sampling data is recorded as S i ＝(S i1 ,S i2 ,...,S iN ) N represents the number of sampling points of the power consumption curve of each plaintext data, also called the sampling length S ij (i-1, …, M, j-1, …, N) represents plaintext P i The power consumption value at sample point j. Thus, a group of M plaintext power consumption curve sample data is obtained, and is marked as S ═ S (S) 1 ,S 2 ,...,S M )。
(2) Attack location selection
When a power consumption attack is performed, an attack position is usually required to be selected, the position represents data which is a function of plaintext p and a secret key k, and d is f (p, k) and is called an intermediate value, and therefore the attack position is selected and also called an intermediate value. The selection of the intermediate value is crucial and influences the difficulty of key breaking. Before the selected position is over, the power consumption data collected at the moment are not obviously different, the key cannot be speculated, and after the selected position is over, the theoretical intermediate value is difficult to calculate, so that the difficulty of key cracking is increased.
(3) Calculating theoretical mean value
Guessing the key information according to the key digit a corresponding to the intermediate value, and recording the guessed key as K (K) 1 ,k 2 ,...,k A ) Where a is related to the number of bits a of the guess key. A is 2 a I.e. for a-bit guessed keys, there are 2 a The key is guessed. Calculating a theoretical intermediate value d according to a correlation function of the secret key k and the plaintext p ih ＝f(p i ,k h ) (i ═ 1, …, M; h is 1, …, A) to giveAn M x N matrix of intermediate values. Each column of the matrix represents the same key k h The intermediate value calculated for different plaintext p, the guess key corresponding to the intermediate value in the column that is the same as the actual key is denoted as k guess 。
(4) Constructing a differential power consumption curve
The purpose of calculating the theoretical intermediate value is to establish a distinguishing function, on the basis, the collected power consumption curves are screened and grouped, and then differential calculation is carried out. First, a distinguishing function associated with the intermediate value is selected, denoted as F (·), and the highest bit of the intermediate value is generally selected as the distinguishing function. According to the high and low level information of the position, the collected power consumption curves are respectively classified as S 0 And S 1 And can be expressed by the following formula:
suppose S 0 Comprising u power consumption curves, S 1 Containing v power consumption curves, then u + v equals M, i.e. 1 guess key k h Corresponding to a total of M power consumption curves. After dividing the power consumption curves into two groups, respectively carrying out arithmetic summation and averaging calculation on the power consumption curves to obtain the mean value of the power consumption curves
And
is formulated as:
subtracting the two groups of mean power consumption curves to obtain a sum key k h The corresponding differential power consumption curve q is expressed by the formula:
repeating the above operation a times to obtain a differential power consumption curves corresponding to a guessed keys, and recording as Q ═ Q 1 ,q 2 ,...,q A ). At the moment of generating the intermediate value, carrying out statistical analysis on the A differential power consumption curves, and guessing a key k corresponding to the power consumption curve with the highest peak guess I.e. the correct key.
According to the principle of differential power consumption attack, the DPA attack can be resisted as long as the power consumption track of the encryption circuit at the intermediate value moment is hidden or changed.
In order to guarantee the safety of the SM4 cryptographic circuit, the invention provides a power consumption attack resistant SM4 cryptographic circuit based on a digital true random number generator. A digital true random number generator module is added in the circuit, and a state machine is rewritten to complete implantation of a random state, so that a power consumption track is disturbed, and the purpose of resisting differential power consumption attack is achieved.
Encryption circuit structure
As shown in fig. 1, in the SM4 encryption circuit for resisting power consumption attack of the present invention, the input plaintext and key are 128 bits, and the circuit includes: the device comprises a digital true random number generator, a round transformation module, a key expansion module, a round counting module, an input/output selection module and a state control center module.
The digital true random number generator can generate a random number in a true sense, and the random number can control the input/output selection module and randomly select the input plaintext and the key of the round transformation; the wheel transformation module has 32 wheels, and each wheel generates a 128-bit intermediate value as input data of next wheel transformation; 4-bit 32-bit data output in the last round is subjected to reverse order conversion operation to obtain a ciphertext; the key expansion module generates 32 round keys for round transformation through 32 round expansion operations; the round counting module has the function of counting the number of rounds of key expansion and round conversion and ensuring 32 rounds of iteration of key expansion and round conversion; the state control center module controls the running state of the whole SM4 encryption circuit; and the input and output selection module completes the input and output selection of each round of transformation and key expansion.
The input and output of the digital true random number generator are all 4-bit data, and the digital true random number generator comprises an entropy source module based on circuit metastable state and clock jitter, a sampling module based on a D trigger and a post-processing module based on exclusive OR operation;
the input of the digital true random number generator is 4 clock signals, and the output is a 4-bit random sequence; the circuit metastable state-based entropy source consists of two exclusive-OR gates, 2-bit data is input, and 1-bit data is output to finish sampling through 3D triggers; the entropy source module based on clock jitter is composed of a 3-level ring oscillator, the input is also 2 bits, and the output 1-bit data is sampled through 1D trigger; and respectively connecting the two output 1-bit data with the input ends of two 4-bit shift registers, and performing XOR operation to obtain a 4-bit random sequence.
The wheel transformation module of the invention inputs 128-bit data and outputs 32-bit data, and the operation unit is 32-bit word, comprising a wheel key adding unit, a byte replacing unit, a linear left shifting unit and an exclusive OR operation unit;
the input of each round of conversion is 128-bit data, which is divided into 4 32-bit words on average, and the lower 3 32-bit words and the round key are connected with the input end of the round key adding unit; the output end of the round key adding unit is connected with the input end of the byte replacing unit; the byte replacement unit consists of 4S boxes with 8-bit input and 8-bit output, and the output end of the byte replacement unit is connected with the input end of the linear left shift unit; the output end of the linear left shift is connected with the input end of the high 32-bit word and XOR operation unit of each round of conversion; the output end of the exclusive-or operation unit outputs 32-bit intermediate value, and the 32-bit intermediate value is cascaded with the lower 96-bit data of the previous round to form 128-bit intermediate value of the next round of conversion.
The key expansion module of the invention has the input of 128 bits and the output of 32 bits, and comprises seven exclusive ors XOR1, XOR2, XOR3, XOR4, XOR5, XOR6, XOR7, a byte replacement unit and a linear left shift unit;
the middle value of each round of key expansion is 128 bits, the key expansion is divided into 4 32-bit words on average, and 4 32-bit system parameters are respectively connected to the input ends of four XOR devices of XOR1, XOR2, XOR3 and XOR 4; wherein, the output ends of the XOR2, the XOR3 and the XOR4 are connected with the input end of the XOR 5; the output of XOR5 is connected with the 32-bit fixed parameter to the input of XOR 6; an output terminal of XOR6 is connected to an input terminal of the byte replacement unit; the output end of the byte replacement unit is connected with the input end of the linear left shift unit; the output end of the linear left shift unit is connected with the input end of the XOR 7; the output of the exclusive or XOR7 is the 32-bit round key.
The input of the round counting module is a 1-bit round counting enabling signal, the output of the round counting module is two counting values of 6 bits, the counting values respectively represent the round numbers corresponding to round conversion and key expansion, and the round counting module comprises two registers, two selectors and two adders. The function of the round counting module is to count the number of rounds of key expansion and round transformation, and ensure 32 rounds of iteration of key expansion and round transformation.
The input/output selection module inputs 4 1-bit state signals, 2 6-bit data and 4 128-bit data, respectively represents encryption enable, round conversion end, key expansion end, encryption completion, key expansion round number, round conversion count, initial input key, key intermediate value of each round, initial input plaintext and round conversion intermediate value of each round, and outputs 2 round conversion intermediate value data of 128 bits and 1-bit encryption end mark signal. The input selection module is used for completing the input selection of each round of the key expansion module and the round transformation module according to control signals received from the state control center module and the digital true random number generator and counting signals k _ counter and r _ counter sent by the round counting module.
The state control center module inputs 1-bit encryption enabling signals and 1-bit self-defined signals representing random states, outputs 5 1-bit signals respectively representing 5 states of key expansion enabling, key expansion proceeding, round conversion enabling, round conversion proceeding and round conversion finishing;
the state control center module is internally provided with 7 states which are respectively initial states S 0 The key expansion enabling state K _ en, the key expansion proceeding state K _ ing, the round transformation enabling state R _ en, the round transformation proceeding state R _ ing, the round transformation ending state R _ end and the random state rand. The circuit defaults to the initial state S 0 After the state control center module receives the 1-bit encryption enabling signal, the round key expansion enabling signal is pulled high, and then the state is transferred to a key expansion state. And after the key expansion is finished, the next state is shifted to, and the round transformation enabling signal is pulled high. At the moment, a random state is inserted and controlled by a random signal R _ R, if the random signal at the moment is detected to be a specific value, the circuit carries out random round conversion operation, and if not, the circuit normally runs. And finishing a small round of encryption in the round conversion state, entering a round conversion ending state R _ end, and storing a round key and an intermediate value. And repeating the cycle for 32 times to finish the encryption of a group of plaintext data.
(II) working principle
As shown in fig. 2, the SM4 encryption algorithm is mainly composed of two parts, namely round transformation and key expansion. The SM4 encryption process comprises dividing 128-bit plaintext into 4 32-bit words, and marking as P 0 ＝(X 0 ,X 1 ,X 2 ,X 3 ). Then, the 128 bits plaintext P of the first round input is processed 0 Divided into two sides, X 0 On the left, X 1 ,X 2 ,X 3 On the right. When the first round of encryption is carried out, X is firstly encrypted 0 ,X 1 ,X 2 ,X 3 Round key K generated by key expansion module 0 Calculation by round function F, the result is marked as X 4 . The right 3 words X of the first round 1 ,X 2 ,X 3 The first 3 words, X, directly as the second round input 4 As the 4 th word, the second round of the conversion input can be written as P 1 ＝(X 1 ,X 2 ,X 3 ,X 4 ). The iterative calculation is carried out through the steps in each round until the output result P of the 32 nd round transformation is obtained 32 ＝(X 32 ,X 33 ,X 34 ,X 35 ) Finally, the final ciphertext is transformed in reverse order to obtain the final ciphertext C ═ X 35 ,X 34 ,X 33 ,X 32 )。
As shown in fig. 3, the round transform of the SM4 cipher circuit is mainly composed of a nonlinear structure S-box and a linear transform L. When the encryption operation is carried out, firstly, the 128-bit input packet plaintext is divided into 4 32-bit words, and the words are recorded from the high order to the low orderP i ，P i+1 ，P i+2 ，P i+3 (i-0, …,31) and the corresponding round key is denoted rk i It needs to be generated by a special key expansion module. P i+1 ，P i+2 ，P i+3 And rk i Performing XOR operation, performing S-box and linear transformation L, and performing XOR operation on the result and P i And carrying out XOR operation to obtain an output result.
In the round transformation structure of the SM4, 4S boxes jointly form a nonlinear structure, and the function of executing byte replacement is a core part for ensuring the security of the SM4 algorithm. Considering that the lookup table consumes large area resources, the invention designs the S box by adopting a complex domain inversion mode, and the essence is that the S box is GF (2) 8 ) The structure of the nonlinear transformation performed on the domain is shown in fig. 4.
As shown in fig. 4, X represents 8-bit input of the S-box, and Y represents 8-bit output of the S-box, which can be specifically expressed as:
Y＝T(TX+V) -1 +V (4)
in equation (1), T and V are two matrices used for affine transformation in S-box, which are:
after S-box, the output 32-bit intermediate value is subjected to a linear transformation L, including a four-step cyclic left shift operation and an exclusive or operation, as shown in fig. 5.
The input of each round of key expansion of the SM4 is 128-bit data, the output is 32-bit intermediate value, and the intermediate value is concatenated with the lower 96 bits of the original round key to form a new 128-bit round key, so that 32 rounds are iterated, and the structure of each round is shown in FIG. 6.
As shown in FIG. 6, the initial 128-bit key MK is first divided into 4 32-bit words, denoted as MK 0 ，MK 1 ，MK 2 ，MK 3 Let 128-bit system parameter FK be denoted as FK 0 ，FK 1 ，FK 2 ，FK 3 Respectively is as follows:
fixed parameter CK i The length of (i ═ 0, …,31) is 32 bits, and is:
the values in equations (5) and (6) are both 16-ary numbers. In fig. 5, the left part is a one-time operation, only for the initial key, and the right part is a round operation, for the intermediate value K associated with the round key i ，K i+1 ，K i+2 ，K i+3 . Obtaining 32-bit string after the intermediate value is subjected to XOR operation, performing XOR operation after the intermediate value is subjected to S box and linear transformation L', and outputting K i+4 I.e. the 32-bit round key rk for the next round i Directly to the corresponding round transformation function.
As shown in fig. 7, the linear transformation L' includes a two-step circular left shift operation and an exclusive or operation.
As shown in fig. 8, in order to defend against differential power consumption attacks, the digital true random number generator is added on the basis of the SM4 cryptographic circuit without adding a safeguard measure. The state machine in each round is provided with a random state which is controlled by a random signal generated by a random number generator, and when the state machine selects the random state, normal round transformation is suspended, and random plaintext and random key are selected to carry out encryption operation, namely pseudo operation. After adding the random pseudo-operation, the SM4 cryptographic circuit is caused to randomly perform other round transformations and round key expansions when a particular round transformation and round key expansion should be performed. The encryption circuit designed by the scheme randomizes both round functions and key expansion, so that the time of generating the intermediate value is not fixed, and the power consumption track of the fixed time is blurred, so that an attacker cannot guess the key according to the differential power consumption curve, and the aim of resisting differential power consumption attack is fulfilled.
As shown in FIG. 9, R, S both ends access the same clock signal, the circuit metastable state based entropy source is completed by two NOR gates, and the bistable characteristic of RS flip-flop is utilized as the entropy source of the true random number generator. At this time, the output of the Q terminal has only two cases, and when CLK1 is low, the output of the Q terminal remains unchanged. When CLK1 is high, the output of the next state at the Q terminal is indeterminate. The output at this time may be 0 or1, and the specific stable state depends on the noise inside the circuit. Because the metastable state can propagate in the circuit, delay sampling is needed to be carried out through a synchronizer in order to obtain a random sequence output after the metastable state is stabilized. Generally, the probability of propagation of a metastable state through a two-stage D trigger is greatly reduced, so that the sampled data is a random sequence output after the metastable state is stable by adopting a three-stage D trigger cascade mode. The entropy source based on oscillator jitter is composed of a NAND gate and two inverters to form a ring oscillator. The start and stop of the oscillator are controlled by the clock signal, and the jitter information of the clock signal CLK3 is reflected by a periodic square wave at the output terminal. CLK3 is a high frequency signal relative to CLK4, i.e., the entropy source clock period is short and the sampling clock CLK4 is a long period signal that is ideally stable. According to the randomness of the leading and lagging clock jitters of the CLK3, a stable random level output can be sampled by the D flip-flop at each rising edge of the CLK 4. And storing the output sequences of the two true random number generators through a 4-bit shift register, and obtaining a post-processed random sequence through XOR operation.
The present invention has been described with reference to the current embodiments, but it should be understood by those skilled in the art that the above embodiments are only illustrative and not restrictive, and any modifications, equivalent substitutions and improvements made within the spirit and scope of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A digital true random number generator-based SM4 power attack resistance encryption circuit, comprising: the device comprises a digital true random number generator, a round transformation module, a key expansion module, a round counting module, an input/output selection module and a state control center module;
the digital true random number generator is connected with the state control center module and the input/output selection module and is used for generating random variables; the random variable is used as a control signal and input to the state control center module, and once the state control center module detects that the random variable is a specific value, the randomization operation is executed; the random variable is used as a control signal to be input into the input and output selection module, and the input and output selection module is controlled to randomly select the plaintext and the secret key to be output;
the round conversion module is connected with the state control center module, the input/output selection module, the key expansion module and the round counting module and is used for carrying out round conversion; the round conversion has 32 rounds, and each round generates a 128-bit intermediate value which is used as input data of the next round conversion; 4-bit 32-bit data output in the last round is subjected to reverse order transformation operation to obtain a ciphertext;
the key expansion module is connected with the state control center module, the input/output selection module, the round conversion module and the round counting module and used for carrying out key expansion, and the key expansion module generates 32 round keys for the round conversion through 32 rounds of expansion operation;
the round counting module counts the number of rounds of the key expansion and the round transformation, and ensures that 32 rounds of iterations of the key expansion and the round transformation are carried out;
the state control center module controls the running states of the digital true random number generator, the round transformation module, the key expansion module, the round counting module and the input/output selection module;
the input and output selection module completes input selection of each round of the key expansion module and the round transformation module according to control signals received from the state control center module and the digital true random number generator and counting signals k _ counter and r _ counter sent by the round counting module;
the plaintext and the secret key are both 128 bits.
2. The digital true random number generator-based power attack resistant SM4 encryption circuit of claim 1, wherein the digital true random number generator comprises an entropy source module based on circuit metastability and clock jitter, a D flip-flop based sampling module, and an XOR based post-processing module;
the input of the digital true random number generator is 4 clock signals, and the output is a 4-bit random sequence; the circuit metastable state-based entropy source consists of two exclusive-OR gates, 2-bit data is input, and 1-bit data is output to finish sampling through 3D triggers; the entropy source module based on clock jitter is composed of a 3-level ring oscillator, the input is also 2 bits, and the output 1-bit data is sampled through 1D trigger; and respectively connecting the two output 1-bit data with the input ends of two 4-bit shift registers, and performing XOR operation to obtain a 4-bit random sequence.
3. The digital true random number generator-based power attack resistant SM4 encryption circuit as claimed in claim 1, wherein the input of the round transformation module is 128-bit data, the output is 32-bit data, and the operation unit is 32-bit word comprising a round key addition unit, a byte replacement unit, a linear left shift unit and an XOR operation unit;
the input of each round of conversion is 128-bit data, which is divided into 4 32-bit words on average, and the lower 3 32-bit words and the round key are connected with the input end of the round key adding unit; the output end of the round key adding unit is connected with the input end of the byte replacing unit; the byte replacement unit consists of 4S boxes with 8-bit input and 8-bit output, and the output end of the byte replacement unit is connected with the input end of the linear left shift unit; the output end of the linear left shift is connected with the input end of the high 32-bit word and XOR operation unit of each round of conversion; the output end of the exclusive-or operation unit outputs a 32-bit intermediate value, and the intermediate value is cascaded with the lower 96-bit data of the previous round to form a 128-bit intermediate value of the next round of conversion.
4. The digital true random number generator based SM4 encryption circuit for resisting power consumption attack according to claim 1, wherein the key expansion module has 128 bits of input and 32 bits of output, and comprises seven exclusive ors XOR1, XOR2, XOR3, XOR4, XOR5, XOR6, XOR7, a byte replacement unit and a linear left shift unit;
the middle value of each round of key expansion is 128 bits, the key expansion is divided into 4 32-bit words on average, and 4 32-bit system parameters are respectively connected to the input ends of four XOR devices of XOR1, XOR2, XOR3 and XOR 4; wherein, the output ends of the XOR2, the XOR3 and the XOR4 are connected with the input end of the XOR 5; the output of XOR5 is connected with the 32-bit fixed parameter to the input of XOR 6; an output terminal of XOR6 is connected to an input terminal of the byte replacement unit; the output end of the byte replacement unit is connected with the input end of the linear left shift unit; the output end of the linear left shift unit is connected with the input end of the XOR 7; the output of the exclusive or XOR7 is a 32-bit round key.
5. The digital true random number generator-based power attack resistant SM4 encryption circuit as claimed in claim 1, wherein the round counting module has an input of a 1-bit round counting enable signal and an output of two 6-bit count values respectively representing the number of rounds corresponding to round conversion and key expansion, and is composed of two registers, two selectors and two adders.
6. The SM4 encryption circuit for resisting power consumption attack based on digital true random number generator is characterized in that the input of the input and output selection module is 4 1-bit state signals, 2 6-bit data and 4 128-bit data, which respectively represent encryption enable, round conversion end, key expansion end, encryption completion, key expansion round number, round conversion count, initial input key, key middle value of each round, initial input plaintext and round conversion middle value of each round, and output is 2 round conversion middle value data of 128 bits and 1-bit encryption end flag signal.
7. The digital true random number generator-based power attack resistant SM4 encryption circuit as claimed in claim 1, wherein the state control center module has inputs of a 1-bit encryption enable signal and a 1-bit custom signal representing a random state, and outputs of 5 1-bit signals respectively representing 5 states of key expansion enable, key expansion progress, round shift enable, round shift progress and round shift end;
the state control center module is internally provided with 7 states which are respectively initial states S 0 A key expansion enabling state K _ en, a key expansion performing state K _ ing, a round transformation enabling state R _ en, a round transformation performing state R _ ing, a round transformation ending state R _ end and a random state rand;
the circuit defaults to the initial state S 0 After the state control center module receives the 1-bit encryption enabling signal, the round key expansion enabling signal is pulled high, and then the state is transferred to a key expansion state; after the key expansion is finished, the next state is transferred, and the round transformation enabling signal is pulled up; at the moment, inserting a random state rand, controlling by a random signal R _ R, if the random signal at the moment is detected to be a specific value, carrying out random round transformation operation by the circuit, otherwise, normally operating the circuit;
finishing a small round of encryption in the round of conversion state, entering a round of conversion ending state R _ end, and storing a round key and an intermediate value; and repeating the cycle for 32 times to finish the encryption of a group of plaintext data.
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