CN114866216A - Chaotic synchronization system and method based on resistance and fractional order equivalent capacitance coupling - Google Patents
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Abstract
The invention discloses a chaotic synchronization system and method based on resistance and fractional order equivalent capacitance coupling, which comprises a coupling drive end, a control end and a coupling response end; the coupling driving end is provided with a coupling driving circuit, the coupling response end is provided with a coupling response circuit, and the control end is provided with a linear coupling circuit; the coupling driving circuit is connected with the coupling response circuit through the linear coupling circuit. The invention adopts the resistor and the fractional order equivalent capacitor to carry out linear coupling synchronization on the driving end and the response end, has simple control structure and higher stability, thereby improving the safety of data in the chaotic synchronization process.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a chaotic synchronization system and a chaotic synchronization method based on coupling of resistance and fractional order equivalent capacitance.
Background
Communication is a ring of importance for national security. At present, data information interaction in the background of the big data era is very frequent and rapid, and the traditional secret communication can not completely meet the safety requirement of the current network communication. The chaotic signal has the characteristics of extreme sensitivity, continuous wide-band spectrum, ergodicity, boundedness, internal randomness, fractal dimension, universality and the like of initial conditions and system parameters, and is consistent with the requirements of cryptography and secret communication.
Chaos is a generalization of a class of complex, chaotic movements that appears to be extremely sensitive to small changes. And extending the chaotic order to the range of fractions to obtain a fractional order chaotic model. The order change enables the fractional order chaos model to show a more complex evolution track, and a plurality of specific properties of the fractional order chaos are evolved: such as fractional derivative or integral synthesis, takes into account the past history and the influence of non-local distribution, and is more accurate in representing the characteristics of the system and the actual physical characteristics. Therefore, compared with an integer order chaotic system, the fractional order chaotic system is more in line with the actual situation and can more accurately reflect the dynamic characteristics of the actual system; and the more complex dynamics and pseudo-randomness improve the security of the system. In addition, the fractional order chaotic system has stronger inhibition capacity on noise interference level parameter disturbance, and the linear resistance coupling control enables chaotic synchronization to have better robustness.
The present synchronous control method of chaotic system, chinese patent (CN113141250A) discloses a synchronous control method and device for secret communication of chaotic system of sending end and receiving end, by setting the system initial value of the chaotic system of sending end; according to the mathematical model of the chaotic system of the sending end, constructing the mathematical model of the chaotic system of the receiving end; setting a system initial value of a chaotic system of a receiving end; according to the mathematical model of the chaotic system of the sending end and the mathematical model of the chaotic system of the receiving end, defining the synchronous error of the chaotic system of the sending end and the chaotic system of the receiving end to obtain an error system; constructing a controller; controlling an error system based on a controller to realize the synchronization of the chaotic system of the sending end and the chaotic system of the receiving end; and the synchronized sending end and the receiving end start to execute secret communication. The control method has the advantages of better synchronization time and quick response capability. However, researches show that a general low-dimensional chaotic system is easy to be attacked by self-adaptive synchronous control and does not have high confidentiality; the low-dimensional chaotic system has simple system dynamics characteristic and small key space, cannot resist phase space reconstruction and is easy to decipher. More importantly, the patent uses the idea of a drive-response synchronization method, which is an open-loop state and is sensitive to noise and parameter mismatch, so that the robustness is poor. More importantly, the controller item of the method consists of three parts including an uncertainty item, an external disturbance item and an error system, and the structure is complex. More components are needed in specific circuit implementation, so that large interference among signals is caused, and the initial value sensitivity of chaotic signals determines that the chaotic signals are easily interfered by the signals, so that large errors can be realized.
Chinese patent (CN110149201A) discloses a secret communication method based on error concealment and chaotic synchronization, which includes the following steps: a transmitting end constructs a driving chaotic system, and encrypts information to be encrypted by using a first parameter in the driving chaotic system to obtain encrypted information; the sending end utilizes the second parameter and the third parameter in the driving chaotic system to cover and superpose the encrypted information to obtain a chaotic signal, and sends the chaotic signal to the receiving end; the receiving end constructs a response chaotic system, and constructs an error signal and a synchronization rule according to the chaotic signal sent by the sending end and the response chaotic system; the receiving end adjusts the synchronous rule to make the error signal approach to zero; and when the error signal approaches zero, obtaining decryption information according to the first parameter of the response chaotic system and the encryption information included in the chaotic signal. The method can improve the safety in the data transmission process. According to the invention, only a synchronization rule (control item) is added at the receiving end, and no synchronization rule is added at the transmitting end, so that from the perspective of an actual system, the linear characteristics of chaotic systems of the transmitting end and the receiving end are changed and become two different systems, and the added control item is very complex and very difficult to realize in actual physics; e3 of the error system of the invention does not contain a nonlinear term, and for a linear system, the stability and the output characteristic of the error system only determine the structure and parameters of the system; the stability and the output dynamic process of the nonlinear system are not only related to the structure and parameters of the system, but also related to the initial conditions of the system and the size of the input signal, so that the difficulty of signal decoding is increased. Therefore, when synchronous secret communication is carried out, the linear system is easier to crack than a nonlinear system, and the safety in the data transmission process is reduced.
Disclosure of Invention
Aiming at the problem that the chaotic synchronization system in the prior art is low in data transmission safety due to nonlinear coupling, the invention provides a chaotic synchronization system and a method based on resistance and fractional order equivalent capacitance coupling, and the resistance and the fractional order equivalent capacitance are adopted to carry out coupling synchronization on a driving end and a response end, so that the linear coupling of the chaotic synchronization system is realized, and the safety of data in the chaotic synchronization process is further improved.
In order to achieve the purpose, the invention provides the following technical scheme:
the chaotic synchronization system based on resistance and fractional order equivalent capacitance coupling comprises a coupling driving end, a control end and a coupling response end; the coupling driving end is provided with a coupling driving circuit, the coupling response end is provided with a coupling response circuit, and the control end is provided with a linear coupling circuit; the coupling driving circuit is connected with the coupling response circuit through the linear coupling circuit.
Preferably, the coupling driving circuit includes a first driving circuit, a second driving circuit and a third driving circuit;
the first driving circuit comprises a first driving variable terminal x 1:
the other end of the first driving variable end x1 is connected with one end of a first resistor R1, the other end of the first resistor R1, one end of a first fractional equivalent capacitor F1 and one end of a second resistor R2 are connected in parallel and then connected with the inverting input end of a first comparator U1, the non-inverting input end of the first comparator U1 is grounded, the other end of the first fractional equivalent capacitor F1 is connected with the first driving variable end x1, the output end of the first comparator U1 and one end of an eighth resistor R8, the other end of the eighth resistor R8 and one end of a ninth resistor R9 are connected in parallel and then connected with the inverting input end of a fourth comparator U4, the non-inverting input end of a fourth comparator U4 is grounded, the output end of the fourth comparator U4 and the other end of the ninth resistor R9 are connected in parallel and then connected with one end of a third resistor R3 and one end of a second driver circuit, and the other end of the second resistor R2 is connected with the eleventh resistor R69556 and the other end of the fourth resistor R2 and the eleventh resistor R8269556 and the second driver circuit in the second driver circuit respectively, The output end of the fifth comparator U5 is connected with the second input end of the second multiplier X2 in the third driving circuit;
the second driving circuit comprises a second driving variable end x2 and a coupling driving end u:
the second driving variable end X2 is connected with one end of a twenty-third resistor R23 in the linear coupling circuit, the coupling driving end U is connected with one end of a thirty-third resistor R30, the first input end of a first multiplier X1 is connected with a first driving variable end X1, the output end of a first multiplier X1 is connected with one end of a fifth resistor R5, the other end of a thirty-third resistor R30, the other end of a third resistor R3, the other end of a fourth resistor R4, the other end of a fifth resistor R5 and one end of a second fractional equivalent capacitor F2 are connected in parallel and then connected with the inverted input end of a second comparator U2, the non-inverting input end of the second comparator U2 is grounded, the other end of the second fractional equivalent capacitor F2, the output end of the second comparator U2 and one end of a tenth resistor R10 are connected in parallel and then connected with the second driving variable end X2, the other end of a tenth resistor R10 and one end of an eleventh resistor R11 are connected in parallel and then connected with the inverted input end of the fifth comparator U5, the non-inverting input end of the fifth comparator U5 is grounded, and the other end of the eleventh resistor R11 and the output end of the fifth comparator U5 are connected in parallel and then connected with the other end of the second resistor R2;
the third drive circuit comprises a third drive variable terminal x 3:
a third driving variable end X3 is connected to a second input end of a first multiplier X1, one end of a sixth resistor R6, the other end of a third fractional order equivalent capacitor F3 and an output end of a third comparator U3, a first input end of a second multiplier X2 is connected to the first driving variable end X1, a second input end of the second multiplier X2 is connected to the other end of the second resistor R2, an output end of the second multiplier X2 is connected to one end of a seventh resistor R7, the other end of the sixth resistor R6, the other end of the seventh resistor R7 and one end of the third fractional order equivalent capacitor F3 are connected in parallel and then connected to an inverting input end of the third comparator U3, and a non-inverting input end of the third comparator U3 is grounded.
Preferably, the coupling response circuit comprises a first response circuit, a second response circuit and a third response circuit;
the first response circuit includes a first response variable terminal y 1:
the other end of the fourteenth resistor R14 and one end of the twelfth resistor R12 are connected in parallel and then connected with the inverting input terminal of the sixth comparator U59642, the other end of the seventeenth resistor R17 are connected with the inverting input terminal of the nineteenth resistor R19 in the second driving circuit, the other end of the seventeenth resistor R16, one end of the fourth equivalent capacitor F4 and one end of the seventeenth resistor R17 are connected in parallel and then connected with the inverting input terminal of the eighth comparator U8, the non-inverting input terminal of the eighth comparator U8, the output terminal of the eighth comparator U8 and one end of the fourteenth resistor R14 are connected in parallel and then connected with the first response variable terminal y1, the other end of the fourteenth resistor R14 and one end of the twelfth resistor R12 are connected in parallel and then connected with the inverting input terminal of the sixth comparator U6, the non-inverting input terminal of the sixth comparator U6 are connected with the ground, the output terminal of the sixth comparator U6 and the other end of the twelfth resistor R12 are connected in parallel and then connected with one end of the eighteenth resistor R18 in the second driving circuit, and the other end of the seventeenth resistor R17 are connected with the nineteenth resistor R19 in the second driving circuit respectively, The other end of the thirteenth resistor R13, the output end of the seventh comparator U7 and the second input end of the fourth multiplier X4 in the third response circuit are connected;
the second response circuit includes a second response variable terminal y2 and a coupled response terminal-u:
the output end of the linear coupling circuit is connected with a coupling response end-U, the coupling response end-U is further connected with one end of a thirty-first resistor R31, the first input end of a third multiplier X3 is connected with a first response variable end y1, the output end of the third multiplier X3 is connected with one end of a twentieth resistor R20, the other end of a thirty-first resistor R31, the other end of an eighteenth resistor R18, the other end of a nineteenth resistor R19, the other end of a twentieth resistor R20 and one end of a fifth-order equivalent capacitor F5 are connected in parallel and then connected with the inverted input end of a ninth comparator U9, the non-inverting input end of the ninth comparator U9 is grounded, the other end of the fifth-order equivalent capacitor F5, the output end of the ninth comparator U9 and one end of a fifteenth resistor R15 are connected in parallel and then connected with a second response variable end y2, and the second response variable end y2 is further connected with a twenty-fourth resistor R24 in the linear coupling circuit, the other end of the fifteenth resistor R15 and one end of the thirteenth resistor R13 are connected in parallel and then connected with the inverting input end of the seventh comparator U7, the non-inverting input end of the seventh comparator U7 is grounded, and the other end of the thirteenth resistor R13 and the output end of the seventh comparator U7 are connected in parallel and then connected with the other end of the seventeenth resistor R17;
the third response circuit includes a third response variable terminal y 3:
a third response variable end y3 is respectively connected with a second input end of a third multiplier X3, one end of a twenty-first resistor R21, the other end of a sixth fractional equivalent capacitor F6 and an output end of a tenth comparator U10, a first input end of a fourth multiplier X4 is connected with the first response variable end y1, a second input end of the fourth multiplier X4 is connected with the other end of a seventeenth resistor R17, an output end of the fourth multiplier X4 is connected with one end of a twenty-second resistor R22, the other end of a twenty-first resistor R21, the other end of a twenty-second resistor R22 and one end of a sixth fractional equivalent capacitor F6 are connected in parallel and then connected with an inverting input end of a tenth comparator U10, and a non-inverting input end of the tenth comparator U10 is grounded.
Preferably, the linear coupling circuit comprises a linear resistor R k And a seventh fractional equivalent capacitance F7:
one end of a twenty-third resistor R23 is connected with a second driving variable end x2, one end of a twenty-fourth resistor R24 is connected with a second response variable end y2, the other end of the twenty-third resistor R23 and one end of a twenty-sixth resistor R26 are connected in parallel and then connected with an inverting input end of an eleventh comparator U11, the other end of the twenty-fourth resistor R24 and one end of a twenty-fifth resistor R25 are connected in parallel and then connected with a non-inverting input end of the eleventh comparator U11, the other end of the twenty-fifth resistor R25 is grounded, the other end of the twenty-sixth resistor R26 and the output end of the eleventh comparator U11 are connected in parallel and then respectively connected with a linear resistor R26 and the output end of the eleventh comparator U11 k Is connected to one end of a seventh fractional order equivalent capacitor F7, and a linear resistor R k Another end of (1), seventh fractional orderThe other end of the equivalent capacitor F7 and one end of the twenty-seventh resistor R27 are connected in parallel and then connected with the inverting input end of the twelfth comparator U12, the non-inverting input end of the twelfth comparator U12 is grounded, the output end of the twelfth comparator U12, the other end of the twenty-seventh resistor R27 and one end of the twenty-eighth resistor R28 are connected in parallel and then connected with the coupling driving end U, the other end of the twenty-eighth resistor R28 and one end of the twenty-ninth resistor R29 are connected in parallel and then connected with the inverting input end of the thirteenth comparator U13, the non-inverting input end of the thirteenth comparator U13 is grounded, and the other end of the twenty-ninth resistor R29 and the output end of the thirteenth comparator U13 are connected in parallel and then connected with the coupling response end-U.
Preferably, the equivalent circuit of the seventh fractional equivalent capacitor F7 is:
one end of the a-th resistor Ra and one end of the first capacitor C1 are connected in parallel and then connected with the input port, the other end of the a-th resistor Ra and the other end of the first capacitor C1 are connected in parallel and then connected with one end of the b-th resistor Rb and one end of the second capacitor C2 respectively, the other end of the b-th resistor Rb and the other end of the second capacitor C2 are connected in parallel and then connected with one end of the C-th resistor Rc and one end of the third capacitor C3 respectively, and the other end of the C-th resistor Rc and the other end of the third capacitor C3 are connected in parallel and then connected with the output port.
The invention also provides a chaotic synchronization method based on resistance and fractional order equivalent capacitance coupling, which specifically comprises the following steps:
s1: constructing a mathematical model of a driving end:
in the formula (1), x 1 ,x 2 ,x 3 Respectively, the drive variables are represented by,
are respectively x 1 ,x 2 ,x 3 Q denotes a fractional derivative;
s2: and (3) constructing a mathematical model of the response end according to the mathematical model of the driving end:
in the formula (2), y 1 ,y 2 ,y 3 Respectively, the response variables are represented in a manner such that,
are each y 1 ,y 2 ,y 3 A derivative of (a);
s3: determining a linear coupling term, and respectively improving the driving end and the response end to obtain a coupling driving end and a coupling response end;
the mathematical model of the linear coupling term is:
in the formula (3), u represents a linear coupling control term, K R The linear resistance coupling coefficient is expressed as,
R k denotes the linear resistance, R 0 ＝100KΩ；
The linear coupling term is combined with the driving end to obtain a coupling driving end, and the mathematical model of the coupling driving end is as follows:
the linear coupling term and the response end are combined to obtain a coupling response end, and the mathematical model is as follows:
in the formulae (4) and (5), x 1 ,x 2 ,x 3 The drive variable is represented by a number of drive variables,
are respectively x 1 ,x 2 ,x 3 A derivative of (a); y is 1 ,y 2 ,y 3 A response variable is represented that indicates the response of the variable,
are each y 1 ,y 2 ,y 3 Q denotes a fractional derivative;
s4: defining a synchronous error between the coupling driving end and the coupling response end according to formulas (4) and (5) to obtain an error system, and arranging the error system at the control end to realize the synchronization of the coupling driving end and the coupling response end;
the mathematical model of the error system is:
in the formula (6), e i ＝x i -y i ,i＝1,2,3；
Preferably, in S1, the mathematical model at the driving end corresponds to a circuit state equation:
the dimensionless equation of state mapped by the circuit equation of state (5) is expressed as follows:
in the formulas (7) and (8), V1, V2 and V3 respectively represent voltages corresponding to x 1 ,x 2 ,x 3 ；t＝τ/t 0 ，R 0 ＝100kΩ,C 0 ＝10nF,t 0 ＝R 0 C 0 F represents a fractional order equivalent capacitance, let R 1 ＝R 2 ＝2.5kΩ，R 3 ＝R 5 ＝R 7 ＝10kΩ，R 4 ＝4kΩ，R 6 ＝33.3kΩ。
Preferably, in S4, the synchronization error of the error system
e i ＝x i -y i ,i＝1,2,3。
Preferably, in S3, q is 0.95, K R ＝1。
In summary, due to the adoption of the technical scheme, compared with the prior art, the invention at least has the following beneficial effects:
1. the invention adopts a fractional order system, and because the fractional order system has the characteristics of historical memory and the like, the dynamic characteristics of the fractional order system are more complex and difficult to decipher, and the safety of chaotic secret communication can be greatly enhanced.
2. Synchronization is realized based on a linear coupling technology: the nonlinear system realizes the continuity and the persistence of coupling through linear feedback, and even under the interference of larger environmental noise, the coupled fractional order chaotic system can still realize synchronization and has stronger anti-noise capability. Therefore, through the linear coupling controller which is simple in structure and easy to implement, the fractional order chaotic system can achieve stable coupling synchronization, the chaotic synchronization system has strong inhibition capacity on noise interference and chaotic system parameter disturbance, and the coupling control fractional order chaotic synchronization system has better robustness. More importantly, mutually coupled nonlinear systems are ubiquitous in nature, and have a very prominent practical value due to the simple structure of the linear coupling of the present invention.
3. The cost is low: the existing fractional order chaotic synchronization system adopts more components, has large interference among signals and larger realization error; the invention can realize the coupling term only by one resistor and the fractional order equivalent capacitor, has simple device and structure, improves the robustness and the universality of the synchronous system and improves the safety of the communication system.
Description of the drawings:
fig. 1 is a circuit diagram of a chaotic synchronization system based on resistance and fractional order equivalent capacitive coupling according to an exemplary embodiment of the present invention.
Fig. 2 is a schematic diagram of a fractional order equivalent capacitance equivalent circuit according to an exemplary embodiment of the invention.
FIG. 3 is a diagram of a maximum Lyapunov exponent with K in an error system according to an exemplary embodiment of the present invention R Simulation schematic of the variations.
Fig. 4 is a schematic diagram of a synchronization error simulation of an error system according to an exemplary embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, a communication between two elements, a direct connection, or an indirect connection via an intermediate medium, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.
Chaotic synchronization is an important condition for realizing chaotic secure communication. The basic idea of chaotic synchronization communication is as follows: the method comprises the steps of adding a transmitted signal source to a chaotic signal generated by a chaotic system to generate a chaotic noise-like signal, encrypting an information source, sending the chaotic signal to a receiver, and separating the chaotic signal in the chaotic signal by a corresponding chaotic system, namely a decryption process, so as to recover the originally transmitted information source.
The invention realizes the linear coupling of the driving system and the response system by using the resistor and the fractional order equivalent capacitor, finally achieves the synchronization, and uses the synchronized chaotic system in the field of secret communication. The flow chart of the invention mainly comprises: the method comprises the five main steps of constructing a driving system and circuit realization thereof, constructing a response system and circuit realization thereof, realizing a coupling term through a resistor and a fractional order equivalent capacitor and drawing a synchronous circuit diagram, constructing an error system and circuit realization thereof according to the coupling driving system and the coupling response system, and realizing the synchronization of the fractional order chaotic system.
As shown in fig. 1, the invention provides a chaotic synchronization system based on resistance and fractional order equivalent capacitance coupling, which comprises a coupling driving end, a control end and a coupling response end, wherein the coupling driving end is provided with a coupling driving circuit 1, the coupling response end is provided with a coupling response circuit 3, the control end is provided with a linear coupling circuit 2, the coupling driving circuit 1 and the coupling response circuit 3, and the coupling driving circuit 1 is connected with the coupling response circuit 3 through the linear coupling circuit 2.
In this embodiment, the coupling drive circuit 1 includes a first drive circuit, a second drive circuit, and a third drive circuit.
The first drive circuit includes a first drive variable terminal x 1:
the other end of the first driving variable end x1 is connected with one end of a first resistor R1, the other end of the first resistor R1, one end of a first fractional equivalent capacitor F1 and one end of a second resistor R2 are connected in parallel and then connected with the inverting input end of a first comparator U1, the non-inverting input end of the first comparator U1 is grounded, the other end of the first fractional equivalent capacitor F1 is connected with the first driving variable end x1, the output end of the first comparator U1 and one end of an eighth resistor R8, the other end of the eighth resistor R8 and one end of a ninth resistor R9 are connected in parallel and then connected with the inverting input end of a fourth comparator U4, the non-inverting input end of a fourth comparator U4 is grounded, the output end of the fourth comparator U4 and the other end of the ninth resistor R9 are connected in parallel and then connected with one end of a third resistor R3 and one end of a second driver circuit, and the other end of the second resistor R2 is connected with the eleventh resistor R69556 and the other end of the fourth resistor R2 and the eleventh resistor R8269556 and the second driver circuit in the second driver circuit respectively, The output terminal of the fifth comparator U5 is connected to the second input terminal of the second multiplier X2 in the third driver circuit. In this embodiment, the circuit formed by the eighth resistor R8, the ninth resistor R9, and the fourth comparator U4 functions as: the first variable signal x1 input to the first drive variable terminal x1 is inverted.
The second driving circuit comprises a second driving variable end x2 and a coupling driving end u:
the second driving variable terminal X2 is connected to the input terminal (one terminal of the twenty-third resistor) of the linear coupling circuit 2, the coupling driving terminal U is connected to one terminal of the thirty-third resistor R30, the first input terminal of the first multiplier X1 is connected to the first driving variable terminal X1, the output terminal of the X1 is connected to one terminal of the fifth resistor R5, the other terminal of the thirty-third resistor R30, the other terminal of the third resistor R3, the other terminal of the fourth resistor R4, the other terminal of the fifth resistor R5, one terminal of the second fractional equivalent capacitor F2 is connected in parallel and then connected to the inverting input terminal of the second comparator U2, the non-inverting input terminal of the second comparator U2 is grounded, the other terminal of the second fractional equivalent capacitor F2, the output terminal of the second comparator U2, one terminal of the tenth resistor R10 is connected in parallel and then connected to the inverting input terminal of the fifth comparator U2, the other terminal of the tenth resistor R10 and one terminal of the eleventh resistor R11 are connected in parallel and then connected to the inverting input terminal of the fifth comparator U5, the non-inverting input end of the fifth comparator U5 is grounded, and the other end of the eleventh resistor R11 and the output end of the fifth comparator U5 are connected in parallel and then connected with the other end of the second resistor R2. In this embodiment, the tenth resistor R10, the eleventh resistor R11, and the fifth comparator U5 form a circuit function as: the second variable signal x2 input to the second drive variable terminal x2 is inverted.
The third drive circuit includes a third drive variable terminal x 3:
a third driving variable end X3 is respectively connected with a second input end of an X1, one end of a sixth resistor R6, the other end of a third fractional order equivalent capacitor F3 and an output end of a third comparator U3, a first input end of a second multiplier X2 is connected with the first driving variable end X1, a second input end of the X2 is connected with the other end of the second resistor R2, an output end of the second multiplier X2 is connected with one end of a seventh resistor R7, the other end of the sixth resistor R6, the other end of a seventh resistor R7 and one end of the third fractional order equivalent capacitor F3 are connected in parallel and then connected with an inverting input end of the third comparator U3, and a non-inverting input end of the third comparator U3 is grounded.
In this embodiment, the mathematical model corresponding to the coupling driving circuit 1 is:
in the formula (1), x 1 ,x 2 ,x 3 Respectively representing the drive variables input by the first drive circuit, the second drive circuit and the third drive circuit,
are respectively x 1 ,x 2 ,x 3 Q denotes the fractional derivative, K R The linear resistance coupling coefficient is expressed as,
R k denotes the linear resistance, R 0 ＝100KΩ。
In this embodiment, correspondingly, the coupling response circuit 3 includes a first response circuit, a second response circuit and a third response circuit.
The first response circuit includes a first response variable terminal y 1:
the other end of the fourteenth resistor R14 and one end of the twelfth resistor R12 are connected in parallel and then connected with the inverting input terminal of the sixth comparator U59642, the other end of the seventeenth resistor R17 are connected with the inverting input terminal of the nineteenth resistor R19 in the second driving circuit, the other end of the seventeenth resistor R16, one end of the fourth equivalent capacitor F4 and one end of the seventeenth resistor R17 are connected in parallel and then connected with the inverting input terminal of the eighth comparator U8, the non-inverting input terminal of the eighth comparator U8, the output terminal of the eighth comparator U8 and one end of the fourteenth resistor R14 are connected in parallel and then connected with the first response variable terminal y1, the other end of the fourteenth resistor R14 and one end of the twelfth resistor R12 are connected in parallel and then connected with the inverting input terminal of the sixth comparator U6, the non-inverting input terminal of the sixth comparator U6 are connected with the ground, the output terminal of the sixth comparator U6 and the other end of the twelfth resistor R12 are connected in parallel and then connected with one end of the eighteenth resistor R18 in the second driving circuit, and the other end of the seventeenth resistor R17 are connected with the nineteenth resistor R19 in the second driving circuit respectively, The other end of the thirteenth resistor R13, the output terminal of the seventh comparator U7, and the second input terminal of the fourth multiplier X4 in the third response circuit are connected.
The second response circuit includes a second response variable terminal y2 and a coupled response terminal-u:
the output end of the linear coupling circuit 2 is connected with a coupling response end-U, the coupling response end-U is further connected with one end of a thirty-first resistor R31, the first input end of a third multiplier X3 is connected with a first response variable end y1, the output end of X3 is connected with one end of a twentieth resistor R20, the other end of a thirty-first resistor R31, the other end of an eighteenth resistor R18, the other end of a nineteenth resistor R19, the other end of a twentieth resistor R20 and one end of a fifth order equivalent capacitor F5 are connected in parallel and then connected with the inverted input end of a ninth comparator U9, the non-inverting input end of the ninth comparator U9 is grounded, the other end of a fifth order equivalent capacitor F5, the output end of the ninth comparator U9 and one end of a fifteenth resistor R15 are connected in parallel and then connected with a second response variable end y2, the second response variable end y2 is further connected with one end of a twenty-fourth resistor R24 in the linear coupling circuit 2, the other end of the fifteenth resistor R15 and one end of the thirteenth resistor R13 are connected in parallel and then connected with the inverting input end of the seventh comparator U7, the non-inverting input end of the seventh comparator U7 is grounded, and the other end of the thirteenth resistor R13 and the output end of the seventh comparator U7 are connected in parallel and then connected with the other end of the seventeenth resistor R17.
The third response circuit includes a third response variable terminal y 3:
a third response variable end y3 is respectively connected with a second input end of the X3, one end of a twenty-first resistor R21, the other end of a sixth fractional order equivalent capacitor F6 and an output end of a tenth comparator U10, a first input end of the X4 is connected with the first response variable end y1, a second input end of the X4 is connected with the other end of a seventeenth resistor R17, an output end of the X4 is connected with one end of a twenty-second resistor R22, the other end of the twenty-first resistor R21, the other end of the twenty-second resistor R22 and one end of the sixth fractional order equivalent capacitor F6 are connected in parallel and then connected with an inverting input end of the tenth comparator U10, and a non-inverting input end of the tenth comparator U10 is grounded.
In this embodiment, the mathematical model of the coupling response circuit 3 is:
in the formula (2), y 1 ,y 2 ,y 3 Respectively representing the response variables output by the first response circuit, the second response circuit and the third response circuit,
are each y 1 ,y 2 ,y 3 Q denotes the fractional derivative, K R The linear resistance coupling coefficient is expressed as,
R k denotes the linear resistance, R 0 ＝100KΩ。
In this embodiment, the driving circuits and the response circuits are in a one-to-one correspondence, for example, the first driving circuit corresponds to the first response circuit, the second driving circuit corresponds to the second response circuit, and the third driving circuit corresponds to the third response circuit.
In this embodiment, the linear coupling circuit 2 includes a linear resistor R k And fractional equivalent capacitance F7:
one end of a twenty-third resistor R23 is connected with a second driving variable end x2, one end of a twenty-fourth resistor R24 is connected with a second response variable end y2, the other end of the twenty-third resistor R23 and one end of a twenty-sixth resistor R26 are connected in parallel and then connected with the inverting input end of an eleventh comparator U11, the other end of the twenty-fourth resistor R24 and one end of a twenty-fifth resistor R25 are connected in parallel and then connected with the non-inverting input end of the eleventh comparator U11, and the other end of the twenty-fifth resistor R25 is connected with the non-inverting input end of the eleventh comparator U11The other end of the twenty-sixth resistor R26 and the output end of the eleventh comparator U11 are connected in parallel and then respectively connected with the linear resistor R k Is connected to one end of a fractional order equivalent capacitor F7, and a linear resistor R k The other end of the third resistor, one end of a twenty-seventh resistor R27 and the other end of the fractional order equivalent capacitor F7 are connected in parallel and then connected with an inverting input end of a twelfth comparator U12, a non-inverting input end of the twelfth comparator U12 is grounded, an output end of the twelfth comparator U12, the other end of the twenty-seventh resistor R27 and one end of the twenty-eighth resistor R28 are connected in parallel and then connected with a coupling driving end U, the other end of the twenty-eighth resistor R28 and one end of the twenty-ninth resistor R29 are connected in parallel and then connected with an inverting input end of a thirteenth comparator U13, a non-inverting input end of the thirteenth comparator U13 is grounded, and the other end of the twenty-ninth resistor R29 and the output end of the thirteenth comparator U13 are connected in parallel and then connected with a coupling response end-U.
In this embodiment, the mathematical model of the linear coupling circuit 2 is:
in the formula (3), u represents a linear coupling control term, K R The linear resistance coupling coefficient is expressed as,
R k denotes the linear resistance, R 0 The resistance can be adjusted as desired, 100K Ω.
In this embodiment, R23 ═ R24 ═ R25 ═ R26 ═ R28 ═ R29 ═ 10K Ω, and R27 ═ 100K Ω.
In this embodiment, each fractional equivalent capacitor is a fractional equivalent capacitor F, that is, F1 ═ F2 ═ F3 ═ F4 ═ F5 ═ F6 ═ F7 ═ F, and an equivalent circuit of the fractional equivalent capacitor F is shown in fig. 2:
one end of the a-th resistor Ra and one end of the first capacitor C1 are connected in parallel and then connected with the input port, the other end of the a-th resistor Ra and the other end of the first capacitor C1 are connected in parallel and then connected with one end of the b-th resistor Rb and one end of the second capacitor C2 respectively, the other end of the b-th resistor Rb and the other end of the second capacitor C2 are connected in parallel and then connected with one end of the C-th resistor Rc and one end of the third capacitor C3 respectively, and the other end of the C-th resistor Rc and the other end of the third capacitor C3 are connected in parallel and then connected with the output port.
In this embodiment, when the fractional order derivative q is 0.95, C1 is 3.616MF, C2 is 4.622MF, C3 is 1.267MF, Ra is 15.1K Ω, Rb is 1.51M Ω, and Rc is 692.9M Ω.
In the prior art, an integer order chaotic system is mostly used, and the chaotic characteristic of the integer order chaotic system is far lower than that of a fractional order chaotic system. Because the fractional order derivative or integral reflects the nature or quantity of a local or a certain point but comprehensively considers the influence of the past history and the non-local distribution, the fractional order chaotic system can more accurately describe the physical model of the actual chaos, and the analysis and research on the synchronous control of the fractional order system have a more universal application range. Moreover, from the viewpoint of energy control, the coupling strength of the coupled chaotic synchronization is much larger than that of the coupled synchronization realized in a chaotic or periodic state. Therefore, the invention realizes coupling synchronization by utilizing the fractional order chaos (q), and the fractional order system has the characteristics of historical memory and the like, has more complex dynamic characteristics and is difficult to decipher, and can greatly enhance the safety of chaotic secret communication.
The invention provides a method for designing a chaotic synchronization system based on resistance and fractional order equivalent capacitance coupling, which specifically comprises the following steps:
s1: constructing a mathematical model of a driving circuit at a driving end:
in the formula (4), x 1 ,x 2 ,x 3 Respectively showing the driving variables input by the first driving circuit, the second driving circuit and the third driving circuit,
are respectively x 1 ,x 2 ,x 3 Q denotes the fractional derivative.
Drive circuit simulation is realized by adopting Multisim software, so that the relation among all voltages in the built drive circuit satisfies formula (2), and based on the circuit principle, the state equation expression of the drive circuit is as follows:
the dimensionless equation of state mapped from equation (5) is expressed as follows:
in the formulas (5) and (6), V 1 、V 2 、V 3 The voltages of the first, second and third driving circuits are shown, respectively, and t is τ/t 0 ，R 0 ＝100kΩ,C 0 ＝10nF,t 0 ＝R 0 C 0 F represents a fractional order equivalent capacitance, let R 1 ＝R 2 ＝2.5kΩ，R 3 ＝R 5 ＝R 7 ＝10kΩ，R 4 ＝4kΩ，R 6 ＝33.3kΩ。
S2: and constructing a mathematical model of the response circuit at the response end according to the mathematical model of the driving circuit:
in the formula (7), y 1 ,y 2 ,y 3 Respectively representing the response variables output by the first response circuit, the second response circuit and the third response circuit,
are each y 1 ,y 2 ,y 3 Q denotes the fractional derivative.
In this embodiment, to achieve synchronization, the circuit structure of the response circuit and the circuit structure of the driving circuit need to be the same, so that signal synchronization can be better performed.
S3: and determining a mathematical model of the linear coupling term, and respectively improving the mathematical model of the driving circuit and the mathematical model of the response circuit to obtain the mathematical model of the coupling driving circuit and the mathematical model of the coupling response circuit.
The mathematical model of the linear coupling term is:
in the formula (8), u represents a linear coupling control term, K R The linear resistance coupling coefficient is expressed as,
R k denotes the linear resistance, R 0 The resistance can be adjusted as desired, 100K Ω.
Then the linear coupling term is combined with the driving circuit to obtain a coupled driving circuit, and the mathematical model of the coupled driving circuit is as follows:
the linear coupling term is combined with the response circuit to obtain a coupling response circuit, and the mathematical model of the coupling response circuit is as follows:
in the formulae (9) and (10), x 1 ,x 2 ,x 3 Respectively showing the driving variables input by the first driving circuit, the second driving circuit and the third driving circuit,
are respectively x 1 ,x 2 ,x 3 A derivative of (a); y is 1 ,y 2 ,y 3 Respectively representing the response variables output by the first response circuit, the second response circuit and the third response circuit,
are each y 1 ,y 2 ,y 3 Q denotes the fractional derivative, K R The linear resistance coupling coefficient is expressed by,
R 0 ＝100KΩ，R k the resistance value of the linear resistor can be adjusted according to the requirement.
S4: and defining the synchronization error of the coupling driving end and the coupling response end according to the formulas (9) and (10), obtaining an error system, and arranging the error system at the control end, thereby realizing the synchronization of the coupling driving end and the coupling response end.
In this embodiment, the mathematical model of the error system is:
in formula (11), e i ＝x i -y i ,i＝1,2,3；
q denotes the fractional derivative, K R The linear resistance coupling coefficient is expressed as,
R 0 ＝100KΩ；R k the resistance value of the linear resistor can be adjusted according to the requirement.
When e is i And (3) if the input signal is 0, i is 1,2 and 3 are gradually stable, the coupled driving end and the coupled response end can realize the synchronization of the fractional order chaotic system.
In this embodiment, the synchronization stability may be judged by using the lyapunov exponent criterion as follows:
for a nonlinear system equation, averaging the stretching or compressing rates of each point of the motion trajectory over a long period of time yields the Lyapunov exponent λ. If lambda is greater than 0, the motion orbit is unstable in each local part, adjacent points are separated in an exponential manner finally, and the chaotic attractor is formed after repeated folding under the action of the overall stability factor of the orbit; if lambda is less than 0, the movement track is also stable locally, and adjacent points are finally close to each other and correspond to periodic movement or stable balance points of a dynamic system; and λ is 0, which corresponds to a bifurcation point, and bifurcates from a negative to positive process, i.e. a multiple cycle process, to a chaotic process. Therefore, when all the lyapunov indexes of the error system (11) in S4 are negative, the state error thereof gradually goes to zero within a limited time, which indicates that the coupling driving end and the coupling responding end are synchronized.
As shown in FIG. 3, when q is 0.95, the maximum Lyapunov exponent in the error system follows K R Schematic view of the variation, can know
The maximum Lyapunov index values in the range are all negative, i.e. the linear resistance is selected
And meanwhile, the chaotic synchronization is realized by the coupling driving end and the coupling response end.
For example, let fractional order derivative q be 0.95, K R 1, i.e. linear resistance R k When the driving value is 100K omega, the driving variable x of the driving end (9) is coupled 1 ,x 2 ,x 3 Is (2,2,2), a response variable y of the coupled response terminal (10) 1 ,y 2 ,y 3 Is (-2, -5,5), the three Lyapunov indices of the error system (11) in S4 are calculated as λ 1 ＝-2.4781,λ 2 ＝-3.2007,λ 3 -5.7004, which is a negative number, indicating that the coupling driver and the coupling response are synchronized.
In this embodiment, the synchronization error of the error system
Multiple timesSimulation to obtain q as 0.95, K R 1, i.e. linear resistance R k As shown in fig. 4, the synchronization error value err (t) gradually goes to zero in a period of time (1s), and the coupling driving end and the coupling responding end reach full synchronization.
Compared with the prior art, the invention has the following advantages:
1. the safety is high: in the prior art, a general integer order chaotic system is mostly used, and the chaotic characteristic of the general integer order chaotic system is far lower than that of a fractional order chaotic system. The fractional order chaotic system can more accurately describe a physical model of an actual chaos. Because the fractional order derivative or integral reflects the nature or the number of a local or a certain point, the influence of past history and non-local distribution is comprehensively considered. Therefore, the fractional order chaotic system can better reflect the engineering physical phenomenon presented by the system, and has a more universal application range for analyzing and researching the synchronous control of the fractional order system. Moreover, from the viewpoint of energy control, the coupling strength of the coupled chaotic synchronization is much larger than that of the coupled synchronization realized in a chaotic or periodic state. Therefore, the invention realizes coupling synchronization by utilizing fractional order chaos, and the fractional order system has the characteristics of historical memory and the like, has more complex dynamic characteristics and is difficult to decipher, and can greatly enhance the safety of chaotic secret communication.
2. Synchronization is realized based on a linear coupling technology: the nonlinear system realizes the continuity and the persistence of coupling through linear feedback, and even under the interference of larger environmental noise, the coupled fractional order chaotic system can still realize synchronization and has stronger anti-noise capability. Therefore, through the linear coupling controller which is simple in structure and easy to implement, the fractional order chaotic system can achieve stable coupling synchronization, the chaotic synchronization system has strong inhibition capacity on noise interference and chaotic system parameter disturbance, and the coupling control fractional order chaotic synchronization system has better robustness. More importantly, mutually coupled nonlinear systems are ubiquitous in nature, and have a very prominent practical value due to the simple structure of the linear coupling of the present invention. In addition, the linear coupling synchronous system does not need to carry out calculation analysis in advance on the chaotic system, and the technology is feasible and easy to realize.
3. The cost is low: the existing fractional order chaotic synchronization system adopts more components, has large interference among signals and larger realization error; the invention can realize the coupling term only by one resistor and the fractional order equivalent capacitor, has simple device and structure, improves the robustness and the universality of the synchronous system and improves the safety of the communication system.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (9)
1. The chaotic synchronization system based on resistance and fractional order equivalent capacitance coupling is characterized by comprising a coupling driving end, a control end and a coupling response end; the coupling driving end is provided with a coupling driving circuit, the coupling response end is provided with a coupling response circuit, and the control end is provided with a linear coupling circuit; the coupling driving circuit is connected with the coupling response circuit through the linear coupling circuit.
2. The chaotic synchronization system based on resistive and fractional order equivalent capacitive coupling according to claim 1, wherein the coupling driving circuit comprises a first driving circuit, a second driving circuit and a third driving circuit;
the first drive circuit comprises a first drive variable terminal (x 1):
the other end of the first driving variable end (x1) is connected with one end of a first resistor (R1), the other end of the first resistor (R1), one end of a first fractional order equivalent capacitor (F1) and one end of a second resistor (R2) are connected in parallel and then connected with the inverting input end of a first comparator (U1), the non-inverting input end of the first comparator (U1) is grounded, the other end of the first fractional order equivalent capacitor (F1) is respectively connected with the first driving variable end (x1), the output end of the first comparator (U1) and one end of an eighth resistor (R8), the other end of an eighth resistor (R8) and one end of a ninth resistor (R9) are connected in parallel and then connected with the inverting input end of a fourth comparator (U4), the non-inverting input end of the fourth comparator (U4) is grounded, the output end of the fourth comparator (U4) and the other end of the ninth resistor (R9) are connected in parallel and then connected with one end of a third driving resistor (R3) in a second driving circuit, the other end of the second resistor (R2) is respectively connected with one end of a fourth resistor (R4) in the second driving circuit, the other end of an eleventh resistor (R11), the output end of a fifth comparator (U5) and the second input end of a second multiplier (X2) in the third driving circuit;
the second driving circuit comprises a second driving variable end (x2) and a coupling driving end (u):
the second driving variable end (X2) is connected with one end of a twenty-third resistor (R23) in the linear coupling circuit, the coupling driving end (U) is connected with one end of a thirtieth resistor (R30), the first input end of a first multiplier (X1) is connected with the first driving variable end (X1), the output end of a first multiplier (X1) is connected with one end of a fifth resistor (R5), the other end of a thirtieth resistor (R30), the other end of a third resistor (R3), the other end of a fourth resistor (R4), the other end of a fifth resistor (R5) and one end of a second fractional order equivalent capacitor (F2) are connected in parallel and then connected with the inverted input end of a second comparator (U2), the non-inverting input end of the second comparator (U2) is grounded, the other end of the second fractional equivalent capacitor (F2), the output end of the second comparator (U2) and the output end of a tenth resistor (R10) are connected in parallel and then connected with the second driving variable end (X2), the other end of the tenth resistor (R10) and one end of the eleventh resistor (R11) are connected in parallel and then connected with the inverting input end of the fifth comparator (U5), the non-inverting input end of the fifth comparator (U5) is grounded, and the other end of the eleventh resistor (R11) and the output end of the fifth comparator (U5) are connected in parallel and then connected with the other end of the second resistor (R2);
the third drive circuit includes a third drive variable terminal (x 3):
the third driving variable end (X3) is respectively connected with the second input end of the first multiplier (X1), one end of a sixth resistor (R6), the other end of a third fractional order equivalent capacitor (F3) and the output end of a third comparator (U3), the first input end of the second multiplier (X2) is connected with the first driving variable end (X1), the second input end of the second multiplier (X2) is connected with the other end of the second resistor (R2), the output end of the second multiplier (X2) is connected with one end of a seventh resistor (R7), the other end of the sixth resistor (R6), the other end of the seventh resistor (R7) and one end of the third fractional order equivalent capacitor (F3) are connected in parallel and then connected with the inverting input end of the third comparator (U3), and the non-inverting input end of the third comparator (U3) is grounded.
3. The chaotic synchronization system based on resistive and fractional order equivalent capacitive coupling according to claim 1, wherein the coupling response circuit comprises a first response circuit, a second response circuit, and a third response circuit;
the first response circuit includes a first response variable terminal (y 1):
a first response variable end (y1) is connected with one end of a sixteenth resistor (R16), the other end of the sixteenth resistor (R16), one end of a fourth fractional equivalent capacitor (F4) and one end of a seventeenth resistor (R17) are connected in parallel and then connected with an inverting input end of an eighth comparator (U8), a non-inverting input end of the eighth comparator (U8) is grounded, the other end of the fourth fractional equivalent capacitor (F4), an output end of the eighth comparator (U8) and one end of a fourteenth resistor (R14) are connected in parallel and then connected with a first response variable end (y1), the other end of the fourteenth resistor (R14) and one end of a twelfth resistor (R12) are connected in parallel and then connected with an inverting input end of a sixth comparator (U6), a non-inverting input end of the sixth comparator (U6) is grounded, an output end of a sixth comparator (U6) and the other end of the twelfth resistor (R12) are connected in parallel and then connected with one end of a eighteenth response circuit (R18), the other end of the seventeenth resistor (R17) is respectively connected with one end of a nineteenth resistor (R19) in the second driving circuit, the other end of a thirteenth resistor (R13), the output end of a seventh comparator (U7) and the second input end of a fourth multiplier (X4) in the third response circuit;
the second response circuit includes a second response variable terminal (y2) and a coupled response terminal (-u):
the output end of the linear coupling circuit is connected with a coupling response end (-U), the coupling response end (-U) is also connected with one end of a thirty-first resistor (R31), the first input end of a third multiplier (X3) is connected with a first response variable end (y1), the output end of a third multiplier (X3) is connected with one end of a twentieth resistor (R20), the other end of the thirty-first resistor (R31), the other end of an eighteenth resistor (R18), the other end of a nineteenth resistor (R19), the other end of a twentieth resistor (R20) and one end of a fifth fractional equivalent capacitor (F5) are connected in parallel and then connected with the inverted input end of a ninth comparator (U9), the non-inverting input end of the ninth comparator (U9) is grounded, the other end of the fifth fractional equivalent capacitor (F5), the output end of the ninth comparator (U9) and one end of a fifteenth resistor (R15) are connected in parallel and then connected with a second response variable end (Y2), the second response variable end (y2) is also connected with one end of a twenty-fourth resistor (R24) in the linear coupling circuit, the other end of a fifteenth resistor (R15) and one end of a thirteenth resistor (R13) are connected in parallel and then connected with the inverting input end of a seventh comparator (U7), the non-inverting input end of the seventh comparator (U7) is grounded, and the other end of the thirteenth resistor (R13) and the output end of the seventh comparator (U7) are connected in parallel and then connected with the other end of a seventeenth resistor (R17);
the third response circuit includes a third response variable terminal (y 3):
the third response variable end (y3) is respectively connected with the second input end of a third multiplier (X3), one end of a twenty-first resistor (R21), the other end of a sixth fractional order equivalent capacitor (F6) and the output end of a tenth comparator (U10), the first input end of a fourth multiplier (X4) is connected with the first response variable end (y1), the second input end of a fourth multiplier (X4) is connected with the other end of a seventeenth resistor (R17), the output end of the fourth multiplier (X4) is connected with one end of a twenty-second resistor (R22), the other end of a twenty-first resistor (R21), the other end of a twenty-second resistor (R22) and one end of a sixth fractional order equivalent capacitor (F6) are connected in parallel and then connected with the inverting input end of the tenth comparator (U10), and the non-inverting input end of the tenth comparator (U10) is grounded.
4. The chaotic synchronization system based on resistive and fractional order equivalent capacitive coupling according to claim 1, wherein the linear coupling circuit comprises a linear resistor (R) k ) And a seventh fractional equivalent capacitance (F7):
one end of a twenty-third resistor (R23) is connected with the second driving variable terminal (x2), one end of a twenty-fourth resistor (R24) is connected with the second response variable terminal (y2), and the twenty-third resistorThe other end of the resistor (R23) and one end of a twenty-sixth resistor (R26) are connected in parallel and then connected with the inverting input end of an eleventh comparator (U11), the other end of the twenty-fourth resistor (R24) and one end of a twenty-fifth resistor (R25) are connected in parallel and then connected with the non-inverting input end of the eleventh comparator (U11), the other end of the twenty-fifth resistor (R25) is grounded, the other end of the twenty-sixth resistor (R26) and the output end of the eleventh comparator (U11) are connected in parallel and then respectively connected with a linear resistor (R3525) k ) Is connected to one end of a seventh fractional order equivalent capacitor (F7), and a linear resistor (R) k ) The other end of the third fractional order equivalent capacitor (F7), the other end of the seventh fractional order equivalent capacitor (F7), and one end of a twenty-seventh resistor (R27) are connected in parallel and then connected with the inverting input end of a twelfth comparator (U12), the non-inverting input end of the twelfth comparator (U12) is grounded, the output end of the twelfth comparator (U12), the other end of the twenty-seventh resistor (R27), and one end of a twenty-eighth resistor (R28) are connected in parallel and then connected with the coupling driving end (U), the other end of the twenty-eighth resistor (R28), and one end of a twenty-ninth resistor (R29) are connected in parallel and then connected with the inverting input end of a thirteenth comparator (U13), the non-inverting input end of the thirteenth comparator (U13) is grounded, and the other end of the twenty-ninth resistor (R29), and the output end of the thirteenth comparator (U13) are connected in parallel and then connected with the coupling response end (-U).
5. The chaotic synchronization system based on the coupling of the resistance and the fractional order equivalent capacitance of claim 4, characterized in that the equivalent circuit of the seventh fractional order equivalent capacitance (F7) is:
one end of an a-th resistor (Ra) and one end of a first capacitor (C1) are connected in parallel and then connected with the input port, the other end of the a-th resistor (Ra) and the other end of a first capacitor (C1) are connected in parallel and then respectively connected with one end of a b-th resistor (Rb) and one end of a second capacitor (C2), the other end of the b-th resistor (Rb) and the other end of a second capacitor (C2) are connected in parallel and then respectively connected with one end of a C-th resistor (Rc) and one end of a third capacitor (C3), and the other end of the C-th resistor (Rc) and the other end of a third capacitor (C3) are connected in parallel and then connected with the output port.
6. The chaotic synchronization method based on resistance and fractional order equivalent capacitance coupling is characterized by comprising the following steps:
s1: constructing a mathematical model of a driving end:
in the formula (1), x 1 ,x 2 ,x 3 Respectively, the drive variables are represented by,
are respectively x 1 ,x 2 ,x 3 Q denotes a fractional derivative;
s2: and (3) constructing a mathematical model of the response end according to the mathematical model of the driving end:
in the formula (2), y 1 ,y 2 ,y 3 Respectively, the response variables are represented as,
are each y 1 ,y 2 ,y 3 A derivative of (a);
s3: determining a linear coupling term, and respectively improving the driving end and the response end to obtain a coupling driving end and a coupling response end;
the mathematical model of the linear coupling term is:
in the formula (3), u represents a linear coupling control term, K R The linear resistance coupling coefficient is expressed as,
R k denotes the linear resistance, R 0 ＝100KΩ；
The linear coupling term is combined with the driving end to obtain a coupling driving end, and the mathematical model of the coupling driving end is as follows:
the linear coupling term and the response end are combined to obtain a coupling response end, and the mathematical model is as follows:
in the formulae (4) and (5), x 1 ,x 2 ,x 3 The drive variable is represented by a number of drive variables,
are respectively x 1 ,x 2 ,x 3 A derivative of (a); y is 1 ,y 2 ,y 3 A response variable is represented that indicates the response of the variable,
are each y 1 ,y 2 ,y 3 Q denotes a fractional derivative;
s4: defining a synchronous error between the coupling driving end and the coupling response end according to formulas (4) and (5) to obtain an error system, and arranging the error system at the control end to realize the synchronization of the coupling driving end and the coupling response end;
the mathematical model of the error system is:
in the formula (6), e i ＝x i -y i ,i＝1,2,3；
7. The method for designing the chaotic synchronization system based on the coupling of the resistance and the fractional order equivalent capacitance according to claim 6, wherein in the step S1, a circuit state equation corresponding to a mathematical model at the driving end is as follows:
the dimensionless equation of state mapped by the circuit equation of state (5) is expressed as follows:
in the formulas (7) and (8), V1, V2 and V3 respectively represent voltages corresponding to x 1 ,x 2 ,x 3 ；t＝τ/t 0 ，R 0 ＝100kΩ,C 0 ＝10nF,t 0 ＝R 0 C 0 F represents a fractional order equivalent capacitance, let R 1 ＝R 2 ＝2.5kΩ，R 3 ＝R 5 ＝R 7 ＝10kΩ，R 4 ＝4kΩ，R 6 ＝33.3kΩ。
8. The method for designing the chaotic synchronization system based on the coupling of the resistance and the fractional order equivalent capacitance according to claim 6, wherein in the step S4, the synchronization error of the error system
e i ＝x i -y i ,i＝1,2,3。
9. The method as claimed in claim 6, wherein in S3, q is 0.95, K is R ＝1。
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