CN114866214A - Method, device and medium for dynamically adjusting long burst communication bit synchronization - Google Patents
Method, device and medium for dynamically adjusting long burst communication bit synchronization Download PDFInfo
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- CN114866214A CN114866214A CN202210299662.8A CN202210299662A CN114866214A CN 114866214 A CN114866214 A CN 114866214A CN 202210299662 A CN202210299662 A CN 202210299662A CN 114866214 A CN114866214 A CN 114866214A
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- 238000004891 communication Methods 0.000 title claims abstract description 33
- 238000013139 quantization Methods 0.000 claims abstract description 5
- 238000005070 sampling Methods 0.000 claims description 31
- 238000004590 computer program Methods 0.000 claims description 8
- 125000004122 cyclic group Chemical group 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 4
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a method, a device and a medium for dynamically adjusting long burst communication bit synchronization, which belong to the field of electromagnetic signal communication and comprise the following steps: step 1, collecting signals, transferring the collected signal quantization data to a processor, and completing related capture; step 2, after capturing the signal, extracting data into a signal which is multiple times of the symbol rate and is acquired, and sending the signal into an O & M timing estimation algorithm for estimating value; step 3, interpolating the current data according to the estimation result; step 4, adjusting the data in real time according to the last estimation result before the next estimation; step 5, performing O & M timing estimation on the adjusted data; and 6, circulating the steps 2 to 5. The invention can carry out real-time bit synchronization on burst long signals, resist symbol drift caused by clock error of a receiver and a transmitter and ensure that all symbols are correctly received.
Description
Technical Field
The present invention relates to the field of electromagnetic signal communication, and more particularly, to a method, an apparatus, and a medium for dynamically adjusting bit synchronization in long burst communication.
Background
In a radio measurement and control equipment receiver based on a software radio idea, a signal sampling frequency point is advanced to an intermediate frequency, and after digital down-conversion, an output baseband signal is a sampling sequence and is not a time continuous analog signal waveform any more. The actual shape of the sampled waveform is not important because all waveforms with the same sampling result are equivalent for detection, and because of the different code rates, the number of samples representing a symbol in the input sample sequence will be different. The core of the bit synchronization problem is no longer how to precisely control the sampling clock phase, but rather to make decisions on the received symbols at precise decision times, more precisely estimating the location of the best decision point for each symbol. Currently, the most widely used timing error algorithms are Gardner timing synchronization and DFT-based O & M timing synchronization algorithms.
The basic idea of the Gardner algorithm is: the amplitude and polarity change information at the decision sampling point of the adjacent code elements is extracted, and the timing error can be extracted from the sampling signal by adding whether the over-searching point between the adjacent code elements is zero or not. The timing error is used for controlling the next sampling moment to be adjusted after certain processing. Therefore, the Gardner algorithm is actually a closed-loop convergence loop, a certain number of symbols are needed to converge the loop, and the symbols in the convergence process are not available and are not suitable for burst communication.
The basic idea of the O & M timing synchronization algorithm is: using the frequency domain delay theorem of the Discrete Fourier Transform (DFT) algorithm, the timing offset will be embodied as the phase error of the associated peak DFT, and the timing error estimate can be obtained by the following formula.
Wherein M is DFT point number, k is over-sampling rate, and N is sequence tailing. And combining the front correlation peak and the rear correlation peak to carry out timing error estimation.
It can be seen that the O & M timing synchronization algorithm is actually an open-loop estimation, and although the best sampling point of the current M point data can be accurately found, it cannot resist the symbol drift caused by the clock error of the receiver and the transmitter in long-time communication.
Disclosure of Invention
The present invention aims to overcome the defects of the prior art, and provides a dynamic adjustment method, a device and a medium for bit synchronization of long burst communication, which can perform real-time bit synchronization on burst long signals, resist symbol drift caused by clock errors of a receiver and a transmitter, and ensure that all symbols are correctly received.
The purpose of the invention is realized by the following scheme:
a dynamic adjusting method for long burst communication bit synchronization includes the following steps:
and interpolating and adjusting the optimal sampling point in real time through a cyclic O & M timing estimation algorithm to finish the extraction of the optimal sampling point of the burst long-time communication signal.
Further, comprising the sub-steps of:
step 5, performing O & M timing estimation on the adjusted data;
and 6, circulating the steps 2 to 5.
Further, in step 1, the acquiring the signal includes acquiring the signal through an AD module.
Further, in step 1, the processor comprises an FPGA processor.
Further, in step 2, the multiple is 4 times.
Further, in step 4, the real-time adjustment of the data is specifically a real-time adjustment of AD data.
Further, the real-time adjustment of the data comprises the sub-steps of:
discarding an AD sample point when the estimated phase is advanced pi/2 compared to the predetermined phase; when the estimated phase lags pi/2 compared with the preset phase, backing off an AD sampling point; when the evaluation phase agrees with the predetermined phase, no operation is performed.
Further, in step 5, the adapted data comprises adapted AD data.
A long burst communication bit synchronization dynamic adjustment device comprising a processor and a memory, said memory having stored therein a computer program which, when loaded by said processor, performs the method as defined in any one of the preceding claims.
A computer-readable storage medium, in which a computer program is stored which is loaded by a processor and which performs the method according to any of the above.
The beneficial effects of the invention include:
the invention makes up the deficiency of O & M timing estimation algorithm and Gardner timing estimation algorithm at the same time, can carry on the real-time bit synchronization to the burst long signal, resist the symbol drift brought by clock error of the receiver and launcher, guarantee all symbols are received correctly.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of the estimated phase advance predetermined phase pi/2 in an embodiment of the present invention;
FIG. 2 is a schematic diagram of the estimated phase lag predetermined phase pi/2 in an embodiment of the present invention;
FIG. 3 is a diagram illustrating the estimated phase coinciding with the predetermined phase in an embodiment of the present invention;
FIG. 4 is a state machine jump diagram in an embodiment of the present invention;
FIG. 5 is a flow chart of method steps in an embodiment of the present invention.
Detailed Description
All features disclosed in all embodiments of the present specification, or all methods or process steps implicitly disclosed, may be combined and/or expanded, or substituted, in any way, except for mutually exclusive features and/or steps.
The technical concept, the technical problems to be solved, the working principle, the working process and the advantages of the present invention will be fully described in detail with reference to the accompanying drawings 1 to 5.
The invention aims to solve the bit synchronization problem of long-time burst communication in engineering, namely, under the condition of not losing any symbol, the method, the equipment and the medium for dynamically adjusting the bit synchronization of the long-time burst communication can be used for carrying out long-time optimal sampling point estimation on burst communication signals, and the method, the equipment and the medium for dynamically adjusting the bit synchronization of the long-time burst communication are realized, so that all communication symbols are ensured to be correctly received in the long-time burst communication.
In the practical application process, the method comprises the following steps:
step 1: signals are collected through AD, collected signal quantization data are transferred to the FPGA, and relevant capture is completed;
step 2: after capturing the signal, the data is extracted to 4 times the symbol rate of the over-sampled signal and sent to the O & M timing estimation for estimation.
And step 3: and interpolating the current data according to the estimation result.
And 4, step 4: before the next estimation, the AD data is adjusted in real time according to the last estimation result, and when the estimation phase is advanced pi/2 compared with the preset phase, one AD sampling point is discarded, as shown in FIG. 1; when the estimated phase lags pi/2 compared with the predetermined phase, an AD sampling point is backed off, as shown in fig. 2, and when the estimated phase matches the predetermined phase, no operation is performed, as shown in fig. 3 and 4, and S1, S2, and S3 in fig. 4 indicate the corresponding states.
And 5: o & M timing estimation is performed on the adjusted AD data.
Step 6: and (6) circulating the steps 2 to 5.
The embodiment of the invention has the following advantages:
the embodiment of the invention simultaneously makes up the defects of an O & M timing estimation algorithm and a Gardner timing estimation algorithm, can perform real-time bit synchronization on burst long signals, resists symbol drift caused by clock errors of a receiver and a transmitter, and ensures that all symbols are correctly received.
Example 1: a dynamic adjusting method for long burst communication bit synchronization includes the following steps:
and (3) interpolating and adjusting the optimal sampling point in real time to complete the extraction of the optimal sampling point of the burst long-time communication signal through a cyclic O & M timing estimation algorithm.
Example 2: on the basis of the embodiment 1, the method comprises the following substeps:
step 5, performing O & M timing estimation on the adjusted data;
and 6, circulating the steps 2 to 5.
Example 3: on the basis of embodiment 2, in step 1, the acquiring the signal includes acquiring the signal through an AD module.
Example 4: on the basis of embodiment 2, in step 1, the processor comprises an FPGA processor.
Example 5: on the basis of example 2, in step 2, the multiple is 4 times.
Example 6: on the basis of embodiment 2, in step 4, the real-time adjustment of the data is specifically performed on AD data.
Example 7: on the basis of embodiment 2, the real-time adjustment of the data comprises the sub-steps of:
discarding an AD sample point when the estimated phase is advanced pi/2 compared to the predetermined phase; when the estimated phase lags pi/2 compared with the preset phase, backing off an AD sampling point; when the estimated phase coincides with the predetermined phase, no operation is performed.
Example 8: on the basis of embodiment 2, in step 5, the adjusted data includes adjusted AD data.
Example 9: a long burst communication bit synchronization dynamic adjustment device, characterized in that the long burst communication bit synchronization dynamic adjustment device comprises a processor and a memory, wherein the memory has stored therein a computer program, which when loaded by the processor and executes the method according to any of embodiments 1 to 8.
Example 10: a computer-readable storage medium, in which a computer program is stored which is loaded by a processor and which performs the method according to any one of embodiments 1 to 8.
Example 11
Based on the embodiment 1, let AD be zero intermediate frequency sampling, the sampling rate be 122.88MHz, and the signal symbol rate be 400 KHz. And after receiving the original data, the FPGA captures the signal. And after capturing the signal, extracting the signal, and performing O & M timing estimation when the sampling rate is 4 times of the symbol rate. The O & M timing estimate length is 2048 points, estimated every 8192 points. And interpolating the signals according to the estimation result to find out the optimal sampling point. And before the next estimation, judging the current estimation value, and returning two AD sampling points for estimation when the estimation value point lags behind the target point by two sampling points. And if the estimated point lags behind the target point by one sampling point, returning an AD sampling point for estimation in the next estimation. If the estimated point lags behind the target point by one sampling point, one AD sampling point is discarded in the next estimation and then the estimation is carried out. And if the evaluation point is matched with the target point, directly carrying out the next evaluation without operation.
The units described in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be disposed in a processor. Wherein the names of the elements do not in some way constitute a limitation on the elements themselves.
According to an aspect of the application, a computer program product or computer program is provided, comprising computer instructions, the computer instructions being stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the method provided in the various alternative implementations described above.
As another aspect, the present application also provides a computer-readable medium, which may be contained in the electronic device described in the above embodiments; or may exist separately without being assembled into the electronic device. The computer readable medium carries one or more programs which, when executed by an electronic device, cause the electronic device to implement the method described in the above embodiments.
The parts not involved in the present invention are the same as or can be implemented using the prior art.
The above-described embodiment is only one embodiment of the present invention, and it will be apparent to those skilled in the art that various modifications and variations can be easily made based on the application and principle of the present invention disclosed in the present application, and the present invention is not limited to the method described in the above-described embodiment of the present invention, so that the above-described embodiment is only preferred, and not restrictive.
Other embodiments than the above examples may be devised by those skilled in the art based on the foregoing disclosure, or by adapting and using knowledge or techniques of the relevant art, and features of various embodiments may be interchanged or substituted and such modifications and variations that may be made by those skilled in the art without departing from the spirit and scope of the present invention are intended to be within the scope of the following claims.
Claims (10)
1. A dynamic adjustment method for bit synchronization of long burst communication is characterized by comprising the following steps:
and (3) interpolating and adjusting the optimal sampling point in real time to complete the extraction of the optimal sampling point of the burst long-time communication signal through a cyclic O & M timing estimation algorithm.
2. The dynamic bit synchronization adjustment method for long burst communication according to claim 1, comprising the sub-steps of:
step 1, collecting signals, transferring the collected signal quantization data to a processor, and completing related capture;
step 2, after capturing the signal, extracting data into a signal which is multiple times of the symbol rate and is acquired, and sending the signal into an O & M timing estimation algorithm for estimating value;
step 3, interpolating the current data according to the estimation result;
step 4, adjusting the data in real time according to the last estimation result before the next estimation;
step 5, performing O & M timing estimation on the adjusted data;
and 6, circulating the steps 2 to 5.
3. The dynamic adjustment method for bit synchronization in long burst communication according to claim 2, wherein in step 1, the acquiring the signal includes acquiring the signal through an AD module.
4. The dynamic adjustment method for long burst communication bit synchronization according to claim 2, wherein in step 1, the processor comprises an FPGA processor.
5. The dynamic adjustment method for bit synchronization in long burst communication according to claim 2, wherein in step 2, the multiple is 4 times.
6. The dynamic bit synchronization adjustment method for long burst communication according to claim 2, wherein in step 4, the real-time adjustment of data is specifically real-time adjustment of AD data.
7. The dynamic adjustment method for bit synchronization in long burst communication according to claim 2, wherein the real-time adjustment of data comprises the sub-steps of:
discarding an AD sample point when the estimated phase is advanced pi/2 compared to the predetermined phase; when the estimated phase lags pi/2 compared with the preset phase, backing off an AD sampling point; when the estimated phase coincides with the predetermined phase, no operation is performed.
8. The dynamic bit synchronization adjustment method for long burst communication according to claim 2, wherein in step 5, the adjusted data comprises adjusted AD data.
9. A long burst communication bit synchronization dynamic adjustment device, characterized in that the long burst communication bit synchronization dynamic adjustment device comprises a processor and a memory, wherein the memory has stored therein a computer program, which when loaded by the processor and executes the method according to any of the claims 1 to 8.
10. A computer-readable storage medium, in which a computer program is stored which is loaded by a processor and which performs the method according to any one of claims 1 to 8.
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Application publication date: 20220805 |