CN114865452A - Efficient vertical cavity surface EML chip with oxidation isolation layer and preparation method - Google Patents

Abstract

The invention discloses a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer and a preparation method thereof, wherein the high-efficiency vertical cavity surface EML chip comprises a VCSEL unit, the oxidation isolation layer and an EOM unit, and the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and is used for preventing the electric potential at the contact position of the two units from influencing the working current in the respective units. The invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. Meanwhile, the invention innovatively creates a differential oxidation method, and the oxidation isolation layer and the oxidation limiting layer can be formed in the same oxidation process by accurately designing the aluminum content deviation of the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer, so that the chip process is greatly simplified and the production cost is reduced.

Description

Efficient vertical-cavity surface EML chip with oxidation isolation layer and preparation method

Technical Field

The invention relates to the technical field of semiconductor photoelectron, in particular to a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer and a preparation method thereof.

Background

With the rapid development of the data communication era, Vertical Cavity Surface Emitting Laser (VCSEL) chips are widely used in the optical communication fields, such as optical interconnection, optical sensing, optical storage, and application scenarios such as data center short-distance communication, 5G base station, HDMI ultra high definition video transmission, etc., due to their excellent characteristics, such as small chip volume, circular light spot output, low working threshold, high coupling efficiency, and convenient integration. The VCSEL chip has good economical efficiency, practicability and reliability, and brings great convenience for information exchange in various industries.

As the amount of data increases, higher requirements are placed on the rate and quality of data transmission. At present, a VCSEL chip mostly adopts a direct modulation working mode to carry out signal transmission, namely, high-speed radio frequency electric signals are adopted for direct modulation. With the increase of the modulation rate, the directly modulated VCSEL chip is prone to generate a Chirp (Chirp) phenomenon during its operation, which may limit the transmission rate of the laser chip, and when the transmission distance increases, transmission Crosstalk (Crosstalk) and optical power attenuation may also be generated, thereby reducing the transmission quality of the signal. If a higher modulation rate is to be achieved, the current density needs to be increased by multiple times without changing the modulation mode, which leads to the problems of increased chip power consumption and shortened lifetime.

Similar to the edge-emitting EML chip, which is an edge-emitting laser chip monolithically integrated with a light-emitting unit DFB and a modulation unit, the conventional vertical-cavity EML chip is a vertical-emitting laser chip monolithically integrated with a light-emitting unit (VCSEL unit) and a modulation unit (EOM unit), and is generally in a structure of "NDBR-active region-oxide confinement layer-PDBR-absorption region-NDBR", and the VCSEL unit and the EOM unit respectively realize optical resonance of the VCSEL unit and enhance light absorption of the EOM unit by sharing the PDBR. However, since there is no electrical isolation between the VCSEL unit and the EOM unit, when a high frequency modulation signal is applied to the EOM unit, the current in the VCSEL unit is affected, thereby affecting the stable output of the VCSEL unit.

Based on the structure, the high-efficiency vertical cavity surface EML chip with the oxidation isolation layer and the preparation method thereof are provided.

Disclosure of Invention

The invention provides a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer and a preparation method thereof, and mainly aims to solve the problems in the prior art.

The invention adopts the following technical scheme:

a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer comprises a VCSEL unit, the oxidation isolation layer and an EOM unit, wherein:

the VCSEL unit comprises a substrate, a buffer layer, a first DBR, a resonant cavity and a second DBR from bottom to top, and the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting layer from bottom to top;

the EOM unit comprises a third DBR, an absorption region and a fourth DBR from bottom to top;

the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential of the contact position of the two units from influencing the working current in the respective units.

The invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. Compared with the mode that the VCSEL unit and the EOM unit are in direct contact in the prior art, the electrical isolation can reduce RC delay in the high-frequency signal transmission process, is beneficial to improving transmission performance, and realizes a better modulation effect.

The high-efficiency vertical cavity surface EML chip further comprises a first electrode, a second annular electrode, a third annular electrode and a fourth annular electrode, wherein:

the first electrode can be a first planar electrode arranged on the lower surface of the substrate or a first annular electrode arranged on the upper surface of the first DBR;

the second annular electrode is arranged on the upper surface of the second DBR;

the third ring electrode is arranged on the upper surface of the third DBR;

the fourth ring-shaped electrode is disposed on an upper surface of the fourth DBR.

Since an oxidation isolation layer having an electrical isolation effect is disposed between the VCSEL unit and the EOM unit, the electrodes cannot be shared, and a four-electrode structure is required. In practical applications, the first electrode can be configured as a first planar electrode or a first ring electrode as required to meet different application scenarios, such as TOP-TOP contact type and TOP-BOTTOM contact type applications.

The substrate is made of GaAs, and the thickness of the oxidation isolation layer and the oxidation limiting layer is 5-5000 nm. The GaAs material system has higher reliability, and when the resonant cavity of the VCSEL unit and the absorption region of the EOM unit both adopt the GaAs material system, the physical properties of the materials of the two units are similar, so that the stability of epitaxial deposition of a chip can be greatly improved, and the difficulty of mass production is reduced.

The GaAs-based material system, and the material of the oxidation isolation layer is Al ₂ O ₃ ，Al ₂ O ₃ Has good electrical insulation effect and is an ideal material for oxidizing the isolation layer. The oxidation isolation layer is formed by oxidizing an oxidation isolation prefabricated layer through a wet oxidation process, and the material of the oxidation isolation prefabricated layer is doped or undoped Al _x Ga _1-x As. The oxidation limiting layer is formed by an oxidation limiting prefabricated layer through a wet oxidation process, and Al with optical and electrical limiting functions is formed in an oxidation area ₂ O ₃ Non-oxidized regionThe pore diameter range of (A) is 2-100 μm; the oxidation limiting prefabricated layer is doped or undoped Al _y Ga _1-y As. It can be seen that the prefabricated layer materials of the oxidation limiting layer and the oxidation isolating layer are AlGaAs materials and are matched with the crystal lattices of a GaAs substrate system, so that one-time epitaxial growth can be realized, the epitaxial production difficulty is reduced, the mass production is facilitated, the epitaxial crystal quality of the VCSEL unit and the EOM unit is ensured, and the reliability of the device is improved.

In the preparation process, because the oxidation-limiting prefabricated layer needs to be partially oxidized to form the photoelectric-limiting aperture, and the oxidation-isolating prefabricated layer needs to be fully oxidized to form the oxidation isolating layer, if the oxidation-limiting prefabricated layer and the oxidation isolating layer are prepared in the same oxidation process, the oxidation-limiting prefabricated layer Al needs to be controlled _y Ga _1-y The aluminum content y of As is less than that of the oxidation isolation prefabricated layer Al _x Ga _1-x Aluminum content x of As. The invention innovatively creates a differential oxidation method, and the alumina content deviation of the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer is accurately designed, so that the oxidation isolation layer and the oxidation limiting layer can be formed in the same oxidation process, the chip process is greatly simplified, and the production cost is reduced.

The first DBR, the second DBR, the third DBR and the fourth DBR are made of Al _i Ga _1-i As/Al _j Ga _1-j A periodic structure of As material. Because the oxidation isolation prefabricated layer adopts Al with higher aluminum content _x Ga _1-x As material, on one hand, in order to prevent the first to fourth DBRs from being excessively oxidized, and on the other hand, since the device resistance is increased due to the increased aluminum content, it should be ensured that Al, which is a material constituting the first to fourth DBRs, is Al _i Ga _1-i As/Al _j Ga _1-j The aluminum content i and j of As is less than that of the oxidation isolation prefabricated layer Al _x Ga _1-x Aluminum content x of As. In addition, care should be taken in applications to avoid the use of aluminum arsenide materials.

As one embodiment thereof, the Al _x Ga _1-x The value range of Al content of As is that x is more than or equal to 0.97; the Al is _i Ga _1-i As/Al _j Ga _1-j Aluminum content i of As andthe value range of j is that i is less than or equal to 0.92, and j is less than or equal to 0.92; the Al is _y Ga _1-y The value range of Al content of As is more than 0.92 and less than 0.97.

As one embodiment, the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; the fourth DBR is a second P-type doped DBR. It can be seen that the epitaxial structure provided by the present invention is an NP-O-NP structure, but in practical applications, the epitaxial structure can be further adjusted to be an NP-O-PN, PN-O-NP or PN-O-PN structure as required, where N refers to an N-type doped DBR, P refers to a P-type doped DBR, and O refers to an oxide isolation layer.

The resonant cavity is of a sandwich structure of a lower waveguide, an active region and an upper waveguide, optical and electrical limitation is carried out by adopting an oxidation limiting layer, and the cavity length of the resonant cavity is integral multiple of the half-lasing wavelength. The gain structure of the quantum well of the resonant cavity can be a single quantum well, a multiple quantum well, a tunnel junction cascade quantum well or a quantum dot, and can be specifically selected from one of InGaAs/GaAs, InGaAs/AlGaAs, InGaAs/GaAsP, GaAs/AlGaAs, AlInGaAs/AlGaAs, InGaAsP/AlGaAs and AlGaInP/GaAs.

With the quantum well of the resonant cavity, the quantum well material of the absorption region can also be one of InGaAs/GaAs, InGaAs/AlGaAs, InGaAs/GaAsP, GaAs/AlGaAs, AlInGaAs/AlGaAs, InGaAsP/AlGaAs and AlGaInP/GaAs, but in order to realize modulation, the wavelength of the quantum well of the absorption region should be controlled to be 5-99nm shorter than that of the quantum well of the resonant cavity.

The absorption region is of a single quantum well or multi-quantum well structure; when the absorption region is of a single quantum well structure, a third waveguide layer is arranged between the absorption region and the second N-type doped DBR, and a fourth waveguide layer is arranged between the absorption region and the second P-type doped DBR. This is due to the fact that the single quantum well structure requires the formation of the FP cavity as the VCSEL unit, but the FP cavity in the absorption region is a passive F-P to enhance absorption, rather than an active F-P as in the VCSEL unit.

When the absorption region adopts a pair of quantum well structures, the EOM unit realizes the modulation of the light intensity of the VCSEL unit based on Quantum Confinement Stark Effect (QCSE). By modulating the bias voltage of the EOM unit, the movement of the absorption sideband of the absorption region is directly realized, and the high-speed modulation of the output light intensity of the VCSEL is indirectly realized. Compared with the traditional direct modulation mode, the high-efficiency modulation using the EOM modulation unit can reduce the design limitation of the VCSEL unit, thereby being beneficial to improving the photoelectric conversion efficiency and optimizing the structural design of the VCSEL unit.

When the absorption region adopts a plurality of pairs of quantum well structures, the EOM unit realizes the modulation of the light intensity of the VCSEL unit based on the reflectivity deviation of the top reflector and the bottom reflector. The bias voltage of the EOM unit is modulated, so that the absorption state of the absorption region is directly influenced, the integral reflectivity of the top reflector is further controlled, and the high-speed modulation of the output light intensity of the VCSEL is indirectly realized.

A preparation method of a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer is characterized by comprising the following steps:

(1) growing a buffer layer, a first DBR, a resonant cavity, a second DBR, an oxidation isolation prefabricated layer, a third DBR, an absorption region and a fourth DBR on a substrate in sequence; the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting prefabricated layer;

(2) preparing a first planar electrode on the lower surface of the buffer layer or preparing a first annular electrode on the upper surface of the first DBR;

(3) manufacturing a second annular electrode on the upper surface of the second DBR;

(4) and oxidizing the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer by adopting a wet oxidation process to form an oxidation isolation layer and an oxidation limiting layer.

(5) And manufacturing a third ring-shaped electrode on the upper surface of the third DBR, and manufacturing a fourth ring-shaped electrode on the upper surface of the fourth DBR.

Further, in the step (1), the epitaxial wafer is grown by metal organic vapor deposition.

Further, in step (1), when the quantum well of the absorption region is a single quantum well structure, it should be noted that a third waveguide layer must be deposited between the absorption region and the third DBR, and a fourth waveguide layer must be deposited between the absorption region and the fourth DBR.

Further, in the step (2), the first electrode in the present invention is preferably a first planar electrode, and the first planar electrode is prepared by etching the substrate by using ICP to expose the buffer layer, and on the surface of the buffer layer away from the first DBR.

Further, in the step (3), a contact layer selective mask SiNx is formed on the upper surface of the second DBR through a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, a photoetching and Reactive Ion Etching (RIE) process, selective edge etching is performed through ICP etching, so that the epitaxial structure above the top of the second DBR is etched to the upper surface of the second DBR, and then the contact layer selective mask SiNx is removed through BOE; and finally, forming a second annular electrode on the upper surface of the second DBR through a photoetching process, an electron beam metal layer evaporation process and a stripping process.

Further, in the step (4), the reason why the oxidation process of oxidizing the isolation preform layer and the oxidation-limiting preform layer after the first electrode and the second ring-shaped electrode are prepared is selected is that: firstly, the advantage that the metal layers (the first electrode and the second annular electrode) are aligned more accurately can be fully utilized in the oxidation process, and the oxidation process is ensured to be accurate and controllable; secondly, the oxidation area of the oxidation process can be reduced by the electrode etching process, so that the oxidation time can be greatly saved, and the uniformity of oxidation is improved; thirdly, the oxidation isolation prefabricated layer and the oxidation limit prefabricated layer can generate stress after being oxidized, and certain influence can be generated on the etching step of the metal electrode part, so that the metal electrode part needs to be manufactured firstly.

Further, in the step (5), the preparation method of the third ring electrode is the same as that of the second ring electrode, and is not described herein again, but it should be noted that during the ICP etching, the selective edge etching must be performed on the epitaxial structure above 200nm away from the bottom of the third DBR to prevent the etching depth from exceeding the oxide isolation layer, which results in the oxide isolation layer failing. The fourth ring-shaped electrode is prepared by a conventional process, which is not described herein. The third annular electrode and the fourth annular electrode are selected to be prepared after the oxidation process because whether the oxidation isolation prefabricated layer is sufficiently oxidized to form the oxidation isolation layer needs to be observed under an infrared microscope in the oxidation process, and if the metal layer above the oxidation isolation prefabricated layer is oxidized again, the appearance condition of the oxidation isolation layer is not favorably observed.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. Compared with the mode that the VCSEL unit and the EOM unit are in direct contact in the prior art, the electrical isolation can reduce RC delay in the high-frequency signal transmission process, is beneficial to improving transmission performance, and realizes a better modulation effect.

The invention innovatively creates a differential oxidation method, and the alumina content deviation of the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer is accurately designed, so that the oxidation isolation layer and the oxidation limiting layer can be formed in the same oxidation process, the chip process is greatly simplified, and the production cost is reduced.

The prefabricated layer materials of the oxidation limiting layer and the oxidation isolating layer are AlGaAs materials and are matched with the crystal lattices of a GaAs substrate system, so that one-time epitaxial growth can be realized, the epitaxial production difficulty is reduced, and the mass production is facilitated. Meanwhile, the epitaxial crystal quality of the VCSEL unit and the EOM unit is ensured, and the reliability of the device is improved.

Drawings

Fig. 1 is a schematic cross-sectional view of a chip according to a first embodiment of the invention.

Fig. 2 is a schematic diagram of a resonant cavity structure of a VCSEL unit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a modulation principle provided in an embodiment of the present invention.

Fig. 4 is a schematic diagram of a modulation principle provided in a second embodiment of the present invention.

In the figure:

10. substrate 11, buffer layer

12. First N type doping DBR 13, resonant cavity

14. First P-type doped DBR 15, oxide spacer

16. A second N-type doped DBR 17, a third waveguide layer

18. Absorption region 19, fourth waveguide layer

110. A second P-type doped DBR 111, a first planar electrode

111', a first ring electrode 112, a second ring electrode

113. Third annular electrode 114, fourth annular electrode

21. A first confinement layer 22, a first waveguide layer

23. Quantum well layer 24, second waveguide layer

25. Second confinement layer 26, oxide confinement layer

20. A top mirror 30, a bottom mirror.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings. Numerous details are set forth below in order to provide a thorough understanding of the present invention, but it will be apparent to those skilled in the art that the present invention may be practiced without these details.

The first embodiment is as follows:

as shown in fig. 1, the present embodiment provides a high-efficiency vertical cavity surface EML chip with an oxide isolation layer, which includes a VCSEL unit, an oxide isolation layer 15 and an EOM unit, wherein the oxide isolation layer 15 is disposed between the VCSEL unit and the EOM unit for preventing an electric potential at a contact of the two units from affecting an operating current in each unit.

As shown in fig. 1, the VCSEL unit includes, from bottom to top, a substrate 10, a buffer layer 11, a first N-type doped DBR12, a resonant cavity 13, and a first P-type doped DBR 14. The EOM cell includes, from bottom to top, a second N-doped DBR16, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19, and a second P-doped DBR 110.

As shown in fig. 1, the chip further includes a first electrode, a second ring electrode 112, a third ring electrode 113, and a fourth ring electrode 114. Specifically, in the present embodiment, the first electrode is a first planar electrode 111 disposed on the lower surface of the substrate 10, and in other embodiments, the first electrode may also be a first ring electrode 111' disposed on the upper surface of the first N-type doped DBR 12; the second ring electrode 112 is disposed on the upper surface of the first P-type doped DBR 14; a third ring electrode 113 is disposed on the upper surface of the second N-doped DBR 16; a fourth ring-shaped electrode 114 is disposed on the upper surface of the second P-type doped DBR 110.

Preferably, the substrate 10 is a Si-doped GaAs substrate with a doping concentration of 1.5e ¹⁸ cm ^-3 。

Preferably, the buffer layer 11 is a Si-doped GaAs layer with a doping concentration of 2e ¹⁸ cm ^-3 And the thickness is 200 nm.

Preferably, the first and second N-doped DBRs 12, 16 are high/low/high/low … …/high index structures, and the high index material is Si-doped Al _0.12 Ga _0.88 As layer, low refractive index material is Si-doped Al _0.9 Ga _0.1 And an As layer. Si-doped Al _0.12 Ga _0.88 The thickness of As layer is 60nm, the doping concentration is 2e ¹⁸ cm ^-3 Si-doped Al _0.9 Ga _0.1 The As layer thickness was 69.4nm and the doping concentration was 2e ¹⁸ cm ^-3 。

As shown in fig. 2, the optical thickness of the resonant cavity 13 is one wavelength, and the resonant cavity 13 includes, from bottom to top, a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxidation confinement layer 26.

Preferably, the first confinement layer 21 is Si-doped Al _0.6 Ga _0.4 As with a thickness of 22nm and a doping concentration of 2e ¹⁷ cm ^-3 。

Preferably, the first waveguide layer 22 is Al _0.45 Ga _0.55 As, 18nm thick;

preferably, the quantum well layer 23 is made of barrier layer Al with a thickness of 10nm _0.35 Ga _0.65 As and a well layer GaAs with the thickness of 8nm, and the lasing wavelength is 850 nm.

Second waveguide layer 24 is preferably Al _0.45 Ga _0.55 As, 30nm thick.

Preferably, the second confinement layer 25 is Si-doped Al _0.6 Ga _0.4 As with a thickness of 62.5nm and a doping concentration of 2e ¹⁸ cm ^-3 。

Preferably, the oxide confinement layer 26 is formed of undoped Al having a thickness of 30nm _0.93 Ga _0.07 The As oxidation limiting prefabricated layer is formed by a wet oxidation process, the aperture of an unoxidized area is reserved by 8 mu m, and an oxidized area forms Al with optical and electrical limiting functions ₂ O ₃ 。

Preferably, the oxide spacer 15 is made of undoped Al with a thickness of 30nm _0.98 Ga _0.02 The As oxidation isolation prefabricated layer is formed into Al with electrical insulation effect by wet oxidation process ₂ O ₃ The isolation layer thereby effectively prevents the potential at the contact of the VCSEL unit and the EOM unit from affecting the current in the VCSEL unit, further improving the performance of the VCSEL.

Preferably, third waveguide layer 17 is Si-doped Al _0.45 Ga _0.55 As with a thickness of 77nm and a doping concentration of 2e ¹⁷ cm ^-3 。

Preferably, the absorption zone 18 is a pair of Al _0.35 Ga _0.65 Quantum well with As As barrier and GaAs well, Al _0.35 Ga _0.65 The thickness of the As barrier layer is 5nm, the thickness of the GaAs well layer is 6nm, the thickness of the absorption region 18 is 450nm, and the wavelength of a quantum well of the absorption region 18 is 830 nm.

Preferably, fourth waveguide layer 19 is C-doped Al _0.45 Ga _0.55 As with a thickness of 77nm and a doping concentration of 2e ¹⁷ cm ^-3 . The third waveguide layer 17 and the fourth waveguide layer 19 are doped N-type and P-type, respectively, to form PN junctions, and the absorption region 18 is formed between the PN junctions.

Preferably, the first P-type doped DBR14 and the second P-type doped DBR110 are periodically stacked high refractive index/low refractive index/high refractive index/low refractive index …/high refractive index structures, and the high refractive index material is C-doped Al _0.12 Ga _0.88 As layer, low refractive index material is C-doped Al _0.9 Ga _0.1 And an As layer. C-doped Al _0.12 Ga _0.88 The thickness of As layer is 60nm, the doping concentration is 2e ¹⁸ cm ^-3 (ii) a C-doped Al _0.9 Ga _0.1 The thickness of the As layer is 69.4nm, and the doping concentration is 2e ¹⁸ cm ^-3 。

As shown in fig. 3, the modulation principle of the present embodiment is: when the third ring electrode 113 and the fourth ring electrode 114 are not biased or are biased at a lower voltage, the absorption curve of the EOM unit is in a blue shift direction compared with the emission wavelength of the VCSEL unit, and the light beam excited by the VCSEL unit does not suffer absorption loss after passing through the EOM unit. When a higher bias voltage is applied to the EOM unit, the absorption spectrum sideband of the EOM unit can rapidly drift to a long wavelength due to Quantum Confinement Stark Effect (QCSE) and covers the emission wavelength of the VCSEL unit, so that the high-speed electrical modulation signal applied to the EOM unit directly influences the movement of the absorption sideband, and the high-speed modulation of the light intensity of the VCSEL light is realized. In this embodiment, the EOM cells are isolated from the VCSEL cells by the oxide isolation layer 15, which is relatively independent, and helps to achieve a better modulation effect.

The preparation method of this example includes the following steps:

1. sequentially growing a buffer layer 11, a first N-type doped DBR12, a resonant cavity 13, a first P-type doped DBR14, an oxidation isolation prefabricated layer, a second N-type doped DBR16, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19 and a second P-type doped DBR110 on a substrate 10 by adopting an MOCVD method; the resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxidation confinement pre-fabricated layer.

The substrate 10 is etched by ICP to expose the buffer layer 11, and a first planar electrode is fabricated on the buffer layer 11 away from the first N-doped DBR surface 12.

Firstly, forming a contact layer selective mask SiNx on the upper surface of the first P-type doping DBR14 through a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, photoetching and Reactive Ion Etching (RIE) process, then performing selective edge etching through ICP etching, so that an epitaxial structure above the top of the first P-type doping DBR14 is etched to the upper surface of the first P-type doping DBR14, and then removing the contact layer selective mask SiNx through BOE; finally, a second ring electrode 112 is formed on the upper surface of the first P-type doped DBR14 by a photolithography process, an e-beam evaporation metal layer process, and a lift-off process.

The component is Al by adopting a wet oxidation process _0.98 Ga _0.02 As oxidation isolation prefabricated layer and Al component _0.93 Ga _0.07 Oxidizing the As oxidation limiting preform layer to form Al ₂ O ₃ The oxidation isolation layer 15 and the oxidation limiting layer 26;

5. referring to the method of step 4, the third ring electrode 113 is formed on the upper surface of the second N-type doped DBR16, but it should be noted that in the ICP etching, the selective edge etching must be performed on the epitaxial structure more than 200nm away from the bottom of the second N-type doped DBR16 to prevent the oxide isolation layer 15 from being etched through, which may cause the oxide isolation layer 15 to fail. A fourth ring-shaped electrode 114 is then formed on the upper surface of the second P-type doped DBR110 using known techniques.

Example two:

as shown in fig. 1 and 2, the structure design of this embodiment is substantially the same as that of the first embodiment, except that the third waveguide layer 17 and the fourth waveguide layer 19 are not provided, and the absorption region 18 is a plurality of pairs of Al _0.35 Ga _0.65 Quantum well with As As barrier and GaAs well, Al _0.35 Ga _0.65 The thickness of the As barrier layer is 5nm, the thickness of the GaAs well layer is 6nm, and the thickness of the absorption region is 450 nm. Increasing the number of quantum wells of the absorbing region 18 reduces the number of cycles of the top second P-type doped DBR 110.

As shown in fig. 1, the bottom mirror 30 is all the part below the resonator 13, and the top mirror 20 is all the part above the resonator 13. The overall reflectivity of the bottom mirror 30 can be designed to be 99.995% and the overall reflectivity of the top mirror 20 can be designed to be 99.89% for the lasing wavelength of the resonant cavity 13 of 850 nm. The absorption region 18 of the EOM cell is placed where the light intensity of the top mirror 20 is maximum.

As shown in fig. 4, the modulation principle of this embodiment is: when no bias voltage or low bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, the absorption region 18 in the EOM unit is in an unabsorbed state, at this time, the reflectivity of the bottom mirror 30 is 99.995%, the reflectivity of the top mirror 20 is 99.89%, photons emitted from the quantum well 23 can form continuous and stable back-and-forth oscillation in the resonant cavity 13, and light output can be formed through the top mirror 20 after the gain reaches a certain value; when a higher bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, the absorption effect of the absorption region 18 in the EOM unit is enhanced, the reflectivity of the top mirror 20 is reduced to 99.68%, and at this time, photons emitted from the quantum well 23 cannot continuously and stably oscillate in the resonant cavity 13, or the gain is insufficient, the light intensity cannot penetrate through the top mirror 20 to stabilize the light output, or the output laser power is reduced. Therefore, by modulating the bias level of the EOM cell and changing the operating state of the absorption region 18, the reflectivity of the top DBR can be affected, thereby achieving high-speed modulation of the light intensity of the VCSEL unit.

The above description is only an embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by using the design concept should fall within the scope of infringing the present invention.

Claims (10)

1. A high-efficiency vertical cavity surface EML chip with an oxidation isolation layer is characterized in that: the device comprises a VCSEL unit, an oxidation isolation layer and an EOM unit, wherein:

the VCSEL unit comprises a substrate, a buffer layer, a first DBR, a resonant cavity and a second DBR from bottom to top, and the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting layer from bottom to top;

the EOM unit comprises a third DBR, an absorption region and a fourth DBR from bottom to top;

the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential of the contact position of the two units from influencing the working current in the respective units.

2. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 1, wherein: the oxidation isolation layer and the oxidation limiting layer are both made of Al ₂ O ₃ Wherein the oxidation isolation layer is made of Al _x Ga _1-x The As oxidation isolation prefabricated layer is formed by oxidizing through a wet oxidation process, and the oxidation limiting layer is made of Al _y Ga _1-y The As oxidation limiting preform layer is formed by a wet oxidation process, and Al _y Ga _1-y The Al content y of As is less than that of Al _x Ga _1-x Aluminum content x of As.

3. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 2, wherein: the first DBR, the second DBR, the third DBR and the fourth DBR are made of Al _i Ga _1-i As/Al _j Ga _1-j Periodic structure of As material, and Al _i Ga _1-i As/Al _j Ga _1-j The Al content i and j of As is less than that of Al _x Ga _1-x Aluminum content x of As.

4. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 3, wherein: the Al is _x Ga _1-x The value range of Al content of As is that x is more than or equal to 0.97; the Al is _i Ga _1-i As/Al _j Ga _1-j The value ranges of the aluminum content i and j of As are that i is less than or equal to 0.92, and j is less than or equal to 0.92; the Al is _y Ga _1-y The value range of Al content of As is more than 0.92 and less than 0.97.

5. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 1, wherein: still include first electrode, second annular electrode, third annular electrode and fourth annular electrode, wherein:

the first electrode is a first planar electrode arranged on the lower surface of the substrate or a first annular electrode arranged on the upper surface of the first DBR;

the second annular electrode is arranged on the upper surface of the second DBR;

the third ring electrode is arranged on the upper surface of the third DBR;

the fourth annular electrode is disposed on an upper surface of the fourth DBR.

6. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 1, wherein: the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; the fourth DBR is a second P-type doped DBR.

7. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 2, wherein: the pore diameter of the unoxidized area of the oxidation limiting layer ranges from 2 to 100 mu m.

8. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 1, wherein: the wavelength of the quantum well of the absorption region is 5-99nm shorter than that of the quantum well of the resonant cavity.

9. The high-efficiency vertical-cavity surface EML chip with an oxide isolation layer as claimed in claim 1, wherein: the absorption region is of a single quantum well or multi-quantum well structure; when the absorption region is of a single quantum well structure, a third waveguide layer is arranged between the absorption region and the third DBR, and a fourth waveguide layer is arranged between the absorption region and the fourth DBR.

10. A preparation method of a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer is characterized by comprising the following steps: the method comprises the following steps:

(1) growing a buffer layer, a first DBR, a resonant cavity, a second DBR, an oxidation isolation prefabricated layer, a third DBR, an absorption region and a fourth DBR on a substrate in sequence; the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting prefabricated layer;

(2) preparing a first planar electrode on the lower surface of the buffer layer or preparing a first annular electrode on the upper surface of the first DBR;

(3) manufacturing a second annular electrode on the upper surface of the second DBR;

(4) oxidizing the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer by adopting a wet oxidation process to form an oxidation isolation layer and an oxidation limiting layer;

(5) and manufacturing a third ring-shaped electrode on the upper surface of the third DBR, and manufacturing a fourth ring-shaped electrode on the upper surface of the fourth DBR.

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