CN114864531A

CN114864531A - Integrated circuit lead frame and semiconductor device thereof

Info

Publication number: CN114864531A
Application number: CN202110147282.8A
Authority: CN
Inventors: 王侑信; 旋乃仁
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-02-03
Filing date: 2021-02-03
Publication date: 2022-08-05

Abstract

The invention provides an integrated circuit lead frame and a semiconductor device thereof. The integrated circuit lead frame comprises a die pad and a plurality of pins. The die pad is used for mounting a die. The plurality of pins are connected to the die by wire bonding. The pins include a pair of first and second pins. The first pin comprises a first body and a first extending part connected with the first body. The second pin comprises a second body and a second extending part connected with the second body. The first extension part and the second extension part extend towards the direction approaching to each other.

Description

Integrated circuit lead frame and semiconductor device thereof

Technical Field

The present invention relates to a lead frame, and more particularly, to an integrated circuit lead frame and a semiconductor device thereof with optimized lead impedance matching.

Background

In order to meet the requirement of high-speed transmission, the Chip mostly adopts the Ball Grid Array (BGA) and Flip Chip (Flip Chip) packaging technologies with high cost, so as to shorten the distance between the die and the substrate and avoid the influence of signal attenuation caused by wire bonding without impedance control. Conventional Wire bonding packaging techniques are less costly than the aforementioned packaging techniques, but have difficulty in providing high speed signals due to the difficulty in controlling the electrical characteristics of the Wire bonds.

Disclosure of Invention

In view of the above, the present invention provides an integrated circuit lead frame and a semiconductor device, which optimize the impedance matching between the leads in the package through the design of the leads and the wire bonding packaging technology, and greatly reduce the manufacturing cost and greatly increase the number of the leads in a single chip, so as to achieve high-density packaging (e.g., multi-row lead packaging), thereby improving the performance and further reducing the manufacturing cost.

According to some embodiments, an integrated circuit lead frame includes a die pad and a plurality of leads. The die pad is used for mounting a die. The plurality of pins are connected to the die by wire bonding. The pins include a pair of first and second pins. The first pin comprises a first body and a first extending part connected with the first body. The second pin comprises a second body and a second extending part connected with the second body. The first extension part and the second extension part extend towards the direction approaching to each other.

According to some embodiments, a semiconductor device includes a die, an integrated circuit lead frame, and a package body. The integrated circuit lead frame comprises a die pad and a plurality of pins. The die pad is used for mounting a die. The plurality of pins are connected to the die by wire bonding. The pins include a pair of first and second pins. The first pin comprises a first body and a first extending part connected with the first body. The second pin comprises a second body and a second extending part connected with the second body. The first extension part and the second extension part extend towards the direction approaching to each other. The packaging body wraps the crystal grain and part of the integrated circuit lead frame.

In summary, according to the embodiments of the present invention, the lead pitch of the wire bonding of the paired leads is shortened by the shape design of the leads (e.g., the contacts of the paired two leads for wire bonding extend in a direction close to each other) and the wire bonding packaging technology, so as to obtain good impedance matching and further provide high-speed signal transmission and reduce the manufacturing cost.

Drawings

Fig. 1 is a schematic perspective view of a semiconductor device according to some embodiments of the present invention.

Fig. 2 is a schematic perspective view of a semiconductor device according to some embodiments of the present invention.

Fig. 3 is a schematic top view of fig. 2.

Fig. 4 is a partially enlarged schematic view of fig. 3.

Fig. 5 is a partially enlarged schematic view of fig. 4.

Fig. 6 is a schematic diagram of a first comparative example.

Fig. 7 is a diagram illustrating insertion loss and reflection loss of an ic leadframe according to some embodiments of the invention and a signal carrier according to a first comparative example.

Fig. 8 is an enlarged, top view of a portion of an ic leadframe according to some embodiments of the invention.

Fig. 9 is an enlarged, top view of a portion of an ic leadframe according to some embodiments of the invention.

Fig. 10 is a schematic diagram of a first lead and a second lead of the same pair in accordance with some embodiments of the invention.

Fig. 11 is a schematic diagram of a first lead and a second lead of the same pair according to some embodiments of the invention.

Fig. 12 is an enlarged, top view of a portion of an ic leadframe according to some embodiments of the invention.

Fig. 13 is an enlarged, top view of a portion of an ic leadframe according to some embodiments of the invention.

Fig. 14 is a schematic diagram of a second comparative example.

Fig. 15 is a schematic diagram of a third comparative example.

Fig. 16 is an enlarged, top view of a portion of an ic leadframe according to some embodiments of the invention.

Fig. 17 is an enlarged, top view of a portion of an ic leadframe according to some embodiments of the invention.

Fig. 18 is a schematic bottom view of a semiconductor device according to some embodiments of the invention.

Fig. 19 is a side cross-sectional view of the same pair of first leads and second leads according to some embodiments of the invention.

Fig. 20 is a top view of an ic leadframe according to some embodiments of the invention.

Fig. 21 is a side cross-sectional schematic view of a semiconductor device of some embodiments of the invention.

Fig. 22 is a schematic diagram of an impedance system of some embodiments of the inventions.

Detailed Description

Referring to fig. 1, fig. 1 is a perspective schematic view of a semiconductor device 10 according to some embodiments of the present invention. The semiconductor device 10 includes a die 11, an ic lead frame 13, and a package 15. The die 11 is a die formed by cutting a wafer. The ic lead frame 13 is a metal structure inside the package of the semiconductor device 10 for transmitting signals of the die 11 to the outside of the semiconductor device 10, so that circuits outside the semiconductor device 10 (e.g., a circuit board outside the semiconductor device 10) can receive the signals from the die 11 via the ic lead frame 13. The package body 15 encapsulates the die 11 and a portion of the ic leadframe 13. The package 15 provides some impact and scratch protection for the die 11. For convenience of description, the semiconductor device 10 includes only one die 11, but the invention is not limited thereto, and the semiconductor device 10 may include a plurality of dies 11.

Refer to fig. 2 and 3. Fig. 2 is a schematic perspective view of a semiconductor device 10 according to some embodiments of the present invention. Fig. 3 is a schematic top view of fig. 2. An integrated circuit lead frame 13 of the semiconductor device 10 includes a die pad 33 and a plurality of leads 17. The die pad 33 is used for disposing the die 11. For convenience of description, only one die 11 is disposed on the die pad 33, but the invention is not limited thereto, and the die pad 33 may be disposed with a plurality of dies 11, that is, a plurality of dies 11 may be disposed on the die pad 33 at the same time. In some embodiments, the Die pad 33 is used for the Die 11 to be adhered and fixed on the Die pad 33 by epoxy (e.g. silver paste) or Die attach film (Die attach film), i.e. Die Bond process. These leads 17 are provided for wire bonding to the die 11. That is, the leads 17 are connected to the pads 19 of the die 11 through wires 21. In some embodiments, the material of the conductive wires 21 is a metal such as copper, gold, etc. In some embodiments, if the material of the conductive wire 21 is copper, the diameter of the conductive wire 21 may be 0.7 mil (mil) to 1 mil; if the material of the conductive wire 21 is gold, the diameter of the conductive wire 21 may be 0.7 mil to 2 mils, but the invention is not limited thereto.

Referring collectively to fig. 4, fig. 4 is a partially enlarged schematic view of fig. 3. These leads 17 include pairs of first leads 171 and second leads 173. The first lead 171 includes a first body 1711 and a first extending portion 1713 connected to the first body 1711. The second lead 173 includes a second body 1731 and a second extension 1733 connected to the second body 1731. The first extension 1713 and the second extension 1733 extend in a direction approaching each other. In other words, the first extension portion 1713 and the second extension portion 1733 extend toward each other. Specifically, referring to fig. 5 in combination, fig. 5 is a partial enlarged view of fig. 4, the first extension portion 1713 has a connecting end 1715 connected to the first body 1711 and a free end 1716 opposite to the connecting end 1715, the second extension portion 1733 has a connecting end 1735 connected to the second body 1731 and a free end 1736 opposite to the connecting end 1735, and a distance between the free ends 1716, 1736 of the first extension portion 1713 and the second extension portion 1733 is shorter than a distance between the connecting ends 1715, 1735 of the first extension portion 1713 and the second extension portion 1733.

Since the first extension portion 1713 and the second extension portion 1733 extend in the direction of each other, when the first lead 171 and the second lead 173 are connected to the pad 19 of the die 11 through the first extension portion 1713 and the second extension portion 1733 via the wire 21, the distance SP between the wires 21 (e.g., the short wire 21A and the long wire 21B described below) can be reduced (e.g., the wires 21 are closer to each other, or the distance SP conforms to the specification of wire bonding package), so as to optimize or adjust the impedance matching between the wires 21, thereby improving the quality of the signal transmitted by the wires 21 and transmitting high-speed signals. For example, the size of the space SP is adjusted to adjust the equivalent inductance and capacitance of the conductive line 21, and the impedance value is calculated according to equation 1, so as to perform impedance matching on the conductive line 21, thereby improving the performance of insertion loss and reflection loss. Where Z of equation 1 is the impedance value of the conductive line 21, L is the unit inductance value of the conductive line 21, and C is the unit capacitance value of the conductive line 21. In some embodiments, the high speed signal is a pair of differential signals. Such as, but not limited to, signals with a nyquist frequency of ten gigahertz (10GHz) to implement USB4.0 or PCIE4.0 application circuitry.

The pitch SP is the distance between the contact 23 to which the pin 17 is connected and the shorter of the two wires 21 (referred to herein as the short wire 21A) and the longer of the two wires 21 (referred to herein as the long wire 21B). For example, as shown in fig. 4, the wire 21 connected to the second lead 173 is shorter than the first lead 171, the second lead 173 is connected to the short wire 21A, whereas the first lead 171 is connected to the long wire 21B, and the distance SP between the short wire 21A and the long wire 21B is the shortest distance from the short wire 21A to the contact 23A of the second lead 173 to the long wire 21B.

Referring to fig. 6, fig. 6 is a schematic diagram of a first comparative example. In the first comparative example, the first lead 171 and the second lead 173 do not have extensions approaching each other. Referring to fig. 4 and 6 together, it can be seen that the pitch SP shown in fig. 4 of the embodiment of the present invention is much smaller than the pitch SP shown in the first comparison fig. 6, so that the conductive wires 21 can be closer to each other.

Referring to fig. 7, fig. 7 is a schematic diagram of insertion loss and reflection loss of signal carriers of an integrated circuit lead frame 13 according to some embodiments of the present invention and a first comparative example. It can be seen that the insertion loss and the reflection loss shown in the embodiment of the present invention perform better than those of the first comparative example, resulting in a significant increase in bandwidth performance.

In some embodiments, as shown in fig. 4 and 5, the first body 1711 and the second body 1731 are circular, and the first extending portion 1713 and the second extending portion 1733 are rectangular, but the invention is not limited thereto, and other shapes are also possible, such as the shapes shown in fig. 8 and 9. Fig. 8 and 9 are enlarged top views of a portion of an ic leadframe 13 according to some embodiments of the invention. Wherein the different shapes result in different capacitive loads generated by the pins 17. For example, if the first lead 171 and the second lead 173 have relatively large areas due to their shapes, the capacitive load (provided) generated by the first lead 171 and the second lead 173 is large.

In some embodiments, as shown in fig. 4, the extending direction of the first extending portion 1713 (referred to herein as the first direction D1) and the extending direction of the second extending portion 1733 (referred to herein as the second direction D2) are parallel to each other. This makes it possible to prevent the wires 21 (the short wires 21A and the long wires 21B) from contacting each other to avoid the occurrence of a short circuit of a circuit (signal), and to control the arrangement of the two wires 21, for example, the positional relationship between the contacts 23 (the

contacts

23A and 23B) of the two wires 21 (the short wires 21A and the long wires 21B) connected to the leads (the first leads 171 and the second leads 173), and the reduction amount of the pitch SP between the wires 21.

In some embodiments, the distance between the first extension 1713 and the second extension 1733 may be configured to be not less than a minimum setting value of a manufacturing process. For example, the first extension 1713 is spaced from the second extension 1733 by a distance of not less than 0.1 mm.

In some embodiments, as shown in fig. 4, there is a correlation between the extending lengths ED1, ED3 of the first and second extending

portions

1713, 1733, the pin spacing PS between the first and

second pins

171, 173, and the body diameters BR1, BR3 of the first and second extending

portions

1713, 1733. Specifically, the extension lengths ED1, ED3, the pin pitch PS, and the body diameters BR1, BR3 are positively correlated to each other. For example, when the pin pitch PS is larger, the body diameters BR1 and BR3 and the extension lengths ED1 and ED3 become larger, and vice versa, the body diameters BR1 and BR3 and the extension lengths ED1 and ED3 become smaller. The pin pitch PS is a distance from a center point of the first body 1711 to a center point of the second body 1731. High density packaging (e.g., packaging of multiple rows of leads 17 of semiconductor device 10) is achieved by different scaling of the lead spacing PS, the extended lengths ED1, ED3, and the body diameters BR1, BR 3.

Refer to fig. 10 and 11. Fig. 10 is a schematic diagram of the first lead 171 and the second lead 173 of the same pair according to some embodiments of the invention. Fig. 11 is a schematic diagram of the first lead 171 and the second lead 173 of the same pair according to some embodiments of the invention. In some embodiments, the body diameters BR1, BR3 of the first body 1711 and the second body 1731 are four to two times the zero point of the extension lengths ED1, ED3 of the first extension 1713 and the second extension 1733, respectively. For example, as shown in fig. 10, when the pin pitch PS is 1 mm, the body diameters BR1 and BR3 are 0.225 mm, and the extended lengths ED1 and ED3 are about twice the body diameters BR1 and BR 3. For another example, as shown in fig. 11, when the pin pitch PS is 0.8 mm, the body diameters BR1, BR3 are 0.425 mm, and the extended lengths ED1, ED3 are about 0.46 times the body diameters BR1, BR 3. Thereby achieving high-density packaging of the chip pins 17.

In some embodiments, the extension lengths ED1, ED3 may be set according to a spacing SP between the wires 21 connected to the first extension 1713 and the second extension 1733, respectively. For example, the extension lengths ED1, ED3 are configured in accordance with the wire diameter of each wire 21 such that the pitch SP is not more than five times. Therefore, the extending lengths ED1 and ED3 of the first extending portion 1713 and the second extending portion 1733 are set to make the pitch SP meet the specification of wire bonding package.

In some embodiments, as shown in fig. 10, when the pin pitch PS between the first pin 171 and the second pin 173 is larger, the extended lengths ED1, ED3 (i.e. the distances from the connecting ends 1715, 1735 to the free ends 1716, 1736) of the first pin 171 and the second pin 173 may be larger, so that the first extension portion 1713 and the second extension portion 1733 are partially staggered, i.e. the free end 1716 of the first extension portion 1713 is staggered with the free end 1736 of the second extension portion 1733. However, as shown in fig. 11, when the pin pitch PS between the first pin 171 and the second pin 173 is small, the extending lengths ED1, ED3 (i.e., the distances from the connecting ends 1715, 1735 to the free ends 1716, 1736) of the first pin 171 and the second pin 173 may be small, so that the first extending portion 1713 and the second extending portion 1733 may not be staggered, i.e., the free end 1716 of the first extending portion 1713 and the free end 1736 of the second extending portion 1733 may not be staggered.

Refer to fig. 12 and 13. Fig. 12 is an enlarged, top view of a portion of an ic leadframe 13 according to some embodiments of the invention. Fig. 13 is an enlarged, top view of a portion of an ic leadframe 13 according to some embodiments of the invention. The free ends 1716, 1736 of the first extension portion 1713 and the second extension portion 1733 (or the interlaced

portions

1716, 1736 of the first extension portion 1713 and the second extension portion 1733) are located on the interlaced axis SA, which points to the die 11 of the die pad 33. It can be seen that the conductive lines 21 are relatively close to each other, i.e., the size of the space SP between the two conductive lines 21 is reduced, and the two conductive lines 21 can maintain a relatively uniform space SP from the die 11 to the first lead 171 and the second lead 173. Refer to fig. 14 and 15. Fig. 14 is a schematic diagram of a second comparative example. Fig. 15 is a schematic diagram of a third comparative example. In the second and third comparative examples, the crossing axis SA where the free ends 1716, 1736 of the first extension portion 1713 and the second extension portion 1733 (or the crossing portions of the free ends 1716, 1736 of the first extension portion 1713 and the second extension portion 1733) are located is not directed to the die 11 of the die pad 33. Referring to fig. 12 to 15 together, it can be seen that the pitch SP shown in fig. 12 and 13 of the embodiment of the present invention is much smaller than the pitch SP shown in fig. 14 and 15 of the second comparative example, and the wires 21 for transmitting differential signals shown in fig. 12 and 13 from the die 11 to the first lead 171 and the second lead 173 can maintain the same pitch SP compared with the second comparative example and the third comparative example of fig. 14 and 15, so as to maintain the quality of the differential signals.

Referring to fig. 16, fig. 16 is a partially enlarged top view of an ic leadframe 13 according to some embodiments of the invention. These leads 17 are located around the die pad 33. The edge region 35 on one side of the die pad 33 is divided into a first region 351 and a second region 353 by an axis DA passing through the die pad 33. The first extending direction D3 of the first extending portion 1713 and the second extending portion 1733 located in the first region 351 is different from the second extending direction D4 of the first extending portion 1713 and the second extending portion 1733 located in the second region 353.

In some embodiments, the position of the axis DA can be configured according to the position of the die 11 on the die pad 33 and the bonding direction thereof, so as to optimize the size of the space SP between the two conductive wires 21. For example, if one die 11 is disposed in the center of die pad 33, axis DA may be the central axis through die pad 33; if one die 11 is disposed on the left (or right) side of the die pad 33, the axis DA may be the central axis of the die 11; if a plurality of crystal grains 11 are provided in the crystal grain seat 33, the axis DA may be an intermediate axis between the crystal grains 11.

In some embodiments, the first extension direction D3 is axisymmetric to the second extension direction D4 according to an axis DA. For example, as shown in fig. 16, the first extending directions D3 of the first extending portion 1713 and the second extending portion 1733 in the first region 351 extend upward to the left and downward to the right, respectively, and the second extending directions D4 of the first extending portion 1713 and the second extending portion 1733 in the second region 353 extend upward to the right and downward to the left, respectively.

In some embodiments, the first lead 171 and the second lead 173 transmit a pair of differential signals. Since the differential signal generally needs to be transmitted by two wires 21 with equal length, equal width and close proximity, the lengths of the different wires 21 (such as the short wire 21A and the long wire 21B shown in fig. 4) and the spacing SP between the wires 21 have a great influence on the quality of the differential signal. Therefore, the length of the wires 21 for transmitting the differential signal and the pitch SP between the wires 21 need to have strict specifications. By transmitting a pair of differential signals through the first lead 171 and the second lead 173 extending in a direction close to each other, the size of the pitch SP can be controlled (e.g., the size of the pitch SP is reduced) to meet the specification of wire bonding package, and thus the characteristic impedance of the conductive wire 21 can be controlled to maintain the quality of the differential signals, so as to transmit high-speed differential signals. The pair of differential signals may be two high-speed or low-speed signals of the same amplitude and opposite phases.

In some embodiments, the first lead 171 and the second lead 173 have the same shape, but the invention is not limited thereto, and the first lead 171 and the second lead 173 may have different shapes. When the first lead 171 and the second lead 173 have the same shape, the attenuation of the signal transmitted through the wire 21 connected to the first lead 171 and the second lead 173 may be uniform (for example, the attenuation of a pair of high-speed differential signals at a high frequency may be uniform), and the quality or amplitude of the signal (for example, a pair of high-speed differential signals) between the wire 21 of the first lead 171 and the second lead 173 may be the same or uniform.

In some embodiments, the first pin 171 or the second pin 173 transmits a power signal. In some embodiments, the first pin 171 and the second pin 173 transmit a pair of power signals. The pair of power signals may be a positive power signal and a negative power signal. In some embodiments, the first pin 171 or the second pin 173 of one of the pairs of pins 17 (i.e., the pairs of the first pin 171 and the second pin 173) may transmit a pair of differential signals or a pair of power signals with the first pin 171 or the second pin 173 of the other pair. In some embodiments, the first pin 171 and the second pin 173 may transmit unpaired signals (e.g., single-ended signals). For example, the first lead 171 and the second lead 173 may transmit non-differential clock signals.

In some embodiments, as shown in fig. 2, 3 and 16, the pins 17 further include a third pin 175. The third lead 175 has the same shape as the first body 1711 or the second body 1731 so as to be consistent with the signal attenuation caused by the first lead 171 and the second lead 173, but the present invention is not limited thereto, and the third lead 175 may have a different shape from the first body 1711 or the second body 1731. In some embodiments, the third pin 175 may carry an unpaired signal (e.g., a single-ended signal). For example, the third pin 175 may carry a non-differential clock signal, etc. In some embodiments, the first pin 171 or the second pin 173 may transmit a pair of power signals or a pair of differential signals with the third pin 175.

In some embodiments, the pairs of the first leads 171 and the second leads 173 may be disposed adjacently. In some embodiments, as shown in fig. 2, 3 and 16, at least one third pin 175 may be disposed between two adjacent pairs of pins 17 (i.e., two adjacent pairs of the first pin 171 and the second pin 173) to enhance the isolation between different pairs of differential signals transmitted by the conductive lines 21 of different pairs of pins 17 (i.e., different pairs of the first pin 171 and the second pin 173) so as to avoid mutual interference between the signals. Here, only one third lead 175 is disposed between two adjacent pairs of leads 17, but the present invention is not limited thereto, and a plurality of third leads 175 may be disposed.

Referring to fig. 17, fig. 17 is an enlarged partial top view of an ic leadframe 13 according to some embodiments of the invention. In some embodiments, the leads 17 can be wire-bonded to the pads 19 of the die 11 or the pads 29 of the die pad 33 via at least one wire 21. That is, the bonding pads 23 of the leads 17 can be respectively soldered to one end of at least one wire 21, and the other end of the wire 21 is soldered to the pad 19 of the die 11 or the pad 29 of the die pad 33. Specifically, one lead 17 (e.g., the first lead 171, the second lead 173, or the third lead 175) can be wire-bonded to the pad 19 of the die 11 or the pad 29 of the die pad 33 via one or more wires 21, so that one lead 17 can transmit one or more identical signals to the outside of the semiconductor device 10 at a time. Thus, one pin 17 may have one or more contacts 23.

In some embodiments, the pads 19 of the die 11 may be wire bonded to the pads 29 of the die pad 33 to transmit the ground signal. Specifically, the pad 29 is soldered to one end of at least one wire 21, the other end of the at least one wire 21 is soldered to the pad 19 of the die 11, and the pad 29 receives a ground signal from the die 11 via the wire 21 and transmits the ground signal to the outside of the semiconductor device 10. In some embodiments, the leads 17 transmit a ground signal to the outside of the semiconductor device 10 when the leads 17 are wire-bonded to the pads 29 of the die pad 33.

Refer to fig. 4 and 17. In some embodiments, the first leads 171 are wire bonded to the pads 19 of the die 11 from the first extensions 1713. The second leads 173 are wire bonded from the second extensions 1733 to the pads 19 of the die 11. That is, the contact 23 of the first lead 171 may be located in the first extension portion 1713, and the contact 23 of the second lead 173 may be located in the second extension portion 1733, so as to control the size of the pitch SP and the impedance matching of the conductive wire 21, so that the first lead 171 and the second lead 173 can transmit high-speed signals.

In some embodiments, the first extension portion 1713 and the second extension portion 1733 can be wire bonded with at least one wire 21 (i.e., the first extension portion 1713 and the second extension portion 1733 can have at least one contact 23). If the first lead 171 and the second lead 173 are connected to the conductive wire 21 only through the first extension 1713 and the second extension 1733, the conductive wire 21 connected to the first lead 171 and the second lead 173 can transmit high-speed signals (e.g., high-speed differential signals), but the invention is not limited thereto, and can also transmit low-speed signals (e.g., low-speed differential signals), power signals, or single-ended signals.

In some embodiments, the first leads 171 are wire bonded from the first body 1711 to the pads 19 of the die 11. The second leads 173 are wire bonded from the second body 1731 to the pads 19 of the die 11. That is, the contact 23 of the first lead 171 may be on the first body 1711, and the contact 23 of the second lead 173 may be on the second body 1731.

In some embodiments, the first body 1711 and the second body 1731 can be wire bonded with at least one wire 21 (i.e., the first body 1711 and the second body 1731 can have at least one contact 23). If the first lead 171 and the second lead 173 are connected to the conductive line 21 only through the first body 1711 and the second body 1731, the conductive line 21 connected to the first lead 171 and the second lead 173 can transmit low-speed signals (such as low-speed differential signals), power signals or single-ended signals. In some embodiments, the first lead 171 can be connected to the plurality of conductive wires 21 through the first extension portion 1713 and the first body 1711, and the second lead 173 can be connected to the plurality of conductive wires 21 through the second extension portion 1733 and the second body 1731, so that the conductive wires 21 connected to the first lead 171 and the second lead 173 can transmit low-speed signals, power signals or single-ended signals.

In some embodiments, the distance SP between each of the conductive wires 21 connecting the first lead 171 and the second lead 173 of the same pair is not greater than five times the diameter of each of the conductive wires 21, so that the lengths of the conductive wires 21 of the first lead 171 and the second lead 173 are similar, and the distance SP is suitable for the requirement, thereby optimizing the impedance matching of the conductive wires 21 to transmit high-speed signals. In the present embodiment, the same pair of the first pin 171 and the second pin 173 having the wire diameter of the spacing SP between the wires 21 not greater than five times can transmit high-speed signals (e.g., a pair of high-speed differential signals), but the invention is not limited thereto, and can also transmit low-speed signals (e.g., a pair of low-speed differential signals), power signals, or single-ended signals.

In some embodiments, as shown in fig. 1, the first lead 171 and the second lead 173 are wire-bonded to the die 11 through at least one conductive line 21, and each conductive line 21 connecting the first lead 171 and the second lead 173 of the same pair has the same loop height LH. For convenience of description, fig. 1 only shows that the first lead 171 and the second lead 173 are wire-bonded to the die 11 through one wire 21, but the invention is not limited thereto, and the first lead 171 and the second lead 173 are wire-bonded to the die 11 through a plurality of wires 21. The conductive lines 21 passing through the first lead 171 and the second lead 173 have the same loop height LH, so that the lengths of the conductive lines 21 passing through the first lead 171 and the second lead 173 can be more similar, the size of the pitch SP of the conductive lines 21 and the impedance matching of the conductive lines 21 can be controlled, and high-speed signals can be transmitted. In the embodiment, the same pair of the first pin 171 and the second pin 173 having the same loop height LH can transmit a high-speed signal (e.g., a pair of high-speed differential signals), but the invention is not limited thereto, and can also transmit a low-speed signal (e.g., a pair of low-speed differential signals), a power signal, a single-ended signal, or the like.

Referring to fig. 18, fig. 18 is a bottom view of a semiconductor device 10 according to some embodiments of the present invention. In some embodiments, fig. 18 may also be a bottom view of an ic leadframe 13. In some embodiments, the first body 1711 and the second body 1731 are exposed outside the package body 15, and the first extension 1713 and the second extension 1733 (not shown in fig. 18) are inside the package body 15. Specifically, the bottom portions of the first body 1711 and the second body 1731 are exposed outside the package 15 for connecting to a circuit outside the semiconductor device 10 (e.g., a circuit board outside the semiconductor device 10), so as to obtain a signal (e.g., a high speed/low speed differential signal, a power signal, a single-ended signal, etc.) from the die 11 or transmit the signal to the die 11. When the first extending portion 1713 and the second extending portion 1733 are encapsulated in the package body 15, the interference caused by the connection of the external circuit, such as the short circuit with other circuits, can be reduced. In some embodiments, the bottom of the pad 29 of the die pad 33 may be exposed outside the package body 15 for connecting a circuit outside the semiconductor device 10 to transmit a signal (e.g., a ground signal). In some embodiments, the bottom of the third lead 175 may be exposed outside the package body 15 for circuit connection outside the semiconductor device 10 to transmit signals (e.g., single-ended signals, etc.). In some embodiments, the area of the leads 17 for wire bonding with the wires 21 (or the area where the contacts 23 can be disposed) (hereinafter referred to as the wire bonding area LA) may be slightly larger than or the same as the area of the bottoms of the leads 17 exposed outside the package body 15 (hereinafter referred to as the exposed area OA). For example, referring to fig. 19, fig. 19 is a schematic side cross-sectional view of the same pair of first leads 171 and second leads 173 in some embodiments of the invention, and the wire bonding areas LA1 and LA3 of the first bodies 1711 of the first leads 171 and the second bodies 1731 of the second leads 173 may be slightly larger than or the same as the exposed areas OA1 and OA3 whose bottoms are exposed outside the package body 15.

Refer to fig. 3 and 20. Fig. 20 is a top view of an ic leadframe 13 according to some embodiments of the invention. It can be seen that the leads 17 (e.g., the first lead 171, the second lead 173, and the third lead 175) are arranged in a plurality of rows around the die pad 33 by the design of the leads 17 of the present invention. For example, as shown in fig. 3, each side of the die pad 33 has two rows of pins 17; as shown in fig. 20, each side of the die pad 33 has three rows of leads 17. So as to greatly increase the number of leads 17 of a single semiconductor device 10.

Referring to fig. 21, fig. 21 is a side cross-sectional schematic view of a semiconductor device 10 of some embodiments of the present invention. In some embodiments, the packaging technology of the semiconductor device 10 may employ Advanced Quad Flat No leads (AQFN). For example, the shape of the ic leadframe 13 at the upper part of the forming line F in fig. 21 may be formed, the device at the upper part of the forming line F is encapsulated (e.g., wrapped) by the package body 15A, the metal part at the lower part of the forming line F (e.g., copper metal of the ic leadframe 13) is etched to form the shape at the lower part of the forming line F, the etched part is filled by the package body 15B, and finally the metal part is exposed outside the package body 15. Since the process of forming the advanced Quad Flat No-lead package is more flexible than the conventional Quad Flat No-lead package (QFN), the shape of the leads 17 can be designed more variously without limitation. In some embodiments, the material used for the package 15A on the upper half of the forming line F may be different from the material used for the package 15B on the lower half of the forming line F, but the invention is not limited thereto, and the material used for the package 15A on the upper half of the forming line F may be the same as the material used for the package 15B on the lower half of the forming line F.

Referring to fig. 22, fig. 22 is a schematic diagram of an impedance system of some embodiments of the present invention. In some embodiments, the material of the package body 15 may be selected according to the impedance system applied to the semiconductor device 10. For example, if the semiconductor device 10 is applied to a 100 ohm impedance system, the material of the package 15 can be a common epoxy resin package material; if the semiconductor device 10 is applied to an 85 ohm or 90 ohm impedance system, the material of the package body 15 may be an alumina type epoxy resin package material, but the invention is not limited thereto.

In some embodiments, the ic leadframe 13 may have a distribution position or number of the leads 17 at one of the corners different from those at the other corners (for example, as shown in fig. 20, the number of the leads 17 at one of the corners of the ic leadframe 13 may be smaller than those at the other corners), so that a user can identify a direction in which the ic leadframe 13 and the semiconductor device 10 including the ic leadframe 13 are disposed (for example, a direction in which the ic leadframe 13 is disposed on the semiconductor device 10 or a direction in which the semiconductor device 10 is disposed on a circuit board). In some embodiments, one of the corners of the die pad 33 may be configured to have a different shape than the other corners. For example, as shown in fig. 2 and 3, one of the corners of the die pad 33 is a notch, and the other corners are not notches, so as to help identify the direction in which the ic lead frame 13 and the semiconductor device 10 are disposed.

Description of reference numerals:

10 semiconductor device

11 crystal grain

19: bonding pad

13 Integrated circuit lead frame

33 die pad

29 bonding pad

17: pin

171 first lead

1711 the first body

1713 the first extension part

1715 connecting ends

1716 free end

D1 first direction

173 the second lead

1731 second body

1733 second extension part

1735 connecting end

1736 free end

D2 second direction

175 third lead

21,21A,21B conducting wire

23,23A,23B contact

SP distance

Staggered axis of SA

ED1, ED3 elongation

35 side area

351 the first region

353 second area

DA axis

D3 first direction of extension

D4 second direction of extension

BR1, BR3 body diameter

PS pin pitch

LH is the height of the line arc

LA, LA1, LA3 bonding area

Exposed areas OA, OA1, OA3

15,15A,15B Package

F is a forming line

Claims

1. An integrated circuit lead frame, comprising:

a die pad for mounting a die; and

the plurality of pins are connected to the crystal grain in a routing mode, wherein the pins comprise a first pin and a second pin which are paired, the first pin comprises a first body and a first extending portion connected with the first body, the second pin comprises a second body and a second extending portion connected with the second body, and the first extending portion and the second extending portion extend towards directions close to each other.

2. The integrated circuit lead frame of claim 1 wherein the first extension extends in a first direction and the second extension extends in a second direction, the first direction and the second direction being parallel to each other.

3. The integrated circuit lead frame of claim 1 wherein the first lead and the second lead are of the same shape.

4. The integrated circuit lead frame of claim 1, wherein the first and second extensions are partially staggered.

5. The integrated circuit lead frame of claim 1 wherein the first lead and the second lead transmit a pair of differential signals.

6. The integrated circuit lead frame of claim 1, wherein the first pin carries a power signal.

7. The integrated circuit leadframe of claim 1, wherein the first lead is wire bonded from the first extension to the die.

8. The integrated circuit lead frame of claim 7 wherein the first lead is further wire bonded from the first body to the die.

9. The integrated circuit lead frame of claim 1 wherein the leads further comprise a third lead, the third lead having a shape substantially the same as the first body or the second body.

10. A semiconductor device, comprising:

a crystal grain;

an integrated circuit leadframe, comprising:

a die pad for mounting the die; and

a plurality of pins for wire bonding to the die, wherein the pins comprise a first pin and a second pin in pair, the first pin comprises a first body and a first extension part connected with the first body, the second pin comprises a second body and a second extension part connected with the second body, and the first extension part and the second extension part extend in a direction close to each other; and

and the packaging body wraps the crystal grain and part of the integrated circuit lead frame.