CN114864406A - MOS anti-irradiation device with double-auxiliary-gate structure and preparation method thereof - Google Patents
MOS anti-irradiation device with double-auxiliary-gate structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 230000003471 anti-radiation Effects 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 219
- 238000000034 method Methods 0.000 claims description 82
- 230000008569 process Effects 0.000 claims description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 49
- 238000005530 etching Methods 0.000 claims description 43
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 32
- 239000011241 protective layer Substances 0.000 claims description 27
- 230000005855 radiation Effects 0.000 claims description 27
- 238000005229 chemical vapour deposition Methods 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 230000036961 partial effect Effects 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 239000007772 electrode material Substances 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- 230000005684 electric field Effects 0.000 abstract description 11
- 239000002245 particle Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 9
- 230000002441 reversible effect Effects 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000002787 reinforcement Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000191 radiation effect Effects 0.000 description 2
- 241000282414 Homo sapiens Species 0.000 description 1
- 230000007488 abnormal function Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
The invention relates to an MOS anti-irradiation device with a double-auxiliary-gate structure and a preparation method thereof. The invention introduces the auxiliary grid to influence the electric field strength below the LDD, can alleviate the transverse electric field formed by the reverse bias of the PN junction at the drain end, reduces the charge collecting capacity of the electrode, and enables the electron-hole pair generated by the injection of high-energy particles to be recombined and disappear before being collected by the electrode. Therefore, the problems of logic error upset and the like of the integrated circuit caused by the single event effect are solved, and the integrated circuit formed by the novel MOS anti-radiation device can stably work in a high-radiation environment.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a MOS (metal oxide semiconductor) anti-radiation device with a double-auxiliary-gate structure and a preparation method thereof.
Background
In recent decades, the aerospace technology has been rapidly developed under the drive of curiosity of human beings on unknown universes, and successful landing is carried out from the first artificial satellite to the manned spacecraft returnable capsule of Shenzhou No. thirteen, so that the aerospace industry of China has achieved the performance of nobody. After the proud's achievement, support of aerospace-level integrated circuits is not left. Because the space equipment is in a complex space environment and a large number of high-energy particles exist in the environment, an integrated circuit in the space equipment is directly exposed to radiation of cosmic rays and the high-energy particles, and the radiation can cause that a common integrated circuit cannot stably complete work or even permanently fails, so that the stability and the reliability of the integrated circuit must be improved to ensure that the space equipment working in the high-radiation environment can correctly run for a long time.
At present, in the field of radiation-resistant reinforcement of integrated circuits in aerospace-level chips, certain differences exist between the research level and the international advanced level, and certain key technologies such as circuit reinforcement and packaging module assembly still fall behind. Due to the limitation of the technical problems of reinforcement, aerospace-grade anti-radiation integrated circuit chips rely on imports to a certain extent, and anti-radiation integrated circuits which can be purchased in China generally fall behind products of several generations, so that the development of aerospace is seriously hindered. Because of this, the development of radiation-resistant integrated circuits must be increased in China, and the aerospace technology can be continuously developed only by filling up short boards.
The existing reinforcement technology is mainly broken through from the following three aspects: one is from the circuit level, design the circuit structure with radiation resistance, dual-mode redundancy, double-interlocking memory storage structure, etc., make the circuit have certain error correction ability; one is from the aspect of the layout, when the layout design is carried out, the influence of the ionizing radiation effect is weakened by adopting special structures such as an annular grid structure, a protective drain and the like; and the other is from the process packaging angle, special ceramic packaging can be used for enhancing the protection of the circuit and weakening the irradiation influence of high-energy particles on internal devices. The methods can weaken the single event effect to a certain extent, but have a plurality of defects, such as the generation of additional anti-radiation circuit structures, the need of specially making layouts and increasing the layout area, the use of ceramic packaging to ensure that the safety of the chip highly depends on the packaging and the like, and are not beneficial to the production and the application of anti-radiation integrated circuit chips. The methods are all proposed aiming at the radiation resistance of the periphery of the device, and the radiation resistance of the device is not involved. It should be appreciated that if the core component MOS field effect transistor of the aerospace-grade integrated circuit has radiation-resistant characteristics, the radiation-resistant performance of the aerospace-grade chip is greatly improved.
The integrated circuit works in a complex environment with high radiation, and after a traditional MOS (metal-oxide-semiconductor) device in the circuit is bombarded by heavy particles, the logic state of the MOS device can be overturned to cause the abnormal function of the circuit or the failure of the device due to the fact that a reverse bias PN junction below a drain end has a strong electric field and the capability of collecting carriers is strong. Most of the existing radiation-resistant reinforcement is proposed around the peripheral circuit, the process and the like of a device, but how to enable the MOS field effect transistor of the aerospace-grade chip to have radiation-resistant performance becomes a problem to be solved urgently.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an MOS anti-radiation device with a double-auxiliary-gate structure and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of an MOS (metal oxide semiconductor) anti-radiation device with a double-auxiliary gate structure, which comprises the following steps:
s1, preparing a P-type Si substrate layer, preparing a P-type Si layer on the P-type Si substrate layer, and preparing SiO on the P-type Si layer 2 A protective layer and a layer on the SiO 2 Si on the protective layer 3 N 4 A layer;
s2, etching the SiO at the position of the groove area 2 Protective layer of said Si 3 N 4 A layer, the P-type Si layer and the P-type Si substrate layer with partial depth, forming a groove, and filling SiO in the groove 2 Material to form SiO 2 A column;
s3, removing the SiO on the P-type Si layer 2 Protective layer and said Si 3 N 4 A layer for preparing a gate oxide layer and a gate electrode on the gate oxide layer on the P-type Si layer, and a gate electrode on the gate electrodeForming lightly doped source and drain regions on the sides;
s4, forming a first Si on the side and top of the gate electrode 3 N 4 A side wall at the first Si 3 N 4 Forming Si side walls at the side parts and the top parts of the side walls, and forming second Si at the side parts and the top parts of the Si side walls 3 N 4 A side wall;
s5, using the second Si 3 N 4 The side wall is used as a mask and is close to the SiO 2 Forming a heavily doped source region and a heavily doped drain region at one side of the pillar, wherein the lightly doped source region and the lightly doped drain region are positioned between the heavily doped source region and the heavily doped drain region;
s6, removing partial depth of the second Si 3 N 4 A side wall and the Si side wall to expose the first Si 3 N 4 Forming a dielectric layer on the surface of the side wall and the surface of the device;
s7, removing the dielectric layer on the Si side wall and the partial deep Si side wall to form a window of the double-auxiliary gate, and forming SiO in the window of the double-auxiliary gate 2 A dielectric layer, then on the SiO 2 Forming an electrode in the auxiliary gate on the dielectric layer, and forming the dielectric layer on the surface of the device, wherein the window of the double auxiliary gates comprises two windows of the auxiliary gates;
and S8, etching the dielectric layer to form a metal contact hole, forming a metal electrode on the surface of the device, etching to remove the dielectric layer at the region except the metal contact hole, and forming a passivation dielectric layer on the surface of the device, wherein the metal contact hole is respectively positioned on the upper sides of the heavily doped source region and drain region and the upper side of the electrode in the auxiliary gate, and finally forming the MOS anti-radiation device with the double-auxiliary-gate structure.
In one embodiment of the present invention, step S1 includes:
s1.1, selecting a Si substrate;
s1.2, cleaning the Si substrate by using an RCA method, and removing an oxide layer on the surface of the Si substrate;
s1.3, doping P-type impurities into the Si substrate to form a P-type Si substrate layer;
s1.4, depositing the P-type Si layer on the P-type Si substrate layer by utilizing a molecular beam epitaxy process;
s1.5, depositing the SiO on the P-type Si layer by using a CVD process 2 A protective layer;
s1.6, CVD process is utilized to form the SiO 2 Depositing said Si on the protective layer 3 N 4 And (3) a layer.
In one embodiment of the present invention, step S2 includes:
s2.1, etching the SiO at the position of the groove area 2 Protective layer of said Si 3 N 4 A layer to form a trench region window;
s2.2, etching the P-type Si layer at the window of the groove area and the P-type Si substrate layer with partial depth by using a dry etching process to form a groove;
s2.3, utilizing a CVD process to perform reaction between Si and the groove 3 N 4 Filling SiO on the layer 2 A material;
s2.4, removing the Si by using a CMP method 3 N 4 SiO on the surface of the layer 2 Material to form SiO 2 And (3) a column.
In one embodiment of the present invention, step S3 includes:
s3.1, respectively using H 3 PO 4 And HF etching the Si on the P-type Si layer 3 N 4 Layer and the SiO 2 A protective layer;
s3.2, depositing a gate oxide layer on the P-type Si layer;
s3.3, depositing a gate electrode material on the gate oxide layer;
s3.4, etching the gate electrode material and the gate oxide layer to form the gate electrode;
and S3.5, etching a window for carrying out source-drain doping on the photoresist, and carrying out ion implantation on the window by adopting an ion implantation process so as to form a lightly doped source region and a lightly doped drain region on two sides of the gate electrode.
In one embodiment of the present invention, step S4 includes:
s4.1, removing the photoresist in the step S3.5, reusing the photoresist to cover the device, and etching and removing the photoresist on the side part and the top part of the gate electrode so as to remove the photoresistDepositing Si on the side and top regions of the gate electrode of photoresist 3 N 4 Material to form the first Si on the side and top of the gate electrode 3 N 4 A side wall;
s4.2, removing the photoresist in the step S4.1, covering the device by using the photoresist again, and removing the first Si by etching 3 N 4 Photoresist on the side part and the top part of the side wall so as to remove the first Si of the photoresist 3 N 4 Depositing Si material on the side wall and the top part of the side wall to form a first Si layer 3 N 4 Forming the Si side wall on the side part and the top part of the side wall;
s4.3, removing the photoresist in the step S4.2, covering the device by using the photoresist again, and etching to remove the photoresist on the side part and the top part of the Si side wall so as to deposit Si on the region of the side part and the top part of the Si side wall with the photoresist removed 3 N 4 Material to form the second Si on the side and top of the Si sidewall 3 N 4 And a side wall.
In one embodiment of the present invention, step S5 includes:
with the second Si 3 N 4 The side wall is used as a mask and is close to the SiO by adopting a self-alignment method 2 One side of the pillar forms a heavily doped source region and drain region.
In one embodiment of the present invention, step S6 includes:
s6.1, removing partial depth of second Si by utilizing CMP (chemical mechanical polishing) process 3 N 4 A side wall and the Si side wall to expose the first Si 3 N 4 The surface of the side wall;
and S6.2, depositing BPSG on the surface of the device by using a CVD process to form a dielectric layer.
In one embodiment of the present invention, step S7 includes:
s7.1, coating photoresist on the surface of the dielectric layer, and etching to remove the dielectric layer on the Si side wall and the Si side wall with partial depth so as to form a window of the double-auxiliary gate;
s7.2, depositing SiO on the window of the double-auxiliary gate 2 Material to form SiO 2 A dielectric layer;
step S7.3, in the SiO 2 Depositing a polysilicon material on the dielectric layer to form an electrode in the auxiliary gate;
and S7.4, depositing BPSG on the surface of the device by using a CVD process to form a dielectric layer.
In one embodiment of the present invention, step S8 includes:
s8.1, etching the dielectric layer by using nitric acid and hydrofluoric acid to form a metal contact hole;
s8.2, depositing a metal wire layer on the surface of the device by using an electron beam evaporation process;
s8.3, etching and removing the metal wire layer at the metal contact hole removing area by utilizing a selective etching process to form a metal electrode, and carrying out planarization treatment by utilizing a CMP process;
and S8.4, depositing a SiN material on the surface of the device by utilizing a CVD (chemical vapor deposition) process to form a passivation dielectric layer, and finally forming the MOS anti-radiation device with the drain terminal composite double-auxiliary-gate structure.
An embodiment of the present invention further provides an MOS irradiation-resistant device having a double-gate structure, where the MOS irradiation-resistant device includes:
a P-type Si substrate layer;
the P-type Si layer is positioned on the P-type Si substrate layer;
two SiO 2 Columns located on the grooves at two ends of the P-type Si substrate layer, and the P-type Si layers are located on the two SiO layers 2 Between the columns;
the gate oxide layer is positioned on part of the P-type Si layer;
the gate electrode is positioned on the gate oxide layer;
the lightly doped source region and the drain region are positioned in the P-type Si layer, and the lightly doped source region and the drain region are positioned on two sides of the gate electrode;
the heavily doped source region and the heavily doped drain region are positioned in the P-type Si layer, and the lightly doped source region and the lightly doped drain region are positioned between the heavily doped source region and the heavily doped drain region;
first Si 3 N 4 The side walls are positioned at the side part and the top part of the gate electrode;
a Si sidewall at the first Si 3 N 4 Two sides of the side wall;
second Si 3 N 4 The side walls are positioned on two sides of the Si side wall;
SiO 2 the dielectric layer is positioned on the Si side wall;
an electrode in the sub-gate on the SiO 2 A dielectric layer;
a dielectric layer on the SiO 2 A column, part of the heavily doped source region and drain region, the first Si 3 N 4 Side wall, second Si 3 N 4 A side wall;
the metal contact holes are respectively positioned on the upper sides of the heavily doped source region and the heavily doped drain region and on the upper side of the electrode in the auxiliary gate;
and the passivation dielectric layer is positioned on the dielectric layer and the metal electrode.
Compared with the prior art, the invention has the beneficial effects that:
firstly, the gate end structure of the device is changed based on the traditional MOS device, the process and the silicon compatibility are good, compared with other radiation-resistant reinforcement technologies such as adding a circuit structure and changing a layout design method, the design structure is simple, and meanwhile, the reliability of aerospace-level equipment and the like is greatly improved. The aerospace-level integrated circuit structure formed by the device has the anti-irradiation characteristic, an additional anti-irradiation circuit structure and a device layout are not needed, the manufacturing cost of the aerospace-level integrated circuit can be obviously reduced, and the anti-irradiation performance is improved. Because the integrated circuit built by the novel MOS device has the radiation-resistant characteristic and is completely compatible with other reinforcement technologies, the service life and the reliability of aerospace-level equipment formed by the device can be improved by times by simultaneously using a plurality of reinforcement technologies.
Secondly, the double-auxiliary-gate structure is added in the gate of the MOS device, so that the problems of logic state error upset, device failure and the like of the MOS device caused by radiation effect such as single event effect are eliminated from the device angle, the MOS device can stably work for a long time in a high-radiation environment, and the cost of space navigation equipment is indirectly reduced.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a MOS radiation-resistant device with a double-gate structure according to an embodiment of the present invention;
fig. 2-27 are schematic process diagrams of a method for manufacturing a MOS radiation-resistant device with a double-side gate structure according to an embodiment of the present invention;
FIG. 28 is a diagram illustrating a mechanism of pulse current generation by heavy particle bombardment of a conventional MOS device according to an embodiment of the present invention;
fig. 29 is a mechanism diagram of a MOS radiation-resistant device with a double-gate structure according to an embodiment of the present invention, which is subjected to heavy particle bombardment to generate a pulse current.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
When the MOS transistor is in the off state, the drain junction is in the reverse bias state, so that the depletion region formed by the junction is wider and has a stronger space electric field, and the electric field has stronger collection capability on charges, which is called as a sensitive region. When the high-energy particles bombard the sensitive area, a large number of electron-hole pairs are generated by ionization on the injection path, and the current formed by the directional transport and collection of the charges is a single electron current, namely a pulse current generated by the radiation effect. Once collected by the electrodes of the semiconductor device, these carriers will cause the logic level of the integrated circuit to be inverted, and under the action of a large electric field, the electron-hole pairs may collide with each other to cause an avalanche effect, so as to ionize more charges, so that the device may be permanently damaged, and further the circuit may be disabled, and finally the device may not work normally. In the space environment where the aerospace equipment works, circuits in the aerospace equipment are bombarded by high-energy particles all the time, once the adverse effects are generated, the whole aerospace equipment can be scrapped, and the development of aerospace industry is seriously influenced.
To solve the problem, please refer to fig. 1 to 27, fig. 1 is a schematic flow chart of a method for manufacturing an MOS radiation-resistant device with a double-side gate structure according to an embodiment of the present invention, and fig. 2 to 27 are schematic process diagrams of a method for manufacturing an MOS radiation-resistant device with a double-side gate structure according to an embodiment of the present invention, the present invention provides a method for manufacturing an MOS radiation-resistant device with a double-side gate structure, and the method for manufacturing an MOS radiation-resistant device with a double-side gate structure includes:
s1, preparing a P-type Si substrate layer, preparing a P-type Si layer on the P-type Si substrate layer, and preparing SiO on the P-type Si layer 2 Protective layer and SiO 2 Si on the protective layer 3 N 4 And (3) a layer.
In one embodiment, step S1 includes:
s1.1, referring to fig. 2, a Si substrate 001 is selected.
Preferably, the Si substrate 001 is a single crystal Si substrate.
S1.2, cleaning the Si substrate 001 by using an RCA method, and removing an oxide layer on the surface of the Si substrate 001.
Specifically, the Si substrate 001 was cleaned using the RCA method, and then cleaned with 10% hydrofluoric acid to remove the oxide layer on the surface of the Si substrate 001.
S1.3, doping P-type impurities into the Si substrate 001 to form a P-type Si substrate layer.
Specifically, a P-type impurity is doped into the Si substrate 001i at a doping concentration of about 1.5 × 10 16 cm -3 And forming a P-type Si substrate layer.
S1.4, referring to fig. 3, depositing a P-type Si layer 002 on the P-type Si substrate layer by using a molecular beam epitaxy process.
Specifically, at the temperature of 500-600 ℃, the components are utilizedDepositing a P-type Si layer 002 with the thickness of 300nm on the surface of the P-type Si substrate layer by a sub-beam epitaxy process, wherein the doping concentration of the P-type Si layer 002 is 3 multiplied by 10 18 cm -3 。
S1.5, referring to FIG. 4, SiO is deposited on the P-type Si layer 002 by CVD (chemical vapor deposition) 2 And a protective layer 003.
Specifically, a CVD process was used to deposit 10nm of SiO on the P-type Si layer 002 2 Material to form SiO 2 And a protective layer 003.
S1.6, see FIG. 5, CVD process on SiO 2 Si deposition on the protective layer 003 3 N 4 Layer 004.
Specifically, the CVD process is used to form SiO 2 Si with 100nm thickness deposited on the surface of the protective layer 003 3 N 4 Material to form Si 3 N 4 Layer 004, due to the large difference in thermal expansion coefficient between silicon nitride and silicon, to prevent the silicon surface from being affected by thermal stress, a thin oxide layer grown between silicon nitride and silicon acts as a buffer
S2 etching SiO at the position of the groove area 2 Protective layer, Si 3 N 4 A layer, a P-type Si layer and a P-type Si substrate layer with partial depth, forming a groove, and filling SiO in the groove 2 Material to form SiO 2 And (3) a column.
In one embodiment, step S2 includes:
s2.1, referring to FIG. 6, etching the SiO in the trench region 2 Protective layer 003, Si 3 N 4 Layer 004 to form trench region windows.
In particular, in SiO 2 Protective layer 003, Si 3 N 4 The SiO layer is etched away from the layer 004 at the position where the trench region is to be formed 2 Protective layer 003 and Si 3 N 4 Layer 004, forming trench region windows.
And S2.2, referring to fig. 7, etching the P-type Si layer 002 and the P-type Si substrate layer 001 with partial depth at the window of the trench region by using a dry etching process to form a trench.
Specifically, a trench with the depth of 300nm is etched in the silicon substrate through the trench region window by using a dry etching process.
S2.3, referring to FIG. 8, Si is neutralized in the trench by a CVD process 3 N 4 Filling SiO on the layer 2 A material.
S2.4, referring to FIG. 9, Si is removed by CMP (Chemical Mechanical Polishing) 3 N 4 SiO on the surface of the layer 2 Material to form SiO 2 And a column 005.
Specifically, the excess silicon dioxide on the surface is removed by a CMP method. Because the silicon nitride has stronger polishing resistance, the silicon nitride plays a role of a polishing stop layer for the CMP process, so that Si is enabled to be 3 N 4 SiO of the upper part 2 All are polished and removed to obtain a flat surface.
S3, removing SiO on the P-type Si layer 2 Protective layer and Si 3 N 4 And the layer is used for preparing a gate oxide layer and a gate electrode positioned on the gate oxide layer on the P-type Si layer, and forming a lightly doped source region and a lightly doped drain region on two sides of the gate electrode.
In one embodiment, step S3 includes:
s3.1, please refer to FIG. 10, respectively using H 3 PO 4 And HF etching Si on P-type Si layer 002 3 N 4 Layer 004 and SiO 2 And protecting layer 003 to obtain a flat surface with shallow trench isolation.
S3.2, referring to fig. 11, a gate oxide layer 006 is deposited on the P-type Si layer 002.
Specifically, a high quality thin gate oxide layer 006 is deposited to a thickness of 5 nm.
S3.3, referring to fig. 12, a gate electrode material 007 is deposited on the gate oxide layer 006.
Specifically, a layer of polysilicon with a thickness of 10nm is deposited on the gate oxide layer 006 as the gate electrode material 007.
S3.4, see fig. 13, the gate electrode material and the gate oxide are etched to form a gate electrode 007.
Specifically, etching was performed to leave only polysilicon having a width of 6nm serving as a gate electrode and serving as an interconnect, and a gate oxide layer thereunder.
And S3.5, referring to FIG. 14, etching a window for source-drain doping on the photoresist, and performing ion implantation on the window by adopting an ion implantation process to form a lightly doped source region and a lightly doped drain region 008 on two sides of the gate electrode.
Specifically, a window for performing source-drain doping of the NMOS transistor is etched on the photoresist, and an ion implantation process is used to perform ion implantation on the NMOS active region to form lightly doped source and drain regions 008 with a doping concentration of 3.0 × 10 17 cm -3 。
S4, forming first Si on the side and top of the gate electrode 3 N 4 Side wall at the first Si 3 N 4 Forming Si side walls at the side parts and the top parts of the side walls, and forming second Si at the side parts and the top parts of the Si side walls 3 N 4 And a side wall.
In one embodiment, step S4 includes:
s4.1, referring to FIG. 15, the photoresist in the step S3.5 is removed, the device is covered by the photoresist again, and the photoresist on the side and the top of the gate electrode is etched and removed, so that Si is deposited on the area on the side and the top of the gate electrode where the photoresist is removed 3 N 4 Material to form first Si on the side and top of the gate electrode 3 N 4 And a side wall 009.
Specifically, the previous photoresist is removed, the NMOS transistor is covered by the photoresist again, the area with the width of 16nm is etched only on the grid electrode and the two sides of the grid electrode, and Si is deposited 3 N 4 Production of first Si 3 N 4 And a side wall 009.
S4.2, referring to FIG. 16, the photoresist in the step S4.1 is removed, the device is covered by the photoresist again, and the first Si is removed by etching 3 N 4 Photoresist on the side and top of the sidewall to remove the first Si of the photoresist 3 N 4 Depositing Si material on the side wall and top region to form first Si 3 N 4 The side and top portions of the sidewall form Si sidewalls 010.
Specifically, the photoresist is removed, the NMOS transistor is covered with the photoresist again, and a region with a width of 5nm is additionally etched only on the basis of the gate electrode and the two sides of the sidewall, and a Si sidewall 010 of intrinsic silicon with a thickness of 10nm is deposited, wherein the Si is used for manufacturing an isolation layer in the double-gate.
S4.3, referring to FIG. 17, removing the photoresist in the step S4.2, covering the device with the photoresist again, and etching to remove the photoresist on the side and the top of the Si side wall so as to deposit Si on the region where the side and the top of the Si side wall of the photoresist are removed 3 N 4 Material to form second Si on the side and top of the Si sidewall 3 N 4 And side walls 011.
Specifically, the photoresist is removed, the NMOS transistor is covered by the photoresist again, windows which are 5nm wider than the grid and the side walls on the two sides are etched, and Si is deposited 3 N 4 Generation of second Si 3 N 4 And the side wall 011 is used for isolating the source electrode, the drain electrode and the double auxiliary gates.
S5, please refer to FIG. 18, with the second Si 3 N 4 The side wall is used as a mask and is close to SiO 2 One side of the pillars forms heavily doped source and drain regions 012, with the lightly doped source and drain regions located between the heavily doped source and drain regions.
Specifically, with the second Si 3 N 4 The side wall is used as a mask and is close to SiO by adopting a self-alignment method 2 Heavily doped source and drain regions 12 are formed on one side of the pillar with a doping concentration of 4.02 x 10 20 cm -3 Forming source and drain and completing LDD (lightly doped drain) and LDS (lightly doped source) regions.
S6, removing partial depth of second Si 3 N 4 Side walls and Si side walls to expose the first Si 3 N 4 And forming a dielectric layer on the surface of the side wall and the surface of the device.
In one embodiment, step S6 includes:
s6.1, referring to FIG. 19, removing a part of the depth of the second Si by CMP process 3 N 4 Side walls and Si side walls to expose the first Si 3 N 4 The surface of the side wall.
S6.2, referring to fig. 20, a CVD process is used to deposit BPSG (Boro-phosphor-silicate Glass) on the device surface to form a dielectric layer 013.
Specifically, a dielectric layer 013 was formed by depositing BPSG over the entire surface of the wafer to a thickness of 25nm using a CVD process.
S7, removing the dielectric layer on the Si side wall and the partial deep Si side wall to form a window of the double-auxiliary gate, and forming SiO in the window of the double-auxiliary gate 2 Dielectric layer, then SiO 2 Forming an electrode in the auxiliary gate on the dielectric layer, and forming the dielectric layer on the surface of the device, wherein the window of the double auxiliary gates comprises two windows of the auxiliary gates;
in one embodiment, step S7 includes:
step S7.1, please refer to fig. 21, coating photoresist on the surface of the dielectric layer 013, and etching to remove the dielectric layer 013 on the Si sidewall and the Si sidewall 010 with a partial depth, so as to form a window of the double-gate;
s7.2, depositing SiO in the window of the double-auxiliary gate 2 Material to form SiO 2 A dielectric layer 015;
specifically, a layer of SiO with a thickness of 5nm is deposited on the window 2 As SiO in sub-gates 2 A dielectric layer 015.
Step S7.3, please refer to FIG. 22, in SiO 2 A polysilicon material is deposited on the dielectric layer 015 to form an electrode 016 in the sub-gate.
In step S7.4, referring to fig. 23, a CVD process is used to deposit BPSG on the surface of the device to form a dielectric layer 013, so as to protect the double sub-gates.
And S8, etching the dielectric layer to form a metal contact hole, forming a metal electrode on the surface of the device, etching to remove the dielectric layer at the region except the metal contact hole, forming a passivation dielectric layer on the surface of the device, and respectively forming metal contact holes on the upper sides of the heavily doped source region and drain region and the upper side of the electrode in the auxiliary gate to finally form the MOS anti-radiation device with a double-auxiliary-gate structure.
In one embodiment, step S8 includes:
s8.1, referring to fig. 24, the dielectric layer 013 is etched with nitric acid and hydrofluoric acid to form metal contact holes.
S8.2, referring to fig. 25, depositing a metal wire layer 017 on the surface of the device by an electron beam evaporation process.
Preferably, the thickness of the metal wire layer is 20 nm.
And S8.3, referring to fig. 26, removing the metal wire layer in the metal contact hole removing area by etching by using a selective etching process to form a metal electrode 017, and performing planarization by using a CMP process.
S8.4, depositing an SiN material on the surface of the device by utilizing a CVD (chemical vapor deposition) process to form a passivation dielectric layer 018, and finally forming the MOS anti-radiation device with the drain terminal composite double-auxiliary-gate structure.
Specifically, referring to fig. 27, a SiN material 018 with a thickness of 20-30 nm is deposited on the entire surface of the substrate by using a CVD process for passivating a dielectric, and finally, the MOS radiation-resistant device with the drain terminal composite double-side gate structure is formed.
According to the invention, a double-auxiliary gate structure is added on a traditional MOS device, the schematic structural diagram is shown in FIG. 27, the double-auxiliary gate structure is composed of undoped silicon 010 and silicon dioxide 015, wherein the silicon dioxide is used as a gate oxide medium and has a height of 5nm, and the silicon dioxide is selected as the gate oxide, so that the process manufacturing is facilitated, and the possibility of polluting a chip due to the introduction of other elements in the process is avoided; the intrinsic silicon is used as an isolation layer, the height of the isolation layer can influence the capability of the sub-gate for controlling the strength of an electric field below the LDD, the thinner the intrinsic silicon is, the stronger the gate control capability of the intrinsic silicon is, but if the intrinsic silicon is too thin, leakage current can be generated to influence the normal working current of the MOS device. After the two aspects are comprehensively considered, the height of the intrinsic silicon of the auxiliary grid in the novel anti-irradiation MOS device provided by the invention is 10nm, so that the channel current of the normal work of the MOS device is not influenced, and the double-auxiliary-grid MOS device has better anti-irradiation capability.
The mechanism of pulse current generated by heavy particle bombardment of the conventional MOS device is shown in FIG. 28, the drain reverse biased PN junction depletion region of the conventional MOS device is wider, the electric field is stronger, the current carrier generated by irradiation effect is stronger in collecting capability, and the formed pulse current may cause damage of the MOS device or cause error of logic function of a circuit. After the double-auxiliary gate structure is introduced, the anti-irradiation mechanism is shown in fig. 29, the double-auxiliary gate structure can weaken the electric field at the drain end, on one hand, the transverse electric field formed by the reverse bias of the PN junction at the drain end can be alleviated, so that the charge collection capability of the electrode is reduced, a large number of electron-hole pairs generated by single particle injection are recombined and disappear before being collected by the electrode, and the probability of the avalanche effect of the generated electron-hole pairs is greatly reduced along with the reduction of the electric field intensity; on the other hand, although the sub-gate is grounded, the sub-gate is insulated from the substrate, so that leakage current does not exist, and the current when the device normally works is not influenced. Since the LDD potential is pulled down after the addition of the sub-gate, the threshold voltage is lowered compared to the conventional MOS device, and the influence of the variation in the threshold voltage can be completely eliminated by taking it into consideration in the circuit design thereof. In conclusion, after the double-auxiliary-gate structure is added, the normal working state of the MOS device is not negatively influenced, and the device has the characteristic of radiation resistance.
The invention provides an MOS anti-irradiation device with a double-auxiliary gate structure, which solves the problem of logic error upset of an integrated circuit caused by a single event effect from the perspective of the device and realizes that the integrated circuit formed by the novel MOS device can stably work in a high-radiation environment.
The invention adds double auxiliary gates at the gate end of the MOS device, the auxiliary gate is composed of intrinsic Si and SiO2, the structure is simple, the integration is easy, the invention is compatible with the existing silicon process, the manufacturing cost is low, and the current of the MOS in normal operation is not influenced.
Example two
Referring to fig. 27, the present invention provides an MOS radiation-resistant device with a double-gate structure based on the first embodiment, where the MOS radiation-resistant device is prepared by the preparation method provided in the first embodiment, and the MOS radiation-resistant device includes:
a P-type Si substrate layer;
the P-type Si layer is positioned on the P-type Si substrate layer;
two SiO 2 Columns located on the grooves at two ends of the P-type Si substrate layer, wherein the P-type Si layer is located on the two SiO layers 2 Between the columns;
the gate oxide layer is positioned on part of the P-type Si layer;
the gate electrode is positioned on the gate oxide layer;
the lightly doped source region and the drain region are positioned in the P-type Si layer, and the lightly doped source region and the drain region are positioned on two sides of the gate electrode;
the heavily doped source region and the heavily doped drain region are positioned in the P-type Si layer, and the lightly doped source region and the lightly doped drain region are positioned between the heavily doped source region and the heavily doped drain region;
first Si 3 N 4 The side walls are positioned at the side part and the top part of the gate electrode;
a Si sidewall at the first Si 3 N 4 Two sides of the side wall;
second Si 3 N 4 The side walls are positioned on two sides of the Si side wall;
SiO 2 the dielectric layer is positioned on the Si side wall;
an electrode in the sub-gate on the SiO 2 A dielectric layer;
a dielectric layer on the SiO 2 A column, part of the heavily doped source region and drain region, the first Si 3 N 4 Side wall, second Si 3 N 4 A side wall;
the metal contact holes are respectively positioned on the upper sides of the heavily doped source region and the heavily doped drain region and on the upper side of the electrode in the auxiliary gate;
and the passivation dielectric layer is positioned on the dielectric layer and the metal electrode.
In the description of the invention, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristic data points described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A preparation method of a MOS anti-radiation device with a double-auxiliary gate structure is characterized by comprising the following steps:
s1, preparing a P-type Si substrate layer, preparing a P-type Si layer on the P-type Si substrate layer, and preparing SiO on the P-type Si layer 2 A protective layer and a layer on the SiO 2 Si on the protective layer 3 N 4 A layer;
s2, etching the SiO at the position of the groove area 2 Protective layer of said Si 3 N 4 A layer, the P-type Si layer and the P-type Si substrate layer with partial depth, forming a groove, and filling SiO in the groove 2 Material to form SiO 2 A column;
s3, removing the SiO on the P-type Si layer 2 Protective layer and said Si 3 N 4 The layer is used for preparing a gate oxide layer and a gate electrode positioned on the gate oxide layer on the P-type Si layer, and a lightly doped source region and a lightly doped drain region are formed on two sides of the gate electrode;
s4, forming a first Si on the side and top of the gate electrode 3 N 4 A side wall at the first Si 3 N 4 Forming Si side walls at the side parts and the top parts of the side walls, and forming second Si at the side parts and the top parts of the Si side walls 3 N 4 A side wall;
s5, using the second Si 3 N 4 The side wall is used as a mask and is close to the SiO 2 Forming a heavily doped source region and a heavily doped drain region at one side of the pillar, wherein the lightly doped source region and the lightly doped drain region are positioned between the heavily doped source region and the heavily doped drain region;
s6, removing partial depth of the second Si 3 N 4 A side wall and the Si side wall to expose the first Si 3 N 4 Forming a dielectric layer on the surface of the side wall and the surface of the device;
s7, removing the dielectric layer on the Si side wall and the partial deep Si side wall to form a window of the double-auxiliary gate, and forming SiO in the window of the double-auxiliary gate 2 A dielectric layer, then on the SiO 2 Forming an electrode in the auxiliary gate on the dielectric layer, and forming the dielectric layer on the surface of the device, wherein the window of the double auxiliary gates comprises two windows of the auxiliary gates;
and S8, etching the dielectric layer to form a metal contact hole, forming a metal electrode on the surface of the device, etching to remove the dielectric layer at the region except the metal contact hole, and forming a passivation dielectric layer on the surface of the device, wherein the metal contact hole is respectively positioned on the upper sides of the heavily doped source region and drain region and the upper side of the electrode in the auxiliary gate, and finally forming the MOS anti-radiation device with the double-auxiliary-gate structure.
2. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S1 includes:
s1.1, selecting a Si substrate;
s1.2, cleaning the Si substrate by using an RCA method, and removing an oxide layer on the surface of the Si substrate;
s1.3, doping P-type impurities into the Si substrate to form a P-type Si substrate layer;
s1.4, depositing the P-type Si layer on the P-type Si substrate layer by utilizing a molecular beam epitaxy process;
s1.5, depositing the SiO on the P-type Si layer by using a CVD process 2 A protective layer;
s1.6, CVD process is utilized to form the SiO 2 Depositing said Si on the protective layer 3 N 4 And (3) a layer.
3. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S2 includes:
s2.1, etching the SiO at the position of the groove area 2 Protective layer of said Si 3 N 4 A layer to form a trench region window;
s2.2, etching the P-type Si layer at the window of the groove area and the P-type Si substrate layer with partial depth by using a dry etching process to form a groove;
s2.3, utilizing a CVD process to perform reaction between Si and the groove 3 N 4 Filling SiO on the layer 2 A material;
s2.4, removing the Si by using a CMP method 3 N 4 SiO on the surface of the layer 2 Material to form SiO 2 And (3) a column.
4. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S3 includes:
s3.1, respectively using H 3 PO 4 And HF etching the Si on the P-type Si layer 3 N 4 Layer and the SiO 2 A protective layer;
s3.2, depositing a gate oxide layer on the P-type Si layer;
s3.3, depositing a gate electrode material on the gate oxide layer;
s3.4, etching the gate electrode material and the gate oxide layer to form the gate electrode;
and S3.5, etching a window for carrying out source-drain doping on the photoresist, and carrying out ion implantation on the window by adopting an ion implantation process so as to form a lightly doped source region and a lightly doped drain region on two sides of the gate electrode.
5. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure as claimed in claim 4, wherein the step S4 comprises:
s4.1, removing the photoresist in the step S3.5, and repeating the stepsCovering the device with photoresist, etching to remove the photoresist on the side and top of the gate electrode, and depositing Si on the region on the side and top of the gate electrode where the photoresist is removed 3 N 4 Material to form the first Si on the side and top of the gate electrode 3 N 4 A side wall;
s4.2, removing the photoresist in the step S4.1, covering the device by using the photoresist again, and removing the first Si by etching 3 N 4 Photoresist on the side part and the top part of the side wall so as to remove the first Si of the photoresist 3 N 4 Depositing Si material on the side wall and the top part of the side wall to form a first Si layer 3 N 4 Forming the Si side wall on the side part and the top part of the side wall;
and S4.3, removing the photoresist in the step S4.2, covering the device by using the photoresist again, and etching to remove the photoresist on the side part and the top part of the Si side wall, so that Si3N4 material is deposited in the region of the side part and the top part of the Si side wall where the photoresist is removed, and the second Si3N4 side wall is formed on the side part and the top part of the Si side wall.
6. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S5 includes:
with the second Si 3 N 4 The side wall is used as a mask and is close to the SiO by adopting a self-alignment method 2 One side of the pillar forms a heavily doped source region and drain region.
7. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S6 includes:
s6.1, removing partial depth of second Si by utilizing CMP (chemical mechanical polishing) process 3 N 4 A side wall and the Si side wall to expose the first Si 3 N 4 The surface of the side wall;
and S6.2, depositing BPSG on the surface of the device by using a CVD process to form a dielectric layer.
8. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S7 includes:
s7.1, coating photoresist on the surface of the dielectric layer, and etching to remove the dielectric layer on the Si side wall and the Si side wall with partial depth so as to form a window of the double-auxiliary gate;
s7.2, depositing SiO on the window of the double-auxiliary gate 2 Material to form SiO 2 A dielectric layer;
step S7.3, preparing SiO 2 Depositing a polysilicon material on the dielectric layer to form an electrode in the auxiliary gate;
and step S7.4, depositing BPSG on the surface of the device by using a CVD process to form a dielectric layer.
9. The method for manufacturing the MOS irradiation-resistant device with the double-side gate structure according to claim 1, wherein the step S8 includes:
s8.1, etching the dielectric layer by using nitric acid and hydrofluoric acid to form a metal contact hole;
s8.2, depositing a metal wire layer on the surface of the device by using an electron beam evaporation process;
s8.3, etching and removing the metal wire layer at the metal contact hole removing area by utilizing a selective etching process to form a metal electrode, and carrying out planarization treatment by utilizing a CMP process;
s8.4, depositing SiN materials on the surface of the device by utilizing a CVD (chemical vapor deposition) process to form a passivation dielectric layer, and finally forming the MOS anti-radiation device with the drain terminal composite double-auxiliary-gate structure.
10. A MOS radiation-resistant device of a double-auxiliary gate structure, comprising:
a P-type Si substrate layer;
the P-type Si layer is positioned on the P-type Si substrate layer;
two SiO 2 Columns located on the grooves at two ends of the P-type Si substrate layer, and the P-type Si layers are located on the two SiO layers 2 Between the columns;
the gate oxide layer is positioned on part of the P-type Si layer;
the gate electrode is positioned on the gate oxide layer;
the lightly doped source region and the drain region are positioned in the P-type Si layer, and the lightly doped source region and the drain region are positioned on two sides of the gate electrode;
the heavily doped source region and the heavily doped drain region are positioned in the P-type Si layer, and the lightly doped source region and the lightly doped drain region are positioned between the heavily doped source region and the heavily doped drain region;
first Si 3 N 4 The side walls are positioned at the side part and the top part of the gate electrode;
a Si sidewall at the first Si 3 N 4 Two sides of the side wall;
second Si 3 N 4 The side walls are positioned on two sides of the Si side wall;
SiO 2 the dielectric layer is positioned on the Si side wall;
an electrode in the sub-gate on the SiO 2 A dielectric layer;
a dielectric layer on the SiO 2 A column, part of the heavily doped source region and drain region, the first Si 3 N 4 Side wall, second Si 3 N 4 A side wall;
the metal contact holes are respectively positioned on the upper sides of the heavily doped source region and the heavily doped drain region and on the upper side of the electrode in the auxiliary gate;
and the passivation dielectric layer is positioned on the dielectric layer and the metal electrode.
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