CN114863978A

CN114863978A - Nonvolatile memory, erasing operation method thereof and nonvolatile memory system

Info

Publication number: CN114863978A
Application number: CN202210617595.XA
Authority: CN
Inventors: 周稳; 刘红涛; 贾建权; 靳磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-06-01
Filing date: 2022-06-01
Publication date: 2022-08-05

Abstract

The application provides a nonvolatile memory, an erasing operation method thereof and a storage system. The erasing operation method comprises the following steps: after time t0 in the pre-erase phase, making the voltage on the first bit line rise with a preset slope, and keeping the target erase voltage reached in the erase phase; applying a ground voltage to the first drain select line before time t2 within the pre-erase phase and maintaining the first drain select line in a floating state after time t 2; and applying a bias voltage to at least one first word line connected to the memory cell to be erased in an erasing phase, wherein the difference between the target erasing voltage and the bias voltage is greater than an erasing threshold value.

Description

Nonvolatile memory, erasing operation method thereof and nonvolatile memory system

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a nonvolatile memory, an erase operation method of the nonvolatile memory, a nonvolatile memory system, a nonvolatile memory suitable for a neural network algorithm, and a nonvolatile memory system suitable for a neural network algorithm.

Background

Non-volatile memory is capable of retaining data stored therein after a power failure and is widely used in computers, cellular phones, smart phones, personal digital assistants, and other electronic device systems. One type of nonvolatile memory may include NAND strings composed of, for example, a plurality of memory cells connected in series, one end of the plurality of NAND strings being connected to a common source line to constitute a block (block), so that the plurality of memory cells included in the NAND strings are erased in units of blocks in one erase operation, and it is difficult to selectively cause some of the memory cells to be erased in one erase operation.

On the other hand, the rapid development of artificial neural networks (referred to as neural networks for short) has led to new wave of research in artificial intelligence. When a non-volatile memory is used for executing a neural network algorithm, a hardware platform of the neural network faces a problem caused by mismatching of storage utilization rate and calculation parameter participation amount along with rapid increase of parameter scale and operation amount of the neural network.

Disclosure of Invention

An aspect of the present application provides an erase operation method of a nonvolatile memory, wherein the nonvolatile memory includes a memory block, the memory block includes a plurality of memory strings, at least one first memory string among the plurality of memory strings is connected between a first bit line and a source line, and includes a drain select transistor adjacent to the first bit line and a plurality of memory cells between the drain select transistor and the source line, the drain select transistor and the memory cells are connected to the drain select line and a word line, respectively, the method including: after time t0 in the pre-erase phase, making the voltage on the first bit line rise with a preset slope, and keeping the target erase voltage reached in the erase phase; applying a ground voltage to the first drain select line before time t2 within the pre-erase phase and maintaining the first drain select line in a floating state after time t 2; and applying a bias voltage to at least one first word line connected to the memory cell to be erased in an erasing phase, wherein the difference between the target erasing voltage and the bias voltage is greater than an erasing threshold value.

In some embodiments, the first memory string further includes a source select transistor located between the plurality of memory cells and the source line, the source select transistor being connected to the source select line, the method further comprising: after time t0 in the pre-erase phase, making the voltage on the source selection line rise with a preset slope, and keeping the target erase voltage reached in the erase phase; or in the pre-erase phase and the erase phase, the source select line is kept in a floating state.

In some embodiments, the method further comprises: before time t3 in the pre-erase phase, a ground voltage is applied to a second word line other than the first word line, and the second word line is kept in a floating state after time t 3.

In some embodiments, the memory block further includes a second drain select line other than the first drain select line, the method further comprising: the ground voltage is applied to the second drain select line prior to time t1 in the pre-erase phase and the second drain select line is held in a floating state after time t1, where time t1 is earlier than time t 2.

In some embodiments, the memory block further includes a second bit line other than the first bit line, the method further comprising: after time t2 in the pre-erase phase, the voltage on the second bit line is raised with a preset slope and the target non-erase voltage reached is maintained during the erase phase.

In some embodiments, the target non-erase voltage is less than the target erase voltage.

In some embodiments, the first memory string further includes a drain dummy memory cell between the drain select transistor and the plurality of memory cells, the drain dummy memory cell being connected to a drain dummy word line, the method further comprising: before time t3 in the pre-erase phase, a ground voltage is applied to the drain dummy word line and the drain dummy word line is kept in a floating state after time t 3.

In some embodiments, the first memory string further includes a source dummy memory cell located between the source select transistor and the plurality of memory cells, the source dummy memory cell connected to a source dummy word line, the method further comprising: prior to time t1 in the pre-erase phase, a ground voltage is applied to the source dummy word line and the source dummy word line is held in a floating state after time t1, where time t1 is earlier than time t 2.

In some embodiments, the bias voltage is a ground voltage.

Another aspect of the present application provides a nonvolatile memory including: a memory block including a plurality of memory strings, at least one first memory string of the plurality of memory strings being connected between a first bit line and a source line and including a drain select transistor adjacent to the first bit line and a plurality of memory cells between the drain select transistor and the source line, the drain select transistor and the memory cells being connected to the drain select line and a word line, respectively; and the peripheral circuitry is configured to: after time t0 in the pre-erase phase, making the voltage on the first bit line rise with a preset slope, and keeping the target erase voltage reached in the erase phase; applying a ground voltage to the first drain select line before time t2 within the pre-erase phase and maintaining the first drain select line in a floating state after time t 2; and applying a bias voltage to at least one first word line connected to the memory cell to be erased in an erasing phase, wherein the difference between the target erasing voltage and the bias voltage is greater than an erasing threshold value.

In some embodiments, the first memory string further includes a source select transistor located between the plurality of memory cells and the source line, the source select transistor connected with the source select line, the peripheral circuitry further configured to: after time t0 in the pre-erase phase, making the voltage on the source selection line rise with a preset slope, and keeping the target erase voltage reached in the erase phase; or in the pre-erase phase and the erase phase, the source select line is kept in a floating state.

In some embodiments, the peripheral circuitry is further configured to: before time t3 in the pre-erase phase, a ground voltage is applied to a second word line other than the first word line, and the second word line is kept in a floating state after time t 3.

In some embodiments, the memory block further comprises second drain select line peripheral circuitry other than the first drain select line further configured to: before time t1 in the pre-erase phase, applying a ground voltage to the second drain select line and maintaining the second drain select line in a floating state after time t1, wherein time t1 is earlier than time t 2.

In some embodiments, the memory block further includes a second bit line other than the first bit line, the peripheral circuitry further configured to: after time t2 in the pre-erase phase, the voltage on the second bit line is raised with a preset slope and the target non-erase voltage reached is maintained during the erase phase.

In some implementations, the first memory string further includes a drain dummy memory cell located between the drain select transistor and the plurality of memory cells, the drain dummy memory cell connected with a drain dummy word line, the peripheral circuitry further configured to: before time t3 in the pre-erase phase, a ground voltage is applied to the drain dummy word line and the drain dummy word line is kept in a floating state after time t 3.

In some implementations, the first memory string further includes a source dummy memory cell located between the source select transistor and the plurality of memory cells, the source dummy memory cell connected with a source dummy word line, the peripheral circuitry further configured to: prior to time t1 in the pre-erase phase, a ground voltage is applied to the source dummy word line and the source dummy word line is held in a floating state after time t1, where time t1 is earlier than time t 2.

In some embodiments, the bias voltage is a ground voltage.

Another aspect of the present application also provides a nonvolatile memory system, including: at least one non-volatile memory as described in any of the previous embodiments; and a controller connected to the at least one non-volatile memory and configured to control peripheral circuits in the non-volatile memory.

The application also provides a nonvolatile memory suitable for a neural network algorithm, wherein the nonvolatile memory comprises a plurality of memory cells in different memory strings, the plurality of memory cells are connected with the same word line and correspond to one neuron in the neural network, and the plurality of memory strings in which the plurality of memory cells are located are respectively connected to a plurality of bit lines; and a peripheral circuit configured to: applying a plurality of bit line voltages to a plurality of bit lines, the bit line voltages as one input to a neuron in a neural network; applying a read voltage to a word line connected to a plurality of memory cells; determining an output of the neuron based on a plurality of conductance values in the plurality of memory cells, the conductance values serving as weights corresponding to inputs of the neuron; and performing a programming operation on at least one of the plurality of memory cells or performing an erasing operation according to the erasing operation method described in any of the foregoing embodiments to adjust the conductance value, wherein the number of the first memory strings and the first word lines is one.

In another aspect, the present application further provides a non-volatile memory system suitable for neural network algorithm, the non-volatile memory system comprising: at least one non-volatile memory as described in any of the previous embodiments; and a controller connected to the at least one non-volatile memory and configured to control peripheral circuits in the non-volatile memory.

According to at least one embodiment of the present application, in one aspect, the present application provides a nonvolatile memory, an erasing operation method of the nonvolatile memory, and a nonvolatile memory system, holes are generated in some selected memory strings in a memory block by using GIDL current, so that the potential of channel layers of the selected memory strings is raised, and at the same time, at least one selected memory cell in the selected memory strings is erased by using the potential difference between some selected word lines and the channel layers of the selected memory strings, which is beneficial to improving the erasing operation flexibility of the nonvolatile memory. Meanwhile, the reading window of the part of the memory cells can be increased by selectively erasing the part of the memory cells, so that the reading accuracy of the memory cells can be improved.

On the other hand, according to the nonvolatile memory applicable to the neural network algorithm and the nonvolatile memory system applicable to the neural network algorithm, the conductance value of a single memory cell in the nonvolatile memory is used as the weight corresponding to one input of the neuron in the neural network, so that the storage utilization rate of the nonvolatile memory for storing the parameters of the neural network can be improved, and the advantage of high storage density of the nonvolatile memory is favorably exerted. Meanwhile, a subtracter is not needed to be additionally arranged to calculate the conductance difference, compatibility with the existing peripheral circuit is facilitated, a part of storage capacity is prevented from being consumed to store the conductance difference, and the storage utilization rate of the non-volatile memory is further improved. In addition, the weight is adjusted by adjusting the conductance value of the single storage unit, so that the problem that the weight cannot be continuously adjusted after the respective conductance values of the two storage units reach the upper limit can be solved, and the realization of a more complex deep neural network is facilitated.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a functional block diagram of a non-volatile storage system connected to a host according to an embodiment of the present application;

FIG. 2 is a functional block diagram of a non-volatile memory according to an embodiment of the present application;

FIG. 3 is an equivalent circuit diagram of a memory cell array according to an embodiment of the present application;

FIG. 4 is a schematic cross-sectional view of the physical structure of a memory string connected to various control lines according to an embodiment of the present application;

FIG. 5 is a flow chart of a method of an erase operation of a non-volatile memory according to an embodiment of the present application;

FIG. 6 is a voltage waveform schematic of various control lines according to the erase operation method shown in FIG. 5;

FIG. 7 is a schematic diagram of a three-layer neural network architecture according to an embodiment of the present application;

FIG. 8 is a flow chart of a training process for a neural network according to an embodiment of the present application;

FIG. 9 is a flow chart of a method of operation of a non-volatile memory for performing a neural network in accordance with an embodiment of the present application;

fig. 10 is an equivalent circuit diagram of a two-dimensional memory cell array among the memory cell arrays shown in fig. 3;

FIG. 11 is a waveform diagram of voltages applied to n word lines to determine the output of a neuron according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a method of operating a non-volatile memory for implementing a neural network in accordance with another embodiment of the present application; and

FIG. 13 is a graph of conductance values of memory cells versus time for performing program and erase operations according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification the expressions first, second, third etc. are only used to distinguish one feature from another, and do not indicate any limitation of features, in particular any order of precedence. Thus, a first portion discussed in this application may also be referred to as a second portion and a first channel structure may also be referred to as a second structure, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1 is a functional block diagram of a non-volatile storage system 10 connected to a host 20 according to an embodiment of the present application. As shown in fig. 1, the electronic device formed by the host 20 and the storage system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an on-board computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device.

Host 20 may comprise a processor of an electronic device and be configured to control the overall operation of storage system 10, as well as to send or receive data to and from storage system 10. The host 20 may be a Central Processing Unit (CPU) or may be a system-on-chip (SoC), such as an Application Processor (AP).

The storage system 10 may store data that is accessed by the host 20. According to an interface protocol by which the storage system 10 is connected to the host 20, the storage system 10 may be configured as, for example, a Universal Flash Storage (UFS) system, a Solid State Disk (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage system, a Peripheral Component Interconnect (PCI) type storage system, a PCI express (PCI-E) type storage system, a Compact Flash (CF) card, a smart media card, or a memory stick, or any other suitable storage system.

As shown in fig. 1, the memory system 10 may include one or more non-volatile memories 110 for storing data and a controller 120 for controlling the non-volatile memories 110.

The controller 120 is coupled to the non-volatile memory 110 and the host 20, and is configured to control the operation of the non-volatile memory 110, manage data stored in the non-volatile memory 110, and communicate with the host 20. The controller 120 may, for example, include a host interface 121, a processor 122, a flash interface 123.

The host interface 121 in the controller 120 may communicate with the host 20 according to a particular communication protocol. The interface protocol of the host interface 210 may include any one of a universal flash memory (UFS) protocol, a Serial Advanced Technology Attachment (SATA) protocol, a Peripheral Component Interconnect (PCI) protocol and a PCI express (PCI-E) protocol, a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a Parallel Advanced Technology Attachment (PATA) protocol, a Small Computer System Interface (SCSI) protocol, a serial SCSI (sas) protocol, and the like.

The processor 122 in the controller 120 may, for example, include one or more ARM cores. The processor 122 may control the inherent operation of the non-volatile memory 110 and provide compatibility to the host 20 by driving firmware called a Flash Translation Layer (FTL). Further, the processor 220 may also implement functions such as Wear Leveling (Wear Leveling), Garbage Collection (Garbage Collection), Bad Block Management (Bad Block Management), etc., by driving other firmware, for example.

The flash interface 123 in the controller 120 may be responsible for managing data to read from and write to the non-volatile memory 110, for example, according to flash commands that conform to the ONFI or Toggle standards. For example, for each non-volatile memory 110, commands, addresses, and data may be transferred thereto through the flash interface 123. For multiple non-volatile memories 110, a particular non-volatile memory 110 may be selected by, for example, a strobe signal, prior to transmitting commands, addresses, and data.

Each non-volatile memory 110 may be referred to as a die (die), which may also be referred to as a memory granule. Each die may be the smallest basic management unit for flash memory communications. Illustratively, the non-volatile memory 110 may be a NAND type memory. One non-volatile memory 110 or multiple non-volatile memories 110 may be integrated into one package. For example, 4-8 non-volatile memories 110 may be packaged together. It should be noted that the number of the nonvolatile memory 110 packages can be designed according to the capacity requirement, and the specific number is not limited in this application.

Fig. 2 is a functional block diagram of a nonvolatile memory 210 according to an embodiment of the present application. Among them, the nonvolatile memory 210 may be one example of the plurality of nonvolatile memories 110 shown in fig. 1. As shown in fig. 2, the nonvolatile memory 210 may include a memory cell array 220 and peripheral circuits such as a page buffer 231, a row decoder 232, a column decoder 233, a voltage generator 234, a logic control module 235, an I/O module 236, and a data bus 237. It should be understood that the operations performed by the above described circuit modules described in this application may be performed by processing circuitry. Alternatively, the processing circuitry may include, but is not limited to, hardware of logic circuitry or a hardware/software combination of a processor executing software.

The memory cell array 220 may include a plurality of memory cells arranged in a three-dimensional array formation. The plurality of memory cells may be connected to a plurality of Bit Lines (BL) and a plurality of Word Lines (WL) in a predetermined connection manner. Illustratively, each memory cell may be any one of a single-layer memory cell (SLC) capable of storing one bit of data, a two-layer memory cell (MLC) capable of storing two bits of data, a three-layer memory cell (TLC) capable of storing three bits of data, and a four-layer memory cell (QLC) capable of storing four bits of data. For example, multiple SLC memory cells connected by the same word line correspond to a Page (Page).

The page buffer (alternatively referred to as "sense amplifier") 231 may be configured to read data from the memory cell array 220 or program (write) data to the memory cell array 220 according to a control signal from the logic control module 235. In some examples, the page buffer 231 may store data to be programmed to one page in the memory cell array 220. In other examples, the page buffer 231 may sense a low-power signal of data stored in memory cells of the memory cell array 220 in a read operation and amplify a small voltage swing to an identifiable logic level.

The row decoder 232 may be configured to be controlled by the logic control module 235 and to select a page in the memory cell array 220. For example, the row decoder 232 may be configured to select a corresponding page by driving a word line using a voltage generated by the voltage generator 234.

The column decoder 233 may be configured to be controlled by the logic control module 235 and select a corresponding bit line by applying a bit line voltage generated by the voltage generator 234.

The voltage generator 234 may be configured to be controlled by the logic control module 235 and generate a word line voltage (e.g., a charging voltage, a ground voltage, a read voltage, a program voltage, a pass voltage, a verify voltage, etc.), a bit line voltage (e.g., an erase voltage, a non-erase voltage, etc.), a source line voltage, and the like, to be provided into the memory cell array 220.

The logic control module 235 may be coupled to each of the peripheral circuit modules described above and configured to control the operation of the respective peripheral circuit modules, and the logic control module 235 may control to perform an erase operation method 500 (refer to fig. 5) and/or an operation method 900 (refer to fig. 9) of the neural network to be described below.

I/O module 236 may be coupled to logical control module 235 to forward control commands received from host 20 (see fig. 1) or controller 120 (see fig. 1) to logical control module 235 and to forward status information received from logical control module 235 to controller 120 (see fig. 1). The I/O module 236 may also be coupled to a column decoder 233 via a data bus 237 for buffering and forwarding data to and from the memory cell array 220.

Fig. 3 is an equivalent circuit diagram of a memory cell array 320 according to an embodiment of the present application.

Among them, the memory cell array 320 may be an example of a portion of the memory cell array 220 shown in fig. 2. For example, the memory cell array 320 shown in fig. 3 may be referred to as a memory block.

As shown in FIG. 3, a memory block may include multiple memory strings (e.g., Str11, Strm1, Str1p, Strmp, etc.). For example, the plurality of memory strings Str 11-Strmp may be arranged in a two-dimensional array with respect to the xy plane. Each memory string (e.g., Str11) may extend in the z-direction and be connected between a source line ACS and a bit line (e.g., BL 1). Illustratively, the memory string Str11 may in turn include drain select transistors DST connected in series with each other ₁₁ Drain dummy memory cell D-DMC ₁₁ Memory cell MC1 ₁₁ ～MCn ₁₁ Source dummy memory cell S-DMC ₁₁ And a source selection transistor SST ₁₁ . Illustratively, for each memory string (e.g., Str11), drain dummy memory cell D-DMC ₁₁ And/or source dummy memory cell S-DMC ₁₁ Can be omitted, orDrain dummy memory cell D-DMC ₁₁ And/or source dummy memory cell S-DMC ₁₁ The number of (2) is not limited to the one shown in FIG. 3, and both may have other numbers, for example, 2 to 5. In addition, it should be noted that each memory string (e.g., Str11) includes a drain select transistor DST ₁₁ Source selection transistor SST ₁₁ And a memory cell MC1 ₁₁ ～MCn ₁₁ Nor is it specifically limited by this application.

A plurality of memory cells (e.g., MCk) in each of the memory strings Str 11-Strmp located at (approximately) the same height from the source line ASC ₁₁ 、MCk _m1 、MCk _1p And MCk _mp Etc.) may be connected to the same word line (e.g., WLk), such that, for example, the memory block includes a plurality of word lines WL 1-WLn. As previously described, multiple memory cells (e.g., MCk) connected to the same word line (e.g., WLk) ₁₁ 、MCk _m1 、MCk _1p And MCk _mp Etc.) may be controlled by the word line (e.g., WLk) that connects a plurality of memory cells (e.g., MCk) ₁₁ 、MCk _m1 、MCk _1p And MCk _mp Etc.) may constitute one page such that, for example, a memory block includes a plurality of pages corresponding to a plurality of word lines WL1 WLn.

A plurality of drain select transistors (e.g., DST) located at (approximately) the same height from the source line ACS among the plurality of memory strings (e.g., Str11 to Strm1) arranged in the x-direction ₁₁ ～DST _m1 ) May be connected to the same drain select line (e.g., DSL1) such that, for example, the memory block includes a plurality of drain select lines DSL1 DSLp disposed in the y-direction.

The other ends of the multiple memory strings (e.g., Str 11-Str 1p) arranged in the y-direction may be connected to the same bit line (e.g., BL 1). Illustratively, each drain select transistor (e.g., DST) at an end of each memory string (e.g., Str 11-Str 1p) ₁₁ ～DST _1p ) May be connected to a bit line BL1 such that, for example, the memory block includes a plurality of bit lines BL 1-BLm arranged along the x-direction.

In some examplesA plurality of source select transistors (e.g., SST) in each of the memory strings Str 11-Strmp in the memory block, which are located at (approximately) the same height from the source line ACS ₁₁ ～SST _mp ) May be connected to each other and to the same source select line SSL, such that, for example, the memory block comprises one source select line SSL.

In some examples, one end of the plurality of memory strings Str 11-Strmp in a memory block may be commonly connected to source line ACS. Illustratively, each source select transistor (e.g., SST) at an end of each memory string Str 11-Strmp ₁₁ ～SST _mp ) May be connected to the source line ACS.

In some examples, a plurality of drain dummy memory cells (e.g., D-DMC) in each memory string Str 11-Strmp in a memory block that are located at (approximately) the same height from source line ACS ₁₁ ～D-DMC _mp ) May be connected to the same drain dummy word line (e.g., D-DWL). A plurality of source dummy memory cells (e.g., S-DMC) located at (approximately) the same height from the source line ACS in each of the memory strings Str 11-Strmp in the memory block ₁₁ ～S-DMC _mp ) May be connected to the same source dummy word line (e.g., S-DWL).

The physical structure of the memory strings in the memory cell array is exemplarily described below. Fig. 4 is a schematic cross-sectional view of a physical structure in which a memory string 400 is connected to respective control lines according to an embodiment of the present application. Storage string 400 may be, for example, storage string Str11 shown in FIG. 3.

As shown in fig. 4, the memory string 400 may include a charge blocking layer 401, a charge trapping layer 402, a tunneling layer 403, and a channel layer 404 disposed in sequence from the outside to the inside. Among them, the charge blocking layer 401, the charge trapping layer 402, and the tunneling layer 403 may be referred to as a functional layer 405. Illustratively, the materials of the charge blocking layer 401, the charge trapping layer 402 and the tunneling layer 403 may be silicon oxide, silicon nitride and silicon oxide, respectively. The material of the channel layer 404 may be a semiconductor material, such as P-type doped polysilicon.

In some examples, the drain select lines DSL1, the drain dummy word lines D-DWL, the word lines WL1 WLn, the source dummy word lines S-DWL, the source select lines SSL may be sequentially disposed at intervals along the extending direction (e.g., z-direction) of the memory string 400. The respective control lines (e.g., WLk) described above may be disposed around the charge blocking layer 401 and in contact with the charge blocking layer 401. Illustratively, the material of the various control lines (e.g., WLk) described above may include tungsten, doped polysilicon, or any suitable conductive material.

In some examples, each word line (e.g., WLk) and the partial functional layer 405 and channel layer 404 corresponding to the word line WLk collectively form a memory cell (e.g., MCk) ₁₁ ). For example, applying a voltage to the word line WLk may cause charges (e.g., electrons) in the channel layer 404 to be injected into the charge trapping layer 402, or cause charges (e.g., holes) in the channel layer 404 to be injected into the charge trapping layer 402 through cooperation of the word line WLk and other control lines. As shown in FIG. 4, a plurality of memory cells (e.g., MC 1) are arranged in the z-direction ₁₁ ～MCn ₁₁ ) The channel layer 404, in other words, a plurality of memory cells (e.g., MC 1) ₁₁ ～MCn ₁₁ ) Can be arranged in series in the z-direction (similar to NAND gates).

Note that, as described above, for one memory cell (e.g., MCk) ₁₁ ) In other words, the charge trapping layer 402 made of a dielectric material (e.g., silicon nitride) may be similar to traps, making it difficult for charges to escape after being injected therein, and thus such a memory cell may be referred to as a charge trapping memory cell. In other examples, the functional layer may sequentially include a charge blocking layer, a floating gate layer, and a tunneling layer, the floating gate layer may be made of, for example, a conductive material, and after charges are injected into the floating gate layer, the charge blocking layer and the tunneling layer made of a dielectric material and located on both sides of the floating gate layer may allow the charges to be stored in the floating gate layer without charge escape, so the memory cell may be referred to as a floating-gate type memory cell.

In some examples, channel plug 406 may be located at one end of memory string 400 and connected to a bit line (e.g., BL 1). For example, the channel plug 406 may be located inside the tunneling layer 403 and in contact with the channel layer 404. Illustratively, the material of the channel plug 406 may be a semiconductor material, such as N-type doped polysilicon. At the other end of the memory string 400, away from the channel plug 406, the channel layer 404 may be connected with the source line ACS. For example, the channel layer 404 protrudes from the end surface of the functional layer 405 and extends into the source line ACS. Illustratively, the material of the source line ACS may be a semiconductor material, such as N-type doped polysilicon. It is noted that the various memory strings (e.g., memory strings Str 11-Strmp shown in FIG. 3) may have the same physical structure, and multiple memory strings (e.g., memory strings Str 11-Strmp shown in FIG. 3) may be connected to the same source line ACS.

FIG. 5 is a flow chart of a method 500 for an erase operation of a non-volatile memory according to an embodiment of the present application. Fig. 6 is a voltage waveform schematic of various control lines according to the erase operation method 500 shown in fig. 5. The erase operation method 500 and the voltage variation of the respective control lines are further described below in conjunction with the plurality of memory strings Str 11-Strmp included in the memory cell array 320 shown in FIG. 3 and the physical structure of the memory string 400 shown in FIG. 4. In fig. 6, the solid line in the voltage variation curve of each control line indicates that the voltage variation curve is realized by the control voltage, and the dotted line indicates that the voltage variation curve is realized by the coupling effect of other control voltages. In the present application, the ground voltage Vgnd is a voltage close to 0V, and for example, the ground voltage Vgnd floats in a range of-10% to 10% with respect to 0V.

As shown in FIG. 3, when storing memory cell MCk in string Str11 ₁₁ The memory cell MCk being a memory cell to be erased ₁₁ May be referred to as a selected memory cell. The storage unit MCk ₁₁ The located storage string Str11 may be referred to as the selected storage string (i.e., the first storage string). Further, with the selected memory cell MCk ₁₁ The connected word line may be referred to as a selected word line Sel WL (i.e., a first word line WLk), and the word lines other than the selected word line WLk may be referred to as unselected word lines Unsel WL (i.e., second word lines WL1 to WL3, WLn-2 to WLn, etc.); the bit line connected to the selected memory string Str11 may be referred to as the selected bit line Sel BL (i.e., the first bit line BL1), while the bit lines other than the selected bit line BL1 may be referred to as the unselected bit lines Unsel BL (i.e., the second bit line BLm, etc.); with the drain select transistor DST in the selected memory string Str11 ₁₁ The connected drain select line may be referred to as a selected drain select line Sel DSL (i.e., a first drain select line DSL1), and the drain select lines other than the selected drain select line DSL1 may be referred to as unselected drain select lines Unsel DSL (i.e., a second drain select line DSLp, etc.).

As shown in fig. 3 and 6, the erase operation process may include a pre-erase phase, an erase phase, and a recovery phase in sequence. The pre-erase phase is a time period before the time t4 in the erase cycle, the erase phase is a time period between the time t4 and the time t5 in the erase cycle, and the recovery phase is a time period after the time t5 in the erase cycle. In some examples, prior to time t0, selected memory cell MCk is associated with ₁₁ The associated respective control lines, such as the selected bit line Sel BL (i.e., the first bit line BL1), the selected drain select line Sel DSL (i.e., the first drain select line DSL1), the selected word line Sel WL (i.e., the first word line WLk), the unselected word lines Unsel WL (i.e., the second word lines WL 1-WL 3, WLn-2-WLn, etc.), the source select line SSL, the drain dummy word line D-DWL, and the source dummy word line S-DWL, may each hold the ground voltage Vgnd.

After time t0 in the pre-erase phase, the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) is set to have a preset slope R ₁ Rises and reaches the target erase voltage Vt-erase at time t4 when the pre-erase phase ends (i.e., the erase phase begins). During the erase phase from time t4 to time t5, the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) is kept constant at the target erase voltage Vt-erase. For example, the target erase voltage is greater than 10V. It is noted that, in some examples, the predetermined slope R may be applied to the selected bit line Sel BL (i.e., the first bit line BL1), for example ₁ The same voltage, so that the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) is at the preset slope R between the time t0 and the time t4, for example ₁ Rises and maintains the trend of the target erase voltage Vt-erase between time t4 and time t 5. In other examples, the target erase voltage Vt-erase may be applied, for example, at time t0, since the control line (e.g., the first bit line BL1) may be equivalent to a series capacitance and resistance, in capacitive couplingUnder the influence of the resultant effect, the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) is made to have a preset slope R between the time t0 and the time t4, for example ₁ Rises and maintains the trend of the target erase voltage Vt-erase between time t4 and time t 5.

Before time t2 of the pre-erase phase, the ground voltage Vgnd is applied to the selected drain select line Sel DSL (i.e., the first drain select line DSL1), and the selected drain select line Sel DSL (i.e., the first drain select line DSL1) is kept in a floating state after time t 2. After time t2 of the pre-erase phase, due to, for example, a coupling effect of the voltage of the channel layer 404 (refer to fig. 4), the selected drain select line Sel DSL (i.e., the first drain select line DSL1) follows a preset slope R, for example, between time t2 and time t4 ₁ Rises and maintains the trend of its target voltage V-sel dsl between time t4 and time t5 of the erase phase. In other words, the selected drain select line Sel DSL (i.e., the first drain select line DSL1) is not affected by the coupling action by applying the ground voltage Vgnd to the selected drain select line Sel DSL (i.e., the first drain select line DSL1) between time t0 and time t 2.

It should be noted that, at time t2 of the pre-erase phase, the difference between the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) (or the voltage transferred to the channel plug 406 (refer to fig. 4) made of, for example, N-type doped polysilicon material) and the voltage on the selected drain select line Sel DSL (i.e., the first drain select line DSL1) can generate GIDL current, so that holes (in the direction shown in fig. 4 [) enter the drain select transistor DST in the selected memory string (e.g., the first memory string Str11) ₁₁ The corresponding channel layer 404 (refer to fig. 4), thereby raising the potential of the channel layer 404. Illustratively, after time t2 of the pre-erase phase, due to the coupling effect of the channel layer 404 (refer to fig. 4) voltage, the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) and the voltage on the selected drain select line Sel DSL (i.e., the first drain select line DSL1) may maintain a constant difference to generate the GIDL current. Illustratively, the time interval between time t2 and time t0 may further satisfy: so that at time t2Thereafter, the difference between the target voltage V-Sel DSL and the target erase voltage Vt-erase reached by the selected drain select line Sel DSL (i.e., DSL1) while remaining in the floating state is less than the erase threshold (e.g., greater than 10V) to avoid the drain select transistor DST in the selected memory string (e.g., first memory string Str11) ₁₁ Is erased. The erase threshold is a minimum value of a voltage difference between the channel layer 404 and a word line or a select line when holes in the channel layer 404 are injected into the charge trapping layer 402.

Between the time of the erase phase t4 and t5, the memory cells MCk to be erased ₁₁ The connected selected word line Sel WL (i.e., the first word line WLk) applies a bias voltage, for example, the bias voltage is the ground voltage Vgnd, such that the voltage in the channel layer 404 continuously rises from time t0 to time t4 due to the voltage on the selected bit line Sel BL (i.e., the first bit line BL1), and also continuously rises from time t0 to time t4 by generating the GIDL current until the voltage in the channel layer 404 reaches the target erase voltage Vt-erase at time t4 when the pre-erase phase ends (i.e., the erase phase begins), and when the bias voltage (e.g., the ground voltage vd) is applied to the selected word line Sel WL (i.e., the first word line WLk), the selected memory cell MCk due to the difference between the target erase voltage Vt-erase voltage and the bias voltage (e.g., the ground voltage Vgnd) being greater than the erase threshold ₁₁ Erased according to the FN tunneling effect. Alternatively, the memory cell MCk to be erased may be always accessed from the pre-erase phase to the erase phase ₁₁ The connected selected word line Sel WL (i.e., the first word line WLk) applies the above-described bias voltage.

It should be noted that, although the present application exemplarily describes that the number of the selected bit lines Sel BL (i.e., the first bit lines BL1) and the selected word lines Sel WL (i.e., the first word lines WLk) is one, the number of the selected bit lines Sel BL (i.e., the first bit lines BL1) and the selected word lines Sel WL (i.e., the first word lines WLk) is not limited to one, and the number of the selected bit lines Sel BL (i.e., the first bit lines BL1) and the selected word lines Sel WL (i.e., the first word lines WLk) may be selectively determined according to the actual erasing requirement of the memory cell, which is not specifically limited by the present application.

According to the erase operation method 500 of the non-volatile memory provided in some embodiments of the present application, holes are generated in some selected memory strings into a memory block using GIDL current, so that the potential of the channel layer of the selected memory strings is raised, and at the same time, at least one selected memory cell in the selected memory strings is erased using the potential difference between some selected word lines and the channel layer of the selected memory strings. In some exemplary embodiments, the non-volatile memory is erased in a unit of a plurality of memory cells included in a memory block, and compared with the exemplary embodiments, the method 500 for erasing a non-volatile memory according to some embodiments of the present application can erase memory cells in a selective memory block, so that the erasing operation of the non-volatile memory is more flexible. Meanwhile, the reading window of the part of the memory cells can be increased by selectively erasing the part of the memory cells, so that the reading accuracy of the memory cells can be improved.

In some examples, prior to time t3 of the pre-erase phase, a ground voltage Vgnd is applied to unselected word lines Unsel WL (e.g., second word lines WL 1-WL 3, WLn-2-WLn, etc.) other than the selected word line Sel WL (i.e., first word line WLk), and the unselected word lines (e.g., second word lines WL 1-WL 3, WLn-2-WLn, etc.) are kept in a floating state during the pre-erase phase and the erase phase after time t 3. Similarly, after time t3, due to the coupling effect of the voltage of the channel layer 404 (see FIG. 4), the unselected word lines (e.g., the second word lines WL 1-WL 3, WLn 2-WLn, etc.) are at a preset slope R between time t3 and time t4 of the pre-erase phase ₁ Rises and maintains the trend of its target voltage V-unsel wl between time t4 and time t5 of the erase phase. Illustratively, the time interval between time t3 and time t0 may further satisfy: after time t3, the difference between the target voltage V-unsel WL and the target erase voltage Vt-erase that the unselected word lines (e.g., second word lines WL 1-WL 3, WLn 2-WLn, etc.) can reach while maintaining the floating state is less than the erase threshold to avoid the selected memory string (e.g., first memory Str11)) Is not selected (e.g., MC 1) ₁₁ ～MC3 ₁₁ 、MCn-2 ₁₁ ～MCn ₁₁ Etc.) are erased.

It is understood that the difference between the target voltage V-unsel WL and the target erase voltage Vt-erase that can be achieved by the unselected word lines (e.g., second word lines WL 1-WL 3, WLn 2-WLn, etc.) while remaining in a floating state is greater than the unselected memory cells (e.g., MC 1) corresponding to these unselected word lines (e.g., second word lines WL 1-WL 3, WLn 2-WLn, etc.) ₁₁ ～MC3 ₁₁ 、MCn-2 ₁₁ ～MCn ₁₁ Etc.) so that the drain select transistor DST is turned on ₁₁ The relatively high potential of the corresponding channel layer 404 (see FIG. 4) can be transferred to the unselected memory cells (e.g., MC 1) ₁₁ ～MC3 ₁₁ 、MCn-2 ₁₁ ～MCn ₁₁ Etc.) so that the potential of the channel layer 404 (see fig. 4) is relatively uniform throughout, thereby improving the selected memory cell MCk ₁₁ The erasing effect of (1).

It should be noted that although the present application illustrates time t3 being later than time t2, the voltage conditions actually required (e.g., to avoid unselected memory cells (e.g., MC 1) may be based on the voltage conditions of the unselected word lines (e.g., second word lines WL 1-WL 3, WLn-2-WLn, etc.). As shown above ₁₁ ～MC3 ₁₁ 、MCn-2 ₁₁ ～MCn ₁₁ Etc.) cause erased and/or unselected memory cells (e.g., MC 1) ₁₁ ～MC3 ₁₁ 、MCn-2 ₁₁ ～MCn ₁₁ Etc.) on). In other words, time t3 may overlap time t2, or time t3 may be earlier than time t 2.

In some examples, after time t0 within the pre-erase phase, the voltage on the source select line SSL is caused to have a preset slope R ₁ Rises and maintains the target erase voltage Vt-erase reached during the erase phase. In other words, a voltage having the same variation trend as the selected bit line Sel BL (i.e., the first bit line BL1) may be applied to the source select line SSL, so that the source select transistor is turned off to prevent the high potential in the channel layer 404 (refer to fig. 4) from being further transferred to the source line ACS, thereby affecting the source line ACSAnd (5) erasing effect. In other examples, the source select line SSL may be kept in a floating state at all times during the pre-erase phase and the erase phase, and as such, the high potential in the channel layer 404 (refer to fig. 4) can be prevented from being further transferred to the source line ACS, thereby affecting the erase effect.

In some examples, as shown in fig. 3, for an unselected memory string (e.g., Str1p, etc.) to which a selected bit line Sel BL (i.e., first bit line BL1) and an unselected drain select line Unsel DSL (i.e., second drain select line DSLp), as shown in fig. 6, a ground voltage Vgnd is applied to the unselected drain select line Unsel DSL (i.e., second drain select line DSLp, etc.) before time t1 within the pre-erase phase, and the unselected drain select line Unsel DSL (i.e., second drain select line DSLp, etc.) is kept in a floating state after time t1 within the pre-erase phase and between time t4 to time t5 during the erase phase, where time t1 is earlier than time t 2. Similar to applying the ground voltage Vgnd to the selected drain select line Sel DSL (i.e., the first drain select swabbs DSL1) before the time t2 of the pre-erase phase, the unselected drain select lines Unsel DSL (i.e., the second drain select lines DSLp, etc.) are not affected by the coupling action by applying the ground voltage Vgnd to the unselected drain select lines Unsel DSL (i.e., the second drain select lines DSLp, etc.) after the time t1 of the pre-erase phase.

It should be noted that, since time t1 is earlier than time t2, the difference between the voltage on the selected bit line Sel BL (i.e., the first bit line BL1) (or the voltage transferred to the channel plug 406 (refer to fig. 4) made of, for example, N-type doped polysilicon material) and the voltage on the unselected drain select line Unsel DSL (i.e., the second drain select line DSLp, etc.) cannot generate GIDL current, so that holes are not allowed to enter the drain select transistor (e.g., DST) in the unselected memory string (e.g., Str1p, etc.) _1p Etc.) of the memory cell, and further, the unselected memory strings (e.g., Str1p, etc.) do not have the condition of the potential of the channel layer being raised, so that the respective unselected memory cells on the unselected memory strings (e.g., Str1p, etc.) are not erased.

In some examples, as shown in FIG. 3For the unselected memory strings (e.g., Strm1, etc.) to which the unselected bit lines Unsel BL (i.e., the second bit lines BLm, etc.) and the selected drain select line Sel DSL (i.e., the first drain select line DSL1) are located, as shown in FIG. 6, after time t2 of the pre-erase phase, the voltage on the unselected bit lines Unsel BL (i.e., the second bit lines BLm, etc.) is made to have a preset slope R ₁ Rises and reaches the target non-erase voltage Vt-nonerase at time t4 when the pre-erase phase ends (i.e., when the erase phase begins). During the erase phase from time t4 to time t5, the voltage on the unselected bit line Unsel BL (i.e., the second bit line BLm, etc.) is kept constant at the target non-erase voltage Vt-nonerase. It is noted that, in some examples, the predetermined slope R may be applied, for example, by applying a predetermined slope R to the unselected bit lines Unsel BL (i.e., the second bit line BLm, etc.) ₁ The same voltage, so that the voltage on the unselected bit line Unsel BL (i.e., the second bit line BLm, etc.) is at the preset slope R, for example, between time t2 and time t4 ₁ Rises and maintains the trend of the target non-erase voltage Vt-nonerase between time t4 and time t 5. In other examples, the target non-erase voltage Vt-nonerase may be applied, for example, at time t2, and the voltage on the unselected bit line Unsel BL (i.e., the second bit line BLm, etc.) is caused to be at a preset slope R, for example, between time t2 and time t4, due to the capacitive coupling effect, since the control lines (e.g., the second bit line BLm, etc.) may be equivalent to a series capacitance and resistance ₁ Rises and maintains the trend of the target non-erase voltage Vt-nonerase between time t4 and time t 5.

Since the selected drain select line Sel DSL (i.e., the first drain select line DSL1) is applied with the ground voltage Vgnd before the time t2 and remains in a floating state after the time t2, the difference between the voltage on the unselected bit line Unsel BL (i.e., the second bit line BLm, etc.) (or the voltage transferred to the channel plug made of, for example, N-type doped polysilicon material) and the voltage on the selected drain select line Sel DSL (i.e., the first drain select line DSL1) cannot generate GIDL current, thereby not causing holes to enter the drain select transistor (e.g., DST1, etc.) in the unselected memory string (e.g., Strm1, etc.) _m1 ) Corresponding channel layerThen, the unselected memory strings (e.g., Strm1, etc.) are further made to have no condition for the potential of the channel layer to rise, so that the respective unselected memory cells on the unselected memory strings (e.g., Strm1, etc.) are not erased. Illustratively, the target non-erase voltage Vt-nonerase is less than the target erase voltage Vt-erase, thereby avoiding the occurrence of breakdown damage due to the fact that the target non-erase voltage Vt-nonerase is too different from the target erase voltage Vt-erase due to the close physical structures of the adjacent selected bit lines and unselected bit lines.

In some examples, as shown in fig. 3, unselected memory strings (e.g., Strmp, etc.) are located for unselected bit lines Unsel BL (i.e., second bit line BLm, etc.) and unselected drain select lines Unsel DSL (i.e., second drain select line DSLm, etc.). As shown in fig. 6, since time t1 is earlier than time t2, the difference between the voltage on the unselected bit line Unsel BL (i.e., second bit line BLm, etc.) (or the voltage passed to the channel plug made of, for example, N-type doped polysilicon material) and the voltage on the unselected drain select line Unsel DSL (i.e., second drain select line DSLp, etc.) cannot generate GIDL current, so that each unselected memory cell on the unselected memory string (e.g., Strmp, etc.) is not erased.

In some examples, as shown in FIG. 3, including a select transistor (e.g., DST) disposed at the drain (e.g., Str11) in each memory string (e.g., Str11) ₁₁ ) And a plurality of memory cells (e.g., MC 1) ₁₁ ～MCn ₁₁ ) Between drain dummy memory cells (e.g., D-DMC) ₁₁ ) In the case of (3), as shown in fig. 6, before time t3 in the erase phase, the ground voltage Vgnd is applied to the drain dummy word line D-DWL, and the drain dummy word line D-DWL is kept in a floating state after time t 3. For example, the same trend of change voltage (i.e., the ground voltage Vgnd) may be applied to the drain dummy word line D-DWL and the unselected word lines Unsel WL (i.e., the second word lines WL 1-WL 3, WLn-2-WLn, etc.) at the same time.

D-DMC for drain dummy memory cells in selected memory string Str11 ₁₁ (refer to fig. 3), applying the above-described voltage to the drain dummy word line D-DWL connected thereto may causeDrain select transistor DST ₁₁ The high potential of the corresponding channel layer 404 (refer to fig. 4) is transferred to the underlying channel layer 404 (refer to fig. 4). Illustratively, the time interval between time t3 and time t0 may further satisfy: after time t3, drain dummy memory cell D-DMC ₁₁ The difference between the target voltage V-ddwl and the target erase voltage Vt-erase that can be achieved while maintaining the floating state is less than the erase threshold to avoid the drain dummy memory cell D-DMC in the selected memory string Str11 ₁₁ Is erased.

D-DMC for drain dummy memory cells in unselected memory strings (e.g., Str1p) _1p (refer to fig. 3), as shown in fig. 6, applying the above-mentioned voltages to the drain dummy word line D-DWL connected thereto may make the unselected drain select line Unsel DSL (i.e., the second drain select line DSLp) reach the target voltage V-Unsel DSL due to coupling in a floating state with the drain dummy memory cell D-DMC _1p The difference of the target voltage V-ddwl reached in the floating state does not cause the drain dummy memory cell D-DMC _1p No HCI (hot carrier injection) occurs to the charge at the corresponding channel layer, thereby avoiding the drain dummy memory cell D-DMC _1p Is disturbed.

In some examples, as shown in fig. 3, including a source select transistor (e.g., SST) disposed at each memory string (e.g., Str11) ₁₁ ) And a plurality of memory cells (e.g., MC 1) ₁₁ ～MCn ₁₁ ) Source dummy memory cell in between (e.g., S-DMC) ₁₁ ) In the case of (3), as shown in fig. 6, before time t1 in the pre-erase stage, the ground voltage Vgnd is applied to the source dummy word line S-DWL, and the source dummy word line S-DWL is kept in a floating state after time t 1. For example, the voltage of the same trend of change (i.e., the ground voltage Vgnd) is applied to the source dummy word line S-DWL and the unselected drain select line Unsel DSL (i.e., the second drain select line DSLp, etc.) at the same timing.

It should be noted that, for the selected memory string Str11, the high potential in the channel layer 404 (refer to fig. 4) is near the drain select transistor DST ₁₁ Generated in the channel layer 404 (reference)Fig. 4) toward the source drain select transistor SST ₁₁ During the pass, the potential within the channel layer 404 (referring to FIG. 4) may exhibit a tendency to decrease along the direction from the drain terminal to the source terminal, in this example, the channel layer 404 (referring to FIG. 4) and the source dummy memory cell S-DMC may be caused by applying the above-described voltage to the source dummy word line S-DWL at time t0 ₁₁ The corresponding increase in potential results in a relatively uniform high potential throughout channel layer 404 (see FIG. 4), which in turn improves the selected memory cell MCk ₁₁ The erasing effect of (1).

In some examples, during a recovery phase after the erase phase, such as the selected bit line Sel BL (i.e., first bit line BL1), the selected drain select line Sel DSL (i.e., first drain select line DSL1), the selected word line Sel WL (i.e., first word line WLk), the unselected word lines Unsel WL (i.e., second word lines WL 1-WL 3, WLn-2-WLn, etc.), the source select line SSL, the drain dummy word line D-DWL, and the source dummy word line S-DWL may be restored to an initial default state of the pre-erase phase, e.g., ground voltage Vgnd, in preparation for performing an erase operation in a next cycle.

In the training process of realizing the neural network by using the nonvolatile memory as the hardware platform, if the nonvolatile memory is erased integrally by using a plurality of memory cells included in the memory block as a unit, the large-scale deep neural network operation is not facilitated to be realized. The application of the neural network and the above-described erase operation method to the neural network will be further described below.

The neural network may be comprised of an input layer, an output layer, and one or more hidden layers between the input layer and the output layer, each layer including one or more neurons. According to the connection relation of each neuron in the neural network, the input traverses each layer in a mathematical transformation mode and is converted into the probability of each output.

FIG. 7 is a schematic diagram of a three-layer neural network architecture 700, according to an embodiment of the present application. As shown in fig. 7, circles in the neural network 700 represent neurons, and connecting lines represent variable weights between each neuron of the previous layer and one neuron of the current layer. FIG. 7 shows a three-input systemNeurons (I) ₁ 、I ₂ 、I ₃ ) Having two output neurons (O) ₁ 、O ₂ ) And has four hidden neurons (H) ₁ 、H ₂ 、H ₃ 、H ₄ ) The hidden layer of (1). Neurons (e.g., hidden neuron H) ₁ ) Can be implemented as a mathematical function that receives a plurality of inputs (I) ₁ 、I ₂ 、I ₃ ) And weighted and then accumulated to produce an output (O) _H1 ＝I ₁ ω ₁ +I ₂ ω ₂ +I ₃ ω ₃ ). Further, neurons are hidden (e.g., H) ₁ ) Generated output O _H1 Can be used as output for each output neuron (e.g., O) ₁ ) Is provided. The output generated by the output neurons may be used as the output of the neural network 700.

In some embodiments, the weight (e.g., ω) ₁ 、ω ₂ 、ω ₃ ) The adjustment may be accomplished using a training process. Furthermore, a neuron (e.g., a hidden neuron or an output neuron) may have a threshold such that when the weighted input accumulation value exceeds the threshold, an output (i.e., an input of a later layer or an output of a neural network) is generated. Alternatively, the output of the neuron may be calculated by some non-linear function (e.g., Sigmoid function). Although fig. 7 shows one hidden layer, a complex Deep Neural Network (DNN) may have many such hidden layers.

Problems such as pattern recognition can be solved based on the trained neural network. For example, a trained neural network can be used to infer a fruit class in an image. Fig. 8 is a flow chart 800 of a training process for a neural network according to an embodiment of the present application. For example, the training process may be based on supervised learning rules. The training process 800 is described in detail below in conjunction with the neural network 700 shown in fig. 7.

In step 801, neuron I is input ₁ 、I ₂ 、I ₃ (refer to fig. 7) training input is received. Illustratively, the training input is a set of images, each image including a fruit category to be identified.

In step 802, neuron I may be input using the current weight ₁ 、I ₂ 、I ₃ Hidden neuron H connected to next layer ₁ 、H ₂ 、H ₃ 、H ₄ . Further, the neuron H will be hidden ₁ 、H ₂ 、H ₃ 、H ₄ Output nerve O connected to the next layer ₁ 、O ₂ And will hide neuron H ₁ 、H ₂ 、H ₃ 、H ₄ As the next layer output neuron O ₁ 、O ₂ Is input. Further, an output neuron O ₁ 、O ₂ As the output of the neural network 500. In other words, the training input from the input layer traverses all hidden layers in this manner until the output layer propagates. Illustratively, as described previously, in the example of identifying fruit categories using a neural network, the hidden layer and the output layer use the current weights to calculate the probability that the fruit in the image is a particular category, and return the label of the target fruit category at step 803.

In step 804, it is determined whether the probability of a particular fruit category output by the neural network satisfies a sufficiently accurate label using the current weights, and if so, the training is complete (step 805). If the results are not accurate enough, the neural network adjusts the weights at step 806 and then loops back to step 804 to run the input data again using the adjusted weights.

When step 805 determines weights for the neural network, the weights may be used to infer the fruit categories in the images as described above based on the weights, and the determined weights may be stored in non-volatile memory 320 (see FIG. 3).

FIG. 9 is a flow chart of a method 900 of operating a non-volatile memory for implementing a neural network in accordance with an embodiment of the present application. Fig. 10 is an equivalent circuit diagram of the two-dimensional memory cell array 1020-1 in the memory cell array 320 shown in fig. 3. The method 900 of operation is further described below in conjunction with fig. 9 and 10. The method of operation 900 may utilize, for example, a portion of the memory cell array 320 illustrated in FIG. 10 (i.e., the two-dimensional memory cell array 1020-1) to perform the forward and backward propagation in the training process of the neural network, as well as the inference process.

As shown in FIG. 10, the two-dimensional memory cell array 1020-1 may be equivalent to a plurality of neurons in a hidden layer or an output layer (hereinafter referred to as a current layer) of a neural network (e.g., the neural network 700 illustrated in FIG. 7). For each memory string (e.g., Str 11-Strm 1) in the two-dimensional memory cell array 1020-1, it can be controlled by the same drain select line DSL1, so that the multiple memory strings Str 11-Strm 1 shown in FIG. 10 can be turned on with multiple bit lines (e.g., BL 1-BLm) under the control of the same drain select line DSL 1.

In step 901, as shown in FIG. 9, a plurality of memory cells (e.g., MC 1) connected by the same word line (e.g., WL1) and located on different memory strings (e.g., Str 11-Strm 1) ₁₁ ～MC1 _m1 ) May correspond to one neuron in the current layer. For example, the two-dimensional memory cell array 1020-1 may correspond to n neurons in the current layer. Further, a plurality of bit line voltages (e.g., V) may be applied to a plurality of bit lines (e.g., BL 1-BLm), respectively _BL1 ～V _BLm ) Bit line voltage (e.g., V) on each bit line (e.g., BL 1-BLm) _BL1 ～V _BLm ) May correspond to one input to one neuron in the current layer. In other words, a plurality of bit line voltages (e.g., V) on a plurality of bit lines _BL1 ～V _BLm ) May correspond to multiple inputs to a neuron in the current layer. For example, for one neuron in the current layer, it may receive m inputs (i.e., m bit line voltages V on m bit lines) _BL1 ～V _BLm )。

In step 902, a memory cell (e.g., MC 1) ₁₁ ) Conductance value G1 ₁₁ Can be used as one input corresponding to a neuron (e.g., bit line voltage V applied to bit line BL1 _BL1 ) The weight of (c). It should be noted that, as described above, for the floating gate type or charge trap type memory cell, the conductance value (i.e., the reciprocal of the resistance value) exhibited by each memory cell is different according to the amount of charges injected into the charge trap layer or the floating gate layer. In this step, the process may be carried out according to the existenceThe above-described characteristics of the memory cells and the electrical connection characteristics of the memory cell array provide execution conditions for determining the output of the neuron in subsequent step 903 by applying a read voltage to the word line to which the memory cell is connected, thereby sensing the current flowing through the memory cell.

Fig. 11 is a waveform diagram of voltages applied to n word lines to determine the output of a neuron according to an embodiment of the present application. As shown in fig. 11, a read pulse voltage Vread (gray) is sequentially applied to the word lines WL1 to WLn to sequentially determine the respective memory cells (e.g., MC 1) connected to the word line WL1 ₁₁ ～MC1 _m1 ) Up to the current value of the respective memory cells to which the word line WLn is connected. In some examples, the bit line voltage V due to the bit line voltages V that have been applied in step 901 to the bit lines BL 1-BLm to which the respective memory strings Str 11-Strm 1 are connected _BL1 ～V _BLm When a read pulse voltage Vread is applied to the word line WL1 at time T1, a sense circuit (not shown), for example, connected to one end (for example, one end to which a bit line is not connected) of each of the memory strings Str11 to Strm1 can sense a current flowing through each of the memory cells MC1 connected to the word line WL1 ₁₁ ～MC1 _m1 The current values of the plurality of memory strings Str 11-Strm 1.

In step 903, at a memory cell (e.g., MC 1) ₁₁ ) Conductance value of (e.g., G1) ₁₁ ) As an input to a neuron of the neural network (e.g., V) _BL1 ) In the case of a corresponding weight, then the one input (e.g., V) _BL1 ) With corresponding weight (e.g. G1) ₁₁ ) Product of (i.e., G1) ₁₁ ×V _BL1 ) May be part of the output of the neuron. Further, since the word line WL1 connects the plurality of memory cells MC1 ₁₁ ～MC1 _m1 Multiple inputs (e.g. V) _BL1 ～V _BLm ) A plurality of weights (e.g. G1) corresponding to the respective ₁₁ ～G1 _m1 ) Product of (i.e., (G1) ₁₁ ×V _BL1 )～(G1 _m1 ×V _BLm ) Can be determined). Further, summing the products may be accomplished by sensing the total current in the common source line ACS, thereby determining the output of the neuron corresponding to word line WL1 (i.e.,

) In turn, n outputs of n neurons of a current layer in the neural network may be determined.

In some examples, as shown in FIG. 11, during the time T1 when the read pulse voltage Vread is applied to word line WL1, the bias pulse voltage Vbias-p may be applied to word lines WL2 WLm. For example, the bias pulse voltage Vbias-p is greater than the read pulse voltage Vread. In other words, for memory string Str11, memory cell MC1 ₁₁ Which may be referred to as the memory cell to be read, stores the memory string Str11 except for the memory cell MC1 ₁₁ Other memory cells than the memory cell to be read can be referred to as non-read memory cells when the bias pulse voltage Vbias-p applied to the non-read memory cells is greater than memory cell MC1 to be read ₁₁ With the applied read pulse voltage Vread, it is possible to sense the current flowing through the memory cell MC1 to be read ₁₁ The influence of the memory cells which are not to be read is effectively avoided during the current, so that the accuracy of obtaining the neuron output is improved.

It should be noted that the voltage waveform diagrams of the word lines WL1 to WLn shown in fig. 11 are merely exemplary, and in other examples, the read pulse voltage Vread may not be applied to the word lines WL1 to WLn one by one in a time domain, in other words, the read pulse voltage Vread may omit applying the read pulse voltage Vread to any one or more word lines, so that the memory cell connected to the one or more word lines does not correspond to one neuron of the current layer in the neural network.

FIG. 12 is a schematic diagram of a method of operating a non-volatile memory for implementing a neural network, according to another embodiment of the present application. As shown in fig. 12, a plurality of memory cells in a plurality of memory strings to which the drain select line DSL1 is connected may constitute one two-dimensional memory cell array (e.g., the first memory cell array 1220-1). Similarly, a plurality of memory strings in the second memory cell array 1220-2 may be connected to another drain select line (not shown), and a plurality of memory strings in the pth memory cell array may be connected to yet another drain select line (e.g., DSLp (refer to fig. 3)). In other words, the first memory cell array 1220-1, the second memory cell array 1220-2 through the pth memory cell array 1220-p may be controlled by p drain select lines, respectively. Among them, the first memory cell array 1220-1 may be the same as the two-dimensional memory cell array 1020 illustrated in fig. 10.

In some examples, for the first memory cell array 1220-1, one end of the plurality of memory strings Str11 to Strm1 in the first memory cell array 1220-1 may be enabled to receive a bit line voltage (e.g., V) by applying a turn-on voltage (i.e., a voltage that turns on a plurality of drain select transistors connected to the drain select line DSL1) to the drain select line DSL1 _BL1 ～V _BLm ). That is, as described in detail above, each corresponding neuron in the first memory cell array 1220-1 may be a part of a plurality of neurons in the current layer of the neural network, and may generate a corresponding output within a predetermined time.

Further, by applying a turn-on voltage to the drain select line corresponding to one or more of the second through pth memory cell arrays 1220-2 through 1220-p, at least a portion of the two-dimensional memory cell arrays 1220-2 through 1220-p can be used as a part of the neurons in the current layer of the neural network to generate corresponding outputs in parallel within a predetermined time, thereby effectively improving the efficiency of performing the forward propagation or inference process in the neural network algorithm using the non-volatile memory.

In step 904, as described above, during the training of the neural network, if the probability of the neural network output does not satisfy the sufficiently accurate label, then the weights in the neural network need to be adjusted. Further, since the conductance value of the memory cell serves as a weight corresponding to the input in each neuron, the weight adjustment corresponding to the input in each neuron can be realized by adjusting the conductance value of the memory cell. It should be noted that adjusting each weight in the neural network according to whether the probability output by the neural network satisfies the sufficiently accurate label may be called Back Propagation (BP) of the neural network.

FIG. 13 is a graph of conductance values of memory cells versus time for performing program and erase operations according to an embodiment of the present application. As shown in fig. 13, in some examples, as the execution time for performing a programming operation on a memory cell increases, the conductance of the memory cell decreases accordingly. Specifically, for example, as the time for performing a program operation on the memory cell increases, more charges in the channel layer of the memory cell are injected into the charge trapping layer 402 (see fig. 4), so that the conductance value of the memory cell decreases, i.e., the conductance value of the memory cell is adjusted. In other examples, the conductance value of the memory cell may also be adjusted by increasing the pulse strength of the programming operation performed on the memory cell such that more charge in the channel layer 404 (see fig. 4) of the memory cell is injected into the charge trapping layer 402 (see fig. 4).

Referring now to the two-dimensional memory cell array 1020-1 illustrated in FIG. 10, for one of the memory cells MC1 ₁₁ The execution of the programming operation is exemplary. Illustratively, memory cell MC1 ₁₁ May be referred to as a memory cell to be programmed. When the program operation is performed on the memory cell to be programmed, a program voltage (e.g., 15-20V) is applied to the word line WL1 connected thereto, and the memory cell MC1 is turned on ₁₁ The drain select transistor DST1 on the memory string Str11 where it is located ₁₁ For and memory cell MC1 ₁₁ The bit line BL1 to which the memory string Str11 is connected is applied with, for example, a ground voltage. Under the action of the high voltage on the word line WL1, charges (e.g., electrons) are injected into the charge trapping layer 402 (refer to FIG. 4) after tunneling to charge up the memory cell MC1 ₁₁ The effect of the conductance value of (c). Optionally, a program-inhibit voltage (e.g., 2V) may be applied to other bit lines (e.g., BLm, etc.) to hinder charge tunneling to inhibit other memory cells in a memory string (e.g., Strm1, etc.) connected to word line WL1 from being programmed.

Illustratively, referring again to FIG. 12, the conductance values of the memory cells in one or more of the second through pth memory cell arrays 1220-2 through 1220-2 may be adjusted in parallel, thereby effectively increasing the efficiency of operations that propagate backward in the performance of neural network algorithms with non-volatile memory.

In other examples, the conductance value of the memory cell increases as the execution time for performing the erase operation on the memory cell increases. Specifically, for example, as the time for performing the erase operation on the memory cell increases, more holes in the charge trapping layer 402 (refer to fig. 2) of the memory cell are injected into the charge trapping layer 402 (refer to fig. 4), so that the conductance value of the memory cell increases, i.e., the conductance value of the memory cell is adjusted. For example, referring to the erase operation method 500 shown in FIG. 5, when the number of first bit lines and first word lines is one, one memory cell (e.g., MC 1) may be implemented ₁₁ ) An erase operation is performed such that the conductance of the memory cell is increased, i.e., the conductance of the memory cell is adjusted. The erase operation method 500 is described in detail above, and is not described herein again.

In some exemplary embodiments, in the case where the non-volatile memory performs bulk erase in units of a plurality of memory cells included in the memory block, the conductance difference of the pair of memory cells is generally adopted as a weight corresponding to one input of a neuron in the neural network (i.e., W ═ G) ⁺ -G ^- ) In other words, the utilization of the parameters of the neural network stored by a plurality of memory cells in the non-volatile memory will be halved on the premise of the same storage capacity (i.e., number of memory cells). Meanwhile, the conductance difference value is adopted to represent the weight corresponding to one input, hardware such as a subtracter needs to be additionally arranged in a nonvolatile memory, and a part of storage capacity is consumed to store the conductance difference value. On the other hand, in the process of adjusting the weight, each weight needs to be independently adjusted by programming and matching the two memory cells, however, for a complicated neural network with a large number of training times, when the conductance values of the two memory cells reach the upper limit, the weights cannot be continuously adjusted. If the weights need to be adjusted continuously, the whole erasing can be performed by taking a plurality of storage units included in the storage block as a unit, so that the previous training result can be destroyed.

According to the non-volatile memory applicable to the neural network provided by some embodiments of the present application, compared with the above exemplary embodiments, the utilization rate of storing parameters of the neural network by using the non-volatile memory can be improved by using the conductance value of a single storage unit in the non-volatile memory as the weight corresponding to one input of the neuron in the neural network, which is beneficial to exerting the advantage of high storage density of the non-volatile memory. Meanwhile, a subtracter is not needed to be additionally arranged to calculate the conductance difference, compatibility with the existing peripheral circuit is facilitated, a part of storage capacity is prevented from being consumed to store the conductance difference, and the storage utilization rate of the non-volatile memory is further improved. On the other hand, the weight is adjusted by adjusting the conductance value of a single storage unit, so that the problem that the weight cannot be continuously adjusted after the respective conductance values of two storage units reach the upper limit can be solved, and the realization of a more complex deep neural network is facilitated.

The above description is only an embodiment of the present application and an illustration of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. An erase operation method of a nonvolatile memory, the nonvolatile memory including a memory block including a plurality of memory strings, at least one first memory string of the plurality of memory strings being connected between a first bit line and a source line and including a drain select transistor adjacent to the first bit line and a plurality of memory cells between the drain select transistor and the source line, the drain select transistor and the memory cells being connected to a first drain select line and a word line, respectively, the method comprising:

after time t0 in the pre-erase phase, making the voltage on the first bit line rise with a preset slope, and keeping the target erase voltage reached in the erase phase;

applying a ground voltage to the first drain select line prior to time t2 within the pre-erase phase and maintaining the first drain select line in a floating state after time t 2; and

and in the erasing phase, applying a bias voltage to at least one first word line connected with a memory cell to be erased, wherein the difference between the target erasing voltage and the bias voltage is larger than an erasing threshold value.

2. The method of erase operations of claim 1, wherein the first memory string further comprises a source select transistor located between the plurality of memory cells and the source line, the source select transistor connected to a source select line, the method further comprising:

after time t0 in a pre-erase phase, raising the voltage on the source select line with the preset slope and maintaining the target erase voltage reached in the erase phase; or

And in the pre-erasing stage and the erasing stage, keeping the source selection line in a floating state.

3. The method of erase operations of claim 1, wherein the method further comprises:

applying a ground voltage to a second word line other than the first word line before a time t3 within the pre-erase phase, and maintaining the second word line in a floating state after the time t 3.

4. The method of claim 1, wherein the memory block further includes a second drain select line other than the first drain select line, the method further comprising:

applying a ground voltage to the second drain select line before a time t1 within the pre-erase phase and maintaining the second drain select line in a floating state after the time t1, wherein the time t1 is earlier than the time t 2.

5. The method of claim 4, wherein the memory block further includes a second bit line other than the first bit line, the method further comprising:

after the time t2 in the pre-erase phase, the voltage on the second bit line is raised with the preset slope and the target non-erase voltage reached is maintained in the erase phase.

6. The erase operation method of claim 5, wherein the target non-erase voltage is less than the target erase voltage.

7. The method of erase operations of claim 1, wherein the first memory string further includes a drain dummy memory cell located between the drain select transistor and the plurality of memory cells, the drain dummy memory cell connected to a drain dummy word line, the method further comprising:

applying a ground voltage to the drain dummy word line before time t3 within the pre-erase phase and maintaining the drain dummy word line in a floating state after time t 3.

8. The method of erase operations of claim 1, wherein the first storage string further includes a source dummy memory cell located between the source select transistor and the plurality of memory cells, the source dummy memory cell connected to a source dummy word line, the method further comprising:

applying a ground voltage to the source dummy word line prior to time t1 within the pre-erase phase and maintaining the source dummy word line in a floating state after time t1, wherein time t1 is earlier than time t 2.

9. The erase operation method of claim 1, wherein the bias voltage is the ground voltage.

10. A non-volatile memory, comprising:

a memory block including a plurality of memory strings, at least a first memory string of the plurality of memory strings being connected between a first bit line and a source line and including a drain select transistor adjacent the first bit line and a plurality of memory cells between the drain select transistor and the source line, the drain select transistor and the memory cells being connected to a first drain select line and a word line, respectively; and

the peripheral circuitry is configured to:

11. The non-volatile memory of claim 10, wherein the first memory string further comprises a source select transistor located between the plurality of memory cells and the source line, the source select transistor connected with a source select line, the peripheral circuitry further configured to:

12. The non-volatile memory of claim 11, wherein the peripheral circuitry is further configured to:

13. The non-volatile memory of claim 10, wherein the memory block further comprises a second drain select line other than the first drain select line, the peripheral circuitry further configured to:

14. The non-volatile memory of claim 13, wherein the memory block further comprises a second bit line other than the first bit line, the peripheral circuitry further configured to:

15. The non-volatile memory of claim 14, wherein the target non-erase voltage is less than the target erase voltage.

16. The non-volatile memory of claim 10, wherein the first storage string further comprises a drain dummy memory cell between the drain select transistor and the plurality of memory cells, the drain dummy memory cell connected with a drain dummy word line, the peripheral circuitry further configured to:

17. The non-volatile memory of claim 10, wherein the first storage string further comprises a source dummy storage cell located between the source select transistor and the plurality of storage cells, the source dummy storage cell connected with a source dummy word line, the peripheral circuitry further configured to:

18. The non-volatile memory of claim 10, wherein the bias voltage is the ground voltage.

19. A non-volatile storage system, comprising:

at least one non-volatile memory as claimed in any one of claims 10 to 18; and

a controller, coupled to the at least one non-volatile memory, configured to control peripheral circuitry in the non-volatile memory.

20. A non-volatile memory adapted for neural network algorithms, said non-volatile memory comprising:

a plurality of memory cells located in different memory strings, the plurality of memory cells being connected to the same word line and corresponding to one neuron in the neural network, the plurality of memory strings in which the plurality of memory cells are located being connected to a plurality of bit lines, respectively; and

a peripheral circuit configured to:

applying a plurality of bit line voltages to the plurality of bit lines, the bit line voltages as one input to a neuron in the neural network;

applying a read voltage to a word line connected to the plurality of memory cells;

determining an output of the neuron based on a plurality of conductance values in the plurality of memory cells, the conductance values as weights to which the inputs of the neuron correspond; and

performing a program operation on at least one of the plurality of memory cells or an erase operation according to the erase operation method of any one of claims 1 to 9 to adjust the conductance value, wherein the number of the first memory strings and the first word lines is one.

21. A non-volatile storage system adapted for use in a neural network, comprising:

at least one non-volatile memory as in claim 20; and