CN114863959A - Programming operation method and device of memory - Google Patents

Programming operation method and device of memory Download PDF

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Publication number
CN114863959A
CN114863959A CN202210350253.6A CN202210350253A CN114863959A CN 114863959 A CN114863959 A CN 114863959A CN 202210350253 A CN202210350253 A CN 202210350253A CN 114863959 A CN114863959 A CN 114863959A
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China
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memory
memory cell
redundant
string
programming operation
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李楷威
宋雅丽
赵向南
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202210350253.6A priority Critical patent/CN114863959A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

The invention relates to a programming operation method and a device of a memory, wherein the memory comprises a first memory string, a first input end and a second input end which are positioned at two ends of the first memory string, the first memory string comprises a plurality of first memory units which are connected in series, and the programming operation method comprises the following steps: performing a first program operation including supplying a first preset voltage to the second input terminal and supplying a second preset voltage to the gate layer of the first memory cell in a programmed state to turn on the first memory cell in the programmed state to precharge the channel in the first memory string; and performing a first programming operation, wherein the first programming operation programs a plurality of first memory cells to be programmed from the first memory cells close to the second input end to the direction far away from the second input end, so that when the memory string is programmed, the charge density of a channel can be effectively reduced in the pre-charging stage of the programming operation, and the programming interference is further reduced.

Description

Programming operation method and device of memory
The present application is a divisional application of the patent with application date of 2021, 01/19, application number of 202110071215.2, entitled method and apparatus for programming operation of memory.
Technical Field
The invention relates to the technical field of memories, in particular to a programming operation method and device of a memory.
Background
As technology evolves, the semiconductor industry is continually looking for new ways of production so that each memory die in a memory device has a greater number of memory cells. Among them, the 3D NAND memory has become a leading-edge three-dimensional memory technology with great development potential due to its advantages of high storage density and low cost.
Currently, in the erasing process of a 3D NAND memory, in order to improve the erasing efficiency and reduce the repeated read-write operation on a memory cell, a half-block erasing scheme is adopted, that is, for a memory block in which data has been written, only data of an upper stack or a lower stack in the memory block is erased, and data of another stack is not erased.
In the programming process of the 3D NAND memory, precharging is required to raise the potential of the entire channel, and after half block erasing is performed, precharging needs to be performed in a different manner since the channel cannot be conducted due to a case where the upper stack or the lower stack is not erased. In particular, where the lower stack is not erased and the upper stack is programmed, a large forward bias voltage is typically provided to the drain terminal during the precharge phase of the programming operation to precharge the channel and program in a top-down programming order. However, such a program operation scheme for the upper stack has a problem that the pre-charge cannot effectively increase the channel potential, and program disturb is severe.
Disclosure of Invention
The invention aims to provide a programming operation method and a programming operation device of a memory, so as to reduce programming interference.
In order to solve the above problems, the present invention provides a program operation method of a memory including a first memory string, and a first input terminal and a second input terminal at both ends of the first memory string, the first memory string including a plurality of first memory cells connected in series, each of the first memory cells including a gate layer, a memory layer storing a data state, and a channel, the data state including a programmed state and an unprogrammed state, the program operation method including:
performing a first program operation including supplying a first preset voltage to the second input terminal and supplying a second preset voltage to the gate layer of the first memory cell in a programmed state to turn on the first memory cell in the programmed state to precharge the channel in the first memory string; and (c) a second step of,
and performing a first programming operation, wherein the first programming operation programs a plurality of first memory cells to be programmed from the first memory cells close to the second input end to the direction far away from the second input end.
The duration of supplying the first preset voltage to the second input end is longer than the duration of supplying the second preset voltage to the grid layer of the first memory unit in the programmed state.
Wherein, the first programming operation is carried out, which specifically comprises:
programming a currently programmed first memory cell;
and when the programming of the currently programmed first storage unit is finished, updating the next first storage unit as the currently programmed first storage unit, and returning to the step of performing the pre-charging for the first programming operation, wherein the next first storage unit is a first storage unit which is adjacent to the currently programmed first storage unit and is positioned on one side of the currently programmed first storage unit, which is far away from the second input end.
Wherein, the first programming operation is carried out, which specifically comprises:
a program voltage is supplied to a gate layer of a currently programmed first memory cell, and a channel-on voltage is supplied to the remaining first memory cells.
Wherein the memory further comprises a first redundant memory string disposed between the first memory string and the second input terminal, the first redundant memory string comprising at least one first redundant memory cell connected in series, each first redundant memory cell comprising a gate layer, a memory layer storing a data state, and a channel, the data state of the at least one first redundant memory cell being a programmed state, the precharging of the first programming operation being performed, and further comprising:
and providing a third preset voltage to the grid layer of the first redundant memory unit in the programmed state to enable the first redundant memory unit in the programmed state to be conducted.
Wherein the memory further comprises a second string between the first input and the first string, and a second redundant string between the first string and the second string, the second string comprising a plurality of second cells connected in series, the second redundant string comprising at least one second redundant cell connected in series, each of the second cells and the second redundant cell comprising a gate layer, a storage layer for storing a data state, and a channel, the data state of the at least one second redundant cell being a programmed state, the precharging of the first programming operation being performed, further comprising:
and providing a fourth preset voltage to the grid layer of the second redundant memory unit in the programmed state to make the second redundant memory unit in the programmed state not conductive.
The programming operation method further comprises the following steps:
after completing programming of the plurality of first memory cells, triggering a second programming operation, the second programming operation comprising:
performing a second program operation including supplying a fifth preset voltage to the second input terminal and supplying a sixth preset voltage to the gate layers of the second memory cell, the first memory cell and the second redundant memory cell in the programmed state to turn on the second memory cell, the first memory cell and the second redundant memory cell in the programmed state to precharge the channels in the first memory string and the second memory string; and the number of the first and second groups,
and performing a second programming operation, wherein the second programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
The memory further comprises a third redundant memory string positioned between the second memory string and the first input end, the third redundant memory string comprises at least one third redundant memory unit connected in series, each third redundant memory unit comprises a gate layer, a memory layer for storing a data state and a channel, the data state of at least one third redundant memory unit is a programmed state, and the programming operation method further comprises the following steps:
after completing programming of the plurality of first memory cells, triggering a third programming operation, the third programming operation comprising:
performing a third program operation including supplying a seventh preset voltage to the first input terminal, supplying an eighth preset voltage to a gate layer of a third redundant memory cell in a programmed state to turn on the third redundant memory cell, and supplying a ninth preset voltage to remaining memory cells between the second input terminal and the third redundant memory cell to turn off the remaining memory cells to precharge a channel in the second memory string;
and performing a third programming operation, wherein the third programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
Wherein the ninth preset voltage is 0V.
The first input end is electrically connected with the source side end of the first memory string, and the second input end is electrically connected with the drain side end of the first memory string.
The memory is a three-dimensional memory, the first input end and the second input end are respectively located at two ends of the first memory string in the longitudinal direction, and the plurality of first memory units are arranged in a stacking mode in the longitudinal direction.
In order to solve the above problems, the present invention also provides a program operation apparatus of a memory including a first memory string, and a first input terminal and a second input terminal at both ends of the first memory string, the first memory string including a plurality of first memory cells connected in series, each of the first memory cells including a gate layer, a memory layer storing a data state, and a channel, the data state including a programmed state and an unprogrammed state, the program operation apparatus including:
the first pre-charging module is configured to perform pre-charging for a first programming operation, where the performing of pre-charging for the first programming operation specifically includes: providing a first preset voltage to the second input end, and providing a second preset voltage to the grid layer of the first memory unit in the programmed state to enable the first memory unit in the programmed state to be conducted so as to pre-charge the channel in the first memory string; and the number of the first and second groups,
the first programming module is used for carrying out a first programming operation, and the first programming operation programs a plurality of first storage units to be programmed from the first storage units close to the second input end to the direction far away from the second input end.
The duration of supplying the first preset voltage to the second input end is longer than the duration of supplying the second preset voltage to the grid layer of the first memory unit in the programmed state.
The first programming module is specifically configured to:
programming a currently programmed first memory cell;
when the programming of the currently programmed first memory cell is completed, updating the next first memory cell to the currently programmed first memory cell, and triggering the first pre-charging module to re-perform the pre-charging of the first programming operation, wherein the next first memory cell is a first memory cell adjacent to the currently programmed first memory cell and located on one side of the currently programmed first memory cell away from the second input terminal.
The first programming module is specifically configured to:
a program voltage is supplied to a gate layer of a currently programmed first memory cell, and a channel-on voltage is supplied to the remaining first memory cells.
Wherein the memory further comprises a first redundant memory string disposed between the first memory string and the second input terminal, the first redundant memory string comprising at least one first redundant memory cell connected in series, each first redundant memory cell comprising a gate layer, a memory layer storing a data state, and a channel, the data state of the at least one first redundant memory cell being a programmed state, the precharging of the first programming operation being performed, and further comprising:
and providing a third preset voltage to the grid layer of the first redundant memory unit in the programmed state to enable the first redundant memory unit in the programmed state to be conducted.
The memory further includes a second string located between the first input terminal and the first string, and a second redundant string located between the first string and the second string, the second string includes a plurality of second memory cells connected in series, the second redundant string includes at least one second redundant memory cell connected in series, each of the second memory cells and the second redundant memory cell includes a gate layer, a memory layer for storing a data state, and a channel, the data state of the at least one second redundant memory cell is a programmed state, and the precharge of the first programming operation is performed, and the memory further includes:
and providing a fourth preset voltage to the grid layer of the second redundant memory unit in the programmed state to make the second redundant memory unit in the programmed state not conductive.
Wherein, the programming operation device further comprises:
a first triggering module for triggering a second programming operation after completing programming of the plurality of first memory cells, the second programming operation including:
performing a second program operation including supplying a fifth preset voltage to the second input terminal and supplying a sixth preset voltage to the gate layers of the second memory cell, the first memory cell and the second redundant memory cell in the programmed state to turn on the second memory cell, the first memory cell and the second redundant memory cell in the programmed state to precharge the channels in the first memory string and the second memory string; and the number of the first and second groups,
and performing a second programming operation, wherein the second programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
Wherein the memory further includes a third redundant memory string between the second memory string and the first input terminal, the third redundant memory string includes at least one third redundant memory cell connected in series, each third redundant memory cell includes a gate layer, a memory layer storing a data state, and a channel, the data state of the at least one third redundant memory cell is a programmed state, and the program operation device further includes:
a second triggering module for triggering a third programming operation after completing programming of the plurality of first memory cells, the third programming operation including:
performing a third program operation including supplying a seventh preset voltage to the first input terminal, supplying an eighth preset voltage to a gate layer of a third redundant memory cell in a programmed state to turn on the third redundant memory cell, and supplying a ninth preset voltage to remaining memory cells between the second input terminal and the third redundant memory cell to turn off the remaining memory cells to precharge a channel in the second memory string;
and performing a third programming operation, wherein the third programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
Wherein the ninth preset voltage is 0V.
The first input end is electrically connected with the source side end of the first memory string, and the second input end is electrically connected with the drain side end of the first memory string.
The memory is a three-dimensional memory, the first input end and the second input end are respectively located at two ends of the first memory string in the longitudinal direction, and the plurality of first memory units are arranged in a stacking mode in the longitudinal direction.
The invention has the beneficial effects that: different from the prior art, the programming operation method of the memory provided by the invention is applied to the memory, the memory comprises a first memory string, a first input end and a second input end which are positioned at two ends of the first memory string, the first memory string comprises a plurality of first memory units which are connected in series, each first memory unit comprises a grid layer, a memory layer for storing a data state and a channel, the data state comprises a programmed state and an unprogrammed state, the programming operation method conducts the first memory unit in the programmed state by pre-charging the first programming operation, wherein the pre-charging comprises the steps of providing a first preset voltage to the second input end and providing a second preset voltage to the grid layer of the first memory unit in the programmed state to pre-charge the channel in the first memory string, and then the first programming operation is carried out, and the first programming operation conducts the plurality of first memory units to be programmed from the first memory unit close to the second input end to the direction far away from the second input end The cell is programmed, so that when the first programming operation is carried out on the first memory string, the problem that the channel potential cannot be effectively improved due to the fact that the channel of the programmed first memory cell is shut off can be avoided in the pre-charging stage of the first programming operation, and programming interference is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for programming a memory according to an embodiment of the present invention;
FIG. 2 is a simplified structural diagram of a three-dimensional memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a three-dimensional memory according to an embodiment of the present invention;
FIG. 4 is an enlarged schematic diagram of the first memory cell of FIG. 3;
FIG. 5 is a timing diagram of a first programming operation provided by an embodiment of the present invention;
FIG. 6 is a schematic diagram of another simplified structure of a three-dimensional memory according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another embodiment of a three-dimensional memory according to the present invention;
FIG. 8 is another timing diagram for a first programming operation provided by the present invention;
FIG. 9 is a timing diagram of a second programming operation provided by the present invention;
FIG. 10 is a timing diagram of a third programming operation provided by the present invention;
FIG. 11 is a schematic structural diagram of a program operation apparatus of a memory according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
In addition, directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], and the like, refer to directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the various figures, elements that are structurally similar are identified with the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, some well-known elements may not be shown in the figures.
The present invention may be embodied in various forms, some examples of which are described below.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a programming operation method of a memory according to an embodiment of the present invention, where a specific flow of the programming operation method of the memory may be as follows:
step S11: the precharging of the first programming operation is performed, including providing a first preset voltage to the second input terminal, and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, so that the first memory cell in the programmed state is conducted to precharge the channel in the first memory string.
In this embodiment, the memory includes a first memory string, and a first input terminal and a second input terminal at two ends of the first memory string, the first memory string includes a plurality of first memory cells connected in series, each of the first memory cells includes a gate layer, a memory layer storing a data state, and a channel, and the data state includes a programmed state and an unprogrammed state. The memory may be specifically a two-dimensional memory, and may also be specifically a three-dimensional memory.
For convenience of description and understanding, the embodiment of the present invention is described by taking the above memory as a three-dimensional memory as an example, and as shown in fig. 2, the three-dimensional memory may include a first memory string 12, and a first input terminal 11 and a second input terminal 14 located at both ends of the first memory string 12 in the longitudinal direction Z. The first memory string 12 includes a plurality of first memory cells 121 arranged in a stack in the longitudinal direction Z. The first memory cells 121 in the first memory string 12 are connected in series, and one end of the first memory string 12 in the longitudinal direction Z is connected in series with the first input terminal 11, and the other end is connected in series with the second input terminal 14.
Specifically, as shown in fig. 3 and 4, the first storage string 12 may be arranged as a vertical string in the stacked structure 15, wherein the stacked structure 15 may include a plurality of layers of alternately stacked conductive layers 151 and dielectric layers 152 in the longitudinal direction Z. The first memory cells 121 may include a gate layer a, a memory layer B, and a channel C, and the channels C of the first memory cells 121 may be connected in a longitudinal direction Z to collectively form a channel layer 16 extending through the stacked structure 15, and the memory layers B of the first memory cells 121 may be connected in the longitudinal direction Z to collectively form a charge storage layer 17 extending through the stacked structure 15 and surrounding the channel layer 16, and the conductive layers 151 of the stacked structure 15 may provide the gate layer a of each first memory cell 121 and a word line WL connected to the gate layer a of each first memory cell 121. The three-dimensional memory may further include a first oxide layer 18 (e.g., a silicon oxide layer) between the channel layer 16 and the charge storage layer 17, and a second oxide layer 19 (e.g., a silicon oxide layer) between the charge storage layer 17 and the stacked structure 15, and the first oxide layer 18 and the second oxide layer 19 may respectively provide a tunneling layer D and a blocking layer E of each of the first memory cells 121, that is, each of the first memory cells 121 has a tunneling layer D between the storage layer B and the channel C and a blocking layer E between the gate layer a and the storage layer B. The channel layer 16 may be a semiconductor layer (e.g., a polysilicon layer), the charge storage layer 17 may be a silicon nitride layer, the conductive layer 151 may be made of tungsten, and the dielectric layer 152 may be made of silicon oxide.
In the present embodiment, the memory layer B of the first memory cell 121 is used to store data states, which may include a programmed state and an unprogrammed state. Specifically, the data state stored in the storage layer B of the selected first memory unit 121 may be in a programmed state by performing a programming operation on the selected first memory unit 121, and the data state stored in the storage layer B of the selected first memory unit 121 may be restored to an unprogrammed state by performing an erasing operation on the selected first memory unit 121.
In an embodiment, the first input terminal 11 may be electrically connected to a source side end of the first memory string 12, and is used for electrically connecting the source side end of the first memory string 12 to a common source (not shown) of a three-dimensional memory, so that a common source driver can provide a driving signal to the first input terminal 11 through the common source. The second input terminal 14 may be electrically connected to a drain side terminal of the first memory string 12, for electrically connecting the drain side terminal of the first memory string 12 to a bit line BL, so that a bit line driver can provide a driving signal to the second input terminal 14 via the bit line BL. Accordingly, before the step S11, the method may further include: an erase operation is performed, including supplying the erase voltage Ve to the first input terminal 11 and supplying a ground voltage (i.e., 0V) to the gate layer a of each first memory cell 121, so as to erase data of each first memory cell 121, such that the data state of each first memory cell 121 is an unprogrammed state.
It is understood that the erase voltage Ve should be large enough to enable a sufficiently large negative voltage difference between the gate layer a and the source of each first memory cell 121, and further enable electrons in the storage layer B of each first memory cell 121 to leave the storage layer B and return to the corresponding channel C by tunneling effect, so as to achieve that the data state stored in the storage layer B of each first memory cell 121 is an erased state or an unprogrammed state, that is, the data state of each first memory cell 121 is switched from a programmed state to an unprogrammed state.
As shown in fig. 5, when the first programming operation is performed on the first memory string 12, the first programming operation can be divided into at least two phases: a precharge phase and a programming phase. In the present embodiment, the first preset voltage V1 is provided to the second input terminal 14 during the pre-charging stage, so that the potential of the second input terminal 14 can be higher than the potential of the first input terminal 11, and an electric field force directed to the second input terminal 14 can be applied to the dissociated electrons in the channel layer 16, and the dissociated electrons can leave the channel layer 16 and be absorbed by the second input terminal 14 under the action of the electric field force.
In this embodiment, when the first programming operation is performed on the first memory string 12, the first programming operation programs the plurality of first memory cells 121 to be programmed from the first memory cells 121 close to the second input terminal 14 to a direction away from the second input terminal 14, that is, the programmed first memory cells 121 or the first memory cells 121 in the programmed state are located on a side of the currently programmed first memory cells 121 away from the first input terminal 11, and the unprogrammed first memory cells 121 or the first memory cells 121 in the unprogrammed state are located on a side of the currently programmed first memory cells 121 close to the first input terminal 11.
In addition, since the conductivity of the channel C of the first memory cell 121 is greatly reduced along with the increase of the threshold voltage of the first memory cell 121 when the data state of the first memory cell 121 is changed from the unprogrammed state to the programmed state, when the first preset voltage V1 on the second input terminal 14 is transmitted to the first input terminal 11 through the channel C of the programmed first memory cell 121, a significant voltage drop occurs between two longitudinal ends of the channel C of the programmed first memory cell 121, so that the potential of the channel layer 16 cannot be effectively increased, and the density of free electrons in the channel layer 16 cannot be effectively reduced. To solve this problem, in the embodiment, when the first programming operation is performed on the first memory string 12, in the pre-charging phase of the first programming operation, in addition to the first preset voltage V1 provided to the second input terminal 14, a second preset voltage V2 is provided to the programmed first memory cell 121 in the first memory string 12, so that the programmed first memory cell 121 is turned on to reduce the voltage drop between the two ends of the channel C of the programmed first memory cell 121 in the longitudinal direction when the first preset voltage V1 on the second input terminal 14 is transmitted to the first input terminal 11 through the channel C of the programmed first memory cell 121, thereby increasing the potential of the channel layer 16, so that electrons in the channel layer 16 have a larger electric field force and are more likely to diffuse to the second input terminal 14, it is more advantageous to reduce the electron density in the channel layer 16 and to reduce program disturb.
The second preset voltage V2 is greater than the threshold voltage of the corresponding programmed first memory cell 121, for example, the threshold voltage of the programmed first memory cell 121 may have a value range of-2 to 5V, and correspondingly, the value range of the second preset voltage V2 may be 5 to 7V. Specifically, as shown in fig. 5, in the precharge phase of the first programming operation, a ground voltage of 0V may be provided to the first input terminal 11, and accordingly, the first preset voltage V1 is a positive voltage and may range from 0V to 4V, for example, 2.2V.
In a specific implementation, in the precharge phase of the first programming operation, the duration of supplying the first preset voltage V1 to the second input terminal 14 may be longer than the duration of supplying the second preset voltage V2 to the gate layer a of the programmed first memory cell 121, so as to ensure that the voltage applied to the gate layer a of the programmed first memory cell 121 is reduced to 0V, that is, when the channel C of the programmed first memory cell 121 is non-conductive or poor in conductive performance, the electrons in the channel C of the programmed first memory cell 121 can still continue to migrate and diffuse toward the second input terminal 14 under the electric field force of the first preset voltage V1, thereby further reducing the electron density in the channel layer 16.
In some embodiments, as shown in fig. 6 and 7, the above-described stack structure 15 may include a first stack structure 15A and a first redundant stack structure 15B which are stacked in the longitudinal direction Z. Accordingly, the first memory string 12 may be disposed in the first stacked structure 15A, the three-dimensional memory may further include a first redundant memory string 20 located between the first memory string 12 and the second input terminal 14, the first redundant memory string 20 may be located in the first redundant stacked structure 15B, and may include at least one first redundant memory cell 201 stacked in the longitudinal direction Z, each first redundant memory cell 201 and the first memory cell 121 have a similar structure, as shown in fig. 4, and may also include a gate layer a, a memory layer B for storing a data state, and a channel C. The first redundant memory cell 201 is a non-data memory cell that does not satisfy the condition for storing user data, and the first memory cell 121 is a data memory cell that satisfies the condition for storing user data. Before the precharge of the first program operation, the data state of at least one first redundant memory cell 201 in the first redundant memory string 20 is set to a programmed state. In one embodiment, the data states of all the first redundant memory cells 201 in the first redundant memory string 20 may be set to a programmed state before the precharging of the first programming operation is performed.
Specifically, in the precharge phase of the first programming operation, as shown in fig. 8, it is further required to provide a third preset voltage V3 to the gate layer a of the programmed first redundant memory cell 201 to turn on the programmed first redundant memory cell 201, so as to ensure that electrons in the channel C of the first memory string 12 located below the first redundant memory string 20 can enter the upper second input terminal 14 through the channel C of the first redundant memory string 20. The third predetermined voltage V3 is not less than the threshold voltage of the corresponding programmed first redundant memory cell 201, and in one embodiment, the third predetermined voltage V3 may be 2.2V.
In other embodiments, as shown in fig. 6 and 7, the stacking structure 15 may include a second stacking structure 15C located on a side of the first stacking structure 15A facing away from the second input end 14, and a second redundant stacking structure 15D located between the first stacking structure 15A and the second stacking structure 15C. Accordingly, the three-dimensional memory may further include a second memory string 13 between the first input 11 and the first memory string 12, and a second redundant memory string 21 between the first memory string 12 and the second memory string 13. The second memory string 13 may be located in the second stacked configuration 15C and the second redundant memory string 21 may be located in the second redundant stacked configuration 15D. The second memory string 13 includes a plurality of second memory cells 131 stacked in the longitudinal direction Z, the second redundant memory string 21 includes at least one second redundant memory cell 211 stacked in the longitudinal direction Z, and each of the second memory cells 131 and the second redundant memory cells 211 has a similar structure to the first memory cell 121, and may also include a gate layer a, a memory layer B for storing a data state, and a channel C, as shown in fig. 4. The second redundant memory cell 211 is a non-data memory cell that does not satisfy the condition for storing user data, and the second memory cell 131 is a data memory cell that satisfies the condition for storing user data. Before the precharge of the first program operation, the data state of at least one second redundant memory cell 211 in the second redundant memory string 21 is set to a programmed state. In one embodiment, the data states of all of the second redundant memory cells 211 in the second redundant memory string 21 may have been set to a programmed state before the precharging of the first programming operation is performed.
Specifically, in the precharge phase of the first programming operation, as shown in fig. 8, a fourth preset voltage V4 may be further applied to the gate layer a of the programmed second redundant memory cell 211 to make the second redundant memory cell 211 in the programmed state non-conductive, so as to ensure that electrons in the channel C of the second memory string 13 located below the second redundant memory string 21 do not enter the channel C of the first memory string 12 located above via the channel C of the second redundant memory string 21. The fourth predetermined voltage V4 is less than the threshold voltage of the corresponding programmed second redundant memory cell 211, and in one embodiment, the fourth predetermined voltage V4 may be the ground voltage 0V.
In the above embodiment, the data states of all the second memory cells 131 in the second memory string 13 can be programmed states or unprogrammed states. In one embodiment, the data states of all the second memory cells 131 in the second memory string 13 can be programmed states. Accordingly, before the step S11, the method may further include: a half block erase operation is performed, which erases only data of the first memory string 12 and does not erase data of the second memory string 13 with respect to the first memory string 12 and the second memory string 13 to which data has been written, to adjust the data states of all the first memory cells 121 in the first memory string 12 to an unprogrammed state before performing the precharge of the first program operation, and the data states of all the second memory cells 131 in the second memory string 13 may be programmed states. In another embodiment, the data states of all the second memory cells 131 in the second memory string 13 can be non-programmed states. Accordingly, before the step S11, the method may further include: an erase operation is performed to erase not only the data of the first memory string 12 but also the data of the second memory string 13 for the first memory string 12 and the second memory string 13 to which the data has been written, so as to adjust the data state of all the first memory cells 121 in the first memory string 12 to an unprogrammed state and simultaneously adjust the data state of all the second memory cells 131 in the second memory string 13 to an unprogrammed state before performing the precharge of the first program operation.
In addition, as shown in fig. 8, in the precharge phase of the first programming operation, a ground voltage 0V may be supplied to the gate layer a of the second memory cell 131.
Step S12: and performing a first programming operation, wherein the first programming operation programs a plurality of first memory cells to be programmed from the first memory cells close to the second input end to the direction far away from the second input end.
Specifically, as shown in fig. 8, after the pre-charge phase of the first programming operation is finished, the programming phase of the first programming operation is entered, and in the programming phase of the first programming operation, a program voltage Vpgm (e.g., 22V) may be provided to the gate layer a of the currently programmed first memory cell 121 to implement data writing; and supplies a channel pass voltage Vpass (e.g., 7.2V) to the remaining first, second, first and second redundant memory cells 121, 131, 201 and 211 to ensure the conduction of the channel layer 16 described above.
It is understood that the programming voltage Vpgm should be large enough to enable a positive voltage difference between the gate layer a and the source of each currently programmed first memory cell 121, so that electrons in the channel C of the currently programmed first memory cell 121 can enter the corresponding storage layer B through a tunneling effect, thereby enabling the data state stored in the storage layer B of the currently programmed first memory cell 121 to be a programmed state, that is, enabling the data state of the currently programmed first memory cell 121 to be switched from an unprogrammed state to a programmed state.
In addition, in practical implementation, the first programming operation may sequentially program the first memory cells 121 in the first memory string 12 in an unprogrammed state from the first memory cells 121 close to the second input terminal 14 to a direction away from the second input terminal 14. After the programming of the currently programmed first memory cell 121 is completed, the step S11 is executed again to re-precharge the channel C of the first memory string 12 before the next first memory cell 121 to be programmed is programmed, so as to remove electrons generated in the channel C due to the preceding programming step. For example, the step S12 may specifically include: programming the currently programmed first memory cell 121; when the programming of the currently programmed first memory cell 121 is completed, the next first memory cell is updated to the currently programmed first memory cell 121, and the process returns to the above step S11, where the next first memory cell is the first memory cell 121 adjacent to the currently programmed first memory cell 121 and located on the side of the currently programmed first memory cell 121 away from the second input terminal 14, so that a loop can be formed, and the programming of one first memory cell 121 to be programmed can be completed each time the loop is completed, until the loop is completed after all first memory cells 121 to be programmed are programmed.
In an embodiment, when the data states of all the second memory cells 131 in the second memory string 13 are the non-programmed state, after the step S12, the method for programming operation may further include:
step S13: after the programming of the plurality of first memory cells is completed, a second programming operation is triggered.
Wherein the second programming operation comprises:
substep S131: and performing a second programming operation, including supplying a fifth preset voltage to the second input terminal, and supplying a sixth preset voltage to the gate layers of the second memory cell, the first memory cell and the second redundant memory cell in the programmed state, so that the second memory cell, the first memory cell and the second redundant memory cell in the programmed state are conducted to precharge the channel in the first memory string and the second memory string.
Specifically, after the programming of the plurality of first memory cells 121 is completed, the data states of all the first memory cells 121 in the first memory string 12 may be programmed states, and the program operation device performs a second program operation to program the second memory cells 131 in the second memory string 13. In this embodiment, when performing the second programming operation on the second memory string 13, the second programming operation programs a plurality of second memory cells 131 to be programmed from the second memory cells 131 close to the second input terminal 14 to a direction away from the second input terminal 14, that is, the programmed second memory cells 131 or the second memory cells 131 in the programmed state are located on a side of the currently programmed second memory cells 131 away from the first input terminal 11, and the unprogrammed second memory cells 131 or the second memory cells 131 in the unprogrammed state are located on a side of the currently programmed second memory cells 131 close to the first input terminal 11.
As shown in fig. 9, when performing the second programming operation on the second memory string 13, the second programming operation may be divided into at least two stages: a precharge phase and a programming phase. In the present embodiment, the fifth preset voltage V5 is provided to the second input terminal 14 during the pre-charge phase of the second programming operation, so that the potential of the second input terminal 14 is higher than the potential of the first input terminal 11, and an electric field force directed to the second input terminal 14 can be applied to the dissociated electrons in the channel layer 16, and the dissociated electrons can leave the channel layer 16 and can be absorbed by the second input terminal 14 under the action of the electric field force.
Furthermore, since the programmed first memory cell 121, the programmed first redundant memory cell 201 and the programmed second redundant memory cell 211 are located between the second input terminal 14 and the second memory string 13 in the longitudinal direction Z, in order to enable the fifth preset voltage V5 on the second input terminal 14 to be transmitted to the first input terminal 11 through the channel C of the programmed first memory cell 121, the programmed first redundant memory cell 201, the programmed second redundant memory cell 211 and the programmed second memory cell 131 and effectively increase the potential of the channel layer 16, in the present embodiment, in the precharge phase of the second programming operation, in addition to the fifth preset voltage V5, the sixth preset voltage V6 is provided to the second memory cell 131, the first redundant memory cell 121, the first redundant memory cell 201 and the second redundant memory cell 211, to ensure the conduction of the memory cell between the currently programmed second memory cell 131 and the second input 14.
The sixth preset voltage V6 is greater than the threshold voltages of the programmed second memory cell 131, the programmed first memory cell 121, the programmed first redundant memory cell 201, and the programmed second redundant memory cell 211, for example, the threshold voltage of the programmed first memory cell 121 may have a value range of-2 to 5V, and correspondingly, the value range of the sixth preset voltage V6 may have a value range of 5 to 7V. The fifth preset voltage V5 may be the same as the first preset voltage V1, for example, a positive voltage, and may range from 0V to 4V, for example, 2.2V.
Substep S132: and performing a second programming operation, wherein the second programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
Specifically, as shown in fig. 9, after the pre-charge phase of the second programming operation is ended, the programming phase of the second programming operation is entered, and in the programming phase of the second programming operation, a program voltage Vpgm (e.g., 22V) may be provided to the gate layer a of the currently programmed second memory cell 131 to implement data writing; and supplies a channel pass voltage Vpass (e.g., 7.2V) to the remaining second memory cell 131, first memory cell 121, first redundant memory cell 201, and second redundant memory cell 211 to ensure conduction of the channel layer 16 described above.
In practical implementation, the second programming operation may sequentially program the second memory cells 131 in the second memory string 13 in an unprogrammed state from the second memory cells 131 close to the second input terminal 14 to a direction away from the second input terminal 14. After the programming of the currently programmed second memory cell 131 is completed, the sub-step S131 is performed again before the next second memory cell 131 to be programmed is programmed, so as to re-precharge the channel C in the first memory string 12 and the second memory string 13, thereby removing electrons generated in the channel C due to the preceding programming step.
In another embodiment, as shown in fig. 6 and 7, the stacking structure 15 may include a fifth stacking structure 15E located between the first input end 11 and the second stacking structure 15C. Accordingly, the three-dimensional memory may further include a third redundant memory string 22 between the second memory string 13 and the first input terminal 11. The third redundant memory string includes at least one third redundant memory cell 221 stacked in the longitudinal direction Z, and each third redundant memory cell 221 has a structure similar to that of the first memory cell 121, and may also include a gate layer a, a memory layer B for storing a data state, and a channel C, as shown in fig. 4. The third redundant memory cell 221 is a non-data memory cell that does not satisfy the condition for storing user data, and the data state of at least one third redundant memory cell 221 in the third redundant memory string 22 is set to a programmed state before the precharging of the first programming operation. In one embodiment, the data states of all third redundant memory cells 221 in the third redundant memory string 22 may be set to a programmed state before the precharging of the first programming operation is performed. Further, the above step S13 may be replaced with the following steps:
step S14: after the programming of the plurality of first memory cells is completed, a third programming operation is triggered.
Wherein the third programming operation comprises:
substep S141: and performing a third programming operation including supplying a seventh preset voltage to the first input terminal, supplying an eighth preset voltage to a gate layer of the third redundant memory cell in a programmed state to turn on the third redundant memory cell, and supplying a ninth preset voltage to the remaining memory cells between the second input terminal and the third redundant memory cell to turn off the remaining memory cells to precharge a channel in the second memory string.
Specifically, after the programming of the plurality of first memory cells 121 is completed, the data states of all the first memory cells 121 in the first memory string 12 may be programmed states, and the program operation device may then perform a third program operation to program the second memory cells 131 in the second memory string 13. In this embodiment, when performing the third programming operation on the second memory string 13, the third programming operation programs a plurality of second memory cells 131 to be programmed from the second memory cells 131 close to the second input terminal 14 to a direction away from the second input terminal 14, that is, the programmed second memory cells 131 or the second memory cells 131 in the programmed state are located on a side of the currently programmed second memory cells 131 away from the first input terminal 11, and the unprogrammed second memory cells 131 or the second memory cells 131 in the unprogrammed state are located on a side of the currently programmed second memory cells 131 close to the first input terminal 11.
As shown in fig. 10, when the third programming operation is performed on the second memory string 13, the third programming operation can be divided into at least two stages: a precharge phase and a programming phase. In the present embodiment, the seventh preset voltage V7 is provided to the first input terminal 11 during the pre-charge phase of the third programming operation in order to make the potential of the first input terminal 11 higher than the potential of the second input terminal 14, so as to apply an electric field force to the dissociated electrons in the channel layer 16, which is directed to the first input terminal 11, and make the dissociated electrons leave the channel layer 16 and be absorbed by the first input terminal 11 under the action of the electric field force.
In addition, since the programmed third redundant memory cell 221 is located between the first input terminal 11 and the second memory string 13 in the vertical direction Z, in order to enable the seventh preset voltage V7 on the first input terminal 11 to be transmitted to the second input terminal 14 through the channel C of the programmed third redundant memory cell 221 and effectively raise the potential of the channel layer 16, in the present embodiment, in the precharge phase of the third programming operation, in addition to the seventh preset voltage V7 being provided to the first input terminal 11, an eighth preset voltage V8 is provided to the programmed third redundant memory cell 221, so that the third redundant memory cell 221 in the programmed state is turned on. Meanwhile, in the precharge phase of the third program operation, the remaining memory cells (including the first memory cell, the first redundant memory cell and the second redundant memory cell) between the second input terminal and the third redundant memory cell may not be turned on, and specifically, the ninth preset voltage may be 0V so that the remaining memory cells are not turned on.
The eighth preset voltage V8 is greater than the threshold voltage of the corresponding programmed third redundant memory cell 221. Specifically, as shown in fig. 10, in the precharge phase of the third programming operation, a ground voltage 0V may be provided to the second input terminal 14, and accordingly, the seventh preset voltage V7 is a positive voltage and may range from 0V to 4V, for example, 2.2V.
Substep S142: and performing a third programming operation, wherein the third programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
The detailed implementation of the substep S142 may refer to the detailed implementation of the substep S132, and thus is not described herein again.
Different from the prior art, the programming operation method of the three-dimensional memory provided in this embodiment is applied to a memory, where the memory includes a first memory string, and a first input terminal and a second input terminal located at two ends of the first memory string, the first memory string includes a plurality of first memory cells connected in series, each first memory cell includes a gate layer, a memory layer storing a data state, and a channel, the data state includes a programmed state and an unprogrammed state, and the programming operation method conducts the first memory cell in the programmed state by performing a pre-charging of the first programming operation, including providing a first preset voltage to the second input terminal, and providing a second preset voltage to the gate layer of the first memory cell in the programmed state, so as to pre-charge the channel in the first memory string, and then performing the first programming operation, where the first programming operation conducts a plurality of first memory cells to be programmed from the first memory cell close to the second input terminal to a direction away from the second input terminal And programming a memory cell, so that when the first programming operation is carried out on the first memory string, the problem that the channel potential cannot be effectively improved due to the channel shutdown of the programmed first memory cell can be avoided in the pre-charging stage of the first programming operation, and the programming interference is reduced.
Referring to fig. 11, fig. 11 specifically illustrates a programming operation device 90 of a memory according to an embodiment of the present invention, where the programming operation device 90 of the memory includes: a first pre-charge module 901 and a first programming module 902, wherein:
(1) first pre-charge module 901
The first pre-charging module 901 is configured to perform pre-charging for a first programming operation, where the pre-charging for the first programming operation specifically includes: the first preset voltage is provided to the second input terminal, and the second preset voltage is provided to the gate layer of the first memory cell in the programmed state, so that the first memory cell in the programmed state is conducted to pre-charge the channel in the first memory string.
In this embodiment, the memory includes a first memory string, and a first input terminal and a second input terminal at two ends of the first memory string, the first memory string includes a plurality of first memory cells connected in series, each of the first memory cells includes a gate layer, a memory layer storing a data state, and a channel, and the data state includes a programmed state and an unprogrammed state. The memory may be specifically a two-dimensional memory, and may also be specifically a three-dimensional memory.
For convenience of description and understanding, the embodiment of the present invention is described taking the above memory as a three-dimensional memory as an example, the three-dimensional memory may include a first memory string, and a first input terminal and a second input terminal located at both ends of the first memory string in a longitudinal direction, the first memory string includes a plurality of first memory cells stacked in the longitudinal direction, each of the first memory cells includes a gate layer, a memory layer storing a data state, and a channel, and the data state includes a programmed state and an unprogrammed state.
The duration of supplying the first preset voltage to the second input end is longer than the duration of supplying the second preset voltage to the grid layer of the first memory unit in the programmed state.
In a specific embodiment, the three-dimensional memory may further include a first redundant memory string located between the first memory string and the second input terminal, the first redundant memory string includes at least one first redundant memory cell stacked in the longitudinal direction, each first redundant memory cell includes a gate layer, a memory layer for storing a data state, and a channel, the data state of the at least one first redundant memory cell is a programmed state, and the performing the pre-charging of the first programming operation may further include:
and providing a third preset voltage to the grid layer of the first redundant memory unit in the programmed state to enable the first redundant memory unit in the programmed state to be conducted.
In some embodiments, the three-dimensional memory may further include a second memory string located between the first input terminal and the first memory string, and a second redundant memory string located between the first memory string and the second memory string, the second memory string includes a plurality of second memory cells stacked in the longitudinal direction, the second redundant memory string includes at least one second redundant memory cell stacked in the longitudinal direction, each of the second memory cells and the second redundant memory cells includes a gate layer, a memory layer storing a data state, and a channel, the data state of the at least one second redundant memory cell is a programmed state, and the performing the pre-charging of the first programming operation may further include:
and providing a fourth preset voltage to the grid layer of the second redundant memory unit in the programmed state to make the second redundant memory unit in the programmed state not conductive.
(2) First programming module 902
The first programming module 902 is configured to perform a first programming operation, where the first programming operation programs a plurality of first memory cells to be programmed from a first memory cell close to the second input end to a direction away from the second input end.
The first programming module 902 is specifically configured to:
a program voltage is supplied to a gate layer of a currently programmed first memory cell, and a channel-on voltage is supplied to the remaining first memory cells.
In specific implementation, the first programming module 902 may specifically be configured to:
programming a currently programmed first memory cell;
when the programming of the currently programmed first memory cell is completed, updating the next first memory cell to the currently programmed first memory cell, and triggering the first pre-charging module to re-perform the pre-charging of the first programming operation, wherein the next first memory cell is a first memory cell adjacent to the currently programmed first memory cell and located on one side of the currently programmed first memory cell away from the second input terminal.
In a specific embodiment, the programming operation device 90 may further include:
(3) first trigger module
The first trigger module is used for triggering the second programming operation after the programming of the plurality of first memory cells is completed.
Wherein the second programming operation may include:
performing a second program operation including supplying a fifth preset voltage to the second input terminal and supplying a sixth preset voltage to the gate layers of the second memory cell, the first memory cell and the second redundant memory cell in the programmed state to turn on the second memory cell, the first memory cell and the second redundant memory cell in the programmed state to precharge the channels in the first memory string and the second memory string; and (c) a second step of,
and performing a second programming operation, wherein the second programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
In another specific embodiment, the three-dimensional memory may further include a third redundant memory string located between the second memory string and the first input terminal, the third redundant memory string includes at least one third redundant memory cell stacked in the longitudinal direction, each third redundant memory cell includes a gate layer, a memory layer for storing a data state, and a channel, the data state of the at least one third redundant memory cell is a programmed state, and the first trigger module may be replaced with:
(4) second trigger module
And the second trigger module is used for triggering the third programming operation after the programming of the plurality of first memory cells is completed.
Wherein the third programming operation may include:
performing a third program operation including supplying a seventh preset voltage to the first input terminal, supplying an eighth preset voltage to a gate layer of a third redundant memory cell in a programmed state to turn on the third redundant memory cell, and supplying a ninth preset voltage to remaining memory cells between the second input terminal and the third redundant memory cell to turn off the remaining memory cells to precharge a channel in the second memory string;
and performing a third programming operation, wherein the third programming operation programs a plurality of second memory cells to be programmed from the second memory cells close to the second input end to the direction far away from the second input end.
The ninth preset voltage may be a ground voltage, that is, 0V.
In the above embodiment, the first input terminal may be electrically connected to a source side terminal of the first memory string, and the second input terminal may be electrically connected to a drain side terminal of the first memory string.
In the specific implementation, the specific implementation of each module may refer to the foregoing method embodiment, and is not described herein again.
Different from the prior art, the programming operation device of the memory provided by this embodiment can avoid the problem that the channel potential cannot be effectively increased due to the channel shutdown of the programmed first memory cell in the pre-charging stage of the first programming operation when the first programming operation is performed on the first memory string, and reduce the programming interference.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (20)

1. A program operation method of a memory, wherein the memory comprises a first memory string, a second redundant memory string and a second memory string which are sequentially connected in series, wherein the first memory string is connected to a bit line; the second memory string is connected to a source line; the first memory string includes a plurality of first memory cells connected in series and a plurality of first word lines coupled to the plurality of first memory cells; the second redundant memory string includes at least one second redundant memory cell in series and a second redundant word line coupled to the at least one second redundant memory cell; the programming operation method comprises the following steps:
precharging the plurality of first memory cells included in the first memory string with a first program operation, wherein the precharging includes: providing a first preset voltage to the bit line; providing a second preset voltage to a first word line coupled to the first memory cell in a programmed state to turn on the first memory cell in the programmed state; and providing a fourth preset voltage to a second redundant word line coupled to the second redundant memory cell in the programmed state to make the second redundant memory cell in the programmed state non-conductive;
performing the first programming operation, wherein the first programming operation is programmed sequentially in a programming order from a first memory cell adjacent to the bit line to a first memory cell adjacent to the second redundant memory string.
2. The method of claim 1, wherein a duration of the first preset voltage is greater than a duration of the second preset voltage.
3. The method of programming operation of a memory according to claim 1, wherein said performing the first programming operation includes:
programming a currently selected first memory cell;
when programming of the currently selected first memory cell is completed, pre-charging a next selected first memory cell for the first programming operation and performing the first programming operation, wherein the next selected first memory cell is located between the currently selected first memory cell and the second redundant memory string and adjacent to the currently selected first memory cell.
4. The method of programming operation of a memory according to claim 1, wherein said performing the first programming operation includes:
providing a program voltage to a first word line coupled to a currently selected first memory cell;
providing a channel-on voltage to a first word line coupled to the remaining first memory cells, the second redundant word line, and a second word line coupled to a second memory cell included in the second memory string.
5. The method of programming operation of a memory of claim 1, wherein the memory further comprises a first redundant memory string located between the first memory string and the bit line, the first redundant memory string comprising at least one first redundant memory cell in series and a first redundant word line coupled to the at least one first redundant memory cell, the pre-charging for the first programming operation further comprising:
providing a third preset voltage to a first redundancy word line coupled to the first redundancy memory cell in a programmed state, so that the first redundancy memory cell in the programmed state is turned on.
6. The method of programming operation of a memory according to claim 1, wherein the second memory string includes a plurality of second memory cells and a plurality of second word lines coupled to the plurality of second memory cells, the method further comprising:
precharging the plurality of second memory cells included in the second memory string with a second program operation; wherein the pre-charging comprises: providing a fifth preset voltage to the bit line; providing a sixth preset voltage to a second word line, the plurality of first word lines, and the second redundant word line coupled to the second memory cell in a programmed state, turning on the second memory cell in the programmed state, the plurality of first memory cells, and the at least one second redundant memory cell;
performing the second programming operation, the second programming operation sequentially programming from a second memory cell adjacent to the second redundant memory string to a second memory cell adjacent to the source line.
7. The method of programming operation of a memory of claim 1, further comprising a third redundant memory string located between the second memory string and the source line, the third redundant memory string comprising at least one third redundant memory cell in series and a third redundant word line coupled to the at least one third redundant memory cell, the method of programming operation further comprising:
precharging a plurality of second memory cells included in the second memory string with a third program operation, wherein the precharging includes: providing a seventh preset voltage to the source line, providing an eighth preset voltage to a third redundant word line coupled to the at least one third redundant memory cell in a programmed state, and turning on the at least one third redundant memory cell in the programmed state; providing a ninth preset voltage to a word line coupled to memory cells between the bit line and the third redundant memory string to make the memory cells between the bit line and the third redundant memory string non-conductive;
and performing the third programming operation, wherein the third programming operation is sequentially programmed in a programming order from a second memory cell adjacent to the second redundant memory string to a second memory cell adjacent to the third redundant memory string.
8. The method according to claim 7, wherein the ninth predetermined voltage is 0V.
9. The method of any one of claims 1 to 8, wherein before the precharging of the first program operation for the plurality of first memory cells included in the first memory string, the method of program operation further comprises:
performing a half-block erase operation on the memory, wherein the half-block erase operation comprises: and performing an erasing operation on only the first memory string and not the second memory string to which data has been written.
10. The method of any one of claims 1 to 8, wherein the memory is a three-dimensional memory.
11. A memory, the memory comprising: the first storage string, the second redundant storage string and the second storage string are sequentially connected in series; and control circuitry for controlling the first memory string, the second redundant memory string, and the second memory string; wherein the first memory string is connected to a bit line; the second memory string is connected to a source line; the first memory string includes a plurality of first memory cells connected in series and a plurality of first word lines coupled to the plurality of first memory cells; the second redundant memory string includes at least one second redundant memory cell in series and a second redundant word line coupled to the at least one second redundant memory cell;
wherein the control circuit is configured to:
precharging the plurality of first memory cells included in the first memory string with a first program operation, wherein the precharging includes: providing a first preset voltage to the bit line; providing a second preset voltage to a first word line coupled to the first memory cell in a programmed state to turn on the first memory cell in the programmed state; and providing a fourth preset voltage to a second redundant word line coupled to the second redundant memory cell in the programmed state to make the second redundant memory cell in the programmed state non-conductive;
performing the first programming operation, wherein the first programming operation is programmed sequentially in a programming order from a first memory cell adjacent to the bit line to a first memory cell adjacent to the second redundant memory string.
12. The memory of claim 11, wherein the duration of the first preset voltage is greater than the duration of the second preset voltage.
13. The memory of claim 11, wherein the control circuit is further configured to:
programming a currently selected first memory cell;
when programming of the currently selected first memory cell is completed, pre-charging a next selected first memory cell for the first programming operation and performing the first programming operation, wherein the next selected first memory cell is located between the currently selected first memory cell and the second redundant memory string and adjacent to the currently selected first memory cell.
14. The memory of claim 11, wherein the control circuit is further configured to:
providing a program voltage to a first word line coupled to a currently selected first memory cell;
providing a channel-on voltage to a first word line coupled to the remaining first memory cells, the second redundant word line, and a second word line coupled to a second memory cell included in the second memory string.
15. The memory of claim 11, further comprising a first redundant memory string positioned between the first memory string and the bit line, the first redundant memory string comprising at least one first redundant memory cell in series and a first redundant word line coupled to the at least one first redundant memory cell, the control circuit further configured to:
providing a third preset voltage to a first redundancy word line coupled to the first redundancy memory cell in a programmed state, so that the first redundancy memory cell in the programmed state is turned on.
16. The memory of claim 11, wherein the second memory string includes a plurality of second memory cells and a second word line coupled to the plurality of second memory cells, the control circuit further controlled to: precharging the plurality of second memory cells included in the second memory string with a second program operation; wherein the pre-charging comprises: providing a fifth preset voltage to the bit line; providing a sixth preset voltage to a second word line, the plurality of first word lines, and the second redundant word line coupled to the second memory cell in a programmed state, turning on the second memory cell in the programmed state, the plurality of first memory cells, and the at least one second redundant memory cell;
performing the second programming operation, the second programming operation sequentially programming from a second memory cell adjacent to the second redundant memory string to a second memory cell adjacent to the source line.
17. The memory of claim 11, further comprising a third redundant memory string located between the second memory string and the source line, the third redundant memory string comprising at least one third redundant memory cell in series and a third redundant word line coupled to the at least one third redundant memory cell, the control circuitry further configured to:
precharging a plurality of second memory cells included in the second memory string with a third program operation, wherein the precharging includes: providing a seventh preset voltage to the source line, providing an eighth preset voltage to a third redundant word line coupled to the at least one third redundant memory cell in a programmed state, and turning on the at least one third redundant memory cell in the programmed state; providing a ninth preset voltage to a word line coupled to memory cells between the bit line and the third redundant memory string to make the memory cells between the bit line and the third redundant memory string non-conductive;
and performing the third programming operation, wherein the third programming operation is sequentially programmed in a programming order from a second memory cell adjacent to the second redundant memory string to a second memory cell adjacent to the third redundant memory string.
18. The memory according to claim 17, wherein the ninth preset voltage is 0V.
19. The memory of any one of claims 11 to 18, wherein prior to the precharging of the first programming operation for the plurality of first memory cells included in the first memory string, the control circuit is further configured to:
performing a half-block erase operation on the memory, wherein the half-block erase operation comprises: and performing an erasing operation on only the first memory string and not the second memory string to which data has been written.
20. The memory according to any one of claims 11 to 18, wherein the memory is a three-dimensional memory.
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