CN114863496A - Fingerprint identification device and electronic equipment - Google Patents

Abstract

A fingerprint identification device and an electronic device are provided. The fingerprint identification device includes: a fingerprint sensing chip; the substrate is arranged below the fingerprint sensing chip and comprises a first connecting area and a first grounding area, the first connecting area is located in the center area of the substrate, the first grounding area is located around the first connecting area and located in the edge area of the substrate, and the fingerprint sensing chip is electrically connected with the substrate through the first connecting area. The fingerprint identification device and the electronic equipment can improve the safety performance of the fingerprint identification device.

Description

Fingerprint identification device and electronic equipment

Technical Field

The present application relates to the field of fingerprint identification technology, and more particularly, to a fingerprint identification device and an electronic device.

Background

In the electric capacity fingerprint identification module use, need distinguish with the fingerprint identification of finger direct contact fingerprint identification module. Because the human body has static, and at the fingerprint identification in-process, can discharge in the twinkling of an eye when the finger contact fingerprint identification zone time, and then can influence the accuracy and the sensitivity of fingerprint identification module. Therefore, the fingerprint identification module requires a targeted electrostatic discharge (ESD) protection design during design.

Along with the development of electronic equipment such as current cell-phone, also more and more strict to the size requirement of fingerprint identification module. For example, with the reduction of the thickness of the mobile phone, the size requirement for the fingerprint identification module applied to the side of the mobile phone is also narrower and narrower, which may cause the ESD protection design on the fingerprint identification module to be more and more difficult to be compatible. If can't produce effectual ESD route of releasing, then static is through in the fingerprint identification module for example the accumulation of parts such as reinforcement steel sheet, probably can take place the secondary breakdown to the circuit board, perhaps releases static to other weak positions of fingerprint identification module, more is unfavorable for the safety of fingerprint identification module on the contrary.

Disclosure of Invention

The embodiment of the application provides a fingerprint identification device and electronic equipment, and the safety performance of the fingerprint identification device can be improved.

In a first aspect, a fingerprint identification device is provided, which includes: a fingerprint sensing chip; the substrate is arranged below the fingerprint sensing chip and comprises a first connecting area and a first grounding area, the first connecting area is located in the central area of the substrate, the first grounding area is located around the first connecting area and located in the edge area of the substrate, and the fingerprint sensing chip is electrically connected with the substrate through the first connecting area.

Among the technical scheme of this application embodiment, the first ground connection district of base plate is located around first connection district, and is located the marginal area of base plate, does not influence first connection district to can realize electrostatic discharge, guarantee fingerprint identification device prevent the ability of static, also can guarantee fingerprint identification device's reliability and security.

In a possible embodiment, the substrate is a multilayer structure, the multilayer structure includes a first routing layer, the first connection region and the first ground region are located on the first routing layer, the first connection region includes a first pad, and the fingerprint sensor chip is electrically connected to the substrate through the first pad.

In a possible embodiment, the substrate further includes a second connection area located in a central region of the substrate and a second ground area located around the second connection area and located in an edge region of the substrate, and the fingerprint identification device further includes: and the circuit board is arranged below the substrate and is electrically connected with the substrate through the second connecting area.

In a possible embodiment, the second connection area corresponds to the first connection area and is located below the first connection area; and/or the second grounding area corresponds to the first grounding area and is positioned below the first grounding area.

In a possible embodiment, the substrate is a multilayer structure, the multilayer structure includes a second routing layer, the second connection region and the second ground region are located on the second routing layer, the second connection region includes a second pad, and the circuit board is electrically connected to the substrate through the second pad.

In a possible implementation, the fingerprint identification device further includes: and the reinforcing plate is positioned below the circuit board.

In a possible embodiment, a first end surface of the first grounding area, which is far away from the first connection area, is located at a second end surface of the substrate, and the second end surface is a cut surface of the substrate.

In a possible embodiment, the first grounding area surrounds the first connection area, and the first grounding area is an annular copper-clad area.

In one possible embodiment, the first ground area includes a first ground line surrounding the first connection area, and a plurality of second ground lines connected to the first ground line and spaced apart from each other, each of the plurality of second ground lines extending from the first ground line in a direction away from the first ground line.

In a possible implementation, the fingerprint identification device further includes: and the packaging layer is arranged above the fingerprint sensing chip and used for packaging the fingerprint sensing chip and the substrate.

In one possible embodiment, the fingerprint recognition device is a capacitive fingerprint recognition device.

In a second aspect, an electronic device is provided, comprising: the fingerprint identification device of the first aspect or any one of the possible embodiments of the first aspect, the fingerprint identification device being located at a side of the electronic device.

Drawings

FIG. 1 is a schematic top view of one possible circuit board in a fingerprint identification module.

FIG. 2 is a schematic top view of another possible circuit board in the fingerprint identification module.

FIG. 3 is a schematic cross-sectional view of a fingerprint identification module.

Fig. 4 is a schematic top view of one possible circuit board according to an embodiment of the present application.

Fig. 5 is a schematic top view of a substrate included in a fingerprint identification device according to an embodiment of the present application.

Fig. 6 is another schematic top view of a substrate included in a fingerprint identification device according to an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view of a fingerprint recognition device according to an embodiment of the present application.

Fig. 8 is a schematic cross-sectional view of a substrate according to an embodiment of the present application.

Fig. 9 is a schematic cross-sectional view of a substrate before dicing according to an embodiment of the present application.

Fig. 10 is a schematic top view of a first routing layer of a substrate according to an embodiment of the present application.

Fig. 11 is another schematic top view of a first routing layer of a substrate according to an embodiment of the present application.

Fig. 12 is a schematic top view of a second routing layer of a substrate according to an embodiment of the present application.

Fig. 13 is another schematic top view of a second routing layer of a substrate according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

It should be understood that the embodiments of the present application can be applied to optical fingerprint systems, including but not limited to optical fingerprint identification systems and products based on optical fingerprint imaging, and the embodiments of the present application are only described by way of example, but not limited to any limitation, and the embodiments of the present application are also applicable to other systems using optical imaging technology, etc.

The existing fingerprint identification module is usually added with an ESD protection design on a Flexible Circuit board (FPC), for example, the design of an electric wire grounding end (GND) is added at the edge of the FPC, and a reinforcing steel sheet in the fingerprint identification module can be connected with the GND position of the FPC through a conductive adhesive.

Fig. 1 and 2 respectively show schematic top views of two possible FPCs in a conventional fingerprint identification module, for example, the FPC 11 shown in fig. 1 has a relatively large size, and can be applied to a fingerprint identification module on the back of a mobile phone; the PFC 12 shown in fig. 2 has a relatively small size, is strip-shaped as a whole, and can be applied to a fingerprint recognition module on the side of a mobile phone.

As shown in fig. 1, the PFC 11 may include a GND 111, wherein the distribution of the GND 111 may be set according to practical applications. In addition, the area of the GND 111 further includes a window area 112, so that the fingerprint recognition module can discharge static electricity through the window area 112.

Similarly, as shown in fig. 2, the FPC 12 includes GND 121, and the distribution of the GND 12 may be set according to the actual application, for example, may be generally set at the edge of the PFC 12. In addition, the area of the GND 121 further includes a window area 122, so that the fingerprint recognition module can discharge static electricity through the window area 122.

Fig. 3 is a schematic cross-sectional view of a conventional fingerprint identification module 10, wherein the fingerprint identification module 10 is taken as a capacitive fingerprint identification module for example. As shown in fig. 3, the fingerprint identification module 10 may include, from top to bottom: an Epoxy Molding Compound (EMC) 101, a fingerprint chip 102, a substrate 104, an FPC105, and a reinforcing steel sheet 106, wherein the fingerprint chip 102 may be fixed to the substrate 104 by a non-conductive glue 103, and the EMC 101 is used to encapsulate the fingerprint chip 102 and the substrate 103. It is to be understood that, as shown in fig. 3, the FPC105 may be provided with a windowed area 1051, and the windowed area 1051 may expose GND for discharge of static electricity. For example, the windowed areas 1051 may be located on both sides of the FPC105, and on the top and bottom surfaces of the FPC105, respectively. In the lower windowed area 1051, the reinforcing steel sheet 106 may be electrically connected to the GND of the FPC105 through a conductive adhesive or the like.

Alternatively, the FPC105 shown in fig. 3 may be a cross-sectional view of the FPC 11 shown in fig. 1, the cross-section being perpendicular to the surface of the FPC 11 shown in fig. 1, and the windowed area 1051 included in the FPC105 may be a side view of the windowed area 111 shown in fig. 1; alternatively, the FPC105 shown in fig. 3 may be a cross-sectional view of the FPC 12 shown in fig. 2, the cross-section being perpendicular to the surface of the FPC 12 shown in fig. 2, and the windowed area 1051 shown in fig. 3 may be a side view of the windowed area 121 shown in fig. 1.

In particular, FIG. 3 also shows possible paths for ESD. As shown in fig. 3, when a finger touches a fingerprint identification area of the fingerprint identification module 10, for example, the finger may touch the upper surface of the EMC 101 or touch the surface of a protective layer disposed on the upper surface of the EMC 101, static electricity may be generated on the surface of the EMC 101, the static electricity may pass through the surface of the EMC 101, a part of the static electricity may be transmitted to a windowing area 1051 on the upper surface of the FPC105, and the windowing area 1051 exposes GND, and the static electricity may be discharged; in addition, there may be a part of static electricity transmitted to the reinforcing steel sheet 106 below, and the part of static electricity may pass through the reinforcing steel sheet 106, pass through the windowing region 1051 electrically connected with the reinforcing steel sheet 106 and located below the FPC105, and then be transmitted to the GND of the FPC105, and then release the static electricity.

However, with the development of electronic devices such as mobile phones, the size requirement of the fingerprint identification module is also stricter. For example, with the reduction of the thickness of the mobile phone, the size requirement for the fingerprint identification module applied to the side of the mobile phone is also narrower and narrower, which may cause the ESD protection design on the fingerprint identification module to be more and more difficult to be compatible. Fig. 4 is a schematic top view of another possible FPC in the existing fingerprint recognition module, and the PFC 13 shown in fig. 4 is a strip shape as a whole, and can be applied to a fingerprint recognition module on the side of a mobile phone. Specifically, as shown in fig. 4, since the size of the side of the mobile phone is limited, the width of the PFC 13 is very small, the GND windowing design of the FPC 12 shown in fig. 2 can no longer be implemented to release static electricity, and the FPC 13 can also not be GND windowed to connect the reinforcing steel sheet through the conductive adhesive. At this moment, the fingerprint identification module can't produce effectual ESD route of releasing, and static is very likely to pass through the accumulation of reinforcement steel sheet even, and then takes place the secondary and punctures and release the weak position to the fingerprint identification module, more is unfavorable for the safety of fingerprint identification module on the contrary.

Therefore, the embodiment of the application provides a fingerprint identification device and an electronic device, which can solve the above problems.

Fig. 5 and 6 respectively show possible schematic diagrams of a substrate included in the fingerprint identification device according to the embodiment of the present application. As shown in fig. 5 and 6, the fingerprint recognition device according to the embodiment of the present application may include: a fingerprint sensing chip (not shown in fig. 5); the substrate 21 is disposed below the fingerprint sensor chip, the substrate 21 includes a first connection region 211 and a first ground region 212, the first connection region 211 is located in a central region of the substrate 21, the first ground region 212 is located around the first connection region 211 and in an edge region of the substrate 21, and the fingerprint sensor chip is electrically connected to the substrate 21 through the first connection region 211.

It should be understood that the fingerprint sensing chip of the embodiment of the present application may be used for fingerprint identification. Specifically, when carrying out fingerprint identification, finger touch fingerprint identification module's fingerprint identification is regional, and fingerprint sensing chip can receive the signal that carries the fingerprint information of finger. For example, the fingerprint identification device in the embodiment of the present application may be a capacitive fingerprint identification device, and the fingerprint sensing chip may be configured to receive an electrical signal carrying fingerprint information of a finger, so as to facilitate fingerprint identification through the electrical signal, but the embodiment of the present application is not limited thereto.

The substrate 21 of the embodiment of the application is located below the fingerprint sensing chip and can be used for transmitting a signal which is received by the fingerprint sensing chip and carries fingerprint information. In particular, the substrate 21 comprises a first connection region 211, and the substrate 21 can be electrically connected to the fingerprint sensor chip through the first connection region 211. Alternatively, as shown in fig. 5 and 6, the first connection region 211 may be located in a central region of the substrate 21, and the first ground region 212 is located around the first connection region 211 and located in an edge region of the substrate 21, where the first ground region 212 is located at GND. For example, the first ground region 212 may be located at an edge of at least one side of the first connection region 211, which facilitates wiring and processing and prevents interference between the first ground region 212 and the first connection region 211.

Therefore, the fingerprint identification device of the embodiment of the present application includes a fingerprint sensing chip and a substrate 21, and a first connection region 211 and a first ground region 212 are disposed on the substrate 21, wherein the first connection region 211 is located in a central region of the substrate 21 and can be used for electrically connecting the substrate 21 and the fingerprint sensing chip; first ground connection region 212 is located around this first connection region 211, and is located the marginal area of base plate 21, does not influence first connection region 211 to can realize electrostatic discharge, guarantee fingerprint identification device's the ability of preventing static, avoid puncturing this fingerprint identification device's weak area, guarantee fingerprint identification device's reliability and security.

Optionally, the wiring manner and the distribution position of the first ground region 212 in the embodiment of the present application may be set according to practical applications. For example, the first ground region 212 may be located at an edge region of one or more sides of the first connection region 211. Specifically, as shown in fig. 5 and fig. 6, the first grounding area 212 surrounds the first connection area 211, that is, the first grounding area 212 may be arranged in a ring shape surrounding the first connection area 211, for example, a square ring, a circular ring, or another ring shape, that is, the first grounding area 212 is arranged around the first connection area 211, so that static electricity around the substrate 21 can be discharged through the first grounding area 212, the effect of discharging static electricity is improved, and the safety of the fingerprint identification device 20 is improved. Alternatively, different from the arrangement of fig. 5 and 6, the first ground region 212 may be located only in a partial edge region of the first connection region 211, for example, the first ground region 212 is located on any side of the first connection region 211, or located in two opposite or intersecting side regions of the first connection region 211, so as to save space. For convenience of description, the embodiments of the present application are mainly described by taking the arrangement shown in fig. 5 and 6 as an example.

Specifically, as shown in fig. 5, the first ground region 212 of the embodiment of the present application is an annular copper-clad region, that is, the first ground region 212 may be a continuous region, which is annular as a whole, so as to surround the first connection region 211, and the annular region is disposed by copper-clad, so as to improve the electrostatic discharge effect of the first ground region 212. Optionally, the shape of the annular copper-clad area may also be set according to practical application, for example, the annular copper-clad area may be an approximately rectangular ring as shown in fig. 5, or may also be a circular ring, or other shapes.

Alternatively, as shown in fig. 6, the first ground region 212 of the embodiment of the present disclosure includes a first ground line 2121 surrounding the first connection region 211, and a plurality of second ground lines 2122 connected to the first ground line 2121 and spaced apart from each other, where each of the second ground lines 2122 of the plurality of second ground lines 2122 extends from the first ground line 2121 toward a direction away from the first ground line 2121, or a direction away from the first connection region 211. Different from the arrangement of the first grounding region 212 shown in fig. 5, in order to reduce the difficulty of arranging the first grounding region 212, the arrangement of the first grounding region 212 shown in fig. 6 may be adopted to balance the electrostatic discharge effect and the processing difficulty. The distance L between two adjacent second grounding lines 2122 in the plurality of second grounding lines 2122 included in the first grounding region 212 may be set according to practical applications. For example, if L is large, the wiring and processing are facilitated, and if L is small, the electrostatic discharge effect of the first ground region 212 can be improved.

It should be understood that the first ground region 212 of the embodiment of the present application is located at the edge of the substrate 21, and may include: at least a partial region of the first ground region 212 belongs to a side of the substrate 21. For example, as shown in fig. 5 and fig. 6, the upper and lower sides of the first grounding region 212, which are oppositely disposed, belong to the side of the substrate 21; the left and right sides of the first ground region 212 are close to the edge of the substrate 21, but there is still a partial region between the left and right sides of the first ground region 212 and the edge of the substrate 21, for example, the partial region may be used to dispose other components, but the embodiment of the present application is not limited thereto.

The fingerprint identification device according to the embodiment of the present application will be described in detail with reference to the accompanying drawings. Fig. 7 shows a schematic cross-sectional view of a fingerprint recognition device 20 according to an embodiment of the present application. The fingerprint identification device 20 of the embodiment of the present application can be applied to an electronic device, for example, the electronic device can be a mobile phone or a notebook computer; the type of the fingerprint recognition device 20 can be set according to the actual application, and the position of the fingerprint recognition device 20 in the electronic device can be set reasonably according to the type of the fingerprint recognition device 20. For example, for convenience of explanation, the fingerprint identification device 20 is exemplified as a capacitive fingerprint identification device 20.

The capacitive fingerprint recognition device 20 may be disposed at any position of the electronic device, for example, the fingerprint recognition device 20 may be disposed at a side of the electronic device. Taking an electronic device as an example of a mobile phone, in order to ensure that the size of the display area on the front side of the mobile phone is not affected and the display area is maximized, the fingerprint identification device 20 may be generally located on the side of the mobile phone or on the back side of the mobile phone, and the embodiment of the present application is not limited thereto.

As shown in fig. 7, the fingerprint sensing chip 22 of the embodiment of the present application is located above the substrate 21, and the fingerprint sensing chip 22 may be fixed on the upper surface of the substrate 21 by a connection structure 23. For example, the connection structure 23 may be a non-conductive adhesive, and the embodiment of the present application is not limited thereto.

Optionally, the fingerprint recognition device 20 may further include: and an encapsulation layer 24 disposed above the fingerprint sensing chip 22, wherein the encapsulation layer 24 is used for encapsulating the fingerprint sensing chip 22 and the substrate 21. Specifically, as shown in fig. 7, the encapsulation layer 24 may cover the upper surface of the fingerprint sensing chip 22, and the encapsulation layer 24 may also be used to cover at least a partial area of the upper surface of the substrate 21, so as to implement the encapsulation of the fingerprint sensing chip 22 and the substrate 21, which is not limited thereto in the embodiments of the present application. Alternatively, the material of the encapsulation layer 24 may be set according to the actual application, for example, the encapsulation layer may adopt EMC, or may adopt other materials.

Optionally, as shown in fig. 7, the fingerprint identification device 20 of the embodiment of the present application further includes: and a circuit board 25 disposed below the substrate 21, wherein the circuit board 25 can be electrically connected to the substrate 21 to receive a signal carrying fingerprint information transmitted through the substrate 21, so as to facilitate fingerprint identification.

Correspondingly, as shown in fig. 7, the substrate 21 further includes a second connection region 213 and a second ground region 214, the second connection region 213 is located in a central region of the substrate 21, the second ground region 214 surrounds the second connection region 213 and is located in an edge region of the substrate 21, and the circuit board 25 is electrically connected to the substrate 21 through the second connection region 213.

It should be understood that, similar to the arrangement manner of the first grounding area 212, the wiring manner and the distribution position of the second grounding area 214 of the embodiment of the present application can be arranged according to practical applications. Specifically, the second ground region 214 may be located at an edge region of one or more sides of the second connection region 213. For example, the second grounding region 214 may be disposed in a manner similar to the first grounding region 212 shown in fig. 5 or fig. 6, that is, the second grounding region 214 may surround the second connection region 213, so that the second grounding region 214 is disposed around the second connection region 213, and static electricity may be discharged through the surrounding second grounding region 214, thereby improving the effect of discharging static electricity and increasing the safety of the fingerprint identification device 20. Alternatively, unlike the arrangement of fig. 5 and 6, the second grounding section 214 may be located only in a partial edge region of the second connection region 213, for example, the second grounding section 214 is located on either side of the second connection region 213, or located in two opposite or intersecting side regions of the second connection region 213, so as to save space. For convenience of description, the embodiments of the present application mainly use the second grounding region 214 in an arrangement similar to that shown in fig. 5 and 6 as an example.

In addition, the second ground region 214 may be disposed in the same manner as or different from the first ground region 212, for example, the second ground region 214 may be disposed in the same manner as the first ground region 212 to improve the processing efficiency of the substrate 21, but the embodiment of the present invention is not limited thereto.

Optionally, as shown in fig. 7, the fingerprint identification device 20 of the embodiment of the present application further includes: a reinforcing plate 26, the reinforcing plate 26 being located below the circuit board 25, the reinforcing plate 26 being used to increase the strength of the fingerprint recognition device 20, or the reinforcing plate 26 being used to support a component located above the reinforcing plate 26.

As shown in fig. 7, when a finger performs fingerprint recognition, static electricity may be generated on the surface of the encapsulation layer 24, and the ESD path of the fingerprint recognition device 20 may include: a part of the generated static electricity can be transmitted to the first grounding region 212 and released by the first grounding region 212; there may also be a portion of static electricity passing through the circuit board 25 and/or the reinforcing plate 26 to reach the second grounding region 214, and the static electricity is discharged from the second grounding region 214, so as to effectively discharge all or most of the static electricity, and avoid breaking through a portion of the weak region of the fingerprint identification device 20, for example, avoiding breaking through the surface of the fingerprint identification device 20, and for example, avoiding breaking through the circuit board 25 of the fingerprint identification device 20, avoiding damage to the circuit board 25, and ensuring the safety of the fingerprint identification device 20.

In the embodiment of the present application, electrostatic discharge can be achieved through the first grounding area 212 disposed on the substrate 21, and it is not necessary to additionally dispose a grounding area for electrostatic discharge on the circuit board 25, for example, it is not necessary to dispose a windowing area on the circuit board 25, so that the space of the circuit board 25 can be saved, and the method is suitable for a scene with a strict requirement on the size of the circuit board 25, especially a scene with a small size of the circuit board 25, for example, the method can be applied to scenes such as a mobile phone side edge, and can meet the size requirement of the fingerprint identification device, and can also ensure the reliability and safety of the fingerprint identification device, and has a good antistatic performance.

The substrate 21 according to the embodiment of the present application will be described in detail with reference to the drawings. Fig. 8 shows a schematic cross-sectional view of the substrate 21 according to an embodiment of the present application, for example, the cross-section of the substrate 21 shown in fig. 8 may be the same as the cross-section of the substrate 21 shown in fig. 7. As shown in fig. 8, the substrate 21 is a multi-layer structure, the multi-layer structure includes a first routing layer 201, and the first connection region 211 and the first ground region 212 are located on the first routing layer 201, so as to implement routing distribution of the first connection region 211 and the first ground region 212.

Optionally, as shown in fig. 8, the first connection region 211 of the first wiring layer 201 may include a first signal region 2112, and the first signal region 2112 may be used for transmitting a fingerprint signal of the fingerprint sensor chip 22, for example, the first signal region 2112 may be used for receiving a fingerprint signal acquired by the fingerprint sensor chip 22, where the fingerprint signal carries fingerprint information for fingerprint identification.

In addition, the first routing layer 201 may also be provided with ink, and the ink covers at least a part of the first routing layer 201, for example, the ink may cover a part of the surface of the first signal area 2112 of the first routing layer 201, and may also cover a part of the surface of the first ground area 214, so as to protect the first routing layer 201.

Optionally, as shown in fig. 8, the multilayer structure may further include: the second wiring layer 202, the second connection region 213 and the second ground region 214 are disposed on the second wiring layer 202, so as to implement the routing distribution of the second connection region 213 and the second ground region 214.

Optionally, as shown in fig. 8, the second connection region 213 may include a second signal region 2132, the second signal region 2132 may be used for transmitting a fingerprint signal, for example, the second signal region 2132 may be used for receiving a fingerprint signal, for example, the fingerprint signal transmitted through the first signal region 2112 of the first routing layer 201 may be received, and the received fingerprint signal may be sent to the circuit board 25, the fingerprint signal carrying fingerprint information for fingerprint identification.

In addition, similar to the first routing layer 201, the second routing layer 202 may also be provided with ink, which covers at least part of the second routing layer 202, for example, the ink may cover part of the surface of the second signal area 2132 of the second routing layer 202, and may also cover part of the surface of the second ground area 214, so as to protect the second routing layer 202.

Optionally, as shown in fig. 8, a core 203 may be further included between the first routing layer 201 and the second routing layer 202, and the core 203 may have an effect of preventing the substrate 21 from warping and improving electrical performance. The material of the core material 203 may be selected according to the actual application.

It should be understood that the first connection region 211 of the first wiring layer 201 can be used to realize electrical connection with the fingerprint sensor chip 22, and the second connection region 213 of the second wiring layer 202 can be used to realize electrical connection with the circuit board 25, so that the first wiring layer 201 can be disposed closer to the fingerprint sensor chip 22, and the second wiring layer 202 can be disposed closer to the circuit board 25, i.e., the first wiring layer 201 is disposed above the second wiring layer 202, so as to shorten the connection path.

Further, in order to improve the processing efficiency, the first connection region 211 and the second connection region 213 of the embodiment of the present application may be disposed corresponding to each other, and the first ground region 212 may also be disposed corresponding to the second ground region 214. For example, as shown in fig. 8, the second connection region 213 corresponds to the first connection region 211 and is located below the first connection region 211; and/or the second ground region 214 corresponds to the first ground region 212 and is located below the first ground region 212.

In the embodiment, as shown in fig. 8, the first end face 2123 of the first ground region 212, which is far away from the first connection region 211, is located at the second end face 215 of the substrate 21, and the second end face 215 is a cut surface of the substrate 21. Specifically, the first end face 2123 may be a copper exposed region of the first ground region 212, so as to facilitate electrostatic discharge. The first ground region 212 may have at least one first end face 2123, for example, in fig. 8, the first ground region 212 has two left and right first end faces 2123, and both the first end faces 2123 may implement electrostatic discharge.

Similarly, as shown in fig. 8, the third end surface 2141 of the second ground region 214 far from the second connection region 213 may also be located on the second end surface 215 of the substrate 21, i.e., both the first end surface 2123 and the third end surface 2141 may be located on the cutting surface of the substrate 21. Moreover, the second ground region 214 may have at least one third end surface 2141, for example, in fig. 8, the second ground region 214 has two left and right third end surfaces 2141, and both the two third end surfaces 2141 may implement electrostatic discharge.

Fig. 9 shows a schematic diagram of the substrate 21 of the embodiment of the present application before cutting. As shown in fig. 9, the substrate 21 is exemplified to have two-sided scribe lines, which are a first scribe line 31 and a second scribe line 32, respectively. Before the substrate 21 is cut, the edge region of the substrate 21 is set as a ground region which extends outward and has a large area so that the first cutting lines 31 and the second cutting lines 32 are located in the ground region, respectively. When the substrate 21 is cut, the substrate 21 is cut along the first cut line 31 and the second cut line 32 respectively to obtain the substrate 21 shown in fig. 8, wherein the first end face 2123 of the first grounding region 212 and the third end face 2141 of the second grounding region 214 of the substrate 21 are a part of the cut surface of the substrate 21 to expose the first end face 2123 and the third end face 2141, so that the first end face 2123 of the first grounding region 212 and the third end face 2141 of the second grounding region 214 achieve the effect of copper exposure, and further static electricity can be released.

It should be understood that as shown in fig. 8 and 9, the substrate 21 of the embodiment of the present application may be a multi-layer structure, which may include a plurality of routing layers, which may include at least one first routing layer 201 and/or at least one second routing layer 202 of the embodiment of the present application. Specifically, when the base 21 of the embodiment of the present application is a multilayer structure, the multilayer structure may include a plurality of routing layers, and each routing layer of the plurality of routing layers may be provided with a grounding area for electrostatic discharge. For example, the plurality of routing layers may include one or more first routing layers 201, the one or more first routing layers 201 being electrically connected to the fingerprint sensing chip 22 either directly or indirectly through other structures; as another example, the plurality of routing layers may also include a first or second routing layer 202, where the first or second routing layer 202 is electrically connected to the circuit board 25 directly or indirectly through other structures. Moreover, since the plurality of routing layers can be electrically connected to each other, the plurality of routing layers can be regarded as including a plurality of routing layers electrically connected to the fingerprint sensor chip 22 and the circuit board 25 at the same time, that is, the plurality of routing layers can be regarded as the first routing layer 201 and the second routing layer 202, which is not limited to this embodiment of the present application.

Fig. 10 and fig. 11 respectively show schematic top views of the first routing layer 201 of the substrate 21 according to the embodiment of the present application before cutting, for example, the first routing layer 201 shown in fig. 10 and fig. 11 may be a schematic top view of the first routing layer 201 shown in fig. 9, where fig. 10 and fig. 11 respectively show two possible arrangement manners of the first ground region 212. Fig. 12 and 13 respectively show schematic top views of the second routing layer 202 of the substrate 21 according to the embodiment of the present application before cutting, for example, the second routing layer 202 shown in fig. 12 and 13 may be a schematic top view of the second routing layer 202 shown in fig. 9, where fig. 12 and 13 respectively show two possible arrangement manners of the second ground region 214.

As shown in fig. 10 and 11, the first ground region 212 of the embodiment of the present application is disposed around the first connection region 211. Optionally, the first connection region 211 includes a first pad 2111, and the fingerprint sensor chip 22 is electrically connected to the substrate 21 through the first pad 2111. In addition, the first connection region 211 may also include a first signal region 2112 for transmitting a fingerprint signal. It should be understood that, since the substrate 21 of the embodiment of the present application may include a plurality of first routing layers 201, the first connection region 211 of each first routing layer 201 of the plurality of first routing layers 201 may be electrically connected to the fingerprint sensing chip 22, for example, for any one first connection region 211, the first connection region 211 may be electrically connected to the fingerprint sensing chip 22 directly, or indirectly. In addition, for the first wiring layer 201 of the base 21 closest to the fingerprint sensor chip 22, the first wiring layer 201 may comprise first pads 2111, and the first wiring layer 201 is electrically connected to the fingerprint sensor chip 22 by soldering the first pads 2111 to the fingerprint sensor chip 22.

Similar to the first wiring layer 201 structure, as shown in fig. 12 and 13, the second ground region 214 of the embodiment of the present application is disposed around the second connection region 213. Optionally, the second connection region 213 includes a second pad 2131, and the circuit board 25 is electrically connected to the substrate 21 through the second pad 2131. In addition, the second connection region 213 may also include a second signal region 2132 for transmitting a fingerprint signal. It should be understood that, since the substrate 21 of the embodiment of the present application may include a plurality of second routing layers 202, the second connection region 213 of each second routing layer 202 of the plurality of second routing layers 202 may be electrically connected to the circuit board 25. In addition, for the second routing layer 202 of the base 21 closest to the circuit board 25, the second routing layer 202 may include a second pad 2131, and the second routing layer 202 is electrically connected to the circuit board 25 by soldering between the second pad 2131 and the circuit board 25.

The wiring mode and the distribution position of the first grounding area 212 in the embodiment of the present application can be set according to practical applications. For example, as shown in fig. 10 and 11, in any of the above-described methods, the ground region of the first wiring layer 201 is provided in a large area before the dicing, and the third dicing line 33 of the first wiring layer 201 passes through the provided ground region. In this way, when the first wiring layer 201 of the substrate 21 is cut, the cut first wiring layer 201 of the substrate 21 as shown in fig. 8 can be obtained by cutting along the third cutting line 33, and the first end face 2123 of the first ground region 212 of the substrate 21 becomes a part of the cut surface of the substrate 21 so as to expose the first end face 2123, and can be used for discharging static electricity. After the first routing layer 201 shown in fig. 10 is cut, a first grounding area 212 shown in fig. 5 can be obtained; after the first routing layer 201 shown in fig. 11 is cut, a first grounding area 212 shown in fig. 6 can be obtained.

Similarly, the wiring manner and the distribution position of the second grounding area 214 in the embodiment of the present application can be set according to practical applications. For example, as shown in fig. 12 and 13, in any of the above-described methods, the ground area of the second wiring layer 202 is set to be large before the dicing, and the fourth dicing line 34 of the second wiring layer 202 passes through the set ground area. In this way, when the second wiring layer 202 of the substrate 21 is cut, the second wiring layer 202 of the substrate 21 after cutting is obtained by cutting along the fourth cutting line 34 as shown in fig. 8, and the third end surface 2141 of the second ground region 214 of the substrate 21 becomes a part of the cutting surface of the substrate 21 to expose the third end surface 2141, and can be used for discharging static electricity. After the second wiring layer 202 shown in fig. 12 is cut, the obtained second grounding area 214 is arranged in a manner similar to that of fig. 5; after the second wiring layer 202 shown in fig. 13 is cut, the second grounding area 214 is obtained in a manner similar to that of fig. 6.

It should be understood that the first wiring layer 201 of the embodiment of the present application may be individually cut by the third cutting line 33, and the second wiring layer 202 may be individually cut by the fourth cutting line 34; alternatively, the third cutting line 33 and the fourth cutting line 34 may be the same, that is, the cutting of the first routing layer 201 and the second routing layer 202 is simultaneously performed, so as to improve the processing efficiency of the substrate 21. Specifically, as shown in fig. 9 in conjunction with fig. 10 to 13, the third cutting line 33 may include a first cutting line 31 and a second cutting line 32 as shown in fig. 9, and the third cutting line 33 and the fourth cutting line 34 coincide with each other and are the same cutting line, so as to realize the synchronous cutting of the substrate 21 having the multilayer structure and improve the processing efficiency.

It should be understood that the arrangement of the wiring pattern and the distribution position of the first ground region 212 and the second ground region 214 may be the same or different. For example, if the first ground region 212 has the structure shown in fig. 10, the second ground region 214 may have the structure shown in fig. 12, or if the first ground region 212 has the structure shown in fig. 11, the second ground region 214 may have the structure shown in fig. 13, so that the distribution position of the second ground region 214 is consistent with the distribution position of the first ground region 212, which may facilitate the processing. For another example, if the first grounding region 212 has the structure shown in fig. 10, the second grounding region 214 may also have the structure shown in fig. 13, or if the first grounding region 212 has the structure shown in fig. 11, the second grounding region 214 may have the structure shown in fig. 12, so that the distribution position of the second grounding region 214 is different from the distribution position of the first grounding region 212, and thus the first grounding region 212 and the second grounding region 214 may be reasonably arranged according to the distribution of static electricity in the actual application of the fingerprint identification device 20, so as to improve the anti-static effect.

Therefore, the fingerprint identification device 20 of the embodiment of the present application includes the fingerprint sensing chip 22 and the substrate 21, and the first connection region 211 and the first ground region 212 are disposed on the substrate 21, wherein the first connection region 211 is located in the central region of the substrate 21 and can be used to electrically connect the substrate 21 and the fingerprint sensing chip 22; the first grounding area 212 is located around the first connection area 211 and at the edge area of the substrate 21, which does not affect the first connection area 211, and can achieve electrostatic discharge, ensure the anti-static capability of the fingerprint identification device 20, and also ensure the reliability and safety of the fingerprint identification device 20. In addition, the first grounding area 212 arranged on the substrate 21 is used for realizing electrostatic discharge, and a grounding area for discharging static electricity does not need to be additionally arranged on the circuit board 25, for example, a windowing area on the circuit board 25 does not need to be arranged, so that the space of the circuit board 25 can be saved, the method is suitable for scenes with strict requirements on the size of the circuit board 25, especially scenes with small size of the circuit board 25, for example, the method can be applied to scenes such as the side edge of a mobile phone, the size requirements of the fingerprint identification device can be met, the reliability and the safety of the fingerprint identification device can be ensured, and the method has good antistatic performance.

While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A fingerprint recognition device, comprising:

a fingerprint sensing chip;

the substrate is arranged below the fingerprint sensing chip and comprises a first connecting area and a first grounding area, the first connecting area is located in the central area of the substrate, the first grounding area is located around the first connecting area and located in the edge area of the substrate, and the fingerprint sensing chip is electrically connected with the substrate through the first connecting area.

2. The fingerprint recognition device of claim 1, wherein the substrate is a multi-layer structure, the multi-layer structure including a first routing layer, the first connection region and the first ground region being located on the first routing layer, the first connection region including a first pad, the fingerprint sensor chip being electrically connected to the substrate through the first pad.

3. The fingerprint recognition device of claim 1, wherein the substrate further comprises a second connection region located at a central region of the substrate and a second ground region located at a periphery of the second connection region and located at an edge region of the substrate,

the fingerprint identification device further comprises:

and the circuit board is arranged below the substrate and is electrically connected with the substrate through the second connecting area.

4. The fingerprint recognition device of claim 3, wherein the second connection area corresponds to and is located below the first connection area; and/or the presence of a gas in the gas,

the second grounding area corresponds to the first grounding area and is located below the first grounding area.

5. The fingerprint recognition device of claim 3 or 4, wherein the substrate is a multi-layered structure including a second routing layer, the second connection region and the second ground region are located on the second routing layer, the second connection region includes a second pad, and the circuit board is electrically connected to the substrate through the second pad.

6. The fingerprint recognition device according to claim 3 or 4, further comprising:

and the reinforcing plate is positioned below the circuit board.

7. The fingerprint identification device according to any one of claims 1 to 4, wherein a first end face of the first grounding area, which is far away from the first connection area, is located at a second end face of the substrate, which is a cut face of the substrate.

8. The fingerprint identification device of any one of claims 1 to 4, wherein the first grounding area surrounds the first connection area, the first grounding area being an annular copper-clad area.

9. The fingerprint recognition device of claim 8, wherein the first ground area includes a first ground line surrounding the first connection area, and a plurality of second ground lines connected to the first ground line and spaced apart from each other, each of the plurality of second ground lines extending from the first ground line in a direction away from the first ground line.

10. The fingerprint recognition device according to any one of claims 1 to 4, further comprising:

and the packaging layer is arranged above the fingerprint sensing chip and used for packaging the fingerprint sensing chip and the substrate.

11. The fingerprint recognition device according to any one of claims 1 to 4, wherein the fingerprint recognition device is a capacitive fingerprint recognition device.

12. An electronic device, comprising:

the fingerprint recognition device according to any one of claims 1 to 11, wherein said fingerprint recognition device is located at a side of said electronic device.

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