CN114861903A - Hardware circuit of time-lag coupling neuron model - Google Patents
Hardware circuit of time-lag coupling neuron model Download PDFInfo
- Publication number
- CN114861903A CN114861903A CN202210678835.7A CN202210678835A CN114861903A CN 114861903 A CN114861903 A CN 114861903A CN 202210678835 A CN202210678835 A CN 202210678835A CN 114861903 A CN114861903 A CN 114861903A
- Authority
- CN
- China
- Prior art keywords
- circuit
- input end
- output end
- integrator
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to a hardware circuit of a time-lag coupling neuron model, and belongs to the field of neuron circuits. The circuit comprises: a first neuron model circuit and a second neuron model circuit; the first neuron model circuit comprises a first neuron main circuit, a first time lag coupling circuit, a first calcium ion channel opening probability steady-state value calculation circuit, a first potassium ion channel opening probability steady-state value calculation circuit and a first activation time constant circuit; the second neuron model circuit comprises a second neuron main circuit, a second time lag coupling circuit, a second calcium ion channel opening probability steady-state value calculation circuit, a second potassium ion channel opening probability steady-state value calculation circuit and a second activation time constant circuit; the second input end of the first time lag coupling circuit is connected with the output end of the second neuron main circuit; and the second input end of the second time lag coupling circuit is connected with the output end of the first neuron main circuit. The invention enlarges the research range of the characteristics of the biological neural network.
Description
Technical Field
The invention relates to the field of neuron circuits, in particular to a hardware circuit of a time-lag coupling neuron model.
Background
In the human brain, hundreds of millions of neuronal cells are coupled to one another to form a complex biological neural network. Biological neural network characteristics are generally studied by building artificial neurons and neural network models. The study of a single neuron model has certain limitations on the study of the characteristics of the biological neural network, and the large-scale neural network model needs to occupy huge computing resources.
Many neurological disorders, such as parkinson's disease and epilepsy, are caused by abnormal synchronous discharges in certain brain regions. Therefore, the study on the synchronization of the coupled neurons is particularly important. However, the existing circuits related to the Morris-Lecar neuron model (ML neuron model) are mostly circuits of single neurons, and have limitation on the research of nervous system diseases.
Disclosure of Invention
The invention aims to provide a hardware circuit of a time-lag coupling neuron model, which aims to solve the problem that the research on the characteristics of a biological neural network by adopting a single neuron model circuit is limited in the prior art.
In order to achieve the purpose, the invention provides the following scheme:
a hardware circuit for a time-lag coupled neuron model, comprising: a first neuron model circuit and a second neuron model circuit;
the first neuron model circuit comprises a first neuron main circuit, a first time lag coupling circuit, a first calcium ion channel opening probability steady-state value calculation circuit, a first potassium ion channel opening probability steady-state value calculation circuit and a first activation time constant circuit;
the second neuron model circuit comprises a second neuron main circuit, a second time lag coupling circuit, a second calcium ion channel opening probability steady-state value calculation circuit, a second potassium ion channel opening probability steady-state value calculation circuit and a second activation time constant circuit;
the output end of the first neuron main circuit is respectively connected with the first input end of the first time lag coupling circuit, the input end of the first calcium ion channel opening probability steady-state value calculation circuit, the input end of the first potassium ion channel opening probability steady-state value calculation circuit and the input end of the first activation time constant circuit; the output end of the first time lag coupling circuit, the output end of the first calcium ion channel opening probability steady-state value calculation circuit, the output end of the first potassium ion channel opening probability steady-state value calculation circuit and the output end of the first activation time constant circuit are connected with the input end of the first neuron main circuit;
the output end of the second neuron main circuit is respectively connected with the first input end of the second time lag coupling circuit, the input end of the second calcium ion channel opening probability steady-state value calculation circuit, the input end of the second potassium ion channel opening probability steady-state value calculation circuit and the input end of the second activation time constant circuit; the output end of the second time lag coupling circuit, the output end of the steady-state value calculation circuit of the second calcium ion channel opening probability, the output end of the steady-state value calculation circuit of the second potassium ion channel opening probability and the output end of the second activation time constant circuit are connected with the input end of the second neuron main circuit;
the second input end of the first time lag coupling circuit is connected with the output end of the second neuron main circuit; and a second input end of the second time lag coupling circuit is connected with an output end of the first neuron main circuit.
Optionally, the first neuron main circuit includes a first integrator, a second integrator, a third integrator, a first multiplier, a second multiplier, a third multiplier, a first inverting adder, a second inverting adder, a third inverting adder, a fourth inverting adder, and a first inverter;
the output end of the steady-state value calculation circuit of the first calcium ion channel opening probability is connected with the first input end of the first multiplier; the output end of the first inverting adder is connected with the second input end of the first multiplier; the output end of the first multiplier is connected with the first input end of the first integrator; the output end of the steady-state value calculation circuit of the opening probability of the first potassium ion channel is connected with the first input end of the fourth inverse adder; the output end of the fourth inverting adder is connected with the first input end of the third multiplier; the output end of the first activation time constant circuit is connected with the second input end of the third multiplier; the output end of the third multiplier is connected with the input end of the third integrator; the output end of the third integrator is connected with the first input end of the second multiplier; the output end of the second inverting adder is connected with the input end of the first inverter; the output end of the first inverter is connected with the second input end of the second multiplier; the output end of the second multiplier is connected with the second input end of the first integrator; the output end of the first time lag coupling circuit is connected with the third input end of the first integrator; the output end of the third inverting adder is connected with the input end of the second integrator; the output end of the second integrator is connected with the fourth input end of the first integrator; the output end of the first integrator is respectively connected with the input end of the first inverse adder, the input end of the second inverse adder, the input end of the third inverse adder, the first input end of the first time lag coupling circuit, the input end of the first calcium ion channel opening probability steady-state value calculating circuit, the input end of the first potassium ion channel opening probability steady-state value calculating circuit and the input end of the first activation time constant circuit.
Optionally, the second neuron main circuit includes a fourth integrator, a fifth integrator, a sixth integrator, a fourth multiplier, a fifth multiplier, a sixth multiplier, a fifth inverting adder, a sixth inverting adder, a seventh inverting adder, an eighth inverting adder, and a second inverter;
the output end of the steady-state value calculation circuit of the opening probability of the second calcium ion channel is connected with the first input end of the fourth multiplier; the output end of the fifth inverting adder is connected with the second input end of the fourth multiplier; the output end of the fourth multiplier is connected with the first input end of the fourth integrator; the output end of the steady-state value calculation circuit of the opening probability of the second potassium ion channel is connected with the first input end of the eighth inverting adder; an output end of the eighth inverting adder is connected with a first input end of the sixth multiplier; an output terminal of the second active time constant circuit is connected to a second input terminal of the sixth multiplier; the output end of the sixth multiplier is connected with the input end of the sixth integrator; the output end of the sixth integrator is connected with the first input end of the fifth multiplier; the output end of the sixth inverting adder is connected with the input end of the second inverter; the output end of the second inverter is connected with the second input end of the fifth multiplier; the output end of the fifth multiplier is connected with the second input end of the fourth integrator; the output end of the second time lag coupling circuit is connected with the third input end of the fourth integrator; the output end of the seventh inverting adder is connected with the input end of the fifth integrator; the output end of the fifth integrator is connected with the fourth input end of the fourth integrator; the output end of the fourth integrator is respectively connected with the input end of the fifth inverse adder, the input end of the sixth inverse adder, the input end of the seventh inverse adder, the first input end of the second time lag coupling circuit, the input end of the second calcium ion channel opening probability steady-state value calculating circuit, the input end of the second potassium ion channel opening probability steady-state value calculating circuit, and the input end of the second activation time constant circuit.
Optionally, the first skew coupling circuit includes a first skew circuit and a first subtractor;
the output end of the first time delay circuit is connected with the second input end of the first subtracter; the first input end of the first subtracter is connected with the output end of the first integrator; the output end of the first subtracter is connected with the third input end of the first integrator; and the input end of the first time delay circuit is connected with the output end of the fourth integrator.
Optionally, the steady-state value calculating circuit of the first calcium ion channel opening probability includes a third subtractor, a first hyperbolic tangent operation circuit, and a ninth inverse adder, which are connected in sequence;
the input end of the third subtracter is connected with the output end of the first integrator; an output terminal of the ninth inverting adder is connected to a first input terminal of the first multiplier.
Optionally, the steady-state value calculating circuit of the first potassium ion channel opening probability includes a fourth subtractor, a second hyperbolic tangent operation circuit, and a tenth inverse adder, which are connected in sequence;
the input end of the fourth subtracter is connected with the output end of the first integrator; an output terminal of the tenth inverting adder is connected to a first input terminal of the fourth inverting adder.
Optionally, the first activation time constant circuit includes a fifth subtractor, an eleventh inverting adder, a third inverter, a first exponential operation circuit, and a second exponential operation circuit;
the input end of the fifth subtracter is connected with the output end of the first integrator; a first output end of the fifth subtracter is connected with an input end of the first exponential operation circuit; a second output end of the fifth subtractor is connected with an input end of the third inverter; the output end of the first exponential operation circuit is connected with the first input end of the eleventh inverting adder; the output end of the third inverter is connected with the input end of the second index arithmetic circuit; the output end of the second exponential operation circuit is connected with the second input end of the eleventh inverting adder; an output terminal of the eleventh inverting adder is connected to a second input terminal of the third multiplier.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the membrane potentials of the two neurons are coupled through the time-lag coupling circuit, so that the neuron model circuit can show richer dynamic characteristics, various discharge behaviors of the time-lag coupling ML neuron model can be accurately reflected, the range of researching the characteristics of the biological neural network by adopting the neuron model circuit is expanded, and a good support is provided for researching the synchronous action mechanism and the transition process of the coupling neurons.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a block diagram of a hardware circuit of a time-lag coupled neuron model according to the present invention;
FIG. 2 is a block diagram of an embodiment of a hardware circuit of a time-lag coupled neuron model according to the present invention;
FIG. 3 is a schematic diagram of the main circuit of a first neuron according to the present invention;
FIG. 4 is a schematic diagram of a first time lag coupling circuit according to the present invention;
FIG. 5 is a schematic diagram of a steady state value calculation circuit for the first calcium channel opening probability according to the present invention;
FIG. 6 is a schematic diagram of a steady state value calculation circuit of the first potassium channel opening probability according to the present invention;
FIG. 7 is a schematic diagram of a first activation time constant circuit of the present invention;
FIG. 8 is a schematic diagram of the second neuron main circuit of the present invention;
FIG. 9 is a schematic diagram of a steady state value calculating circuit of the second calcium ion channel opening probability according to the present invention;
FIG. 10 is a schematic diagram of a steady-state value calculation circuit of the second potassium channel opening probability according to the present invention;
FIG. 11 is a schematic diagram of a second activation time constant circuit of the present invention;
FIG. 12 is a schematic diagram of a second skew coupling circuit according to the present invention;
FIG. 13 shows the equation R in the present invention 77 ＝R 159 ＝1kΩ，R 81 ＝R 82 ＝R 163 ＝R 164 When the k omega is 100k omega, the implementation result of the hardware circuit of the time-lag coupling neuron model is shown in a schematic diagram;
FIG. 14 shows the equation R in the present invention 77 ＝R 159 ＝1kΩ，R 81 ＝R 82 ＝R 163 ＝R 164 When the time lag coupling neuron model is 75k Ω, the implementation result of a hardware circuit of the time lag coupling neuron model is shown in a schematic diagram;
FIG. 15 shows the equation R in the present invention 77 ＝R 159 ＝1kΩ，R 81 ＝R 82 ＝R 163 ＝R 164 When the k is 10k omega, the implementation result of the hardware circuit of the time-lag coupling neuron model is shown in a schematic diagram;
FIG. 16 shows the equation R in the present invention 81 ＝R 82 ＝R 163 ＝R 164 ＝100kΩ，R 77 ＝R 159 When the number is 500 Ω, the implementation result of the hardware circuit of the time-lag coupling neuron model is shown schematically;
FIG. 17 shows the equation R in the present invention 81 ＝R 82 ＝R 163 ＝R 164 ＝100kΩ，R 77 ＝R 159 When the time lag coupling neuron model is 2k omega, the implementation result of a hardware circuit of the time lag coupling neuron model is shown in a schematic diagram;
FIG. 18 shows the equation R in the present invention 81 ＝R 82 ＝R 163 ＝R 164 ＝100kΩ，R 77 ＝R 159 When the k Ω is 5, the hardware circuit of the time-lag coupling neuron model is implemented to obtain a schematic diagram.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a hardware circuit of a time-lag coupling neuron model, which aims to solve the problem that the research on the characteristics of a biological neural network by adopting a single neuron model circuit is limited in the prior art.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a structural diagram of a hardware circuit of a time-lag coupled neuron model provided by the present invention, and as shown in fig. 1, the hardware circuit of the time-lag coupled neuron model includes: a first neuron model circuit and a second neuron model circuit. In practical applications, a neural system with two coupled neurons can show more complex and abundant motion patterns than a single neuron, and can reflect partial characteristics of a neural network.
The synaptic cleft of a neuron causes a certain delay in information transmission, which is called time lag. The coupled neuron system affected by the time lag presents richer nonlinear dynamics phenomena, the action mechanism and the transition process of synchronous formation of the coupled neuron system are researched, and an idea can be provided for the research of neuroscience. The hardware circuit of the time-lag coupling neuron model has richer dynamic characteristics and can reflect the action mechanism and the transition process of forming synchronization.
The first neuron model circuit comprises a first neuron main circuit, a first time lag coupling circuit, a first calcium ion channel opening probability steady-state value calculation circuit, a first potassium ion channel opening probability steady-state value calculation circuit and a first activation time constant circuit.
The second neuron model circuit comprises a second neuron main circuit, a second time lag coupling circuit, a steady-state value calculation circuit of a second calcium ion channel opening probability, a steady-state value calculation circuit of a second potassium ion channel opening probability and a second activation time constant circuit.
The output end of the first neuron main circuit is respectively connected with the first input end of the first time lag coupling circuit, the input end of the first calcium ion channel opening probability steady-state value calculation circuit, the input end of the first potassium ion channel opening probability steady-state value calculation circuit and the input end of the first activation time constant circuit; the output end of the first time lag coupling circuit, the output end of the first calcium ion channel opening probability steady-state value calculating circuit, the output end of the first potassium ion channel opening probability steady-state value calculating circuit and the output end of the first activation time constant circuit are connected with the input end of the first neuron main circuit.
The output end of the second neuron main circuit is respectively connected with the first input end of the second time lag coupling circuit, the input end of the second calcium ion channel opening probability steady-state value calculation circuit, the input end of the second potassium ion channel opening probability steady-state value calculation circuit and the input end of the second activation time constant circuit; the output end of the second time lag coupling circuit, the output end of the steady-state value calculation circuit of the second calcium ion channel opening probability, the output end of the steady-state value calculation circuit of the second potassium ion channel opening probability and the output end of the second activation time constant circuit are connected with the input end of the second neuron main circuit.
The second input end of the first time lag coupling circuit is connected with the output end of the second neuron main circuit; and a second input end of the second time lag coupling circuit is connected with an output end of the first neuron main circuit.
FIG. 2 is a block diagram of an embodiment of a hardware circuit of a time-lag coupled neuron model according to the present invention; as shown in fig. 2, the hardware circuit of the time-lag coupled neuron model involves amplification, integration, squaring, and multiplication of signals, and these operations can be conveniently implemented by electronic components such as an operational amplifier and an analog multiplier, and the whole equivalent circuit is driven by a ± 18V dc power supply.
The first neuron main circuit comprises a first integrator, a second integrator, a third integrator, a first multiplier, a second multiplier, a third multiplier, a first inverting adder, a second inverting adder, a third inverting adder, a fourth inverting adder and a first inverter.
The output end of the steady-state value calculation circuit of the first calcium ion channel opening probability is connected with the first input end of the first multiplier; the output end of the first inverting adder is connected with the second input end of the first multiplier; the output end of the first multiplier is connected with the first input end of the first integrator; the output end of the steady-state value calculation circuit of the opening probability of the first potassium ion channel is connected with the first input end of the fourth inverse adder; the output end of the fourth inverting adder is connected with the first input end of the third multiplier; the output end of the first activation time constant circuit is connected with the second input end of the third multiplier; the output end of the third multiplier is connected with the input end of the third integrator; the output end of the third integrator is connected with the first input end of the second multiplier; the output end of the second inverting adder is connected with the input end of the first inverter; the output end of the first inverter is connected with the second input end of the second multiplier; the output end of the second multiplier is connected with the second input end of the first integrator; the output end of the first time lag coupling circuit is connected with the third input end of the first integrator; the output end of the third inverting adder is connected with the input end of the second integrator; the output end of the second integrator is connected with the fourth input end of the first integrator; the output end of the first integrator is respectively connected with the input end of the first inverse adder, the input end of the second inverse adder, the input end of the third inverse adder, the first input end of the first time lag coupling circuit, the input end of the first calcium ion channel opening probability steady-state value calculating circuit, the input end of the first potassium ion channel opening probability steady-state value calculating circuit and the input end of the first activation time constant circuit.
In practical application, the time scale factor k ═ R is selected 14 C 1 10000, k T is 10000T, and the equation of the system after time scale transformation is:
wherein, V 1,2 Representing the membrane potential between the first neuron and the second neuron, V 2,1 Representing the membrane potential between the second neuron and the first neuron, w 1,2 Representing a recovery variable, u, between a first neuron and a second neuron 1,2 Indicating that the first neuron and the second neuron regulate V 1,2 And w 1,2 Is determined. t is a time variable, τ 1,2 Denotes the time lag between a first neuron and a second neuron, λ (V) is the activation time constant, λ 1,2 (V 1,2 ) Is the activation time constant, w, between the first neuron and the second neuron ∞ Steady state value, w, representing the probability of opening of potassium ion channels ∞1,2 Steady state value, m, representing the probability of opening of potassium channel between first neuron and second neuron ∞ Steady state value, v, representing the probability of opening of calcium ion channels 1 ，v 2 ，v 3 ，v 4 Is a steady state parameter, g k 、g ca And g l Each represents K + Maximum conductance, Na + Maximum conductance and leakage current maximum conductance, v k 、v ca And v l Respectively, represent the corresponding inversion voltages. μ represents a time scale factor and is to maintain slow degeneration of the system. D represents the electric coupling strength. The system parameters are: g l ＝0.5，g k ＝2.0，g ca ＝1.0，v l ＝-0.5，v k ＝-1，v ca ＝1.0，v 1 ＝-0.01，v 2 ＝0.15，v 3 ＝0.1，v 4 ＝0.05，μ＝0.005。
In practical applications, a schematic diagram of the first neuron main circuit is shown in fig. 3, and the main equation of the first neuron main circuit is as follows:
wherein M00_1 represents an output value of the steady-state value calculation circuit for the first calcium ion channel opening probability, W00_1 represents an output value of the steady-state value calculation circuit for the first potassium ion channel opening probability, TW1 represents an output value of the first active time constant circuit, VT1 represents an output value of the first time lag coupling circuit, V 1 Is the membrane potential of the first ML neuron, V 2 For the membrane potential of the second ML neuron, W1 represents the recovery variable of the first neuron, W2 represents the recovery variable of the second neuron, and I1 represents the modulation of V by the first neuron 1 And a slow variable of W1, I2 indicates that a second neuron modulates V 2 And a slow variable of W2. Resistance R 9 ＝R 10 ＝20kΩ，R 11 ＝R 19 ＝1kΩ，R 12 ＝500Ω，R 13 ＝100kΩ，R 24 ＝2kΩ，R 1 ＝R 2 ＝R 3 ＝R 4 ＝R 5 ＝R 6 ＝R 7 ＝R 8 ＝R 14 ＝R 15 ＝R 16 ＝R 17 ＝R 18 ＝R 20 ＝R 21 ＝R 22 ＝ R23 ＝R 25 ＝R 26 10k omega, capacitance C 1 ＝C 2 ＝10nF，C 3 10 muF, voltage source V L1 ＝-0.5V，V K1 ＝-1V，V CA1 ＝1V，V 01 When the voltage is 0.2V, an AD633 multiplier with multiplication gain of 0.1 is adopted, and the model of the operational amplifier is LM 324.
Further, the first time lag coupling circuit includes a first time lag circuit and a first subtractor.
The output end of the first time delay circuit is connected with the second input end of the first subtracter; the first input end of the first subtracter is connected with the output end of the first integrator; the output end of the first subtracter is connected with the third input end of the first integrator; and the input end of the first time delay circuit is connected with the output end of the fourth integrator. In practical applications, a schematic diagram of the first time lag coupling circuit is shown in fig. 4.
The equation for the first time-lag coupled circuit is as follows:
in FIG. 4, operational amplifier U7A and resistor R 76 、R 77 、R 78 And a capacitor C 4 And an input V 2 Form a time-lag circuit, U C Is a capacitor C 4 The voltage at two ends and the time lag parameter tau of the circuit can pass through the resistor R 77 And a capacitor C 4 Is 2R 77 C 4 To change; operational amplifier U7B and resistor R 79 、R 80 、R 81 、R 82 And input V 1 A subtractor (first subtractor) is constructed.
Resistance R 79 ＝R 80 ＝100kΩ，R 76 ＝R 78 ＝10kΩ，C 4 The op amps U7A, U7B are model LM324 at 10 nF.
Further, the steady-state value calculation circuit of the first calcium ion channel opening probability includes a third subtractor, a first hyperbolic tangent operation circuit, and a ninth inverse adder, which are connected in sequence. The input end of the third subtracter is connected with the output end of the first integrator; an output terminal of the ninth inverting adder is connected to a first input terminal of the first multiplier. In practical applications, a schematic diagram of a circuit for calculating the steady-state value of the opening probability of the first calcium ion channel is shown in fig. 5.
The equation of the steady-state value calculation circuit for the first calcium ion channel opening probability is as follows:
VEE is a negative voltage of 18V, V BE Is the base-emitter voltage of bipolar transistor Q3, about 0.646V, U T Is transistor thermal voltage, U at normal temperature T Is 26 mV.
In FIG. 5, operational amplifier U3A and resistor R 27 、R 28 、R 29 、R 30 And an input V 1 And a voltage source V 01_1 Constitute a subtracter (third subtracter), a bipolar transistor Q3 and a resistor R 33 、R 34 、R 35 A current source circuit formed with the DC power supply VEE, bipolar transistors Q1, Q2, a DC power supply VCC and a resistor R 31 、R 32 An operational amplifier U3B and a resistor R 36 、R 37 、R 38 、R 39 Form a subtracter, an operational amplifier U3C and a resistor R 40 、R 41 、R 42 And a voltage source V 3 An inverting adder is formed.
The output voltage of the hyperbolic tangent operation circuit is as follows:
V in is the input voltage, VEE is a negative voltage of 18V, V BE Is the base-emitter voltage, U, of a bipolar transistor Q3 T Is transistor thermal voltage, U at normal temperature T Is 26 mV.
Resistance R 27 ＝R 28 ＝150kΩ，R 29 ＝R 30 ＝52kΩ，R 31 ＝R 32 ＝1kΩ，R 33 ＝11.7kΩ，R 34 ＝6.2kΩ，R 35 ＝R 36 ＝R 37 ＝R 38 ＝R 39 ＝R 40 ＝R 41 ＝R 42 ＝10kΩ，Voltage source V 01_1 ＝-10mV，V 3 The bipolar transistors Q1, Q2 and Q3 are NPN transistors Q2N3904, and the operational amplifiers U3A, U3B and U3C are LM324, 500 mV.
Further, the steady state value calculation circuit of the first potassium ion channel opening probability includes a fourth subtractor, a second hyperbolic tangent operation circuit, and a tenth inverse adder, which are connected in sequence. The input end of the fourth subtracter is connected with the output end of the first integrator; an output terminal of the tenth inverting adder is connected to a first input terminal of the fourth inverting adder. In practical applications, a schematic diagram of a circuit for calculating the steady-state value of the opening probability of the first potassium ion channel is shown in fig. 6.
The equation of the steady-state value calculation circuit of the first potassium ion channel opening probability is as follows:
in FIG. 6, operational amplifier U4A and resistor R 43 、R 44 、R 45 、R 46 And an input V 1 And a voltage source V 03_1 Constitute a subtracter (fourth subtracter), a bipolar transistor Q6 and a resistor R 49 、R 50 、R 51 A current source circuit formed with the DC power supply VEE, bipolar transistors Q4, Q5, a DC power supply VCC and a resistor R 47 、R 48 An operational amplifier U4B and a resistor R 52 、R 53 、R 54 、R 55 Form a subtracter, an operational amplifier U4C and a resistor R 56 、R 57 、R 58 And a voltage source V 4 An inverting adder is formed.
Resistance R 43 ＝R 44 ＝50kΩ，R 45 ＝R 46 ＝52kΩ，R 47 ＝R 48 ＝1kΩ，R 49 ＝11.7kΩ，R51＝6.2kΩ，R 50 ＝R 52 ＝R 53 ＝R 54 ＝R 55 ＝R 56 ＝R 57 ＝R 58 10k omega, voltage source V 03_1 ＝100mV，V 4 The bipolar transistors Q4, Q5 and Q6 are NPN transistors Q2N3904, and the operational amplifiers U4A, U4B and U4C are LM324, 500 mV.
Further, the first activation time constant circuit includes a fifth subtractor, an eleventh inverting adder, a third inverter, a first exponential operation circuit, and a second exponential operation circuit. The input end of the fifth subtracter is connected with the output end of the first integrator; a first output end of the fifth subtracter is connected with an input end of the first exponential operation circuit; a second output end of the fifth subtractor is connected with an input end of the third inverter; the output end of the first exponential operation circuit is connected with the first input end of the eleventh inverting adder; the output end of the third inverter is connected with the input end of the second index arithmetic circuit; the output end of the second exponential operation circuit is connected with the second input end of the eleventh inverting adder; an output terminal of the eleventh inverting adder is connected to a second input terminal of the third multiplier. In practical applications, a schematic diagram of the first activation time constant circuit is shown in fig. 7.
The equation for the λ (V) circuit is as follows:
in FIG. 7, operational amplifier U5A and resistor R 59 、R 60 、R 61 、R 62 And an input V 1 And a voltage source V 03_2 A subtracter (fifth subtracter) is formed, operational amplifiers U5B and U5C, bipolar transistors Q7 and Q8, and a resistor R 63 、R 64 、R 65 And a voltage source V 5 An exponential operational circuit, an operational amplifier U6A and a resistor R are formed 66 、R 67 An inverting amplifier is formed, operational amplifiers U6B, U6C, bipolar transistors Q9, Q10 and a resistor R 68 、R 69 、R 70 And a voltage source V 6 Form an exponential operation circuit, operational amplificationDevice U5D and resistor R 71 、R 72 、R 73 Form an inverting adder, an operational amplifier U6D and a resistor R 74 、R 75 An inverting amplifier is constructed.
The output voltage of the exponential operation circuit is:
resistance R 59 ＝R 60 ＝100kΩ，R 61 ＝R 62 ＝26kΩ，R 71 ＝R 72 ＝60kΩ，R 73 ＝ 20 kΩ，R 63 ＝R 64 ＝R 65 ＝R 66 ＝R 67 ＝R 68 ＝R 69 ＝R 70 ＝R 74 ＝R 75 10k omega, voltage source V 5 ＝V 6 ＝500mV，V 03_2 The bipolar transistors Q7, Q8, Q9 and Q10 are NPN transistors Q2N3904, and the operational amplifiers U5A, U5B, U5C, U5D, U6A, U6B, U6C and U6D are LM324, which is 100 mV.
The second neuron main circuit comprises a fourth integrator, a fifth integrator, a sixth integrator, a fourth multiplier, a fifth multiplier, a sixth multiplier, a fifth inverting adder, a sixth inverting adder, a seventh inverting adder, an eighth inverting adder and a second inverter.
The output end of the steady-state value calculation circuit of the opening probability of the second calcium ion channel is connected with the first input end of the fourth multiplier; the output end of the fifth inverting adder is connected with the second input end of the fourth multiplier; the output end of the fourth multiplier is connected with the first input end of the fourth integrator; the output end of the steady-state value calculation circuit of the opening probability of the second potassium ion channel is connected with the first input end of the eighth inverse adder; an output end of the eighth inverting adder is connected with a first input end of the sixth multiplier; an output terminal of the second active time constant circuit is connected to a second input terminal of the sixth multiplier; the output end of the sixth multiplier is connected with the input end of the sixth integrator; the output end of the sixth integrator is connected with the first input end of the fifth multiplier; the output end of the sixth inverting adder is connected with the input end of the second inverter; the output end of the second inverter is connected with the second input end of the fifth multiplier; the output end of the fifth multiplier is connected with the second input end of the fourth integrator; the output end of the second time lag coupling circuit is connected with the third input end of the fourth integrator; the output end of the seventh inverting adder is connected with the input end of the fifth integrator; the output end of the fifth integrator is connected with the fourth input end of the fourth integrator; the output end of the fourth integrator is respectively connected with the input end of the fifth inverse adder, the input end of the sixth inverse adder, the input end of the seventh inverse adder, the first input end of the second time lag coupling circuit, the input end of the second calcium ion channel opening probability steady-state value calculating circuit, the input end of the second potassium ion channel opening probability steady-state value calculating circuit, and the input end of the second activation time constant circuit. In practical application, a schematic diagram of the second neuron main circuit is shown in fig. 8.
The structure of the second neuron model circuit is the same as that of the first neuron model circuit, and the specific circuit schematic diagram of the second neuron model circuit is shown in fig. 8-12, which is not described herein again.
When R is 77 ＝R 159 1k Ω, i.e.. tau 1，2 At 0.2, FIGS. 13-15 show the results of the implementation of the time-lag coupled ML neuron circuit, and it can be seen that by varying R 81 、R 82 、R 163 And R 164 Coupled strength D, the time-lag coupled ML neuron circuit can exhibit synchronous, near-synchronous, and asynchronous firing behavior. FIG. 13 is R 81 ＝R 82 ＝R 163 ＝R 164 Membrane potential V of two neurons at 100k Ω, i.e. D1.0 1 And V 2 When the two neurons are in a synchronous state; FIG. 14 is R 81 ＝R 82 ＝R 163 ＝R 164 75k Ω, i.e.Membrane potential V of two neurons when D is 0.75 1 And V 2 When the two neurons are approximately synchronized; FIG. 15 is R 81 ＝R 82 ＝R 163 ＝R 164 Membrane potential V of two neurons at 10k Ω, i.e. D0.1 1 And V 2 When the two neurons are not synchronized.
When R is 81 ＝R 82＝ R 163 ＝R 164 Fig. 16-18 achieve the results for time-lag coupled ML neuron circuits when D is 1.0, which is 100k Ω, and it can be seen that by varying R 77 And R 159 Resistance of, i.e. hysteresis τ 1，2 The time-lag coupled ML neuron circuit is capable of exhibiting synchronous, near-synchronous, and asynchronous firing behavior. FIG. 16 is R 77 ＝R 159 500 Ω, i.e. τ 1，2 Membrane potential V of two neurons at 0.1 1 And V 2 When the two neurons are in a synchronous state; FIG. 17 is R 77 ＝R 159 2k Ω, i.e. τ 1，2 Membrane potential V of two neurons at 0.4 1 And V 2 When the two neurons are approximately synchronized; FIG. 18 is R 77 ＝R 159 5k Ω, i.e.. tau 1，2 Membrane potential V of two neurons at 1.0 1 And V 2 When the two neurons are not synchronized.
The invention provides a circuit for simulating and realizing a time-lag coupling ML neuron model, which can accurately reflect various discharge behaviors of the time-lag coupling ML neuron model, provide good support for researching the synchronous action mechanism and the transition process of the coupling neurons, and provide an idea for ML neuron network hardware integrated on a large scale.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (7)
1. A hardware circuit for a time-lag coupled neuron model, comprising: a first neuron model circuit and a second neuron model circuit;
the first neuron model circuit comprises a first neuron main circuit, a first time lag coupling circuit, a first calcium ion channel opening probability steady-state value calculation circuit, a first potassium ion channel opening probability steady-state value calculation circuit and a first activation time constant circuit;
the second neuron model circuit comprises a second neuron main circuit, a second time lag coupling circuit, a second calcium ion channel opening probability steady-state value calculation circuit, a second potassium ion channel opening probability steady-state value calculation circuit and a second activation time constant circuit;
the output end of the first neuron main circuit is respectively connected with the first input end of the first time lag coupling circuit, the input end of the first calcium ion channel opening probability steady-state value calculation circuit, the input end of the first potassium ion channel opening probability steady-state value calculation circuit and the input end of the first activation time constant circuit; the output end of the first time lag coupling circuit, the output end of the first calcium ion channel opening probability steady-state value calculation circuit, the output end of the first potassium ion channel opening probability steady-state value calculation circuit and the output end of the first activation time constant circuit are connected with the input end of the first neuron main circuit;
the output end of the second neuron main circuit is respectively connected with the first input end of the second time lag coupling circuit, the input end of the second calcium ion channel opening probability steady-state value calculation circuit, the input end of the second potassium ion channel opening probability steady-state value calculation circuit and the input end of the second activation time constant circuit; the output end of the second time lag coupling circuit, the output end of the steady-state value calculation circuit of the second calcium ion channel opening probability, the output end of the steady-state value calculation circuit of the second potassium ion channel opening probability and the output end of the second activation time constant circuit are connected with the input end of the second neuron main circuit;
the second input end of the first time lag coupling circuit is connected with the output end of the second neuron main circuit; and a second input end of the second time lag coupling circuit is connected with an output end of the first neuron main circuit.
2. The hardware circuit of a time-lag coupled neuron model of claim 1, wherein the first neuron main circuit comprises a first integrator, a second integrator, a third integrator, a first multiplier, a second multiplier, a third multiplier, a first inverting adder, a second inverting adder, a third inverting adder, a fourth inverting adder, and a first inverter;
the output end of the steady-state value calculation circuit of the first calcium ion channel opening probability is connected with the first input end of the first multiplier; the output end of the first inverting adder is connected with the second input end of the first multiplier; the output end of the first multiplier is connected with the first input end of the first integrator; the output end of the steady-state value calculation circuit of the opening probability of the first potassium ion channel is connected with the first input end of the fourth inverse adder; the output end of the fourth inverting adder is connected with the first input end of the third multiplier; the output end of the first activation time constant circuit is connected with the second input end of the third multiplier; the output end of the third multiplier is connected with the input end of the third integrator; the output end of the third integrator is connected with the first input end of the second multiplier; the output end of the second inverting adder is connected with the input end of the first inverter; the output end of the first inverter is connected with the second input end of the second multiplier; the output end of the second multiplier is connected with the second input end of the first integrator; the output end of the first time lag coupling circuit is connected with the third input end of the first integrator; the output end of the third inverting adder is connected with the input end of the second integrator; the output end of the second integrator is connected with the fourth input end of the first integrator; the output end of the first integrator is respectively connected with the input end of the first inverse adder, the input end of the second inverse adder, the input end of the third inverse adder, the first input end of the first time lag coupling circuit, the input end of the first calcium ion channel opening probability steady-state value calculating circuit, the input end of the first potassium ion channel opening probability steady-state value calculating circuit and the input end of the first activation time constant circuit.
3. The hardware circuit of the time-lag coupled neuron model of claim 2, wherein the second neuron main circuit comprises a fourth integrator, a fifth integrator, a sixth integrator, a fourth multiplier, a fifth multiplier, a sixth multiplier, a fifth inverting adder, a sixth inverting adder, a seventh inverting adder, an eighth inverting adder, and a second inverter;
the output end of the steady-state value calculation circuit of the opening probability of the second calcium ion channel is connected with the first input end of the fourth multiplier; the output end of the fifth inverting adder is connected with the second input end of the fourth multiplier; the output end of the fourth multiplier is connected with the first input end of the fourth integrator; the output end of the steady-state value calculation circuit of the opening probability of the second potassium ion channel is connected with the first input end of the eighth inverting adder; an output end of the eighth inverting adder is connected with a first input end of the sixth multiplier; an output terminal of the second active time constant circuit is connected to a second input terminal of the sixth multiplier; the output end of the sixth multiplier is connected with the input end of the sixth integrator; the output end of the sixth integrator is connected with the first input end of the fifth multiplier; the output end of the sixth inverting adder is connected with the input end of the second inverter; the output end of the second phase inverter is connected with the second input end of the fifth multiplier; the output end of the fifth multiplier is connected with the second input end of the fourth integrator; the output end of the second time lag coupling circuit is connected with the third input end of the fourth integrator; the output end of the seventh inverting adder is connected with the input end of the fifth integrator; the output end of the fifth integrator is connected with the fourth input end of the fourth integrator; the output end of the fourth integrator is respectively connected with the input end of the fifth inverse adder, the input end of the sixth inverse adder, the input end of the seventh inverse adder, the first input end of the second time lag coupling circuit, the input end of the second calcium ion channel opening probability steady-state value calculating circuit, the input end of the second potassium ion channel opening probability steady-state value calculating circuit, and the input end of the second activation time constant circuit.
4. The hardware circuit of the time-lag coupled neuron model according to claim 3, wherein the first time-lag coupling circuit comprises a first time-lag circuit and a first subtractor;
the output end of the first time delay circuit is connected with the second input end of the first subtracter; the first input end of the first subtracter is connected with the output end of the first integrator; the output end of the first subtracter is connected with the third input end of the first integrator; and the input end of the first time delay circuit is connected with the output end of the fourth integrator.
5. The hardware circuit of the time-lag coupling neuron model according to claim 2, wherein the steady-state value calculating circuit of the first calcium ion channel opening probability comprises a third subtractor, a first hyperbolic tangent operation circuit and a ninth inverse adder which are connected in sequence;
the input end of the third subtracter is connected with the output end of the first integrator; an output terminal of the ninth inverting adder is connected to a first input terminal of the first multiplier.
6. The hardware circuit of the time-lag coupling neuron model according to claim 2, wherein the steady-state value calculating circuit of the first potassium channel opening probability comprises a fourth subtractor, a second hyperbolic tangent operation circuit and a tenth inverse adder connected in sequence;
the input end of the fourth subtracter is connected with the output end of the first integrator; an output terminal of the tenth inverting adder is connected to a first input terminal of the fourth inverting adder.
7. The hardware circuit of a time-lag coupled neuron model of claim 2, wherein the first activation time constant circuit comprises a fifth subtractor, an eleventh inverting adder, a third inverter, a first exponential operation circuit, and a second exponential operation circuit;
the input end of the fifth subtracter is connected with the output end of the first integrator; a first output end of the fifth subtracter is connected with an input end of the first exponential operation circuit; a second output end of the fifth subtractor is connected with an input end of the third inverter; the output end of the first exponential operation circuit is connected with the first input end of the eleventh inverting adder; the output end of the third inverter is connected with the input end of the second index arithmetic circuit; the output end of the second exponential operation circuit is connected with the second input end of the eleventh inverting adder; an output terminal of the eleventh inverting adder is connected to a second input terminal of the third multiplier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210678835.7A CN114861903B (en) | 2022-06-15 | 2022-06-15 | Hardware circuit of time-lag coupled neuron model |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210678835.7A CN114861903B (en) | 2022-06-15 | 2022-06-15 | Hardware circuit of time-lag coupled neuron model |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114861903A true CN114861903A (en) | 2022-08-05 |
| CN114861903B CN114861903B (en) | 2023-05-26 |
Family
ID=82625049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210678835.7A Active CN114861903B (en) | 2022-06-15 | 2022-06-15 | Hardware circuit of time-lag coupled neuron model |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114861903B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110004579A1 (en) * | 2008-03-14 | 2011-01-06 | Greg Snider | Neuromorphic Circuit |
| CN105787291A (en) * | 2016-01-29 | 2016-07-20 | 西安交通大学 | Circuit for realizing Morris-Lecar neuron model by simulation |
| CN111967589A (en) * | 2020-08-21 | 2020-11-20 | 清华大学 | Neuron analog circuit, driving method thereof and neural network device |
-
2022
- 2022-06-15 CN CN202210678835.7A patent/CN114861903B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110004579A1 (en) * | 2008-03-14 | 2011-01-06 | Greg Snider | Neuromorphic Circuit |
| CN105787291A (en) * | 2016-01-29 | 2016-07-20 | 西安交通大学 | Circuit for realizing Morris-Lecar neuron model by simulation |
| CN111967589A (en) * | 2020-08-21 | 2020-11-20 | 清华大学 | Neuron analog circuit, driving method thereof and neural network device |
Non-Patent Citations (1)
| Title |
|---|
| 杨雨潼;刘深泉;: "FHN-ML电耦合神经元的发放模式和分岔分析" * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114861903B (en) | 2023-05-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Gökçe et al. | Twitter and politics: Identifying Turkish opinion leaders in new social media | |
| Zhu et al. | Effect of users’ opinion evolution on information diffusion in online social networks | |
| Zhang et al. | Network public opinion propagation model based on the influence of media and interpersonal communication | |
| CN110633422B (en) | Microblog friend recommendation method based on heterogeneous information network | |
| CN111970335B (en) | Information recommendation method and device and storage medium | |
| Banik et al. | The kbgen challenge | |
| WO2020237898A1 (en) | Personalized recommendation method for online education system, terminal and storage medium | |
| CN106709132A (en) | Mathematical modeling teaching system | |
| Li et al. | A reconfigurable bidirectional associative memory network with memristor bridge | |
| CN114861903A (en) | Hardware circuit of time-lag coupling neuron model | |
| Mao et al. | Dynamical analysis of coupled bidirectional FitzHugh–Nagumo neuronal networks with multiple delays | |
| Gruzd et al. | Trends in scholarly use of online social media | |
| Li et al. | Social media for ubiquitous learning and adaptive tutoring [guest editors' introduction] | |
| Karimi-Aghdam | Rethinking Vygotskian cultural-historical theory in light of Pepperian root metaphor theory: Dynamic interplay of organicism and contextualism | |
| Kong et al. | Application Research of Personalized Recommendation Technology in College English Teaching Reform under The Background of Big Data | |
| CN108280153B (en) | Intelligent aggregation method for fragmented knowledge | |
| Mohammad et al. | Human-like motion of a humanoid in a shadowing task | |
| Huang | Research on the evaluation of English teaching quality based on grey relational analysis | |
| Willet et al. | A tweet by any other frame: Three approaches to studying educator interactions on Twitter | |
| Veksler et al. | Goal‐Proximity Decision‐Making | |
| Liu et al. | Uniform stability of discrete impulsive systems | |
| Liu et al. | A special hybrid projective synchronization in symmetric chaotic system with unknown parameter | |
| Liu et al. | Multimodal Social Network Dataset Based on Goldbach Conjecture Proved Event in Zhihu | |
| Pratama | The analysis of meme virality factors in Twitter of scholar protest on September 2019 | |
| Majumder et al. | Keynote Talks and Tutorial |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |