CN114861592A - Switching-on overvoltage modeling method applied to eGaN HEMT - Google Patents

Switching-on overvoltage modeling method applied to eGaN HEMT Download PDF

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CN114861592A
CN114861592A CN202210369654.6A CN202210369654A CN114861592A CN 114861592 A CN114861592 A CN 114861592A CN 202210369654 A CN202210369654 A CN 202210369654A CN 114861592 A CN114861592 A CN 114861592A
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闫东
杭丽君
何远彬
曾平良
何震
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Hangzhou Dianzi University
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Abstract

The invention discloses a switching-on overvoltage modeling method applied to an eGaN HEMT, and belongs to the field of research on modeling of power electronic devices. The method comprises the following steps: the method comprises the steps of carrying out equivalent transformation on a circuit in the switching-on process on the basis of a power half-bridge double-pulse test circuit to obtain equivalent circuit diagrams in different time intervals, solving an overvoltage analysis model in the switching-on process through Laplace variation and inverse transformation on the basis of the equivalent circuit diagrams, and extracting parameters of parasitic capacitance and parasitic inductance in the circuit to ensure the accuracy of the model.

Description

Switching-on overvoltage modeling method applied to eGaN HEMT
Technical Field
The invention belongs to the technical field of power electronic device modeling, and relates to a switching-on overvoltage modeling method applied to an eGaN HEMT.
Background
The problem of drain-source voltage overvoltage caused by devices in a power half-bridge circuit in the switching transient process seriously affects the normal operation of power switching devices, and the overvoltage peak value is further increased along with the increase of the switching speed; once the voltage overshoot approaches the breakdown voltage of the power device, not only the switching speed cannot be further increased, but also the stability of the device, even the power electronic converter, is affected. Previous research was based primarily on conventional Si-based power half-bridge circuits and focused primarily on overvoltages during turn-off transients, since the turn-on speed of Si-based power devices was not fast enough that no significant turn-on overvoltages occurred. However, in a power half-bridge circuit composed of an eGaN HEMT (enhanced gallium nitride high electron mobility transistor) device, the switching-on overvoltage caused by rapid switching-on of the device is more serious, the passing voltage is even more serious than the switching-off overvoltage under a certain switching condition, and the voltage peak value in the switching-on transient process is even higher than the voltage overshoot in the switching-off transient process under different working currents and different gate resistances, so the problem of the switching-on overvoltage of the eGaN HEMT device in the power half-bridge circuit gradually arouses the attention of domestic and foreign research.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a switching-on overvoltage modeling method applied to an eGaN HEMT, which obtains an equivalent circuit decomposed in the switching-on process by performing equivalent transformation on a half-bridge circuit, and deduces a switching-on overvoltage analysis model of the equivalent circuit. The method comprises the following steps:
s10, building a power half-bridge double-pulse test circuit;
s20, obtaining an equivalent circuit decomposed in the opening process;
s30, solving an overvoltage analysis model;
and S40, extracting parasitic parameters.
Preferably, in the power half-bridge double-pulse test circuit built at S10, Q 2 And Q 1 The top and bottom switching devices eGaN HEMTs of the test circuit are respectively; v DC For the circuit bus voltage, V g For driving the power supply, C DC Is a circuit buffer capacitor, L is a load inductor, C gs Is parasitic capacitance of gate and source, C ds Is parasitic capacitance of drain and source, C gd Is parasitic capacitance of gate and drain, Q 2 And Q 1 All have a group C gs 、C ds And C gd ；L loop Is the total stray inductance of the power loop, L g To drive parasitic inductances, R g To drive a resistor, Q 1 And Q 2 Each gate of (a) is connected with a group of R in series g And L g Is connected to R stray Is loop stray resistance, Q 2 Drain of (1) and R stray Is connected to one end of R stray Is connected with one end of L, and the other end of L is connected with Q 2 Is connected to the source of (a); q 1 And L of loop One end is connected with L loop Another end of (1) and C DC Is connected at one end to C DC The other end of the eGaN HEMT is connected with the other end of the L, and parameters of the eGaN HEMT in the switching-on process comprise a bottom switch Q 1 Drain current i of d_B Drain-source voltage v ds_B Grid source voltage v g_B And a top switch Q 2 Of the drain-source voltage v ds_T 。
Preferably, in said S20, the period from t1 to t2 is called di/dt transient, and an equivalent circuit of the period is derived, during which the top switch Q is turned on 2 In a reverse conducting state, V r Represents Q 2 Reverse conducting voltage drop of, and v ds_T Remains unchanged and is equal to-V r ；Q 1 Drain current i of d_B Fast rise, Q 1 Of the drain-source voltage v ds_B At L loop At an initial voltage V DC +V r A voltage drop Δ V is generated, i.e., at time t3, V ds_B At a voltage value V m ，
Figure BDA0003587633980000021
time t3 is when Q 1 Drain current i of d_B Up to rated load current I L When it comes to a dv/dt transient, and derives the equivalent circuit for the time period t2 to t3, during which the top switch Q is turned on 2 Stopping reverse conduction and no longer having voltage clamping effect, and following i d_B Greater than the load current I L Start to Q 2 Output capacitor C oss Charging and output capacitor C oss The relation with the junction capacitance is C oss Cgd + Cds; will Q 2 Equivalent to output capacitance C oss At this time v ds_T Start of increase, v ds_B And continues to descend.
Preferably, the S30 includes a top switch Q by laplace transform analysis of the equivalent circuit in S20 2 Turn-on voltage v of ds_T The peak analysis is simplified to:
Figure BDA0003587633980000031
wherein, L, R, C are loop stray inductance L respectively loop Stray resistance R stray An output capacitor C oss ；v ds_T The expression (c) relates to two stimuli: one is V DC -V r +RI L A direct current component representing the voltage difference between the off state and the on state of the upper switch; the other is v ds_B It is a transient element modeled as a ramped controllable voltage source; bottom switch Q 1 Of the drain-source voltage v ds_B The drain-source voltage during the dv/dt transient is reduced to a ramp function:
Figure BDA0003587633980000032
in the formula, t d To switch on the voltage fall time during the transient, V m Is v ds_B By combining equations (2) to (3) and solving for v by inverse Laplace transform ds_T The analytical model of (2):
Figure BDA0003587633980000033
wherein the content of the first and second substances,
Figure BDA0003587633980000034
as parasitic vibrationAnd the oscillating angle frequency and the tau are 2L/R and are damping time constants.
Preferably, in S40, non-linear C is included oss The curve fitting method comprises the following steps:
Figure BDA0003587633980000035
wherein, C omax Is the maximum value of capacitance, k 1 ,k 2 ,k 3 ,k 4 For presetting the fitting parameters, L loop All parasitic inductances and package stray inductances in the power supply loop are integrated, v in the turn-on waveform ds_B Is measured in the switching waveform, and L is determined according to equation (1) loop 。
The invention has the following beneficial effects:
compared with the prior art, the invention provides a switching-on overvoltage modeling method applied to an eGaN HEMT, which is based on a power half-bridge double-pulse test circuit, performs equivalent transformation on the circuit in the switching-on process to obtain equivalent circuit diagrams in different time intervals, solves an overvoltage analysis model in the switching-on process through Laplace variation and inverse transformation on the basis of the equivalent circuit diagrams, and extracts parasitic capacitance and parasitic inductance parameters in the circuit to ensure the accuracy of the model.
Drawings
FIG. 1 is a flow chart of a switching-on overvoltage modeling method applied to an eGaN HEMT according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a switching-on overvoltage modeling method applied to an eGaN HEMT according to an embodiment of the invention;
FIG. 3 is a power half-bridge dipulse test circuit diagram of the switching-on overvoltage modeling method applied to the eGaN HEMT according to the embodiment of the invention;
FIG. 4 is a waveform diagram of an equivalent circuit turn-on process applied to the turn-on overvoltage modeling method of the eGaN HEMT according to the embodiment of the invention;
FIG. 5 is a di/dt interval equivalent circuit diagram of the switching-on overvoltage modeling method applied to the eGaN HEMT according to the embodiment of the invention;
FIG. 6 is a dv/dt interval equivalent circuit diagram of the switching-on overvoltage modeling method applied to an eGaN HEMT according to the embodiment of the invention;
fig. 7 is a laplacian transfer function derivation diagram of the switching-on overvoltage modeling method applied to the gan HEMT of the embodiment of the present invention;
FIG. 8 is a non-linear capacitance fitting result graph of the switching-on overvoltage modeling method applied to an eGaN HEMT according to the embodiment of the invention;
fig. 9 is a diagram of a switching-on overvoltage waveform when the driving resistance is 1 Ω, which is applied to the switching-on overvoltage modeling method of the edan HEMT according to the embodiment of the present invention;
fig. 10 is a diagram of a switching-on overvoltage waveform when the driving resistance is 5 Ω according to the switching-on overvoltage modeling method for the edan HEMT of the embodiment of the present invention;
fig. 11 is a waveform diagram of the turn-on overvoltage when the driving resistance is 10 Ω according to the turn-on overvoltage modeling method for the edan HEMT of the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Referring to fig. 1 and 2, a flow chart of the method steps of the invention is shown, which comprises the following steps:
s10, building a power half-bridge double-pulse test circuit;
s20, obtaining an equivalent circuit decomposed in the opening process;
s30, solving an overvoltage analysis model;
and S40, extracting parasitic parameters.
In S10, in order to evaluate the turn-on overvoltage of the eGaN HEMT, a power half-bridge double-pulse test circuit is built, see FIG. 3, Q 2 And Q 1 The top and bottom switching devices eGaN HEMTs of the test circuit are respectively; v DC For the circuit bus voltage, V g For driving the power supply, C DC Is a circuit buffer capacitor, L is a load inductor, C gs Is parasitic capacitance of gate and source, C ds Is parasitic capacitance of drain and source, C gd Is parasitic capacitance of gate and drain, Q 2 And Q 1 All have a group C gs 、C ds And C gd ；L loop Is the total stray inductance of the power loop, L g To drive parasitic inductances, R g To drive a resistor, Q 1 And Q 2 Each gate of (a) is connected with a group of R in series g And L g Is connected to R stray Is loop stray resistance, Q 2 Drain of (1) and R stray Is connected to one end of R stray Is connected with one end of L, and the other end of L is connected with Q 2 Is connected to the source of (a); q 1 And L of loop One end is connected with L loop Another end of (1) and C DC Is connected at one end to C DC Is connected to the other end of L.
FIG. 4 is a diagram of an ON waveform depicting a typical ON waveform for various parameters of an eGaN HEMT during the ON process, including in particular a bottom switch Q 1 Drain current i of d_B Drain-source voltage v ds_B Grid source voltage v g_B And a top switch Q 2 Of the drain-source voltage v ds_T . From the waveform diagram of fig. 4, v can be seen ds_T In the process of opening t 3 There is a large voltage spike at all times, and if the voltage is too high, the safe operation of the device is seriously threatened.
Let the period t1 to t2 in the open waveform diagram of fig. 4 be called di/dt transient in S20, and derive the equivalent circuit for this period, see fig. 5, during which the top switch Q is turned on 2 In a reverse conducting state, V r Represents Q 2 Reverse conducting voltage drop of, and v ds_T Remain unchanged, etcin-V r ；Q 1 Drain current i of d_B Fast rise, Q 1 Of the drain-source voltage v ds_B At L loop At an initial voltage V DC +V r A voltage drop Δ V is generated, i.e., at time t3, V ds_B At a voltage value V m ，
Figure BDA0003587633980000061
time t3 is when Q 1 Drain current i of d_B Up to rated load current I L When it comes to a dv/dt transient, and derives the equivalent circuit for the time period t2 to t3, during which the top switch Q is turned on 2 Stopping reverse conduction and no longer having voltage clamping effect, and following i d_B Greater than the load current I L Start to Q 2 Output capacitor C oss Charging and output capacitor C oss The relation with the junction capacitance is C oss Cgd + Cds; will Q 2 Equivalent to output capacitance C oss At this time v ds_T Start of increase, v ds_B And continues to descend.
S30 includes the analysis of the equivalent circuit in S20 by performing a Laplace transform analysis, the derivation of which is shown in FIG. 7, top switch Q 2 Turn-on voltage v of ds_T The peak analysis is simplified to:
Figure BDA0003587633980000062
wherein, L, R, C are loop stray inductance L respectively loop Stray resistance R stray An output capacitor C oss ；v ds_T The expression (c) relates to two stimuli: one is V DC -V r +RI L A direct current component representing the voltage difference between the off state and the on state of the upper switch; the other is v ds_B It is a transient element, modeled as a ramped controllable voltage source; bottom switch Q 1 Of the drain-source voltage v ds_B During dv/dt transientsThe drain-source voltage in (1) is reduced to a ramp function:
Figure BDA0003587633980000063
in the formula, t d To switch on the voltage fall time during the transient, V m Is v ds_B The initial voltage of (a). Since the switching speed determines the slew rate of the voltage source. The mechanism leading to the upper switching overvoltage is therefore due to the high dv/dt acting simultaneously with the LRC series resonant network. Because the eGaN HEMT device has higher switching speed capability and smaller on-state resistance, the overshoot voltage is higher, and the parasitic ringing duration is longer. Combining the formulas (2) to (3), and obtaining v through inverse Laplace transform calculation ds_T The analytical model (2):
Figure BDA0003587633980000071
wherein the content of the first and second substances,
Figure BDA0003587633980000072
is the parasitic oscillation angular frequency and τ 2L/R is the damping time constant.
In S40, it is found from equation (4) that the parasitic capacitance and parasitic inductance of the edan HEMT also have an important influence on the on-overvoltage, and the output capacitance C is oss Is a following v ds_T Has strong nonlinearity, and therefore needs to be applied to C oss The overvoltage model can be obtained more accurately by performing accurate modeling. In the specific embodiment, the GS61004B eGaN HEMT device manufactured by GaN systems is taken as an example, and the device manufacturer provides C oss In order to make the analytic model more accurate, a method including non-linear C is provided oss The curve fitting method comprises the following steps:
Figure BDA0003587633980000073
wherein, C omax Is the maximum value of capacitance, k 1 ,k 2 ,k 3 ,k 4 See table 1 for preset fitting parameters. The results of the fitting are shown in FIG. 8, and the results demonstrate that C is oss The model has higher accuracy, and the error is within 5%.
TABLE 1 fitting parameters
Parameter(s) Value of
C omax 311PF
k 1 -0.456
k 2 -0.51
k 3 9.5
k 4 -0.256
L loop All parasitic inductances in the power supply loop and package stray inductances are concentrated. But L loop Is unknown because it is determined by the specific layout of the circuit and the PCB design layout. The present invention estimates L using information already in the experimental opening waveform loop Not only is the method very simple, but also the actual situation is reflected with great convincing force. In the on waveform v ds_B Pressure ofThe decrease Δ V and di/dt can be measured in the switching waveform, and L is determined according to equation (1) loop 。
The experimental results are shown in fig. 9-11, different driving resistors are used to control the switching-on speed, different switching-on overvoltage waveforms are obtained, the comparison results are compared with the simulation results obtained by model calculation, and the comparison results show that the model has higher precision and can more accurately predict the overvoltage peak value.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (5)

1. A switching-on overvoltage modeling method applied to an eGaN HEMT is characterized by comprising the following steps:
s10, building a power half-bridge double-pulse test circuit;
s20, obtaining an equivalent circuit decomposed in the opening process;
s30, solving an overvoltage analysis model;
and S40, extracting parasitic parameters.
2. The method of claim 1, wherein in the power half-bridge double-pulse test circuit built at S10, Q is 2 And Q 1 The top and bottom switching devices eGaN HEMTs of the test circuit are respectively; v DC For the circuit bus voltage, V g For driving the power supply, C DC Is a circuit buffer capacitor, L is a load inductor, C gs Is parasitic capacitance of gate and source, C ds Is parasitic capacitance of drain and source, C gd Is parasitic capacitance of gate and drain, Q 2 And Q 1 All have a group C gs 、C ds And C gd ；L loop Is the total stray inductance of the power loop, L g To drive parasitic inductances, R g To drive a resistor, Q 1 And Q 2 Each gate of (a) is connected with a group of R in series g And L g Is connected to R stray Is loop stray resistance, Q 2 Of the drain electrodeAnd R stray Is connected to one end of R stray Is connected with one end of L, and the other end of L is connected with Q 2 Is connected to the source of (a); q 1 And L of loop One end is connected with L loop Another end of (1) and C DC Is connected at one end to C DC The other end of the eGaN HEMT is connected with the other end of the L, and parameters of the eGaN HEMT in the switching-on process comprise a bottom switch Q 1 Drain current i of d_B Drain-source voltage v ds_B Grid source voltage v g_B And a top switch Q 2 Of the drain-source voltage v ds_T 。
3. The method as claimed in claim 2, wherein the time period from t1 to t2 in S20 is called di/dt transient, and an equivalent circuit of the time period is derived, during which the top switch Q is turned on 2 In a reverse conducting state, V r Represents Q 2 Reverse conducting voltage drop of, and v ds_T Remains unchanged and is equal to-V r ；Q 1 Drain current i of d_B Fast rise, Q 1 Of the drain-source voltage v ds_B At L loop At an initial voltage V DC +V r A voltage drop Δ V is generated, i.e., at time t3, V ds_B At a voltage value V m ，
Figure FDA0003587633970000011
time t3 is when Q 1 Drain current i of d_B Up to rated load current I L When it comes to a dv/dt transient, and derives the equivalent circuit for the time period t2 to t3, during which the top switch Q is turned on 2 Stopping reverse conduction and no longer having voltage clamping effect, and following i d_B Greater than the load current I L Start to Q 2 Output capacitor C oss Charging and output capacitor C oss The relation with the junction capacitance is C oss Cgd + Cds; will Q 2 Equivalent to output capacitance C oss At this time v ds_T Start of increase, v ds_B And continues to descend.
4. The method of claim 3, wherein the S30 includes a top switch Q by performing a Laplace transform analysis on the equivalent circuit in S20 2 Turn-on voltage v of ds_T The peak analysis is simplified to:
Figure FDA0003587633970000021
wherein, L, R, C are loop stray inductance L respectively loop Stray resistance R stray An output capacitor C oss ；v ds_T The expression (c) relates to two stimuli: one is V DC -V r +RI L A direct current component representing the voltage difference between the off state and the on state of the upper switch; the other is v ds_B It is a transient element modeled as a ramped controllable voltage source; bottom switch Q 1 Of the drain-source voltage v ds_B The drain-source voltage during the dv/dt transient is reduced to a ramp function:
Figure FDA0003587633970000022
in the formula, t d To switch on the voltage fall time during the transient, V m Is v ds_B By combining equations (2) to (3) and solving for v by inverse Laplace transform ds_T The analytical model of (2):
Figure FDA0003587633970000023
wherein the content of the first and second substances,
Figure FDA0003587633970000024
is the parasitic oscillation angular frequency and τ 2L/R is the damping time constant.
5. The method according to claim 4, wherein S40 includes a non-linear C oss The curve fitting method comprises the following steps:
Figure FDA0003587633970000025
wherein, C omax Is the maximum value of capacitance, k 1 ,k 2 ,k 3 ,k 4 For presetting the fitting parameters, L loop All parasitic inductances and package stray inductances in the power supply loop are integrated, v in the turn-on waveform ds_B Is measured in the switching waveform, and L is determined according to equation (1) loop 。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115859889A (en) * 2022-11-16 2023-03-28 广东工业大学 Method for selecting drive resistor of eGaN HEMT power converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115859889A (en) * 2022-11-16 2023-03-28 广东工业大学 Method for selecting drive resistor of eGaN HEMT power converter
CN115859889B (en) * 2022-11-16 2023-07-18 广东工业大学 Selection method of driving resistor of eGaN HEMT power converter

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