CN114860598A

CN114860598A - Chip configuration code test system and method

Info

Publication number: CN114860598A
Application number: CN202210492426.8A
Authority: CN
Inventors: 陈俊蓉; 邱建峰; 戚晨希; 段有楠
Original assignee: Suzhou Centec Communications Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2022-05-07
Filing date: 2022-05-07
Publication date: 2022-08-05

Abstract

The embodiment of the invention provides a chip configuration code test system and a method, belonging to the field of software test. The development device includes a plurality of application program interfaces for configuring code. And the test module is used for sending out a test command. And the intermediate device is used for responding to the test command, analyzing the target application program interface of the development equipment, calling the input parameters of the target configuration code, and accessing the IP core by using the input parameters. And the IP core is used for responding to the input parameters, executing the logic corresponding to the input parameters to obtain an execution result, and judging whether the target configuration code normally runs or not according to the execution result. Therefore, the configuration code of the high-speed serial interface can be tested before the chip is subjected to chip flow, so that the time consumption of chip testing is reduced, and the chip testing efficiency is improved.

Description

Chip configuration code test system and method

Technical Field

The invention relates to the field of software testing, in particular to a system and a method for testing chip configuration codes.

Background

A SerDes is an interface circuit in high-speed data communication, and the SerDes can realize high-speed long-distance transmission by using an emphasis/equalization technique, so that a high-speed serial interface provided by the SerDes is often used in chip design.

The high-speed serial interface is used as an important module of a physical layer of the exchange chip for transmitting signals, plays a role in signal transmission in the exchange chip, and if the high-speed serial interface cannot normally run or work, the debugging of other modules of the exchange chip can be seriously hindered, so that the progress cannot be pushed forward. At present, a simulation test environment is difficult to build through an FPGA (field programmable gate array), and generally, after a chip stream is back-filmed, the environment with a high-speed serial interface is used for debugging a related configuration Code (SDK Code), so that the chip test is long in time consumption and low in efficiency.

Disclosure of Invention

In view of the above, the present invention provides a system and a method for testing chip configuration codes, and can solve the problems of long time consumption and low efficiency in chip testing caused by the fact that the related codes of the high-speed serial interface of the chip can only be debugged after the chip is taped.

In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions.

In a first aspect, an embodiment of the present invention provides a chip configuration code testing system, which adopts the following technical solution.

A chip configuration code test system comprises development equipment, a middleware and an evaluation board, wherein the evaluation board comprises a test module and an IP core of a high-speed serial interface related to a design chip;

the development equipment comprises a plurality of application program interfaces of configuration codes, wherein each configuration code realizes a target configuration of the high-speed serial interface;

the test module is used for sending a test command, wherein the test command comprises a target application program interface;

the middleware is used for responding to the test command, analyzing the target application program interface of the development equipment, calling the input parameters of the target configuration code, and accessing the IP core by using the input parameters;

and the IP core is used for responding to the input parameters, executing the logic corresponding to the input parameters to obtain an execution result, and judging whether the target configuration code normally runs or not according to the execution result.

Further, the evaluation board further comprises a status register, and the system further comprises a judger;

the IP core is used for writing the execution result into the status register;

the judger is configured to read the execution result from the status register, and obtain an operation result of the target configuration code according to a comparison result between the execution result and the target result of the target configuration code.

Further, the evaluation board further comprises a display module;

and the display module is used for receiving and displaying the execution result output by the IP core, or reading the execution result from the status register and displaying the execution result.

Further, the middleware is further configured to convert the programming language of the target configuration code into the language environment of the IP core.

Further, the target configuration comprises a loopback interface configuration, an equalization configuration, a rate switching and an auto-negotiation configuration.

Further, the mediator includes a plurality of decorator functions, one of the application program interfaces corresponding to one of the decorator functions;

and the decorator function analyzes each application program interface of the development equipment, calls the input parameters of each configuration code, and accesses the IP core by using the input parameters.

Further, the evaluation board further comprises an IO interface;

and the intermediate device calls the IO interface by taking the input parameter as an input parameter so as to access the IP core.

In a second aspect, an embodiment of the present invention further provides a method for testing a chip configuration code, which adopts the following technical solution.

A chip configuration code testing method implemented based on the chip configuration code testing system according to the first aspect, the method comprising:

sending a test command through a test module, wherein the test command comprises a target application program interface;

responding to the test command through a middleware, analyzing the target application program interface of the development equipment, calling an input parameter of a target configuration code, and accessing the IP core by using the input parameter;

responding to the input parameters through the IP core, executing the logic corresponding to the input parameters to obtain an execution result, and judging whether the target configuration code operates normally according to the execution result.

Further, the method further comprises:

writing the execution result into a status register through an IP core;

and reading the execution result from the status register through a judger, and obtaining the running result of the target configuration code according to the comparison result of the execution result and the target result of the target configuration code.

Further, the step of accessing the IP core using the input parameter includes:

and the intermediate device takes the input parameters as input parameters to call an IO interface of the evaluation board so as to access the IP core.

In a third aspect, an embodiment of the present invention provides a computer storage medium, which adopts the following technical solutions.

A computer storage medium having stored thereon a computer program which, when executed by a processor, implements a chip configuration code testing method according to the second aspect.

In a fourth aspect, an embodiment of the present invention provides a processor, which adopts the following technical solutions.

A processor for running a computer program, the processor implementing the chip configuration code testing method of the second aspect when running the computer program.

The chip configuration code test system and the method provided by the embodiment of the invention build a test system related to the high-speed serial interface by using the IP core of the high-speed serial interface used in designing the chip and combining the development equipment and the middleware, wherein the development equipment comprises a plurality of configuration codes and application program interfaces for realizing the target configuration of the serial interface, therefore, under the test command of the test module, the intermediate device accesses the IP core on the evaluation board based on the input parameter of the configuration code obtained by analyzing the target application program interface on the development equipment to debug the target configuration code on the IP core, so that before the chip is not taped, can test each configuration code of the high-speed serial interface of chip to can flow the test consuming time of the high-speed serial interface that significantly reduces after the piece comes out at the chip, and then reduce that the chip test is consuming time, raise the efficiency.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 shows one of block schematic diagrams of a chip configuration code test system provided by an embodiment of the present invention.

Fig. 2 is a second block diagram of a chip configuration code testing system according to an embodiment of the present invention.

Fig. 3 is a flowchart illustrating a chip configuration code testing method according to an embodiment of the present invention.

Fig. 4 is a second flowchart illustrating a chip configuration code testing method according to an embodiment of the present invention.

Icon: 100-chip configuration code test system; 110-a development device; 120-application program interface; 130-an intermediate device; 140-evaluation plate; 150-a test module; 160-IP core; 170-status register; 180-judging device; 190-display module.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The high-speed serial interface is used as an important module of a physical layer of the exchange chip for transmitting signals, plays a role in signal transmission in the exchange chip, and if the high-speed serial interface cannot normally run or work, the debugging of other modules of the exchange chip can be seriously hindered, so that the progress cannot be pushed forward.

Generally, a high-speed serial interface is configured by a configuration code to implement various types of communication services. The configuration code of the high-speed serial interface which is not debugged has larger uncertainty and has larger potential risk. Therefore, before using a high-speed serial interface, the relevant configuration code needs to be debugged.

At present, a simulation test environment is difficult to build through an FPGA (field programmable gate array), and generally, after a chip stream (chip stream refers to chip production), the environment with a high-speed serial interface is used for debugging a related SDK Code, so that the chip test is long in time consumption and low in efficiency.

Based on the above consideration, embodiments of the present invention provide a chip configuration code testing scheme, which can debug/test the relevant configuration codes of the high-speed serial interface of the chip before the chip is taped, so as to improve the chip testing efficiency and shorten the chip testing duration. Hereinafter, this scheme will be described from a plurality of embodiments.

In one embodiment, referring to fig. 1, a chip configuration code testing system 100 is provided, which includes a development device 110, a mediator 130, and an evaluation board 140, wherein the evaluation board 140 includes a testing module 150 and an IP core 160 for designing a high-speed serial interface of a chip.

A development device 110 including a plurality of application program interfaces 120 of configuration code.

Wherein each configuration code implements a target configuration for the high-speed serial interface. The target configuration implemented by the configuration code includes but is not limited to: loopback interface configuration, balance configuration, rate switching and auto-negotiation configuration.

It should be understood that the target configuration includes all functional configurations of the high-speed serial interface, and the above target configurations are only some examples and are not only limited.

And a test module 150 for issuing a test command.

Wherein the test command includes the target application program interface 120.

The test module 150 includes a test interface, transmits a test command through the test interface, and specifies a debugged configuration code, i.e., a target configuration code, through the target application program interface 120 in the test command.

The middleware 130 is configured to, in response to the test command, parse the target application program interface 120 of the development device 110, retrieve an input parameter of the target configuration code, and access the IP core 160 using the input parameter.

Based on the consideration of the adaptability between the configuration code on the development device 110 side and the IP core 160, the middleware 130 is used to analyze the target application program interface 120 of the development device 110, call the input parameters of the target configuration code, and access the IP core 160 by using the input parameters, so as to ensure that the IP core 160 can execute the logic of the target configuration code.

And the IP core 160 is configured to respond to the input parameter, execute a logic corresponding to the input parameter to obtain an execution result, and determine whether the target configuration code operates normally according to the execution result.

Each configuration code has an expected result corresponding to the configuration code, if the execution result is the same as the expected result, the operation is normal, and if the execution result is not the same as the expected result, the execution is abnormal.

It should be understood that the logic corresponding to the input parameter refers to the logic of the target configuration code.

In this embodiment, the IP core 160 provides a high-speed serial interface for a manufacturer or a developer of the high-speed serial interface to design a logic block, a data block, or a circuit module of the high-speed serial interface, and has a logic function of the high-speed serial interface.

Compared with the traditional method, the debugging of the related configuration codes of the high-speed serial interface of the chip can be carried out only after the chip is streamed: the chip configuration code test system 100 provided by the invention builds a test system related to a high-speed serial interface by using the IP core 160 of the high-speed serial interface used in designing the chip and combining the development equipment 110 and the intermediate device 130. The development device 110 includes a plurality of configuration codes for implementing target configuration of the serial interface and the application program interface 120, so that the middleware 130 accesses the IP core 160 on the evaluation board 140 based on the input parameters of the configuration codes obtained by analyzing the target application program interface 120 on the development device 110 under the test command of the test module 150 to perform a test of the target configuration codes on the IP core 160, and thus each configuration code of the high-speed serial interface of the chip can be tested before the chip is not subjected to chip flow, so that the test time consumption of the high-speed serial interface can be greatly reduced after the chip flow comes out, the test time consumption of the chip can be further reduced, and the efficiency can be improved.

The development device 110 includes, but is not limited to: personal computers, notebook computers, ipads and other terminal devices, and a Software Development Kit (SDK) is installed in the development device 110. The configuration code for the high-speed serial interface may be developed and written on a software development kit and stored within the development device 110.

The primary purpose of the application program interface 120, i.e., the API, is to provide the application (software development kit) with the ability for a developer to access a set of routines without having to access source code or understand the details of the internal workings.

Considering the situation where the language environment of the software development kit (i.e., the language of the configuration code) in development device 110 may not be the same as the language environment of IP core 160, in one embodiment, middleware 130 is also used to convert the change-to-language of the target configuration code into the language environment of IP core 160.

For example, if the language environment of the IP core 160 is Python environment and the language environment of the software development kit is C language, the middle layer may convert the configuration code from C language to Python language or Python language to C language. If the test command sent by the test module 150 is in Python language, the middleware 130 converts the test command into C language, and then parses the target api 120. The intermediate device 130 converts the target configuration code into Python language and then extracts the input parameters.

Further, referring to fig. 2, the middleware 130 may include a plurality of decorator functions, and one application program interface 120 of the development device 110 may correspond to one decorator function.

The decorator function parses each application program interface 120 of the development device 110, calls the input parameters of each configuration code, and accesses the IP core 160 using the input parameters.

The decorator function can add additional functions, i.e., package other functions and change the behavior of the packaged function (object, configuration code in this embodiment) without any code change for other functions (configuration code).

The access function is added to the original configuration code through the decorator function, and the middleware 130 can also perform language conversion so that the IP core 160 can execute the logic of the target configuration code according to the input parameters without hindrance.

It should be understood that other functions may be added to the original configuration code through the decorator function, for example, functions of comparing the execution results or alarming when the execution results are abnormal, and the present embodiment is not limited in particular.

To describe the process of accessing IP core 160 in more detail, in one embodiment, evaluation board 140 further includes an IO interface, where the IO interface is an IO interface of IP core 160. It should be understood that the IO interface includes a read IO and a write IO.

The mediator 130 enables access to the IP core 160 using the input parameters by: the mediator 130 calls the IO interface with the input parameter as an entry parameter to access the IP core 160.

In more detail, please continue to follow fig. 2, the development device 110 further includes an IO interface, after the middleware 130 receives the test command, the language conversion and the input parameter calling are performed on the target configuration code through the IO interface of the development device 110 from the target application program interface 120 for the decorator function corresponding to the target configuration code, and the IO interface of the IP core 160 is called through the IO decorator function corresponding to the IO interface of the development device 110, so as to access the IP core 160 by using the input parameter.

In the above manner, access to the IP core 160 using the input parameters of the target configuration code is achieved.

Further, with reference to fig. 2, the chip configuration code testing system 100 of the present invention further includes a determiner 180, and the evaluation board 140 further includes a status register 170.

And an IP core 160 for writing the execution result to the status register 170.

The decider 180 is configured to read the execution result from the status register 170, and obtain an operation result of the target configuration code according to a comparison result between the execution result and the target result of the target configuration code.

The status register 170 stores the execution result of the IP core 160 after executing the logic of each configuration code, so that the decider 180 can read the execution result from the status register 170 to judge the execution result of the target configuration code.

Referring to fig. 2, the evaluation board 140 of the chip configuration code testing system 100 may further include a display module 190.

And a display module 190, configured to receive and display the execution result output by the IP core 160, or read the execution result from the status register 170 and display the execution result.

And the display module 190 is further configured to obtain an operation result of the target configuration code sent by the determiner 180, and display the operation result.

That is, the display module 190 displays the execution result and/or the operation result of the target configuration code, so as to remind the debugging personnel of the result of the target configuration code and make the debugging personnel clear at a glance.

In another embodiment, the chip configuration code testing system 100 may include a development device 110 and an evaluation board 140, the development device 110 including a plurality of application program interfaces 120 for configuration codes and an intermediary 130, the evaluation board 140 including a test module 150 and an IP core 160 for a high-speed serial interface for designing a chip.

And a test module 150 for issuing a test command.

Wherein the test command includes the target application program interface 120.

The middleware 130 is configured to, in response to the test command, parse the target application program interface 120 of the development device 110, call an input parameter of the target configuration code, and access the IP core 160 using the input parameter.

That is, the middleware 130 is a functional module of the development device 110, and the chip configuration code testing system 100 is constructed to realize the same function as the chip configuration code testing system 100 of the first embodiment.

In yet another embodiment, the chip configuration code testing system 100 may include a development device 110 and an evaluation board 140, the development device 110 including a plurality of application program interfaces 120 for configuration codes, the evaluation board 140 including a mediator 130, a test module 150, and an IP core 160 for designing a high-speed serial interface of a chip.

And a test module 150 for issuing a test command.

Wherein the test command includes the target application program interface 120.

That is, the chip configuration code test system 100 is constructed with the mediator 130 as a functional module of the evaluation board 140, and functions as the chip configuration code test system 100 of the first embodiment are realized.

It should be understood that the above-described embodiments are merely examples of several implementations of the chip configuration code test system 100 and are not intended to be limiting. In practical applications, the development device 110, the middleware 130, and the evaluation board 140 may be configured and combined differently to build different chip configuration code test systems 100, so as to implement the test functions.

In the chip configuration code test system 100 provided above, the middleware 130 (including the decorator function) is introduced to change the configuration code (SDK code) of the high-speed serial interface as little as possible to accept the parameters of the interfaces in different language environments, so as to implement the function of mixed calling of different languages. Also, the mediator 130 allows the logic of the configuration code to be executed in the un-configured IP core 160 to improve the environmental adaptability of the chip configuration code testing system 100.

It should be noted that the evaluation board 140 further includes an IP core 160 of a chip, and the development device 110 may further include a configuration code of the chip, so that chip function debugging before chip flow can also be achieved.

The test system can be used for debugging configuration codes before chip stream is back in addition to performing performance test by using the evaluation board 140 of the high-speed serial interface, thereby effectively reducing the uncertainty of the codes in the Bring Up period after chip stream and improving the risk controllability of the codes.

Experiments prove that by adopting the chip configuration code testing system 100, the debugging time of the high-speed serial interface of the chip is reduced from 2 months to 1 month approximately at the BringUp stage of the chip, and the chip verification efficiency is greatly improved.

Based on the same inventive concept as the above embodiment, in an embodiment, referring to fig. 3, a chip configuration code testing method is provided, which is implemented based on the above chip configuration code testing system 100 and may include the following steps.

And S101, sending a test command through the test module.

Wherein the test command includes the target application program interface 120.

And S102, responding to the test command through the intermediate device, analyzing a target application program interface of the development equipment, calling an input parameter of a target configuration code, and accessing the IP core by using the input parameter.

S103, responding to the input parameters through the IP core, executing the logic corresponding to the input parameters to obtain an execution result, and judging whether the target configuration code normally runs or not according to the execution result.

In the above chip configuration code testing method, the intermediate device 130 accesses the IP core 160 on the evaluation board 140 based on the input parameter of the configuration code obtained by analyzing the target application program interface 120 on the development device 110 under the test command of the test module 150 to test the target configuration code on the IP core 160, so that each configuration code of the high-speed serial interface of the chip can be tested before the chip is not subjected to tape-out, thereby greatly reducing the test time consumption of the high-speed serial interface after the chip is subjected to tape-out, further reducing the test time consumption of the chip and improving the efficiency.

Further, in order to facilitate learning of the operation result, referring to fig. 4, the chip configuration code testing method provided by the present invention may further include the following steps.

And S104, writing the execution result into the status register through the IP core.

And S105, reading the execution result from the status register through the judger, and obtaining the running result of the target configuration code according to the comparison result of the execution result and the target result of the target configuration code.

To further understand how the intermediate device 130 accesses the IP core 160 using the input parameter, in one embodiment, for step S103, accessing the IP core 160 using the input parameter may be implemented by the intermediate device 130 calling the input parameter as an input parameter to the IO interface of the evaluation board 140 to access the IP core 160.

For specific limitations of the chip configuration code testing method, reference may be made to the above limitations of the chip configuration code testing system 100, which are not described herein again.

In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a processor implements any of the steps of the chip configuration code testing method of the chip configuration code based testing system 100 described above.

In one embodiment, a processor is provided for running a computer program, which when running the computer program implements any one or several of the steps of the chip configuration code testing method of the chip configuration code based testing system 100 described above.

It should be understood that the processor may be the processor of the development device 110, the mediator 130, and the evaluation board 140 in the above chip configuration code test system 100.

The various functional modules (development device 110, middleware 130, test module 150, and IP core 160) in the above chip configuration code test system 100 may be implemented in whole or in part by software, hardware, and a combination thereof. The functional modules can be embedded in a hardware form or independent from a processor in the computer device, or can be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. The system embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip configuration code test system is characterized by comprising development equipment, a middleware and an evaluation board, wherein the evaluation board comprises a test module and an IP core of a high-speed serial interface related to a design chip;

2. The chip configuration code testing system of claim 1, wherein the evaluation board further comprises a status register, the system further comprising a determiner;

the IP core is used for writing the execution result into the status register;

3. The chip configuration code testing system of claim 2, wherein the evaluation board further comprises a display module;

and the display module is used for receiving and displaying the execution result output by the IP core, or reading the execution result from the state register and displaying the execution result.

4. The chip configuration code testing system of claim 1, wherein the middleware is further configured to convert the programming language of the target configuration code into the language environment of the IP core.

5. The chip configuration code test system according to claim 1, wherein the target configuration comprises a loopback interface configuration, an equalization configuration, a rate switch, and an auto-negotiation configuration.

6. The chip configuration code testing system according to any one of claims 1 to 5, wherein the mediator includes a plurality of decorator functions, one of the application program interfaces corresponding to one of the decorator functions;

7. The chip configuration code test system according to any one of claims 1 to 5, wherein the evaluation board further comprises an IO interface;

8. A chip configuration code testing method implemented based on the chip configuration code testing system according to any one of claims 1 to 7, the method comprising:

9. The chip configuration code testing method according to claim 8, further comprising:

writing the execution result into a status register through an IP core;

10. The chip configuration code testing method according to claim 8 or 9, wherein the step of accessing the IP core using the input parameter includes: