CN114860219A - Configuration method, device and equipment of chip application routine and storage medium - Google Patents
Configuration method, device and equipment of chip application routine and storage medium Download PDFInfo
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- CN114860219A CN114860219A CN202110065297.XA CN202110065297A CN114860219A CN 114860219 A CN114860219 A CN 114860219A CN 202110065297 A CN202110065297 A CN 202110065297A CN 114860219 A CN114860219 A CN 114860219A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
- G06F3/0481—Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
- G06F3/0482—Interaction with lists of selectable items, e.g. menus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
- G06F3/0484—Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
- G06F3/04847—Interaction techniques to control parameter settings, e.g. interaction with sliders or dials
Abstract
The invention provides a configuration method, a configuration device, equipment and a storage medium of a chip application routine. The configuration method of the chip application routine comprises the following steps: displaying a mode configuration option; displaying chip configuration options of the selected mode in response to a selection operation of the mode configuration options; displaying application routine configuration options of the selected chip in response to a selection operation of the chip configuration options; the selected application routine is configured on the selected chip in response to a selection operation of the corresponding application routine configuration option. Compared with the prior art, the technical scheme provided by the invention has the beneficial effects that for example, different configuration modes are provided in a visual mode for a user to select, the chip application development modes are enriched, and for example, no matter which configuration mode is selected, handwritten codes can be replaced by the visual parameter configuration mode in the configuration process of the chip application routine, so that the reliability of the chip application development is improved.
Description
Technical Field
The present invention relates to the field of chip application routine configuration technologies, and in particular, to a method, an apparatus, a device, and a storage medium for configuring a chip application routine.
Background
With the increasing change of electronic information technology, the electronic products are updated more and more rapidly, so that the life cycle of the chip begins to exhibit a continuously shortened variation trend, which presents a very serious challenge to the chip design. The method not only needs to meet different requirements of updating and upgrading of electronic products on chip application in time, but also needs to reduce the development threshold of chip application and accelerate the research and development speed of chip products, thereby shortening the development time of the electronic products.
Chip applications typically require the configuration of attributes such as function, performance, etc. to a single or multiple chip pins by way of programming. At present, chip application mainly depends on configuration by a research and development personnel through a code handwriting mode. This approach is too dependent on the familiarity and development experience of the developers with the chip, and may result in different effects and design goals being achieved, thereby causing the project schedule to be affected. Moreover, when an application having the same function is developed across chips, it is necessary to newly become familiar with the characteristics of the chip and to newly develop the application.
Disclosure of Invention
The invention aims to provide a configuration method, a configuration device, equipment and a storage medium of a chip application routine.
The configuration method of the chip application routine provided by the embodiment of the invention comprises the following steps: displaying a mode configuration option; displaying chip configuration options of the selected mode in response to a selection operation of the mode configuration options; displaying application routine configuration options of the selected chip in response to a selection operation of the chip configuration options; the selected application routine is configured on the selected chip in response to a selection operation of the corresponding application routine configuration option.
Optionally, the mode configuration options include a normal mode option; the chip configuration options include example engineering options; displaying the application routine configuration options of the selected chip in response to the selection operation of the chip configuration options includes: displaying an example project list in response to a selection operation of an example project option; determining a chip corresponding to the selected example project as a selected chip in response to a selection operation on the example project list; the application routine configuration options for the selected chip are displayed.
Optionally, displaying the application routine configuration options of the selected chip comprises: initializing the selected chip; displaying the application routine configuration options of the selected chip after initialization.
Optionally, the application routine configuration options include a list of configurable application routines for the selected chip.
Optionally, the application routine configuration options include a list of routine configurable parameters; configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option includes: displaying a list of routine configurable parameters of the selected application routine in response to a selection operation on the list of configurable application routines; obtaining a parameter configuration scheme of the selected application routine in response to a selection operation on the routine configurable parameter list; and configuring the parameter configuration scheme to the selected chip.
Optionally, the application routines in the configurable application routine list have a default parameter configuration scheme; configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option includes: a parameter configuration scheme is configured to the selected chip in response to a selection operation of the list of configurable application routines.
Optionally, the parameter configuration scheme includes attribute information of pin configuration; configuring the parameter configuration scheme on the selected chip includes: obtaining a pin suitable for configuring attribute information in the selected chip; and configuring the attribute information to the pins.
Optionally, the mode configuration option comprises an expert mode option; the chip configuration options include a chip model option; displaying the application routine configuration options of the selected chip in response to the selection operation of the chip configuration options includes: displaying a chip model list in response to a selection operation of the chip model option; application routine configuration options for the selected chip are displayed in response to a selection operation on the chip model list.
Optionally, the chip configuration options include chip family options; the configuration method comprises the following steps: displaying a chip series list in response to a selection operation of the chip series option; a chip model option of the selected series is displayed in response to a selection operation of the chip series list.
Optionally, the application routine configuration options include a list of configurable peripherals of the selected chip.
Optionally, the application routine configuration options include a list of peripheral configurable parameters; configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option includes: displaying a peripheral configurable parameter list of the selected peripheral in response to a selection operation on the configurable peripheral list; obtaining a parameter configuration scheme of the selected peripheral in response to a selection operation on the peripheral configurable parameter list; creating a new application routine based on the selected peripheral and its corresponding parameter configuration scheme and configuring the parameter configuration scheme of the new application routine to the selected chip.
Optionally, the parameter configuration scheme includes attribute information of pin configuration; creating a new application routine includes: obtaining a pin suitable for configuring attribute information in the selected chip; generating a default configuration file for the new application routine based on the selected peripheral and its parameter configuration scheme, the configured pins and their attribute information.
Optionally, the configuration method further comprises publishing the new application routine into the example project.
Optionally, the parameter configuration scheme includes attribute information of pin configuration; configuring the parameter configuration scheme of the new application routine on the selected chip comprises: obtaining a pin suitable for configuring attribute information in the selected chip; and configuring the attribute information to the pins.
Optionally, displaying a chip display area to display pins of the selected chip in response to a selection operation of the chip configuration option, wherein the layout of the pins in the chip display area is consistent with the layout in the selected chip entity; configuring the attribute information to the pins includes highlighting the pins configured with the attribute information in the chip display area.
Optionally, configuring the attribute information to the pin includes: carrying out feasibility verification on the pins and attribute information thereof; and when the feasibility verification is passed, generating a corresponding configuration file for the selected chip, wherein the configuration file comprises the selected chip, the selected application routine and the parameter configuration scheme thereof, the configured pins and the attribute information thereof.
The configuration device for the chip application routine provided by the embodiment of the invention comprises: a first configuration module for displaying mode configuration options; the second configuration module is used for responding to the selection operation of the mode configuration option and displaying the chip configuration option of the selected mode; a third configuration module to display application routine configuration options for the selected chip in response to a selection operation of the chip configuration options; and the fourth configuration module is used for responding to the selection operation of the application program configuration option and configuring the selected application program to the selected chip.
The configuration device for the chip application routine provided by the embodiment of the invention comprises: a processor; a memory having stored thereon a computer program operable on the processor; wherein the computer program, when executed by the processor, implements the steps of the configuration method of the chip application routine provided by the embodiments of the present invention.
A computer-readable storage medium provided by an embodiment of the present invention stores a computer program, and when the computer program is executed, the computer program implements the steps of the configuration method of the chip application routine provided by the embodiment of the present invention.
Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effects. For example, different configuration modes are provided in a visual mode for a user to select, and the mode of chip application development is enriched.
For another example, no matter which configuration mode is selected, handwritten codes can be replaced by a visualized parameter configuration mode in the configuration process of the chip application routine, so that the reliability of chip application development is improved.
For another example, when the common mode is selected, the chip application can be rapidly developed based on a certain example engineering, so as to effectively reduce the threshold of the chip application development, accelerate the development speed of the chip product, and shorten the development time of the electronic product.
For another example, when the expert mode is selected, the chip application can be custom developed based on specific requirements to meet the diversified requirements of the chip application.
As another example, custom chip applications may also be deployed in the example project for common mode selection.
Drawings
FIG. 1 is a flow chart illustrating a method for configuring a chip application routine according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a layout of a visual creation interface according to an embodiment of the invention;
FIG. 3 is a schematic diagram of another layout of a visualization creation interface in an embodiment of the invention;
FIG. 4 is a schematic layout of a visual configuration interface according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another layout of a visual configuration interface according to an embodiment of the invention;
FIG. 6 is a functional block diagram of a configuration apparatus for a chip application routine in an embodiment of the present invention;
fig. 7 is a schematic block diagram of a configuration device for a chip application routine in an embodiment of the present invention.
Detailed Description
In the prior art, chip application mainly depends on configuration by a developer in a code handwriting mode. This approach is too dependent on the familiarity and development experience of the developers with the chip, and may result in different effects and design goals being achieved, thereby causing the project schedule to be affected. Moreover, when an application having the same function is developed across chips, it is necessary to newly become familiar with the characteristics of the chip and to newly develop the application.
Different from the prior art, embodiments of the present invention provide a method, an apparatus, a device, and a storage medium for configuring a chip application routine. The configuration method of the chip application routine comprises the following steps: displaying a mode configuration option; displaying chip configuration options of the selected mode in response to a selection operation of the mode configuration options; displaying application routine configuration options of the selected chip in response to a selection operation of the chip configuration options; the selected application routine is configured on the selected chip in response to a selection operation of the corresponding application routine configuration option.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the beneficial effect. For example, different configuration modes are provided in a visual mode for a user to select, and the mode of chip application development is enriched. For another example, no matter which configuration mode is selected, handwritten codes can be replaced by a visualized parameter configuration mode in the configuration process of the chip application routine, so that the reliability of chip application development is improved.
In order to make the objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments accompanied with figures are described in detail below.
Referring to fig. 1, a method for configuring a chip application routine provided in an embodiment of the present invention includes:
s1, displaying mode configuration options;
s2, responding to the selection operation of the mode configuration option, displaying the chip configuration option of the selected mode;
s3, responding to the selection operation of the chip configuration option, displaying the application routine configuration option of the selected chip;
s4, responding to the selection operation of the corresponding application program configuration option to configure the selected application program on the selected chip.
In a specific implementation of step S1, the mode configuration options may be displayed via a visual creation interface.
Referring to fig. 2 and 3, in some embodiments, the creation interface 100 of the visualization may include a create mode selection area 110 and a create mode configuration area 120. Wherein the creation mode selection area 110 is adapted to display mode configuration options, and the creation mode configuration area 120 is adapted to display chip configuration options of a corresponding creation mode.
In an embodiment of the present invention, the mode configuration options may include a general mode option 111 and an expert mode option 112.
In a specific implementation, the normal mode option 111 is adapted to be operated by a user to select the normal mode. Expert mode option 112 is adapted to be operated by a user to select expert mode. Wherein the generic mode is adapted to configure the chip based on the developed application routines and the expert mode is adapted to create new application routines to configure the chip.
In particular, the developed application routine is an application routine that has been developed and validated for feasibility and reliability, which reflects an example engineering of the developed chip application, and corresponding parameters are pre-configured to the chip to enable the chip to implement specific application functions, which may be issued by the manufacturer of the chip or by an expert chip designer. While a new application routine is an application routine that has not yet been developed, which can be newly created by selecting the expert mode.
In some embodiments, a typeface of "build from example" may be displayed in the area of the normal mode option 111 to indicate that the normal mode may configure the chip based on the application routines that have been developed. The wording "blank item" may also be displayed in the area of the expert mode option 112 to indicate that the expert mode may create a new application routine to configure the chip.
For convenience of description, the following description will be made separately for two cases of a user selecting a normal mode and a user selecting an expert mode.
First, a case where the user selects the normal mode is explained.
When a selection operation of the normal mode option 111 in the creation mode selection area 110 by the user is received, it may be determined that the normal mode is selected.
In some embodiments, the selection operation of the normal mode option 111 by the user may be an operation in which the user directly touches or clicks an area where the normal mode option 111 is located with a mouse.
Accordingly, in a specific implementation of step S2, the chip configuration options of the normal mode may be displayed in the creation mode configuration area 120 in response to a user selection operation of the normal mode option 111.
Corresponding to the normal mode option 111, the chip configuration options may include example engineering options.
In an embodiment of the invention, a chip may configure at least one application routine, including at least one developed application routine and/or at least one new application routine. At the same time, at least one chip may be used to configure application routines of the same functionality (i.e., application routines of the same functionality may be configured across chips), e.g., two or more chips may each be used to configure a ticker application.
In particular implementations, a developed application routine may serve as an example project that may reflect a functional application and the chip on which the application is configured.
Referring to FIG. 2, in some embodiments, example project options may include a drop down option 121 and/or a search option 122 adapted to be manipulated by a user to display an example project list 123.
In a specific implementation, the pull-down option 121 is adapted to be operated by a user to further select a chip.
In some embodiments, the operation performed by the user on the pull-down option 121 may be an operation in which the user directly touches or clicks the area where the pull-down option 121 is located with a mouse.
In some embodiments, the word "all routines" may be displayed in the area where the pull down option 121 is located to indicate that a desired configuration of chips may be selected from all example projects based on the pull down option 121.
In some embodiments, a list of example projects displayed based on operation of the drop-down option 121 may be displayed in the creation mode configuration area 120 and immediately below the drop-down option 121.
In particular implementations, the list of example projects displayed based on operation of the drop down option 121 may include all of the example projects. Specifically, each example project may be displayed in the example project list in order from top to bottom.
In some embodiments, the list of example projects displayed based on the manipulation of the drop-down option 121 may include at least one example project to implement the same function, where each example project corresponds to a different configuration chip. For example, the example project list includes two example projects for implementing the ticker function, specifically example project a and example project B, where the ticker application in example project a is configured on chip a, and the ticker application in example project B is configured on chip B.
Further, the selected example project and its corresponding selected chip may be determined based on a user selection operation of the example project list. For example, the selected example project may be determined to be a ticker application routine configured on chip a based on a user selection operation of example project a in the example project list, and the chip a corresponding to the example project may be determined to be the selected chip.
In a specific implementation, the search option 122 is also adapted to be manipulated by the user to further select the chip.
In some embodiments, the user's operation of search option 122 may be an operation of entering a desired configuration of application routines and/or chips in search option 122 using a keyboard. In a specific implementation, words related to application routines and/or chips for which configuration is desired may be entered, for example, "ticker" may be entered in search option 122 when configuration of a chip for which a ticker application has been developed is desired, and "smart appliance" may be entered in search option 122 when, for example, a chip for which configuration is desired is applied to a smart appliance.
In some embodiments, a word "mass chip application routine for you to select" may be displayed in the area of the search option 122 to indicate that a chip of a desired configuration may be searched from all of the example projects based on the search option 122.
In particular implementations, matching example projects may be searched from the total of example projects for display in the example project list in response to operation of search option 122.
In some embodiments, a list of example projects 123 displayed based on operation of the search option 122 may be displayed in the creation mode configuration area 120 and below the example project options.
In some embodiments, the example project list 123 displayed based on operation of the search option 122 may include at least one example project that matches a chip of a desired configuration. For example, it is desirable to configure a chip in which a ticker application has been developed, and two example projects matching therewith, specifically, example project a and example project B, can be searched in all the example projects, wherein the ticker application in example project a is configured in chip a and the ticker application in example project B is configured in chip B, and thus, the example project a and the example project B can be included in the example project list 123 displayed based on the operation of the search option 122. Specifically, these example projects may be displayed in sequence in the example project list 123 in the manner of icons.
Further, the selected example project and its corresponding selected chip may be determined based on user manipulation of the example project list 123. For example, the selected example project may be determined to be a ticker application routine configured on chip B based on a user selection operation of example project B in the example project list 123, and the chip B corresponding to the example project may be determined to be the selected chip.
Accordingly, in a specific implementation of step S3, displaying the application configuration options for the selected chip in response to the selection operation of the chip configuration options includes:
s311, displaying an example project list in response to the operation of the example project option;
s312, in response to the selection operation of the example project list, determining the chip corresponding to the selected example project as the selected chip;
s313, displaying the application routine configuration options of the selected chip.
Since the chips in the example project have been pre-configured with the corresponding parameters, i.e., have a default parameter configuration scheme, in some embodiments, displaying the application routine configuration options for the selected chip may include:
s3131, initializing the selected chip;
s3132, displaying the application routine configuration options of the selected chip after initialization.
In this way, the default parameter configuration scheme of the selected chip can be cancelled by initializing the chip, so that a new parameter configuration scheme can be subsequently reconfigured to the chip according to specific requirements. For example, the selected example project is a ticker application routine configured on a chip a, wherein the chip a has been pre-configured with a default scheme with parameters of a ticker mode of reciprocating back and forth, a ticker number of times of cycling for one hundred times, and the like, and the configured default scheme can be cancelled by initializing the chip a, so that a specific scheme of the ticker application can be reconfigured according to specific requirements later.
In a particular implementation, application routine configuration options for a selected chip may be displayed via a visual configuration interface.
Referring to FIG. 4, in some embodiments, the visualized configuration interface 200 may include an application routine configuration area 210 for displaying application routine configuration options for the selected chip.
Corresponding to the normal mode option 111, the application routine configuration options may include a list 211 of configurable application routines for the selected chip.
In a specific implementation, all application routines that are configurable for the selected chip may be included in the configurable application routine list 211 of the chip, and these application routines are developed application routines.
In some embodiments, the various application routines in the configurable application routine list 211 may be displayed in the application routine configuration area 210 sequentially from top to bottom.
In a specific implementation, the list of configurable application routines 211 is adapted to be operated by a user to select application routines of a desired configuration.
In some embodiments, the operation performed by the user on the configurable application routine list 211 may be an operation in which the user directly touches or clicks an area in the configurable application routine list 211 where an application routine desired to be configured is located with a mouse.
Referring to fig. 4, for example, the configurable application routine list 211 of the selected chip (i.e., the current chip) may include N application routine options, i.e., ATIM _ PWM option, ATIM _ Capture option, ATIM _ Timing option … … I2C _ EEPROM option, I2C _ slave _ Master option, I2C _ slave tx option … …. Where I2C _ slave tx is an application routine that is desired to be configured on the selected chip, the user may operate on the area where the I2C _ slave tx option is located to select I2C _ slave tx as the application routine that is desired to be configured, i.e., the selected application routine.
In particular implementations, each application routine in the list of configurable application routines 211 has a default parameter configuration scheme.
Accordingly, in a specific implementation of step S4, configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option may include:
s41, configuring the default parameter configuration scheme of the selected application routine to the selected chip in response to the selection operation of the configurable application routine list 211.
In the embodiment of the invention, not only the default parameter configuration scheme of the selected application routine can be directly configured on the selected chip, but also a new configuration parameter scheme can be reselected according to specific requirements to be configured on the selected chip.
In particular implementations, the application routine configuration options may also include a list of routine configurable parameters for the selected application routine.
Accordingly, in a specific implementation of step S4, configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option includes:
s411, responding to the selection operation of the configurable application routine list, displaying a routine configurable parameter list of the selected application routine;
s412, responding to the selection operation of the routine configurable parameter list to obtain a parameter configuration scheme of the selected application routine;
s413, configuring the parameter configuration scheme to the selected chip.
In particular implementations, a list of routine configurable parameters of the selected application routine may also be displayed via the visualized configuration interface 200. In particular, the visualized configuration interface 200 may further include a parameter configuration area 220 for displaying a list 221 of routine configurable parameters of the selected application routine.
In particular implementations, all configurable parameters of the selected application routine may be included in the routine configurable parameter list 221. Specifically, the configurable parameters may be displayed in the parameter configuration area 220 from top to bottom.
In particular implementations, routine configurable parameter list 221 is adapted to be manipulated by a user to select a corresponding configurable parameter.
In some embodiments, the selection operation performed by the user on the routine configurable parameter list 221 may be an operation of directly touching or clicking an area in which a corresponding configuration parameter in the routine configurable parameter list 221 is located through a mouse.
Further, in response to a user selecting the routine configurable parameter list 221, an input option may be provided to obtain a configuration scheme for the configuration parameter.
In a specific implementation, the input option is adapted to be operated by a user to input a configuration scheme for the configuration parameter. For example, the configurable parameter of the ticker application may include a horse race mode, the routine configurable parameter list 221 includes a horse race mode option, and the user may input "reciprocate back and forth" as a configuration scheme of the horse race mode based on an operation on the horse race mode option.
In some embodiments, the configuration scheme of the at least one configurable parameter of the selected application routine may be obtained in the manner described above. These placement schemes are subsequently placed on the selected chip.
In some embodiments, a code paste option may also be included in the routine configurable parameter list 221, which is adapted to be manipulated by a user to enter a code to configure a selected chip.
In some embodiments, the configurable parameters of the selected application routine comprise configurable parameters of a pin. Accordingly, the parameter configuration scheme of the selected application routine includes attribute information of the pin configuration.
In some embodiments, the attribute information of the pin configuration may reflect the function of the pin, such as ground, serial, clock, timer, pull-up, pull-down, etc.
Accordingly, in an implementation of step S413, configuring the parameter configuration scheme to the selected chip may include:
s4131, obtaining pins suitable for configuring corresponding attribute information in the selected chip;
s4132, configuring the corresponding attribute information to the obtained pins.
In a specific implementation, configuring the corresponding attribute information to the obtained pins may include:
carrying out feasibility verification on the pin and the attribute information thereof;
and when the feasibility verification is passed, generating a corresponding configuration file for the selected chip, wherein the configuration file comprises the selected chip, the selected application routine and the parameter configuration scheme thereof, the configured pins and the attribute information thereof.
In the embodiment of the present invention, the feasibility verification of the pins and the attribute information thereof is implemented by using a conventional technical means in the field, and details are not described here.
Referring to fig. 4, in some embodiments, the visualized configuration interface 200 may further include a chip display area 230 for displaying pins of the selected chip, and the layout of the displayed pins in the chip display area 230 is consistent with the layout of the pins in the selected chip entity.
Correspondingly, the configuration method of the chip application routine provided by the embodiment of the present invention may further include:
the chip show area is displayed to show pins of the selected chip in response to a selection operation of the chip configuration option.
Accordingly, configuring the corresponding attribute information to the obtained pin may further include:
the pins to which the attribute information has been configured are highlighted in the chip presentation area 230.
In some embodiments, conflicts in pin configuration may arise when multiple application routines are configured for the same chip, in which case the conflicting pins may also be highlighted.
In a particular implementation, pins that have successfully configured attributes and pins that have generated configuration conflicts may be highlighted in different colors.
In a specific implementation, a plurality of pins can be simultaneously suitable for configuring the same attribute information, and when the pin configuration conflicts, other pins can be reselected to configure the attribute information.
Next, a case where the user selects the expert mode is explained.
When a selection operation of the user for the expert mode option 112 in the creation mode selection area 110 is received, it may be determined that the expert mode is selected.
In some embodiments, the user's selection of the expert mode option 112 may be a user directly touching or clicking with a mouse on the area where the expert mode option 112 is located.
Accordingly, in a specific implementation of step S2, the expert-mode chip configuration options may be displayed in the creation mode configuration area 120 in response to a user selection operation of the expert-mode option 112.
Corresponding to expert mode option 112, chip configuration options may include chip model option 124.
In a specific implementation, chip model option 124 is adapted to be manipulated by a user to display a list of chip models.
In some embodiments, the user's selection of the chip model option 124 may be a user's direct touch or clicking with a mouse on the area where the chip model option 124 is located.
In some embodiments, chip model option 124 may be a drop-down option, and a list of chip models may be displayed in create mode configuration area 120 in response to operation of the drop-down option.
In a specific implementation, the chip model list may include all selectable chip models, and each chip model may be sequentially displayed in the chip model list from top to bottom.
Accordingly, in a specific implementation of step S3, displaying the application routine configuration options of the selected chip in response to the selection operation of the chip configuration options includes:
s321, displaying a chip model list in response to a selection operation of the chip model option;
s322, in response to the selection operation to the chip model list, the application routine configuration options of the selected chip are displayed.
In a specific implementation, the list of chip models is also adapted to be manipulated by a user to select a chip of a desired configuration model.
In some embodiments, the operation of selecting the chip model list by the user may be an operation of directly touching or clicking an area where a corresponding chip model in the chip model list is located by using a mouse. Application routine configuration options for a chip of the selected model (i.e., the selected chip) may be displayed in response to a selection operation on the chip model list.
In some embodiments, the chip configuration options may also include a chip family option 125.
Correspondingly, the configuration method of the chip application routine provided by the embodiment of the invention further comprises the following steps:
s323 displaying a chip series list in response to a selection operation of the chip series option;
s324, in response to a selection operation to the list of chip series, a chip model option of the selected series is displayed.
In a specific implementation, the chip family option 125 is also adapted to be manipulated by a user to select a chip family of a desired configuration.
In some embodiments, the operation performed by the user on the chip series option 125 may be an operation in which the user directly touches or clicks the area where the chip series option 125 is located by using a mouse.
In some embodiments, the chip family option 125 may be a drop-down option, and a list of chip families may be displayed in the creation mode configuration area 120 in response to operation of the drop-down option.
In a specific implementation, all the selectable chip series may be included in the chip series list, and each chip series may be sequentially displayed in the chip series list from top to bottom.
In a specific implementation, the list of chip families is also adapted to be manipulated by the user to select a chip model of the selected family.
In some embodiments, the selection operation performed by the user on the chip series list may be an operation in which the user directly touches or clicks an area in the chip series list where the corresponding chip series is located with a mouse. A chip model option 124 or a chip model list of the selected series may be displayed in response to a selection operation of the chip series list.
In some embodiments, the chip configuration options may also include an engineering name option 126. Project name option 126 is adapted to be manipulated by a user to enter a project name.
In some embodiments, the chip configuration options may also include a create engineering option 127. The create engineering option 127 is adapted to be manipulated by a user to display application routine configuration options for a selected chip.
In a particular implementation, application routine configuration options for a selected chip may be displayed via a visual configuration interface.
Referring to FIG. 5, in some embodiments, the visualized configuration interface 200 may include an application routine configuration area 210 for displaying application routine configuration options for the selected chip.
Corresponding to the expert mode option 112, the application routine configuration options may include a list of configurable peripherals 212 for the selected chip.
In a particular implementation, all configurable peripherals of the chip are included in the configurable peripheral list 212 of the selected chip. Specifically, each configurable peripheral is an internal peripheral of the chip.
In some embodiments, each configurable peripheral in the list of configurable peripherals 212 may be displayed in the application routine configuration area 210 sequentially from top to bottom.
In particular implementations, the list of configurable peripherals 212 is adapted to be manipulated by a user to select a desired configuration of peripherals.
In some embodiments, the user's selection of the configurable peripheral list 212 may be a user directly touching or clicking with a mouse on an area of the configurable peripheral list 212 where a peripheral desired to be configured is located.
Referring to fig. 5, for example, the configurable peripheral list 212 of the selected chip (i.e., the current chip) may include N peripheral options, respectively AES option, ATM option, ADC option … … I2C option, UART0 option … …. The UART0 is a peripheral of a desired configuration, and the user can operate the area where the UART0 option is located to select the UART0 as the peripheral of the desired configuration, i.e., the selected peripheral.
Further, the specific scheme configuration of the selected peripheral is required.
Accordingly, in a specific implementation of step S4, configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option includes:
s421, responding to the selection operation of the configurable peripheral list and displaying the peripheral configurable parameter list of the selected peripheral;
s422, responding to the selection operation of the peripheral configurable parameter list to obtain the parameter configuration scheme of the selected peripheral;
s423, creating a new application routine based on the selected peripheral and the corresponding parameter configuration scheme thereof and configuring the parameter configuration scheme of the new application routine to the selected chip.
In particular implementations, the visualized configuration interface 200 may include a parameter configuration area 220 for displaying a list 222 of peripheral configurable parameters for the selected peripheral.
In particular implementations, all of the configurable parameters of the selected peripheral may be included in the peripheral configurable parameter list 222. Specifically, each configurable parameter may be displayed in the parameter configuration area 220 from top to bottom in sequence.
In a particular implementation, the peripheral configurable parameter list 222 is adapted to be manipulated by a user to select parameters of a desired configuration.
In some embodiments, the operation of selecting the peripheral configurable parameter list 222 by the user may be an operation of directly touching or clicking with a mouse an area in the peripheral configurable parameter list 222 where the parameter desired to be configured is located. A specific configuration scheme for the selected parameter may be obtained in response to the operation. For example, in response to the operation, corresponding input options may be displayed in the parameter configuration area 220 for the user to input a particular configuration scheme for the selected parameter.
In some embodiments, the configuration scheme of the at least one configurable parameter of the selected peripheral may be obtained in the manner described above. The configuration schemes are configured on the selected chip to form a parameter configuration scheme for the selected peripheral.
In some embodiments, the parameter configuration scheme of the at least one peripheral device may be obtained in the above manner. These parameter configuration schemes are used to create new application routines and to configure the selected chips.
In a specific implementation, the configurable parameters of the selected peripheral include configurable parameters of pins. Accordingly, the parameter configuration scheme of the selected peripheral may include attribute information of the pin configuration.
Accordingly, in a specific implementation of step S423, creating a new application routine based on the selected peripheral and its corresponding parameter configuration scheme includes:
s4231, obtaining pins suitable for configuring corresponding attribute information in the selected chip;
s4232, generating a default configuration file about the new application routine based on the selected peripheral and the parameter configuration scheme thereof, the configured pins and the attribute information thereof.
Further, the configuration method of the chip application routine provided by the embodiment of the present invention may further include:
new application routines are published into the example project.
In particular implementations, a feasibility and reliability audit is also required before a new application routine is released to an example project to ensure that the application routine released to the example project is truly valid.
In the embodiment of the present invention, the feasibility and reliability of the application program may be checked by using a conventional technical means in the field, and details are not described here.
Accordingly, in a specific implementation of step S423, configuring the parameter configuration scheme of the new application routine to the selected chip may include:
s4233, obtaining pins suitable for configuring corresponding attribute information in the selected chip;
s4234, configuring the corresponding attribute information to the obtained pin.
In a specific implementation, configuring the corresponding attribute information to the obtained pins may include:
carrying out feasibility verification on the pin and the attribute information thereof;
and when the feasibility verification is passed, generating a corresponding configuration file for the selected chip, wherein the configuration file comprises the selected chip, the selected application routine and the parameter configuration scheme thereof, the configured pins and the attribute information thereof.
In the embodiment of the present invention, the feasibility verification of the pins and the attribute information thereof may be implemented by using a conventional technical means in the field, and details are not described here.
Referring to fig. 5, in some embodiments, the visualized configuration interface 200 may further include a chip display area 230 for displaying pins of the selected chip, and the layout of the displayed pins in the chip display area 230 is consistent with the layout of the pins in the selected chip entity.
Correspondingly, the configuration method of the chip application routine provided by the embodiment of the invention further comprises the following steps:
the chip show area is displayed to show pins of the selected chip in response to a selection operation of the chip configuration option.
Accordingly, configuring the corresponding attribute information to the obtained pin may further include:
the pins to which the attribute information has been configured are highlighted in the chip presentation area 230.
In some embodiments, conflicts in pin configuration may arise when multiple application routines are configured for the same chip, in which case the conflicting pins may also be highlighted.
In a particular implementation, pins that have successfully configured attributes and pins that have generated configuration conflicts may be highlighted in different colors.
In a specific implementation, a plurality of pins can be simultaneously suitable for configuring the same attribute information, and when the pin configuration conflicts, other pins can be reselected to configure the attribute information.
In some embodiments, the creation interface 100 may also be returned from the configuration interface 200 for expert mode for the user to reselect to normal mode. Likewise, the creation interface 100 may also be returned from the configuration interface 200 for the normal mode for the user to reselect the expert mode.
In some embodiments, the method for configuring the chip application routine may further include:
displaying a project management interface, wherein the project management interface is suitable for displaying application routines configured by a user so that the user can directly select the corresponding application routines to be configured on the chip or select the corresponding application routines to modify the configuration parameters of the application routines.
The embodiment of the invention also provides a configuration device of the chip application routine.
Referring to fig. 6, the configuration apparatus 300 of the chip application routine may include a first configuration module 310, a second configuration module 320, a third configuration module 330, and a fourth configuration module 340.
Specifically, the first configuration module 310 is used to display the mode configuration options; the second configuration module 320 is used for responding to the selection operation of the mode configuration option and displaying the chip configuration option of the selected mode; the third configuration module 330 is used for displaying the application routine configuration options of the selected chip in response to the selection operation of the chip configuration options; the fourth configuration module 340 is used for configuring the selected application routine on the selected chip in response to the selection operation of the corresponding application routine configuration option.
The embodiment of the invention also provides configuration equipment of the chip application routine.
Referring to fig. 7, the configuration apparatus 400 of the chip application routine may include a processor 410 and a memory 420.
In particular, the memory 420 has stored thereon a computer program that is executable on the processor 410; wherein the computer program, when executed by the processor, implements the steps of the configuration method of the chip application routine provided by the embodiments of the present invention.
Embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed, the steps of the configuration method of the chip application routine provided in the embodiments of the present invention are implemented.
In a specific implementation, the configuration method of the chip application routine provided by the embodiment of the present invention may further support online, offline, and background active updates through conventional technical means in the field.
In the embodiment of the present invention, step numbers are labeled in some steps of the configuration method of the chip application routine, for example, S1, S2, S3, S4, S311 … …, and these step numbers are only used to facilitate the description of the configuration method, and are not used to limit the execution order of the steps in the configuration method.
While specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even if only a single embodiment is described with respect to a particular feature. The characteristic examples provided in the present disclosure are intended to be illustrative, not limiting, unless differently stated. In particular implementations, the features of one or more dependent claims may be combined with those of the independent claims as technically feasible according to the actual requirements, and the features from the respective independent claims may be combined in any appropriate manner and not merely by the specific combinations enumerated in the claims.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.
Claims (19)
1. A method for configuring a chip application routine, comprising:
displaying a mode configuration option;
displaying chip configuration options of the selected mode in response to a selection operation of the mode configuration options;
displaying application routine configuration options of the selected chip in response to a selection operation of the chip configuration options;
configuring the selected application routine to the selected chip in response to a selection operation of the application routine configuration option.
2. The configuration method of claim 1, wherein the mode configuration option comprises a normal mode option; the chip configuration options include example engineering options; the displaying of the application routine configuration options of the selected chip in response to the selection operation of the chip configuration options comprises:
displaying an example project list in response to a selection operation of the example project option;
determining a chip corresponding to the selected example project as a selected chip in response to a selection operation on the example project list;
the application routine configuration options for the selected chip are displayed.
3. The configuration method of claim 2, wherein displaying application routine configuration options for the selected chip comprises:
initializing the selected chip;
displaying the application routine configuration options of the selected chip after initialization.
4. The configuration method of claim 2, wherein the application routine configuration options include a list of configurable application routines for the selected chip.
5. The configuration method of claim 4, wherein the application routine configuration options include a list of routine configurable parameters; said configuring the selected application routine on the selected chip in response to the selection operation of the application routine configuration option comprises:
displaying a list of routine configurable parameters of the selected application routine in response to a selection operation on the list of configurable application routines;
obtaining a parameter configuration scheme for the selected application routine in response to a selection operation on the routine configurable parameter list;
and configuring the parameter configuration scheme to the selected chip.
6. The configuration method according to claim 4, wherein the application routines in the list of configurable application routines have a default parameter configuration scheme; said configuring the selected application routine on the selected chip in response to the selection operation of the application routine configuration option comprises:
configuring the parameter configuration scheme to the selected chip in response to a selection operation of the list of configurable application routines.
7. The configuration method according to claim 5 or 6, wherein the parameter configuration scheme includes attribute information of pin configuration; configuring the parameter configuration scheme on the selected chip includes:
obtaining a pin suitable for configuring the attribute information in the selected chip;
and configuring the attribute information to the pin.
8. The configuration method of claim 1, wherein the mode configuration option comprises an expert mode option; the chip configuration options include a chip model option; the displaying of the application routine configuration options of the selected chip in response to the selection operation of the chip configuration options comprises:
displaying a chip model list in response to a selection operation of the chip model option;
displaying application routine configuration options of the selected chip in response to a selection operation of the chip model list.
9. The configuration method of claim 8, wherein the chip configuration options include a chip family option; the configuration method comprises the following steps:
displaying a chip series list in response to a selection operation of the chip series option;
displaying the chip model options of the selected series in response to a selection operation of the chip series list.
10. The configuration method of claim 8, wherein the application routine configuration options include a list of configurable peripherals of the selected chip.
11. The configuration method of claim 10, wherein the application routine configuration options include a list of peripheral configurable parameters; said configuring the selected application routine on the selected chip in response to the selection operation of the application routine configuration option comprises:
displaying a peripheral configurable parameter list of the selected peripheral in response to a selection operation of the configurable peripheral list;
obtaining a parameter configuration scheme of the selected peripheral in response to a selection operation on the peripheral configurable parameter list;
a new application routine is created based on the selected peripheral and its corresponding parameter configuration scheme and the parameter configuration scheme of the new application routine is configured on the selected chip.
12. The configuration method according to claim 11, wherein the parameter configuration scheme includes attribute information of pin configuration; the creating of the new application routine comprises:
obtaining a pin suitable for configuring the attribute information in the selected chip;
generating a default configuration file for the new application routine based on the selected peripheral and its parameter configuration scheme, the configured pins and their attribute information.
13. A method of configuring as claimed in claim 11 or 12, comprising publishing the new application routine to an example project.
14. The method according to claim 11, wherein the parameter configuration scheme includes attribute information of pin configuration; configuring the parameter configuration scheme of the new application routine on the selected chip comprises:
obtaining a pin suitable for configuring the attribute information in the selected chip;
and configuring the attribute information to the pin.
15. The configuration method of claim 14, comprising displaying a chip show area to show pins of the selected chip in response to a selection operation of the chip configuration option, a layout of the pins in the chip show area being consistent with a layout in a physical object of the selected chip;
configuring the attribute information to the pins includes highlighting the pins configured with the attribute information in the chip display area.
16. The method of claim 14, wherein configuring the attribute information to the pin comprises:
carrying out feasibility verification on the pins and attribute information thereof;
and when the feasibility verification is passed, generating a corresponding configuration file for the selected chip, wherein the configuration file comprises the selected chip, the selected application routine and the parameter configuration scheme thereof, the configured pins and the attribute information thereof.
17. An apparatus for configuring a chip application routine, comprising:
a first configuration module for displaying mode configuration options;
the second configuration module is used for responding to the selection operation of the mode configuration option and displaying the chip configuration option of the selected mode;
a third configuration module to display application routine configuration options of the selected chip in response to a selection operation of the chip configuration options;
a fourth configuration module to configure the selected application routine to the selected chip in response to a selection operation of the application routine configuration option.
18. A configuration apparatus for a chip application routine, comprising:
a processor;
a memory having stored thereon a computer program operable on the processor;
wherein the computer program realizes the steps of the configuration method according to any one of claims 1 to 16 when executed by the processor.
19. A computer-readable storage medium, storing a computer program, characterized in that the computer program, when executed, implements the steps of the configuration method according to any of claims 1 to 16.
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