CN114846785A

CN114846785A - Image forming apparatus and image forming method

Info

Publication number: CN114846785A
Application number: CN201980103051.8A
Authority: CN
Inventors: 樱木孝正
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2022-08-02
Also published as: WO2021127809A1

Abstract

An embodiment of the present application may relate to an imaging apparatus including a comparator, a pixel, and a control circuit, wherein the comparator includes a switch, a first transistor, and a first capacitor, wherein the first capacitor is charged when the switch is turned on, and wherein the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit using power charged in the first capacitor after the switch is turned off, and outputs an output signal.

Description

Image forming apparatus and image forming method

Technical Field

The embodiments described below relate to an imaging apparatus/method for still images and/or movies, for example.

Background

Imaging apparatuses and imaging methods for still images and/or movies are generally widely used. Imaging devices such as digital cameras, cellular phones, terminal equipment, and automobiles (in-vehicle cameras), but are not limited thereto.

Disclosure of Invention

The present disclosure including the aspects shown below may relate to an imaging apparatus/method for still images and/or movies, for example. It is to be understood that the following disclosure is not intended to limit or restrict the pending application/invention.

A first aspect is an imaging apparatus including a comparator, a pixel, and a control circuit, wherein the comparator includes a switch, a first transistor, and a first capacitor, wherein the first capacitor is charged when the switch is turned on, and wherein the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit using power charged in the first capacitor after the switch is turned off, and outputs an output signal.

A second aspect is the imaging apparatus according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

A third aspect is the imaging apparatus according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

A fourth aspect is the imaging device according to the above aspect, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

A fifth aspect is the imaging device according to the above aspect, wherein the first transistor flows a bias current to drive the comparator when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor.

A sixth aspect is the imaging device according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

A seventh aspect is the imaging device according to the above aspect, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

An eighth aspect is the imaging apparatus according to the above aspect, wherein the comparator is disconnected from a common power source of the imaging apparatus when the switch is turned off.

A ninth aspect is the imaging apparatus according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

A tenth aspect is the imaging apparatus according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

An eleventh aspect is an imaging method for an imaging apparatus including a comparator, a pixel, and a control circuit, the imaging method comprising: charging a first capacitor of the comparator when a switch of the comparator is turned on; comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor after the switch is turned off; and outputting the output signal.

A twelfth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

A thirteenth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

A fourteenth aspect is the imaging method according to the above aspect, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

A fifteenth aspect is the imaging method according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.

A sixteenth aspect is the imaging method according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

A seventeenth aspect is the imaging method according to the above aspect, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

An eighteenth aspect is the imaging method according to the above aspect, wherein the comparator is disconnected from a common power source of the imaging device when the switch is turned off.

A nineteenth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

A twentieth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

The above disclosure does not limit or restrict the present application/invention.

Drawings

Fig. 1 is a schematic view of an imaging apparatus described in one embodiment.

Fig. 2 is a circuit diagram of an embodiment.

FIG. 3 is a timing diagram of one embodiment.

Fig. 4 is a circuit diagram of an embodiment.

FIG. 5 is a timing diagram of one embodiment.

Detailed Description

The following disclosure includes examples only. The scope of the invention and application should not be considered as being limited by the embodiments shown below.

FIG. 1 shows a schematic view of an imaging apparatus of an embodiment. The imaging apparatus 100 includes a camera module 110, a pixel 120, an analog to digital (AD) converter 130, and a timing generator (T/G) 140. Imaging device 100 may include logic circuit 150 in place of T/G140. The imaging device 100 may also include a set of lenses, a battery, a memory, and a screen or panel, among others. The imaging device 100 may also include a processor, hard disk, optical drive, transceiver, speaker, microphone, and the like.

The camera module 110 includes pixels 120, an AD converter 130, and a T/G140. As described above, the T/G140 may be replaced with a logic circuit 150 external to the camera module 110. The camera module 110 may be the image sensor circuit shown in fig. 2.

The pixels 120 may be Complementary Metal Oxide Semiconductor (CMOS) image sensors, Charge Coupled Device (CCD) image sensors, or other devices. The pixel 120 may be composed of a plurality of pixels. The pixel 120 may further include a color filter. The pixel 120 receives light through a lens not shown in the figure and outputs an analog signal corresponding to the intensity of the received light.

The AD converter 130 is input with an analog signal from the pixel 120 and outputs a digital signal indicating the intensity of light received by the pixel 120. A processor not shown in the figure may receive the digital signal from the AD converter 130 and generate image data. The processor may store the image data in, for example, a memory. The image data may be a still image or a part of a movie.

The T/G140 (or the logic circuit 150) outputs a pulse signal indicating an operation timing based on which the constituent elements of the imaging apparatus 100 operate. For example, when a timing signal is input from the T/G140 (or the logic circuit 150), the AD converter 130 may compare the voltage of the analog signal output from the pixel 120 with a reference voltage not shown in fig. 1.

Hereinafter, details of the AD converter 130 are explained with reference to the drawings.

The imaging device may include an AD converter, for example, a single slope analog to digital converter (SS ADC). In general, it is desirable to reduce the power consumption of SS ADCs without causing side effects.

For example, the power consumption of the AD converter (except for the SS ADC) can be reduced only by reducing the bias current of the comparator included in the AD converter. One example of a bias circuit that reduces power consumption is implemented using a dynamic bias circuit. On the other hand, less bias current may degrade the performance of the comparator (e.g., analog-to-digital conversion performance): reduced speed, increased noise and/or reduced AD accuracy.

As described above, in general, it is desirable to reduce power consumption of an ADC. It should be noted that it is not an optimal choice to apply a dynamic bias circuit of the comparator, which can reduce the power consumption of the AD converter, to the SS ADC.

Because in general a comparator with a dynamic bias circuit can compare input signals corresponding to input digital signals, which cannot be generated during AD conversion operations in an SS ADC.

In general, dynamically biasing the comparators may cause large "stripe noise". This is because the dynamic bias circuit causes a large variation in the supply current of the comparator. This may negatively affect the image quality.

Hereinafter, the first embodiment will be explained. Fig. 2 shows an image sensor circuit including two input pixel signal lines (Vpixel1 and Vpixel2) and two single slope ADCs. The image sensor circuits shown in fig. 2 show a simplified structure in order to explain their operation more easily. In practical image sensors, more ADCs are required to be placed, which are typically column-wise to accommodate the number of pixel signal outputs. The image sensor circuit shown in fig. 2 corresponds to the camera module shown in fig. 1.

Input pixel signal lines Vpixel1 and Vpixel2 are included in the pixels 120 shown in fig. 1. Each of the input pixel signal lines Vpixel1 and Vpixel2 corresponds to one pixel. I1 and I2 shown in fig. 2 are comparators. The comparator I1 receives signals from pixels not shown in fig. 2 through an input pixel signal line Vpixel 1. The comparator I2 inputs a signal from a pixel not shown in fig. 2 through an input pixel signal line Vpixel 1.

VRAMP1 and VRAMP2 shown in fig. 2 represent ramp reference voltages provided by lines. Comparator I1 receives the ramp reference voltage VRAMP1 from terminal 3. Comparator I1 receives the ramp reference voltage VRAMP2 from terminal 2. The comparator 2 has the same structure as the comparator I1. The ramp reference voltages VRAMP1 and VRAMP2 may be output from a control circuit (e.g., the logic circuit 150 shown in fig. 1) not shown in fig. 2.

VDD _ common shown in fig. 2 is a common power source shared with all or part of the comparators. The comparator I1 receives the common power supply VDD _ common through the terminal 1 and performs its operation. The comparator I2 has the same structure as the comparator I1. The common power supply VDD _ common may be supplied with power from a power supply circuit not shown in the drawing.

The comparator I1 receives the ramp reference voltage VRAMP1/VRAMP2 and the input pixel voltage (hereinafter, Vpixel1 for ease of understanding), and performs a comparison operation. The comparator I1 outputs a signal indicating its comparison result from the terminal Vout1 shown in fig. 2. The comparator I2 outputs a signal indicating its comparison result from the terminal Vout2 shown in fig. 2.

Comparator I1 includes transistors M1, M2, M3, M4, M6, M7, M8, M9, and M10. The comparator I1 includes capacitors Cp, C _G And Cs. Comparator I1 includes switch SW 1. Comparator I1 includes terminals 1 through 5. Terminal 1 is connected to a common power supply VDD _ common. Terminal 2 receives a ramp reference voltage VRAMP 2. Terminal 3 receives a ramp reference voltage VRAMP 1. The terminal 4 is connected to the input pixel signal line Vpixel 1. The output signal from the comparator I1 is output from the terminal 5 and supplied to the counter circuit I3.

The comparator I2 has substantially the same structure as the comparator I1. There is little difference between them. A terminal 4 of the comparator I2 is connected to the input pixel signal line Vpixel2, and an output signal of the comparator I2 is supplied to the counter circuit I4 through a terminal 5.

The counter circuit I3 receives an output signal from the terminal Vout 1. The counter circuit I3 receives a clock signal (CLK). The counter circuit I3 counts clocks included in the clock signal for a predetermined period of time, while the counter circuit detects an output signal from the terminal Vout 1. The clock signal (CLK) may be output by a control circuit (e.g., the logic circuit 150 of fig. 1) shown in the drawings.

The counter circuit I4 receives an output signal from the terminal Vout 2. The counter circuit I4 receives a clock signal (CLK). The counter circuit 4 counts clocks included in the clock signal for a predetermined period of time, while the counter circuit detects an output signal from the terminal Vout 1. The clock signal (CLK) may be provided by a control circuit (e.g., the logic circuit 150 of fig. 1) shown in the figures.

The operation of the image sensor circuit shown in fig. 2 is described with reference to the timing chart shown in fig. 3. In fig. 3, it is assumed that a first pixel signal level (hereinafter, Vpixel1 for ease of understanding) corresponding to the input pixel signal line Vpixel1 is lower than a second pixel signal level (hereinafter, Vpixel2 for ease of understanding) corresponding to the input pixel signal line Vpixel 2. In actual use, the first pixel signal level Vpixel1 may be higher than the second pixel signal level Vpixel2 or the same as the second pixel signal level Vpixel 2. The horizontal axis of fig. 3 is the time axis.

In fig. 3, the ramp reference voltage VRAMP2 is higher than the ramp reference voltage VRAMP1 and accurately tracks the ramp reference voltage VRAMP1 at a predetermined offset level (Vth). The ramp reference voltage VRAMP1 is initially at a predetermined initial level (Vinit). At a predetermined timing, the ramp reference voltage VRAMP1 begins to ramp up from Vinit at a constant rate. For example, when the user operates the imaging device to take a picture or a movie, the ramp reference voltage starts to ramp up. When the ramp reference voltage VRAMP1 starts to ramp up, the ramp reference voltage VRAMP2 simultaneously starts to ramp up from a predetermined level (Vinit + Vth) higher than VRAMP1 at the same rate as VRAMP 1. Both the ramp reference voltages VRAMP1 and VRAMP2 pause the ramp-up at the same timing and hold it at a predetermined level.

The offset level Vth is a predetermined voltage, and may be designed to cause a target bias current to flow through the voltage used by the transistor M5 shown in fig. 2. The transistor M5 has a source terminal connected to ground. When a voltage is applied to the gate terminal of the transistor M5, the transistor M5 acts as a current source for the comparator.

The transistor M5 shown in fig. 2 may be a MOS transistor. For example, the drain current (Id) of the transistor M5 is determined as follows.

Id＝k*W/L*(Vgs–Vt) ² (1)

In formula (1), k: constant, W: channel width, L: channel length, Vgs: voltage difference between gate terminal and source terminal, Vt: a threshold voltage.

If it is assumed that "k", "W", "L", and "Vt" are all known and the target drain current Id can be determined or predetermined, "Vgs" can be automatically calculated using equation (1). When the source terminal is grounded and Vth is applied to the gate terminal, Vth is equal to Vgs. Therefore, a predetermined offset level Vth is applied to the gate terminal of the transistor M5.

Here, the target drain current Id may be determined in consideration of, for example, power consumption, random noise, voltage gain, transient response, and the like of the comparators I1 and I2.

In fig. 2, each pixel signal (Vpixel1 or Vpixel2 for ease of understanding) is fed to the negative input (terminal 4) of a comparator I1 (or I2), and a comparator I1 (or I2) compares the pixel signal Vpixel1 (or Vpixel2) with a ramp reference voltage Vramp 1. Another ramp reference voltage Vramp2 is used to apply a voltage to the gate terminal of transistor M5. The reference voltage Vramp2 may be provided by a sample/hold circuit not shown in the drawings. Transistor M5 acts as a bias current source for comparator I1 (or I2).

Hereinafter, the basic operation of the comparator I1/I2 is explained. The comparators I1, I2 in this embodiment may be differential amplifiers. The comparators I1 and I2 have the same structure, including transistors M1 to M5. Transistors M1 and M2 may be NMOS differential input transistors driven by current source transistor M5. The transistors M3 and M4 serve as load transistors for the input transistors M1 and M2. The transistors M3 and M4 may be understood as current mirror circuits.

In this embodiment, assuming that the transistors M1 and M2 are the same size, the transistors M3 and M4 are the same size. When the gate terminal voltage of the transistor M1 is higher than the gate terminal voltage of the transistor M2, the drain current (IdM1) of the transistor M1 is larger than the drain current (IdM2) of the transistor M2. The drain current (IdM1) of the transistor M1 is equal to the drain current (IdM3) of the transistor M3. Since the transistors M3 and M4 act as a current mirror circuit, the drain current of the transistor M3 is mirrored to the drain current of the transistor M4 (IdM3 IdM 4).

The output current of the comparator I1 (or I2) is generated by the difference (IdM 4-IdM 2) between the drain current of the transistor M2 and the drain current of the transistor M4. Since the drain current from transistor M2 is less than the drain current of transistor M1, the drain current difference between transistors M1 and M2 (IdM 1-IdM 2) exceeds the output current of comparator I1 (or I2) at terminal 5. The output terminal impedance may be designed to have a high value, and therefore, the output voltage may rise accordingly.

In fig. 2, each signal from a pixel (input pixel voltage Vpixel1/Vpixel2) is fed to the negative input (terminal 4) of a comparator I1 (or I2). Comparator I1 (or I2) compares the pixel signal to a ramp reference voltage (Vramp 1). The other ramp reference voltage (Vramp2) is used to provide a voltage to the gate terminal of transistor M5 (through transistor M7) through a sample/hold circuit. Transistor M5 acts as a bias current source for comparator I1 (or I2).

As described above, the predetermined offset level Vth may be designed to bias the current source transistor M5 to flow the target bias current to the voltage level of the comparator I1 (or I2). When the ramp reference signal Vramp1 reaches the same level as the input pixel signal (Vpixel1/Vpixel2), the comparator I1 (or I2) may have a voltage gain with a level sufficient to compare the input signal. The timing at which this occurs is "T5" shown in fig. 3.

As shown in fig. 2, the output from the comparator I1 (or I2) is supplied to the counter circuit I3 (or I4) through the terminal Vout1 (or Vout 2). The counter circuit I3 (or I4) counts the number of pulses supplied from the terminal CLK while the output voltage level from the output of the comparator I1 (or I2) is held at a low level. This case corresponds to "T1" to "T5" shown in fig. 3. In a similar manner, when the ramp reference voltage VRAMP1 is lower than the input pixel voltage Vpixel2, the counter circuit I4 counts the number of pulses applied through the terminal CLK. Therefore, the output value from the counter circuit I3 may be different from the output value of the counter circuit I4. For example, the logic circuit 150 shown in fig. 1 may receive the output value from the counter circuit I3 (or I4) and generate an image using the output digital value.

In fig. 3, at timing T1, when the pulse Φ PW changes to the high level, the switch SW1 is turned on. The common power supply VDD _ common is supplied to the local power supply line VDD1 (or VDD2) of the comparator I1 (or I2) through the switch SW 1. The capacitor Cp, which is a storage capacitor, is charged to have the same voltage as the common power supply VDD _ common. Before "T1", the switch SW1 remains open and the capacitor Cp having one ground terminal is not charged. The pulses Φ PW and other pulse signals may be provided from, for example, the logic circuit 150 or the T/G140.

At timing T1, the pulse Φ PW changes to high level, and the switch SW1 turns on accordingly. Then, from the timings T1 to T2, the capacitor Cp is charged. At timing T2, the pulse Φ PW changes to low level, the switch SW1 is opened, and the local power supply line Vdd1 (or Vdd2) of the comparator I1 (or I2) is disconnected from the common power supply Vdd _ common. After T3, comparator I1 (or I2) uses the power stored in capacitor Cp for its operation. Thus, for example, when comparator I1 (or I2) performs the comparison function, the local power lines of each comparator can be isolated from each other, and thus, the negative effects caused by power line-related crosstalk between comparators (I1, I2) can be reduced. This may contribute to improving the quality of the image obtained by the imaging apparatus 100, since the power supply lines are less cross-talk and more stable. Further, the comparator I1 (or I2) consumes power only when a comparison operation is required, and therefore, the power consumption of the imaging apparatus 100 can be reduced. It should be noted that the imaging device 100 may include millions or more pixels and comparators. The power consumption of these entire circuits can be significantly reduced, which is very advantageous for an apparatus that obtains a high-resolution image.

At a timing T3, the pulse Φ 1 supplied from the logic circuit 150 or the T/G140 changes to the high level, and the transistors M8 and M10 in the comparator I1 (or I2) turn on. Capacitor C _G Is connected to the terminal 4 through the transistor M8, and the input pixel voltage Vpixel1 (or Vpixel2) is applied to the terminal 4. Capacitor C _G Is connected to the ground terminal of the comparator I1 (or I2) through the transistor M10.

In fig. 3, when the pulse Φ 1 changes to the high level, the pulse Φ applied to the gate terminal of the transistor M6 changes to the high level at the same time. The transistor M6 having a grounded source terminal is turned on, and then, the capacitor Cs connected to the drain terminal and the source terminal of the transistor M6 is discharged. The source terminal of the transistor M5 is connected to the capacitor Cs, and therefore, the voltage level of the source terminal of the transistor M5 becomes the ground level.

At timing T4, the pulse Φ 1 goes low, and the pulse Φ 2 supplied from the logic circuit 150 or the T/G140 goes high. The transistors M8 and M10 are turned off due to the pulse Φ 1 applied to their gate terminals. When the transistor M8 is turned off, the capacitorC _G Is disconnected from terminal 4. When the transistor M10 is turned off, the capacitor C _G Is disconnected from the ground terminal of the comparator I1 (or I2).

At timing T4, transistor M7 is turned on due to a pulse Φ 2 applied to the gate terminal of transistor M7. Capacitor C _G Is connected to terminal 2 through transistor M7. At timing T4, transistor M9 is turned on due to a pulse Φ 2 applied to the gate terminal of transistor M9. Capacitor C _G Is connected to the gate terminal of the transistor M5 through the transistor M9. Transistor M5 acts as a current source in comparator I1. Since the ramp reference voltage Vramp2 is applied to terminal 2, and capacitor C _G Is preserved, i.e. the capacitor C _G The voltage difference between the two terminals of (a) is kept constant, so it can be understood that the gate voltage of the transistor M5 (shown as "VGATE" in fig. 2) can be calculated with the following formula "Vinit + Vth-Vpixel 1". In the case of comparator I2, the equation is "Vinit + Vth-Vpixel 2".

At timing T5 shown in fig. 3, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel 1. Since the voltage increase in the ramp reference voltage Vramp1 applied to the comparator I1 is obtained by "Vpixel 1-Vinit" and the voltage difference between the ramp reference voltage Vramp1 and Vramp2 is Vth, the voltage applied to the gate terminal of the transistor M5 in the comparator I1 can be obtained according to the formula shown below.

{(Vinit+Vth–Vpixel1)+(Vpixel1–Vinit)}＝Vth

This means that transistor M5 can pass a bias current large enough to drive comparator I1, the output of comparator I1 goes high, and there is a certain amount of delay time in response to its input voltage change. These responses are shown in fig. 3 as "Vout 1" and "ibias 1".

At the display T6 shown in fig. 3, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel 2. Since the voltage in the ramp reference voltage Vramp1 of the comparator I2 is increased to (Vpixel 2-Vinit), where the voltage difference between the ramp reference voltages Vramp1 and Vramp2 is Vth, it can be understood that the Voltage (VGATE) applied to the gate terminal of the transistor M5 included in the comparator I2 is obtained by the formula shown below. This is similar to comparator I1.

{(Vinit+Vth–Vpixel2)+(Vpixel2–Vinit)}＝Vth

This means that transistor M5 can pass a bias current large enough to drive comparator I2, the output of comparator I2 goes high, and there is a certain amount of delay time in response to its input voltage change. These responses are shown in fig. 3 as "Vout 2" and "ibias 2".

As described above, since the bias current of each comparator I1/I2 flows only when the level of the ramp reference voltage Vramp1 approaches its input pixel signal level (Vpixel1 or Vpixel2), the power consumption of the comparators I1 and I2 is reduced compared to comparators driven by constant current sources in some conventional SS ADCs. In addition, the timing of the bias current flowing in the comparator I1/I2 can be automatically controlled by the input signal level and the ramp reference level (Vramp1/Vramp 2).

The capacitance of the capacitor Cp shown in fig. 2 is used to operate the comparator I1/I2 after T2 shown in fig. 3. At timing T2, switch SW1 is open, and comparator I1/I2 is disconnected from the common power supply VDD _ common. When implementing the comparison operation with comparator I1/I2, it may be helpful to have the following information: how the capacitance of the capacitor Cp can be estimated, and how the comparator (I1/I2) disclosed above operates correctly on its local power line (VDD1/VDD2) after being disconnected from the common power line (VDD _ common).

Before estimating the capacitance of the capacitor Cp (simply referred to herein as "Cp" for ease of understanding), it is understood that the total charge flowing into the capacitor Cs during the comparison of the comparators I1/I2 is less than Vth × Cs. For ease of understanding, in this formula, "Cs" represents the capacitance of the capacitor Cs. For proper operation of the comparator I1/I2, the minimum supply voltage applied to the capacitor Cs can be estimated based on various aspects of the voltage gain, input-output time delay, input offset voltage, and output dynamic range of the comparator I1/I2. In order to achieve these specifications required to achieve ADC specifications, the drain-source voltage of each transistor in the comparator I1/I2 needs to be kept at a voltage higher than the so-called saturation voltage (Vds _ min) calculated according to the formula shown below.

Vds_min＝Vgs–Vt

Therefore, by adding the saturation voltages Vds _ min of each of the transistors M4, M2, and M5, the minimum power supply voltage (Vdd _ min) can be estimated, as shown below. In this embodiment, it is assumed that the sizes of these transistors are the same.

Vdd_min＝3*Vds_min

The capacitance of the capacitor Cp needs to be greater than "Cs × Vth/(VDD _ common-VDD _ min)". From this calculation, the minimum capacitance of the capacitor Cp can be estimated. Such minimum capacitance may reduce power consumption of the imaging apparatus 100. Further, when the comparator I1/I2 is placed in a chip, by using such calculation results, the silicon area shared by the capacitors Cp can be minimized. Minimizing silicon area may help reduce imaging apparatus 100 cost.

Hereinafter, the second embodiment is explained. Fig. 4 shows comparators I1 and I2. The reference numerals of fig. 3 correspond to fig. 2. The comparator I1/I2 comprises transistors M1 to M10, wherein M1, M2, M5, M6, M7, M8, M9, M10 are all PMOS transistors, and M3 and M4 are NMOS transistors, and further comprises terminals 1 to 5, a capacitor C _G Cp and Cs, and switch SW 1. Note that the transistors M1 to M10 are different from fig. 2. I3 and I4 are counter circuits. CLK provides a clock signal from, for example, T/G140 or logic circuit 150 shown in FIG. 1. FIG. 5 is a timing diagram of the operation of the comparator I1/I2. In fig. 4 and 5, it is assumed that the pixel signal level Vpixel1 is higher than the pixel signal level Vpixel2, the ramp reference voltage VRAMP2 is lower than the ramp reference voltage VRAMP1, and the ramp reference voltage VRAMP2 accurately tracks the ramp reference voltage VRAMP1 at a predetermined offset level (Vth). The ramp reference voltage VRAMP1 ramps down from a predetermined initial level (Vinit) at a constant rate. The operation of the transistors M1-M4 is similar to that of fig. 2.

In fig. 4, each pixel signal/voltage (Vpixel1 and Vpixel2 for ease of understanding) is provided to the negative input terminal (terminal 4) of a comparator I1 (or I2), which comparator I1 (or I2) compares the pixel signal Vpixel1 (or Vpixel2) with a ramp reference voltage (VRAMP 1). Another ramp reference voltage (VRAMP2) may provide a voltage through a sample/hold circuit to the gate terminal of transistor M5, which transistor M5 acts as a bias current source for comparator I1 (or I2).

As described above, "Vth" can be designed to bias the current source transistor (M5) to flow the bias current to the voltage level of the comparator I1 (or I2). Thus, the comparator I1 (or I2) may have a voltage gain that is large enough to compare the input signal when the ramp reference voltage Vramp1 reaches the same voltage as the input pixel signal Vpixel1 (or Vpixel 2).

As described above, the counter circuit I3 (or I4) inputs the signal output from the comparator I1 (or I2). The counter circuit I3 (or I4) counts the number of pulses supplied through the CLK terminal, and the output signal from the comparator I1 (or I2) is held at a low level.

In fig. 5, at timing T1, the pulse Φ PW changes to the high level, and the switch SW1 turns on accordingly. The common power VDD _ common is supplied to the local power line of each comparator (VDD1, VDD2) through the switch SW1, and charges the storage capacitor Cp to have the same level as VDD _ common. From the timings T1 to T2, the capacitor Cp is charged.

At timing T2, the pulse Φ PW changes to low, and the switch SW1 is turned off. The local power supply line (Vdd1/Vdd2, shown as Vdd in fig. 4) of each comparator (I1, I2) is disconnected from the common power supply line (Vdd _ common). At timing T3, the pulse Φ 1 which has been at the high level and applied to the gate terminals of the transistors M8 and M10 becomes the low level. Therefore, the transistors M8 and M10 in the comparator I1 (or I2) are turned on. Capacitor C _G Is connected to the terminal 4 through a transistor M10. Terminal 4 receives an input pixel signal Vpixel1 (or Vpixel2), and capacitor C _G Is connected to VDD1 derived from the common power supply VDD _ common through a transistor M8. After the timing T3, the comparator I1 (or I2) performs its operation using the power stored in the capacitor Cp. Thus, for example, when comparator I1 (or I2) performs the comparison function, the local power lines of each comparator can be isolated from each other, and thus, the power-line-related crosstalk between comparators (I1, I2) can be reducedNegative effects.

When the pulse Φ 1 which has been at the high level and applied to the gate terminals of the transistors M8 and M10 becomes the low level while the pulse Φ res applied to the gate terminal of the transistor M6 becomes the low level, the transistors M8, M10, and M6 are turned on. The capacitor Cs connected to the transistor M6 is discharged, and the voltage applied to the source terminal of the transistor M5 reaches the same level as Vdd1/Vdd2, that is, the same level as the common power supply Vdd _ common.

At timing T4, the pulse Φ 1 changes to the high level, while the pulse Φ 2 changes to the low level. Transistors M8 and M10, which receive the pulse Φ 1 at the gate node, turn off, and transistors M7 and M9, which receive the pulse Φ 2 at the gate node, turn on. Thus, the capacitor C _G Is disconnected from the terminal 4 (through the transistor M10) and the common power supply Vdd (through the transistor M8) and is connected to the terminal 2 (through the transistor M9) and the gate terminal of the transistor M5 (through the transistor M7). The transistor M5 serves as a current source for the comparator I1 (or I2). The ramp reference voltage VRAMP2 is applied to terminal 2, and thus, capacitor C _G The charge on is preserved. Capacitor C _G The voltage difference between the two terminals of transistor M5 is still present and the voltage on the gate terminal of transistor M5 is calculated by "Vinit-Vth + Vdd-Vpixelx (x ═ 1 or 2)".

At a timing T5, the ramp reference voltage VRAMP1 reaches the same voltage as the input pixel signal Vpixel 1. The voltage of the ramp reference voltage VRAMP1 applied to the comparator I1 is lowered to (Vinit-Vpixel 1), the voltage difference between the ramp reference voltages VRAMP1 and VRAMP2 is Vth, and therefore, the gate terminal of the transistor M5 in the comparator I1 reaches the voltage shown below.

(Vinit–Vth+Vdd1–Vpixel1)–(Vinit–Vpixel1)＝Vdd1–Vth

This formula indicates that the transistor M5 can pass a bias current large enough to drive the comparator I1, and the output signal of the comparator I1 goes low and has a certain amount of delay time in response to its input voltage change. In fig. 5, the responses are shown as "Vout 1" and "ibias 1".

At a timing T6, the ramp reference voltage VRAMP1 reaches the same voltage as the input pixel signal Vpixel 2. The voltage of the ramp reference voltage VRAMP1 applied to the comparator I2 is lowered to (Vinit-Vpixel 2), and the voltage difference between the ramp reference voltages VRAMP1 and VRAMP2 is Vth. The voltage applied to the gate terminal of the transistor M5 in the comparator I2 is calculated by the formula shown below.

(Vinit–Vth+Vdd2–Vpixel2)–(Vinit–Vpixel2)＝Vdd2–Vth

This means that if transistor M5 can pass a bias current large enough to drive comparator I2, the output of comparator I2 goes low and there is a certain amount of delay time to respond to its input voltage change. These responses are shown in fig. 5 as "Vout 2" and "ibias 2".

It will be appreciated that imaging devices typically have a large number of pixels arranged along a plurality of columns and rows. The timing diagrams included in fig. 3 and/or fig. 5 may be applied to the pixels, and the pixels on each column or each row may operate simultaneously according to the same timing described in fig. 3 or fig. 5, for example. The logic circuit 150 or the T/G140 may output signals and/or pulses to control the comparator I1/I2.

The above-described embodiments may have various advantages. First, the bias current of each of the above comparators in the SS ADC depends on the voltage difference between the input signal and the ramp reference voltage applied to the comparator, for example. The bias current of the comparator only starts to flow when the ramp reference voltage level approaches the input signal level. Thus, the dynamic bias circuit is fully compatible with the SS ADC, and in addition, reduces the power consumption of the SS ADC.

Next, for example, the local power line of each of the above-described comparators in the SS ADC is connected to the common power supply (VDD _ common) through the switch (SW 1). Such separate local power supply lines each have a storage capacitor (Cp).

As described in the above-described embodiment, immediately before the start of AD conversion, these switches (SW1) are turned off, and at the same time, the local power supply line of each comparator corresponding to the pixels arranged on one column is disconnected from the common (sensor) power supply line (VDD _ common).

The power supply current for each column of comparators is provided by the storage capacitor (Cp) rather than by the common (sensor) power supply line (VDD _ common). Therefore, negative effects, such as fluctuations generated in each local power supply line (Vdd1/Vdd2), do not propagate to other local power supply lines, and thus, for example, "stripe noise" can be eliminated.

The present application may have other aspects in addition to the above-described embodiments. For example, a first aspect is an imaging device including a comparator, a pixel, and a control circuit, wherein the comparator includes a switch, a first transistor, and a first capacitor, wherein the first capacitor is charged when the switch is turned on, and wherein the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit using power charged in the first capacitor after the switch is turned off, and outputs an output signal.

An eleventh aspect is an imaging method for an imaging apparatus including a comparator, a pixel, and a control circuit, the imaging method including: charging a first capacitor of the comparator when a switch of the comparator is turned on; comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor after the switch is turned off; and outputting the output signal.

The embodiments disclosed above are examples, and it should be understood that the invention and the scope of the present application is not limited or restricted by such disclosure.

Claims

1. An imaging apparatus comprising a comparator, a pixel, and a control circuit, wherein,

the comparator includes a switch, a first transistor, and a first capacitor, wherein,

the first capacitor is charged when the switch is turned on, and wherein,

the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor after the switch is turned off, and outputs an output signal.

2. The imaging apparatus of claim 1, wherein the ramp signal comprises a first ramp signal and a second ramp signal.

3. The imaging apparatus of claim 2, wherein the ramp signal comprises a predetermined voltage difference between the first ramp signal and the second ramp signal.

4. The imaging apparatus according to claim 1, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

5. The imaging device according to claim 1, wherein the first transistor flows a bias current to drive the comparator when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor.

6. The imaging apparatus of claim 1, wherein the capacitance of the first capacitor is large enough to drive the comparator.

7. The imaging apparatus according to claim 1, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

8. The imaging apparatus of claim 1, wherein the comparator is disconnected from a utility power source of the imaging apparatus when the switch is open.

9. The imaging apparatus according to claim 1, wherein the first ramp signal and the second ramp signal are ramp-up signals.

10. The imaging apparatus according to claim 1, wherein the first ramp signal and the second ramp signal are ramp-down signals.

11. An imaging method for an imaging apparatus including a comparator, a pixel, and a control circuit, the imaging method comprising:

charging a first capacitor of the comparator when a switch of the comparator is turned on;

comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor after the switch is turned off;

and outputting the output signal.

12. The imaging method of claim 11, wherein the ramp signal comprises a first ramp signal and a second ramp signal.

13. The imaging method of claim 12, wherein the ramp signal comprises a predetermined voltage difference between the first ramp signal and the second ramp signal.

14. The imaging method according to claim 11, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

15. The imaging method according to claim 11, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to a gate terminal of the first transistor, the first transistor flows a bias current to drive the comparator.

16. The imaging method of claim 11, wherein the capacitance of the first capacitor is large enough to drive the comparator.

17. The imaging method according to claim 11, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

18. The imaging method according to claim 11, wherein the comparator is disconnected from a utility power of the imaging device when the switch is turned off.

19. The imaging method according to claim 11, wherein the first ramp signal and the second ramp signal are ramp-up signals.

20. The imaging method of claim 11, wherein the first ramp signal and the second ramp signal are ramp down signals.