CN114842812B

CN114842812B - Display panel and control method thereof

Info

Publication number: CN114842812B
Application number: CN202210551550.7A
Authority: CN
Inventors: 傅晓立
Original assignee: Shenzhen Skyworth RGB Electronics Co Ltd
Current assignee: Shenzhen Skyworth RGB Electronics Co Ltd
Priority date: 2022-05-20
Filing date: 2022-05-20
Publication date: 2023-08-15
Anticipated expiration: 2042-05-20
Also published as: CN114842812A

Abstract

The invention relates to the technical field of electronic equipment and discloses a display panel and a control method thereof, wherein a system-level chip, a signal adjusting module, a first clock signal output module and a display module which are connected in sequence are arranged; the system level chip outputs a first time sequence control signal and an output signal to the signal adjustment module, and outputs a second time sequence control signal to the first clock signal output module and the second clock signal output module respectively; the signal adjustment module outputs a target control signal to the first clock signal output module and the second clock signal output module according to the first timing control signal and the output signal; the first clock signal output module and the second clock signal output module output clock signals to the display module according to the target control signals and the second time sequence control signals, and the 12CK and more panels can be lightened without developing a new chip.

Description

Display panel and control method thereof

Technical Field

The present invention relates to the field of electronic devices, and in particular, to a display panel and a control method thereof.

Background

As LCD (liquid crystal display) panels are developed toward higher order, such as 8k 120hz,8k144hz, and even higher refresh rate panels that have appeared in recent years, GOA (gate drive array) designs are also more complex. For example, FHD 60HZ panels have 4, 6 and 8 CK's, with 6CK being the most common. The number of UD 60HZ panels CK is 6, 8 and 10, wherein the number is 8 CK. The UD 120HZ or UD 144HZ panel has 6, 8, 10 and 12CK designs, wherein FIG. 1 is a partial GOA timing diagram of a UD 144HZ panel from prior art B. As can be seen from fig. 1, in order to drive the panel, the Level shift IC needs to have 12CK output channels, each of which is connected to a corresponding CK input interface of an XB (connection COF and TCON board FFC), and outputs the correct timing to normally light the panel.

However, most of the panels are 10CK or less, so that the level shift integrated circuit (Level Shifter Integrated Circuit, also called voltage level shift integrated circuit) driving the panel is mainly 10CK or less, and as the LSIC connected to the panel end, the output channel of 10CK cannot drive 12CK or more, and if the panel driving 10CK or less is used to drive 12CK or more, display abnormality occurs.

The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present invention and is not intended to represent an admission that the foregoing is prior art.

Disclosure of Invention

The invention mainly aims to provide a display panel and a control method thereof, and aims to solve the technical problem that a 12CK panel and more than the 12CK panel cannot be driven in the display panel in the prior art.

In order to achieve the above object, the present invention provides a display panel including: the system level chip, the signal adjusting module, the first clock signal output module and the display module are connected in sequence, and the signal adjusting module is also connected with the second clock signal output module and the display module in sequence;

the system-in-chip is used for outputting a first time sequence control signal and an output signal to the signal adjustment module and respectively outputting a second time sequence control signal to the first clock signal output module and the second clock signal output module;

the signal adjustment module is configured to output a target control signal to the first clock signal output module and the second clock signal output module according to the first timing control signal and the output signal;

the first clock signal output module and the second clock signal output module output clock signals to the display module according to the target control signal and the second time sequence control signal.

Optionally, the output signal includes: a first output signal;

the signal adjustment module is further configured to output the first timing control signal to the first clock signal output module and output a low level signal to the second clock signal output module when the first output signal is at a low level;

the signal adjustment module is further configured to output the first timing control signal to the second clock signal output module and output a low level signal to the first clock signal output module when the first output signal is at a high level.

Optionally, the signal adjustment module includes: a first signal adjustment circuit and a second signal adjustment circuit;

the control end and the input end of the first signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the first signal adjusting circuit is connected with the first clock signal output module;

the control end and the input end of the second signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the second signal adjusting circuit is connected with the second clock signal output module;

the first signal adjusting circuit is configured to output the first timing control signal to the first clock signal output module when the first output signal is at a low level;

The second signal adjusting circuit is configured to output the first timing control signal to the second clock signal output module when the first output signal is at a high level.

Optionally, the first signal adjustment circuit includes: a first switching tube, the second signal adjusting circuit includes: a second switching tube;

the grid electrode of the first switching tube and the source electrode of the first switching tube are respectively connected with the system-in-chip, and the drain electrode of the first switching tube is connected with the first clock signal output module;

the grid electrode of the second switching tube and the source electrode of the second switching tube are respectively connected with the system-in-chip, and the drain electrode of the second switching tube is connected with the second clock signal output module.

Optionally, the output signal further comprises: a second output signal and a third output signal;

the signal adjustment module is further configured to output the first timing control signal to the first clock signal output module and output a low level signal to the second clock signal output module when the second output signal is at a high level and the third output signal is at a low level;

the signal adjustment module is further configured to output the first timing control signal to the second clock signal output module and output a low level to the first clock signal output module when the second output signal is at a low level and the third output signal is at a high level.

Optionally, the signal adjustment module further comprises: a third signal adjustment circuit and a fourth signal adjustment circuit;

the control end of the third signal adjusting circuit and the input end of the third signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the third signal adjusting circuit is connected with the first clock signal output module;

the control end of the fourth signal adjusting circuit and the input end of the fourth signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the fourth signal adjusting circuit is connected with the second clock signal output module;

the third signal adjusting circuit is configured to output the first timing control signal to the first clock signal output module when the second output signal is at a high level and the third output signal is at a low level;

the fourth signal adjusting circuit is configured to output the first timing control signal to the second clock signal output module when the second output signal is at a low level and the third output signal is at a high level.

Optionally, the third signal adjustment circuit includes: and a third switching tube, the fourth signal adjusting circuit comprising: a fourth switching tube;

The grid electrode of the third switching tube and the source electrode of the third switching tube are respectively connected with the system-in-chip, and the drain electrode of the third switching tube is connected with the first clock signal output module;

the grid electrode of the fourth switching tube and the source electrode of the fourth switching tube are respectively connected with the system-in-chip, and the drain electrode of the fourth switching tube is connected with the second clock signal output module.

Optionally, the first clock signal output module or the second clock signal output module includes: a 3 in 1 power management integrated circuit, the 3 in 1 power management integrated circuit comprising: a power management integrated circuit, a first level shifting integrated circuit, and an image multimedia integrated circuit;

the power management integrated circuit is respectively connected with the first level shift integrated circuit and the image multimedia integrated circuit, the first level shift integrated circuit is also connected with the system-in-chip and the display module, and the image multimedia integrated circuit is also connected with the display module.

Optionally, the first clock signal output module or the second clock signal output module further includes: a second level shifting integrated circuit;

The input end of the second level shift integrated circuit is respectively connected with the signal adjusting module and the system-in-chip, and the output end of the second level shift integrated circuit is connected with the display module.

In addition, in order to achieve the above object, the present invention further provides a display panel control method, which is applied to the display panel described above, the display panel includes a system-in-chip, a signal adjustment module, a first clock signal output module, and a display module that are sequentially connected, the signal adjustment module is further sequentially connected to a second clock signal output module and the display module, and the method includes the following steps:

the system-in-chip outputs a first time sequence control signal and an output signal to the signal adjustment module, and outputs a second time sequence control signal to the first clock signal output module and the second clock signal output module respectively;

the signal adjustment module outputs a third time sequence control signal and a fourth time sequence control signal with preset time intervals to the first clock signal output module and the second clock signal output module according to the output signals and the time sequence signals with target time intervals, and the levels of the third time sequence control signal and the fourth time sequence control signal are opposite;

The first clock signal output module and the second clock signal output module output clock signals to the display module according to the third time sequence control signal and the fourth time sequence control signal of the preset time interval and the second time sequence control signal.

The invention sets up the system-level chip, signal adjustment module, first clock signal output module and display module that connect sequentially in the display panel, the said signal adjustment module is also connected with second clock signal output module and said display module sequentially; the system-in-chip is used for outputting a first time sequence control signal and an output signal to the signal adjustment module and respectively outputting a second time sequence control signal to the first clock signal output module and the second clock signal output module; the signal adjustment module is configured to output a target control signal to the first clock signal output module and the second clock signal output module according to the first timing control signal and the output signal; the first clock signal output module and the second clock signal output module output clock signals to the display module according to the target control signals and the second time sequence control signals, the first time sequence control signals and the output signals are received through the signal adjustment module, the target control signals are output to the first clock signal output module and the second clock signal output module, the first clock signal output module and the second clock signal output module output correct clock signals through adjustment of the output signals, and the 12CK and more panels can be quickly lightened and driven.

Drawings

FIG. 1 is a partial GOA timing diagram of a prior art UD 144HZ panel;

FIG. 2 is a schematic diagram of a first embodiment of a display panel according to the present invention;

FIG. 3 is a schematic diagram showing a structure of a first clock signal output module and a second clock signal output module in a second embodiment of the display panel according to the present invention;

FIG. 4 is a schematic diagram showing a structure of a first clock signal output module and a second clock signal output module according to a second embodiment of the display panel of the present invention;

FIG. 5 is a schematic diagram of a signal adjustment module of a display panel according to a second embodiment of the invention;

FIG. 6 is a schematic structural diagram of a display panel according to a third embodiment of the present invention;

FIG. 7 is a flowchart of a display panel control method according to a first embodiment of the present invention;

FIG. 8 is a schematic diagram of a clock signal driving timing diagram of a display panel control method according to the present invention

FIG. 9 is a schematic diagram of a clock signal driving timing diagram of a display panel according to a second embodiment of the invention;

fig. 10 is a schematic diagram of a clock signal driving timing diagram of a display panel according to a third embodiment of the invention.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				1	System-on-chip	23	Fourth signal adjusting circuit
2	Signal adjusting module	M1～M4	First to fourth MOS transistors
				20	First signal adjusting circuit	3	First clock signal output module
21	Second signal adjusting circuit	4	Display module
				22	Third signal adjusting circuit	5	Second clock signal output module

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a first embodiment of a display panel according to the present invention.

In this embodiment, the display panel includes: the system-in-chip 1, the signal adjusting module 2, the first clock signal output module 3 and the display module 4 are sequentially connected, and the signal adjusting module 2 is also sequentially connected with the second clock signal output module 5 and the display module 4; the system-in-chip 1 is configured to output a first timing control signal and an output signal to the signal adjustment module 2, and output a second timing control signal to the first clock signal output module 3 and the second clock signal output module 5, respectively; the signal adjustment module 2 is configured to output a target control signal to the first clock signal output module 3 and the second clock signal output module 5 according to the first timing control signal and the output signal; the first clock signal output module 3 and the second clock signal output module 5 are configured to output a clock signal to the display module 4 according to the target control signal and the second timing control signal.

It should be noted that, the System on Chip 1 refers to an SOC (System on Chip), and the System on Chip 1 is used to control outputting a correct first timing control signal and an output signal to the signal adjustment module 2, where the output signal refers to a GPIO (GeneralPurpose Input Output, general purpose input/output) signal, and the GPIO signal may include a high level signal and a low level signal. The first timing control signal refers to the CPV1 signal, the second timing control signal refers to the CPV2 signal, the system on chip 1 outputs the GPIO signal and the CPV1 signal to the signal adjustment module 2, and simultaneously the system on chip 1 outputs the CPV2 signal to the first clock signal output module 3 and the second clock signal output module 5.

In the present embodiment, the target control signal refers to a level signal and a CPV1 signal, and the level signal includes a high level signal and a low level signal. When the system-in-chip 1 outputs the GPIO signal and the CPV1 signal to the signal adjustment module 2, the signal adjustment module 2 selects the corresponding clock signal output module to output the CPV1 signal and the level signal according to the level state of the GPIO signal, for example, when the GPIO signal is a low level signal, the signal adjustment module 2 transmits the CPV1 signal to the first clock signal output module 3 and transmits the low level signal to the second clock signal output module 5; or when the GPIO signal is a high level signal, the signal adjustment module 2 transmits the CPV1 signal to the first clock signal output module 3 and transmits the high level signal to the second clock signal output module 5; or when the GPIO signal is at a low level, the signal adjustment module transmits the CPV1 signal to the second clock signal output module 5 and transmits the low level signal to the first clock signal output module 3; or when the GPIO signal is at a high level, the signal adjustment module transmits the CPV1 signal to the second clock signal output module 5 and transmits the high level signal to the first clock signal output module 3.

In an implementation, the clock signal includes a first clock signal and a second clock signal. The system-in-chip 1 further outputs the second timing control signal CVP2 to the first clock signal output module 3 and the second clock signal output module 5, and when the first clock signal output module 3 receives the CPV1 signal and the CVP2 signal, the first clock signal may be output, and the first clock signal may include CK1-CK6 or CK1-CK8, and may be further clock signals, for example, CK1-CK9, CK1-CK10, and the like, which is not limited in this embodiment. When the second clock signal output module 5 receives the CPV1 signal and the CPV2 signal, the second clock signal is output, and when the first clock signal is CK1 to CK6, the second clock signal includes: CK7-CK12, when the first clock signal is CK1-CK8, the second clock signal includes: CK9-CK16, when the first clock signal is CK1-CK9, the second clock signal comprises: CK10-CK18. When the display module 4 receives the first clock signal and the second clock signal, the lighting driving is performed by the clock signals. The display module 4 is a display panel, and when the display panel is 12CK, the display panel can be turned on by receiving the clock signals of CK1-CK6 output by the first clock signal output module 3 and the clock signals of CK7-CK12 output by the second clock signal output module 5, and the display panel 12CK and above can be turned on by the clock signals output by the first clock signal output module 3 and the second clock signal output module 5, without developing a new chip.

In the embodiment, a system-level chip, a signal adjusting module, a first clock signal output module and a display module which are sequentially connected are arranged in a display panel, and the signal adjusting module is also sequentially connected with a second clock signal output module and the display module; the system-in-chip is used for outputting a first time sequence control signal and an output signal to the signal adjustment module and respectively outputting a second time sequence control signal to the first clock signal output module and the second clock signal output module; the signal adjustment module is configured to output a target control signal to the first clock signal output module and the second clock signal output module according to the first timing control signal and the output signal; the first clock signal output module and the second clock signal output module output clock signals to the display module according to the target control signals and the second time sequence control signals, the first time sequence control signals and the output signals are received through the signal adjustment module, the target control signals are output to the first clock signal output module and the second clock signal output module, the first clock signal output module and the second clock signal output module output correct clock signals through adjustment of the output signals, and the 12CK and more panels can be quickly lightened and driven.

Based on the above-described first embodiment, a second embodiment of the display panel of the invention is proposed. The output signals in this embodiment include a first output signal, and the signal adjustment module 2 is further configured to output the first timing control signal to the first clock signal output module 3 and output a low level signal to the second clock signal output module 5 when the first output signal is at a low level; the signal adjustment module 2 is further configured to output the first timing control signal to the second clock signal output module 5 and output a low level signal to the first clock signal output module 3 when the first output signal is at a high level.

It may be understood that, when the first output signal is a low level signal, the signal adjustment module 2 outputs the first timing control signal CPV1 in the target control signal to the first clock signal output module 3 according to the low level signal and outputs the low level signal in the target control signal to the second clock signal output module 5, the first clock signal output module 3 outputs the first clock signal to the display panel according to the CPV1 signal and the CPV2 signal, when the first output signal is a high level signal, the signal adjustment module 2 outputs the first timing control signal CPV1 in the target control signal to the second clock signal output module 5 according to the high level signal and outputs the low level signal in the target control signal to the first clock signal output module 3, and the second clock signal output module 5 outputs the second clock signal to the display panel according to the CPV1 signal and the CPV2 signal, and the display panel receives the first clock signal and the second clock signal and then performs lighting driving.

The first clock signal output module 3 or the second clock signal output module 5 includes: a 3 in 1 power management integrated circuit (PowerManagementIC, PMIC), i.e., a 3 in 1 PMIC. The 3 in 1 power management integrated circuit includes: a power management integrated circuit, a first level shifting integrated circuit, and an image multimedia integrated circuit; the power management integrated circuit is respectively connected with the first level shift integrated circuit and the image multimedia integrated circuit, the first level shift integrated circuit is also connected with the system-in-chip 1 and the display module 4, and the image multimedia integrated circuit is also connected with the display module 4.

Fig. 3 is a schematic structural diagram of a first clock signal output module and a second clock signal output module of the display panel according to the present invention.

The power management integrated circuit is a PMIC of 3 in 1, the PMIC comprises a separated PMIC, a first Level shift integrated circuit and an image multimedia integrated circuit, the first Level shift integrated circuit is a Level shift integrated circuit, the image multimedia integrated circuit is a GM IC, the separated PMIC is connected with the signal adjustment module 2 and the display panel respectively through outputting VGH signals and VGL signals to the Level shift integrated circuit, the separated PMIC is also connected with the GM IC, the separated PMIC outputs AVDD signals and 3.3V voltage signals to the GM IC, the GM IC outputs GM or VCM signals to the display panel, and the separated PMIC also outputs AVDD signals, HAVDD signals or 1.8V voltage signals to the display panel. The model of the PMIC of 3 in 1 is RT6970 in this example.

Fig. 4 is a schematic diagram of a first clock signal output module and a second clock signal output module in the display panel according to the present invention.

The first clock signal output module 3 or the second clock signal output module 5 further comprises: and the input end of the second level shift integrated circuit is respectively connected with the signal adjusting module 2 and the system-in-chip 1, and the output end of the second level shift integrated circuit is connected with the display module 4. The first clock signal output module 3 or the second clock signal output module 5 may also be a Level shift integrated circuit Level Shifter IC, where the Level Shifter IC is directly connected to the signal adjustment circuit 2 and the display module 4, and outputs a clock signal to the display module 4 directly through the Level Shifter IC according to the target control signal and the second timing control signal. The Level shift IC is model RT8949. The first clock signal output module 3 and the second clock signal output module 5 may also be a 3 in 1PMIC and a separate Level shifter IC, which is not limited in this embodiment. In this embodiment, the first clock signal output module 3 is a 3 in 1PMIC, and the second clock signal output module 5 is a Level shifter IC.

Fig. 5 is a schematic diagram of a signal adjusting module of a display panel according to a second embodiment of the invention.

In this embodiment, the signal adjustment module 2 includes: a first signal conditioning circuit 20 and a second signal conditioning circuit 21.

It should be understood that the signal adjustment module 2 includes a first signal adjustment circuit 20 and a second signal adjustment circuit 21, and the first signal adjustment circuit 20 and the second signal adjustment circuit 21 may be Switch integrated circuits (Switch ICs) through which the target control signals are output to the first clock signal output module 3 and the second clock signal output module 5 for the output signal and the first timing control signal CPV 1.

In a specific implementation, the control end and the input end of the first signal adjustment circuit 20 are respectively connected with the system-in-chip 1, and the output end of the first signal adjustment circuit 20 is connected with the first clock signal output module 3; the control end and the input end of the second signal adjustment circuit 21 are respectively connected with the system-in-chip 1, and the output end of the second signal adjustment circuit 21 is connected with the second clock signal output module 5; the first signal adjusting circuit 20 is configured to output the first timing control signal to the first clock signal output module 3 when the first output signal is at a low level; the second signal adjusting circuit 21 is configured to output the first timing control signal to the second clock signal output module 5 when the first output signal is at a high level.

Specifically, the model of the system-in-chip 1 is RT2885N, the system-in-chip 1 also outputs other control signals such as STV, and the system-in-chip 1 is provided with a CPV1 interface, a CPV2 interface, a GPIO interface, and a STV interface. The first clock signal output module 3 and the second clock signal output module 5 are provided with a CPV1 interface, a CPV2 interface, and an STV interface. The first clock signal output module 3 receives the CPV2 signal and the STV1 signal output from the system on chip 1, and the second clock signal output module 5 receives the CPV2 signal and the STV2 signal output from the system on chip 1.

In this embodiment, the first signal adjusting circuit 20 includes: the first switching tube, the second signal adjusting circuit 21 includes: a second switching tube; the grid electrode of the first switching tube and the source electrode of the first switching tube are respectively connected with the system-in-chip 1, and the drain electrode of the first switching tube is connected with the first clock signal output module 3; the grid electrode of the second switching tube and the source electrode of the second switching tube are respectively connected with the system-in-chip 1, and the drain electrode of the second switching tube is connected with the second clock signal output module 5.

Specifically, the first switch tube and the second switch tube may include MOS tubes, in this embodiment, the first switch tube is a first MOS tube M1, M1 is a PMOS tube, the second switch tube is a second MOS tube M2, M2 is an NMOS tube, the gate of the first MOS tube M1 and the gate of the second MOS tube M2 are both connected with the GPIO interface of the system-level chip 1, the GPIO level signal is output to the first MOS tube M1 and the second MOS tube M2, the source of the first MOS tube M1 and the source of the second MOS tube M2 are both connected with the CPV1 interface of the system-level chip 1, the CPV1 signal is output to the first MOS tube M1 and the second MOS tube M2, the drain of the first MOS tube M1 is connected with the first clock signal output module 3, the CPV1+ signal is output, and the drain of the first MOS tube M2 is connected with the second clock signal output module 5, and the CPV 1-signal is output. When the GPIO interface of the SOC system-level chip 1 outputs a low-level first output signal or L signal, the first MOS transistor M1 is turned on, the second MOS transistor M2 is turned off, and the first timing control signal CPV1 is transmitted to the first clock signal output module 3 through the first MOS transistor M1, that is, the signal output by cpv1+ is a CPV1 signal, and the signal output by CPV 1-is a low-level signal. The target control signal is to output the CPV1 signal to the first clock signal output module 3 and the low level signal to the second clock signal output module 5. The first clock signal output module 3 outputs a first clock signal to the display panel according to the CPV1 signal and the CPV2 signal output from the system on chip 1.

When the GPIO interface of the system-in-chip 1 outputs a high-level first output signal or an H signal, the second MOS transistor M2 is turned on, the first MOS transistor M1 is turned off, the first timing control signal CPV1 is transmitted to the second clock signal output module 5 through the second MOS transistor M2, that is, the signal output by cpv1+ is a low-level signal, and the signal output by CVP 1-is a CPV1 signal. The target control signal is to output the CPV1 signal to the second clock signal output module 5 and output the low level signal to the first clock signal output module 3. The second clock signal output module 5 outputs a second clock signal to the display panel according to the CPV1 signal and the CPV2 signal output from the system on chip 1. The display panel receives the first clock signal and the second clock signal to perform lighting driving on the panel.

The first signal adjusting circuit and the second signal adjusting circuit are arranged in the signal adjusting module; the control end and the input end of the first signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the first signal adjusting circuit is connected with the first clock signal output module; the control end and the input end of the second signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the second signal adjusting circuit is connected with the second clock signal output module; the first signal adjusting circuit is configured to output the first timing control signal to the first clock signal output module when the first output signal is at a low level; the second signal adjusting circuit is configured to output the first timing control signal to the second clock signal output module when the first output signal is at a high level, control on-off between the first signal adjusting circuit and the second signal adjusting circuit by controlling a level state of the output signal, and output a corresponding target control signal to the first clock signal output module and the second clock signal output module, thereby outputting a corresponding clock signal to the display module, and enabling the display module to perform lighting driving.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a third embodiment of a display panel according to the present invention.

Based on the first and second embodiments, the output signal of this embodiment further includes: a second output signal and a third output signal; the signal adjustment module 2 is further configured to output the first timing control signal to the first clock signal output module 3 and output a low level signal to the second clock signal output module 5 when the second output signal is at a high level and the third output signal is at a low level; the signal adjustment module 2 is further configured to output the first timing control signal to the second clock signal output module 5 and output the low level to the first clock signal output module 3 when the second output signal is at the low level and the third output signal is at the high level.

In this embodiment, the system-on-chip 1 includes a second output signal GPIO1 interface and a third output signal GPIO2 interface, when the system-on-chip 1 outputs a high-level second output signal and a low-level third output signal, the signal adjustment module 2 outputs a first timing control signal CPV1 in the target control signal to the first clock signal output module 3 according to the high-level second output signal, and outputs a low-level signal in the target control signal to the second clock signal output module 5 according to the low-level third output signal, and the first clock signal output module 3 outputs a first clock signal to the display panel according to the CPV1 signal and the CPV2 signal; when the second output signal is at a low level and the third output signal is at a high level, the signal adjustment module 2 outputs a low level signal of the target control signals to the first clock signal output module 3 according to the second output signal at a low level, and outputs a first timing control signal CPV1 of the target control signals to the second clock signal output module 5 according to the third output signal at a high level, the second clock signal output module 5 outputs a second clock signal to the display panel according to the CPV1 signal and the CPV2 signal, and the display module 4 performs lighting driving according to the first clock signal and the second clock signal.

Further, the signal adjustment module 2 further includes: a third signal adjustment circuit 22 and a fourth signal adjustment circuit 23; the control end of the third signal adjustment circuit 22 and the input end of the third signal adjustment circuit 22 are respectively connected with the system-in-chip 1, and the output end of the third signal adjustment circuit 22 is connected with the first clock signal output module 3; the control end of the fourth signal adjustment circuit 23 and the input end of the fourth signal adjustment circuit 23 are respectively connected with the system-in-chip 1, and the output end of the fourth signal adjustment circuit 23 is connected with the second clock signal output module 5; the third signal adjustment circuit 22 is configured to output the first timing control signal to the first clock signal output module 3 when the second output signal is at a high level and the third output signal is at a low level; the fourth signal adjusting circuit 23 is configured to output the first timing control signal to the second clock signal output module 5 when the second output signal is at a low level and the third output signal is at a high level.

The third signal adjustment circuit 22 includes: the third switching tube, the fourth signal adjusting circuit 23 includes: a fourth switching tube; the grid electrode of the third switching tube and the source electrode of the third switching tube are respectively connected with the system-in-chip 1, and the drain electrode of the third switching tube is connected with the first clock signal output module 3; the grid electrode of the fourth switching tube and the source electrode of the fourth switching tube are respectively connected with the system-in-chip 1, and the drain electrode of the fourth switching tube is connected with the second clock signal output module 5.

Specifically, the third switching tube and the fourth switching tube include MOS tubes, in this embodiment, the third switching tube is a third MOS tube M3, the fourth switching tube is a fourth MOS tube M4, M3 and M4 are all NMOS tubes, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4 are all connected with the GPIO interface of the system-Level chip 1, the gate of the third MOS tube M3 is connected with the GPIO1 interface of the system-Level chip 1, the gate of the fourth MOS tube M4 is connected with the GPIO2 interface of the system-Level chip 1, the source of the third MOS tube M3 and the source of the fourth MOS tube M4 are all connected with the CPV1 interface of the system-Level chip 1, the drain of the third MOS tube M3 is connected with the CPV1 interface of the 3-in-1 PMIC in the first clock signal output module 3, the drain of the fourth MOS tube M4 is connected with the CPV1 interface of the Level shift IC in the second clock signal output module 5, and outputs the CPV 1-signal.

In a specific implementation, when the GPIO1 interface of the system-in-chip 1 outputs the second output signal of the high level or H signal and the GPIO2 interface outputs the third output signal of the low level or L signal, the third MOS transistor M3 is turned on, the fourth MOS transistor M4 is turned off, the first timing control signal CPV1 is transmitted to the 3-in-1 PMIC of the first clock signal output module 3 through the third MOS transistor M3, that is, the signal output by cpv1+ is a CPV1 signal, and the signal output by CPV 1-is a low level signal. The target control signal is to output the CPV1 signal to the first clock signal output module 3 and the low level signal to the second clock signal output module 5. The 3-in-1 PMIC in the first clock signal output module 3 outputs a first clock signal to the display panel according to the CPV1 signal and the CPV2 signal output from the system on chip 1.

When the GPIO1 interface of the system-in-chip 1 outputs the second output signal of the low Level or the L signal and the GPIO2 interface outputs the third output signal of the high Level or the H signal, the third MOS transistor M3 is turned off, the fourth MOS transistor M4 is turned on, the first timing control signal CPV1 is transmitted to the Level shift IC of the second clock signal output module 5 through the fourth MOS transistor M4, that is, the signal output by cpv1+ is the low Level signal, and the signal output by CPV 1-is the first timing control signal CPV1. The target control signal is to output a low Level signal to the first clock signal output module 3 and output a CPV1 signal to the second clock signal output module 5, and the Level Shifter IC in the second clock signal output module 5 outputs a second clock signal to the display panel according to the CPV1 signal and the CPV2 signal output by the system-in-chip 1. The display panel receives the first clock signal and the second clock signal to perform lighting driving on the panel.

The third signal adjusting circuit and the fourth signal adjusting circuit are arranged in the signal adjusting module; the control end of the third signal adjusting circuit and the input end of the third signal adjusting circuit are respectively connected with the system-in-chip, and the output end of the third signal adjusting circuit is connected with the first clock signal output module; the control end of the fourth signal adjustment circuit and the input end of the fourth signal adjustment circuit 23 are respectively connected with the system-in-chip, and the output end of the fourth signal adjustment circuit is connected with the second clock signal output module; the third signal adjusting circuit is configured to output the first timing control signal to the first clock signal output module when the second output signal is at a high level and the third output signal is at a low level; the fourth signal adjusting circuit is configured to output the first timing control signal to the second clock signal output module when the second output signal is at a low level and the third output signal is at a high level. The on-off state between the first signal adjusting circuit and the second signal adjusting circuit is controlled by controlling the level state of the output signal, and corresponding target control signals are output to the first clock signal output module and the second clock signal output module, so that corresponding clock signals are output to the display module, and the display module is enabled to be driven to light.

Referring to fig. 7, fig. 7 is a flowchart illustrating a first embodiment of a control method of a display panel according to the present invention.

In this embodiment, the display panel control method is applied to the display panel described above, and the display panel includes: the system-in-chip, the signal adjustment module, the first clock signal output module and the display module are sequentially connected, and the signal adjustment module is further sequentially connected with the second clock signal output module and the display module.

The display panel control method comprises the following steps:

step S10: the system-in-chip outputs a first time sequence control signal and an output signal to the signal adjustment module, and outputs a second time sequence control signal to the first clock signal output module and the second clock signal output module respectively.

It should be noted that, the System on Chip refers to an SOC (System on Chip), and the System on Chip is used to control and output a correct first timing control signal and an output signal to the signal adjustment module, where the output signal refers to a GPIO (GeneralPurpose Input Output, general purpose input/output) signal, and the GPIO signal may include a high level signal and a low level signal. The first timing control signal refers to a CPV1 signal, the second timing control signal refers to a CPV2 signal, and the system-on-chip outputs the GPIO signal and the CPV1 signal to the signal adjustment module while the system-on-chip outputs the CPV2 signal to the first clock signal output module and the second clock signal output module. The signal adjustment module outputs a CPV1+ signal to the first clock signal output module and outputs a CPV1-signal to the second clock signal output module.

Step S20: the signal adjustment module outputs a third time sequence control signal and a fourth time sequence control signal with preset time intervals to the first clock signal output module and the second clock signal output module according to the output signals and the time sequence signals with target time intervals, and the levels of the third time sequence control signal and the fourth time sequence control signal are opposite.

Step S30: the first clock signal output module and the second clock signal output module output clock signals to the display module according to the third time sequence control signal and the fourth time sequence control signal of the preset time interval and the second time sequence control signal.

The target control signal refers to a level signal and a CPV1 signal, and the level signal includes a high level signal and a low level signal. When the system-in-chip outputs the GPIO signal and the CPV1 signal to the signal adjustment module, the signal adjustment module selects the corresponding clock signal output module to output the CPV1 signal and the level signal according to the level state of the GPIO signal, for example, when the GPIO signal is a low level signal, the signal adjustment module transmits the CPV1 signal to the first clock signal output module and transmits the low level signal to the second clock signal output module; or when the GPIO signal is a high-level signal, the signal adjustment module transmits the CPV1 signal to the first clock signal output module and transmits the high-level signal to the second clock signal output module; or when the GPIO signal is at a low level, the signal adjustment module transmits the CPV1 signal to the second clock signal output module and transmits the low level signal to the first clock signal output module; or when the GPIO signal is at a high level, the signal adjustment module transmits the CPV1 signal to the second clock signal output module and transmits the high level signal to the first clock signal output module.

In an implementation, the clock signal includes a first clock signal and a second clock signal. The system-in-chip further outputs the second timing control signal CVP2 to the first clock signal output module and the second clock signal output module, and when the first clock signal output module receives the CPV1 signal and the CVP2 signal, the first clock signal may include CK1-CK6 or CK1-CK8, and may be further clock signals, such as CK1-CK9, CK1-CK10, and the like, which is not limited in this embodiment. When the second clock signal output module receives the CPV1 signal and the CPV2 signal, the second clock signal is output, and when the first clock signal is CK1-CK6, the second clock signal includes: CK7-CK12, when the first clock signal is CK1-CK8, the second clock signal includes: CK9-CK16, when the first clock signal is CK1-CK9, the second clock signal comprises: CK10-CK18. When the display module receives the first clock signal and the second clock signal, the display module is driven to be lightened through the clock signals. When the display panel is 12CK, the display module can be lightened by receiving clock signals of CK1-CK6 output by the first clock signal output module and clock signals of CK7-CK12 output by the second clock signal output module, and the panels above and 12CK can be lightened by the clock signals output by the first clock signal output module and the second clock signal output module without developing a new chip additionally.

In this embodiment, the target time interval may be 0.5s, 1s, etc., and may be set according to specific requirements, the preset time interval may be controlled according to the phase relationship between the CPV1 signal and the CPV2 signal, the display panel driving 12CK is described by taking the display panel driving 12CK as an example, the third timing control signal is cpv1+, the fourth timing control signal is CPV 1-signal, the levels of the third timing control signal and the fourth timing control signal are opposite, when the third timing control signal is at the high level, the fourth timing control signal is at the low level, the first clock signal output module outputs the third timing control signal, the fourth timing control signal is output to the second clock signal output module, the first clock signal outputting the first clock signal of CK1-CK6 is output to the display module through the first clock signal output module, the second clock signal outputting the second clock signal of CK7-CK12 is output to the display module, and the display module receives the first clock signal CK 1-6 and the second clock signal CK7-CK12 within the preset time interval, and the display panel driving 12 is bright.

As shown in fig. 8, fig. 8 is a schematic diagram of a clock signal driving timing of a display panel control method according to the present invention, wherein cpv1+ and CPV 1-output corresponding control signals at preset time intervals, and when cpv1+ is a high level signal, cpv1-is a low level signal. When CPV1+ is a high level signal, the high level width and the phase difference of the CK1-CK6 signals are controlled by shifting the phase relation of CPV2, and when CPV 1-is a high level signal, the high level width and the phase difference of the CK7-CK12 signals are controlled by shifting the phase relation of CPV2, so that the clock signals of CK1-CK12 are outputted.

As shown in fig. 5, when the output signal is the GPIO signal of the first output signal, the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected with the GPIO interface of the system-in-chip respectively, and output the GPIO signal, the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected with the CPV1 interface of the system-in-chip respectively, as shown in fig. 9, fig. 9 is a schematic diagram of the driving timing sequence in the second embodiment of the display panel according to the present invention, when the GPIO signal is the low level signal, the GPIO interface outputs the low level first output signal to the first MOS transistor M1 and the second MOS transistor M2, and when the first MOS transistor M1 receives the low level signal, the second MOS transistor M2 is turned off, CPV1+ outputs the CPV1 signal, and CPV 1-outputs the low level signal. When the GPIO signal is a high-level signal, the GPIO interface outputs a first high-level output signal to the first MOS tube M1 and the second MOS tube M2, the first MOS tube M2 is turned off when receiving the high-level signal, the second MOS tube M2 is turned on when receiving the high-level signal, CPV1+ outputs a low-level signal, and CPV 1-outputs a CPV1 signal.

As shown in the display panel structure diagram of fig. 6, when the output signals are the GPIO1 signal of the second output signal and the GPIO2 signal of the third output signal, the gate of the third MOS transistor M3 is connected with the GPIO1 interface of the system-in-chip, the gate of the fourth MOS transistor M4 is connected with the GPIO2 interface of the system-in-chip, the GPIO1 signal and the GPIO2 signal are output, the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are respectively connected with the CPV1 interface of the system-in-chip, the drain of the third MOS transistor M3 is connected with the CPV1 interface of the 3-in-1 PMIC in the first clock signal output module, the CPV1+ signal is output, and the drain of the fourth MOS transistor M4 is connected with the CPV1 interface of the Level shift IC in the second clock signal output module, and the CPV 1-signal is output.

As shown in fig. 10, fig. 10 is a schematic diagram of a driving timing diagram in a third embodiment of the display panel according to the present invention. When the GPIO1 signal is a high-level signal and the GPIO2 signal is a low-level signal, the third MOS tube M3 is turned on, the fourth MOS tube M4 is turned off, CPV1+ outputs the CPV1 signal, CPV 1-outputs the low-level signal, when the GPIO1 signal is a low-level signal and the GPIO2 signal is a high-level signal, the fourth MOS tube M4 is turned on, the third MOS tube M3 is turned off, CPV1+ outputs the low-level signal, and CPV 1-outputs the CPV1 signal.

It should be understood that the foregoing is illustrative only and is not limiting, and that in specific applications, those skilled in the art may set the invention as desired, and the invention is not limited thereto.

It should be noted that the above-described working procedure is merely illustrative, and does not limit the scope of the present invention, and in practical application, a person skilled in the art may select part or all of them according to actual needs to achieve the purpose of the embodiment, which is not limited herein.

In addition, technical details not described in detail in the present embodiment may refer to the display panel control method provided in any embodiment of the present invention, and are not described herein again.

Furthermore, it should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.

The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. Read Only Memory)/RAM, magnetic disk, optical disk) and including several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. A display panel, the display panel comprising: the system level chip, the signal adjusting module, the first clock signal output module and the display module are connected in sequence, and the signal adjusting module is also connected with the second clock signal output module and the display module in sequence;

2. The display panel of claim 1, wherein the output signal comprises: a first output signal;

3. The display panel of claim 2, wherein the signal adjustment module comprises: a first signal adjustment circuit and a second signal adjustment circuit;

4. The display panel of claim 3, wherein the first signal adjustment circuit comprises: a first switching tube, the second signal adjusting circuit includes: a second switching tube;

5. The display panel of claim 1, wherein the output signal further comprises: a second output signal and a third output signal;

6. The display panel of claim 5, wherein the signal adjustment module further comprises: a third signal adjustment circuit and a fourth signal adjustment circuit;

7. The display panel of claim 6, wherein the third signal adjustment circuit comprises: and a third switching tube, the fourth signal adjusting circuit comprising: a fourth switching tube;

8. The display panel of any one of claims 1-7, wherein the first clock signal output module or the second clock signal output module comprises: a 3 in 1 power management integrated circuit, the 3 in 1 power management integrated circuit comprising: a power management integrated circuit, a first level shifting integrated circuit, and an image multimedia integrated circuit;

9. The display panel of any one of claims 1-7, wherein the first clock signal output module or the second clock signal output module further comprises: a second level shifting integrated circuit;

10. A display panel control method, characterized in that the display panel control method is applied to the display panel according to any one of the above claims 1 to 9, the display panel comprising: the system-in-chip, the signal adjustment module, the first clock signal output module and the display module which are connected in sequence, wherein the signal adjustment module is also connected with the second clock signal output module and the display module in sequence, and the method comprises the following steps: