CN114841352A

CN114841352A - Quantum calculation processing method and device and electronic equipment

Info

Publication number: CN114841352A
Application number: CN202210513889.8A
Authority: CN
Inventors: 方堃
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2022-05-11
Filing date: 2022-05-11
Publication date: 2022-08-02
Anticipated expiration: 2042-05-11
Also published as: CN114841352B

Abstract

The disclosure provides a quantum computing processing method and device and electronic equipment, and relates to the technical field of quantum computing, in particular to the technical field of quantum circuits. The specific implementation scheme is as follows: obtaining first information, the first information being used to characterize a first structure of the first quantum circuit, the first structure indicating that the first quantum circuit includes a first double-bit quantum gate; decomposing the first quantum circuit based on the first information to obtain M pieces of second information and M weight coefficients corresponding to the M pieces of second information; determining M pieces of third information based on the M pieces of second information, wherein the M pieces of third information are used for respectively representing third structures of M third quantum circuits which are equivalent to the second quantum circuits one by one; simulating the M third quantum circuits based on the M third information to obtain M probability information; and determining a task result of the quantum computing task based on the M probability information and the M weight coefficients.

Description

Quantum calculation processing method and device and electronic equipment

Technical Field

The present disclosure relates to the field of quantum computing technologies, and in particular, to a quantum computing processing method and apparatus, and an electronic device.

Background

The quantum circuit model is a general quantum computation model and can realize any quantum algorithm. The algorithm in the quantum circuit model can be described by using a quantum circuit diagram, which can represent the quantum circuit model very intuitively. A quantum circuit is simulated on a classical computer to realize a quantum algorithm, execute a quantum computing task and provide a basic test environment for the design of the quantum algorithm, so that the design of the quantum algorithm, quantum software and even a quantum computer can be assisted.

At present, the quantum circuit may be simulated based on simulation modes of different data structures such as state vector multiplication (state vector multiplication), decision graph (decision graph), tensor network (tensor network), and the like, or by converting the quantum circuit into a one-way quantum computer (1 WQC) model.

Disclosure of Invention

The disclosure provides a quantum computing processing method and device and electronic equipment.

According to a first aspect of the present disclosure, there is provided a quantum computation processing method including:

obtaining first information characterizing a first structure of a first quantum circuit, the first structure indicating that the first quantum circuit includes a first dual-bit quantum gate, the first quantum circuit being configured to perform quantum computing tasks;

decomposing the first quantum circuit based on the first information to obtain M pieces of second information and M weight coefficients corresponding to the M pieces of second information, wherein the M pieces of second information are used for representing a second structure of M second quantum circuits equivalent to the first quantum circuit, the second structure indicates that the second quantum circuit comprises a single-bit quantum gate obtained by performing qubit decomposition on the first double-bit quantum gate, and M is an integer greater than 1;

determining M pieces of third information based on the M pieces of second information, wherein the M pieces of third information are used for respectively representing third structures of M pieces of third quantum circuits which are equivalent to the second quantum circuits one by one, the third structures indicate that preparation of quantum states in the third quantum circuits is positioned before quantum gate operation, and measurement of quantum bits under calculation is positioned after the quantum gate operation;

simulating the M third quantum circuits based on the M third information to obtain M probability information, wherein the probability information is used for representing the result probability distribution after quantum state evolution is carried out based on one third quantum circuit;

and determining a task result of the quantum computing task based on the M pieces of probability information and the M pieces of weight coefficients.

According to a second aspect of the present disclosure, there is provided a quantum computation processing apparatus including:

an obtaining module configured to obtain first information characterizing a first structure of a first quantum circuit, the first structure indicating that the first quantum circuit includes a first dual-bit quantum gate, the first quantum circuit being configured to perform quantum computation tasks;

a decomposition module, configured to decompose the first quantum circuit based on the first information to obtain M pieces of second information and M pieces of weight coefficients corresponding to the M pieces of second information, where the M pieces of second information are used to represent a second structure of M second quantum circuits equivalent to the first quantum circuit, the second structure indicates that the second quantum circuit includes a single-bit quantum gate obtained by performing qubit decomposition on the first two-bit quantum gate, and M is an integer greater than 1;

a first determining module, configured to determine M pieces of third information based on the M pieces of second information, where the M pieces of third information are used to respectively characterize third structures of M third quantum circuits that are one-to-one equivalent to the second quantum circuits, where the third structures indicate that preparation of quantum states in the third quantum circuits is before operation of a quantum gate, and measurement based on computation of a qubit is after operation of the quantum gate;

the simulation module is used for simulating the M third quantum circuits based on the M third information to obtain M probability information, and the probability information is used for representing the result probability distribution after quantum state evolution is carried out based on one third quantum circuit;

and the second determination module is used for determining a task result of the quantum computing task based on the M pieces of probability information and the M pieces of weight coefficients.

According to a third aspect of the present disclosure, there is provided an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any one of the methods of the first aspect.

According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform any one of the methods of the first aspect.

According to a fifth aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements any of the methods of the first aspect.

According to the technology disclosed by the invention, the problem that the quantum circuit is difficult to simulate is solved, and the simulation difficulty of the quantum circuit is reduced, so that the processing difficulty of a quantum computing task is reduced.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of an exemplary quantum circuit diagram;

FIG. 2 is a schematic diagram of an exemplary quantum circuit list;

fig. 3 is a schematic flow diagram of a quantum computing processing method according to a first embodiment of the disclosure;

FIG. 4 is a schematic diagram of a quantum gate in a quantum circuit partitioned with a CZ gate as a reference;

fig. 5-14 are schematic structural diagrams of a second quantum circuit;

fig. 15-22 are schematic structural diagrams of a third quantum circuit;

fig. 23 is a schematic structural diagram of a quantum circuit diagram of a specific example;

fig. 24 is a schematic structural diagram of a quantum computing processing device according to a second embodiment of the present disclosure;

FIG. 25 is a schematic block diagram of an example electronic device used to implement embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

First embodiment

In the embodiment, the quantum computing processing method relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and can be widely applied to the quantum algorithm simulation scene. The quantum computing processing method of the disclosed embodiment can be executed by the quantum computing processing device of the disclosed embodiment. The quantum computing processing apparatus of the embodiments of the present disclosure may be configured in any electronic device to execute the quantum computing processing method of the embodiments of the present disclosure. The electronic device may be a server or a terminal device, and is not limited specifically here.

The quantum circuit is simulated on a classical computer, and a basic test environment can be provided for the design of a quantum algorithm, so that the design of the quantum algorithm, quantum software and even the quantum computer is assisted, and an economic and convenient algorithm demonstration platform can be provided for education workers and learners of the quantum algorithm, therefore, the quantum circuit simulation is a direction of important attention in academic and industrial fields.

Since the length of the column vector describing the quantum state increases exponentially with the corresponding bit number, it is difficult for a classical computer to simulate a large-scale quantum system, for example, a quantum circuit simulator in the related art can usually simulate the calculation of tens of qubits at most, and thus, the problem of simulation difficulty is common in quantum circuit simulation. However, the Quantum circuit is simulated by converting the Quantum circuit into a One-Way Quantum Computer (1 WQC) model, and although the simulation efficiency of the Quantum circuit can be improved to some extent, this method is not suitable for the Quantum circuit with an entangled structure.

The purpose of this embodiment is to break through the entanglement structure of the quantum circuit, to reduce the simulation difficulty of the quantum circuit, thereby reducing the simulation difficulty of the quantum algorithm. The quantum circuit with the entangled structure, particularly the strongly entangled structure (such as an annular structure formed by entangled gates) is widely applied to the variational quantum algorithm, so that the quantum circuit can be efficiently simulated by breaking the entangled structure of the quantum circuit, thereby effectively simulating the variational quantum algorithm and having important significance for the research and development and application of the variational quantum algorithm in the fields of artificial intelligence, chemical engineering and medicine, financial science and technology and the like.

In order to better explain the scheme of the present embodiment, a quantum circuit model is explained below.

The quantum circuit model is a commonly used quantum computing model. The evolution of the quantum state is completed by performing quantum gate operation on the initial quantum state, and the calculation result is extracted by quantum measurement. And the quantum circuit diagram represents the whole process of quantum circuit model calculation.

Fig. 1 is a schematic diagram of an exemplary quantum circuit diagram, and as shown in fig. 1, a qubit system may be represented by a horizontal line, and qubits are numbered sequentially from top to bottom, where the qubits are often numbered from zero, and the total number of qubits is defined as the width of the quantum circuit, and is denoted by N.

It is usually agreed that the quantum circuit diagram is read from left to right, and the leftmost end is an initial quantum state, wherein each qubit is usually initialized to a zero state, and then different quantum gate operations are sequentially applied to the initial state to complete the evolution of the quantum state. And finally, performing quantum measurement on each qubit system at the rightmost end of the quantum circuit diagram to obtain a measurement result.

The quantum circuit in fig. 1 may be composed of all single-bit quantum gates and control not gates acting on adjacent bits, and if the quantum circuit includes dual-bit quantum gates of non-adjacent bits, it may be changed into quantum gates of adjacent bits by adding SWAP gates.

Quantum measurements in quantum circuits can be defaulted to measurements on a computational basis.

The quantum circuit diagram, except for the initial quantum state and quantum measurement, can be stored by recording all quantum gates in an ordered list according to the action order, according to the storage rule as recorded in table 1.

TABLE 1 storage information table of quantum circuit diagram

Wherein, name is the name of quantum gate, while _ qubit is the qubit acted by quantum gate, while _ qubit of single-bit quantum gate is the qubit acted by quantum gate, while _ qubit of double-bit quantum gate is the list [ control, target ] composed of control bit control and controlled bit target, parameter is the parameter of quantum gate, and if there is no parameter, the default is None.

Given a total of N quantum gates in the quantum circuit diagram, a single stored quantum gate can be designated as g _i (i is more than or equal to 1 and less than or equal to N), after the quantum circuit diagram is stored according to the action sequence of the quantum gate, an ordered list Q obtained can be recorded as shown in the following formula (1):

Q＝[g ₁ ,g ₂ ,...,g _N ] (1)

for example, the quantum circuit shown in fig. 1 may be stored using an ordered list Q as follows:

Q＝[[Rz,0,α],[H,1,None],[Rx,0,β],[CNOT,[0,1],None]，[CNOT,[1,2],None]]。

fig. 2 is a schematic diagram of an exemplary structure of a quantum circuit list, which allows a visual understanding of the structure of the ordered list Q, and as shown in fig. 2, the quantum circuit includes 5 quantum gates, one-to-one corresponding to the elements in the ordered list Q. The quantum circuit reads the quantum gates in the ordered list Q from left to right during actual execution, and executes corresponding quantum gate operations on the specified quantum bits in sequence.

The quantum circuit model is introduced in detail above, and the quantum computing processing method provided by the embodiment of the present disclosure is explained in detail below based on the quantum circuit model.

As shown in fig. 3, the present disclosure provides a quantum computation processing method, including the steps of:

step S301: first information is obtained, the first information characterizing a first structure of a first quantum circuit, the first structure indicating that the first quantum circuit includes a first dual-bit quantum gate, the first quantum circuit being configured to perform quantum computing tasks.

The first information may be structural information of the first quantum circuit, and may characterize a first structure of the first quantum circuit. The first quantum circuit may be any quantum circuit capable of implementing a quantum algorithm, may be used to execute a quantum computing task corresponding to the quantum algorithm, and may be represented by a quantum circuit diagram.

Wherein the first quantum circuit may include N quantum gates, N being a positive integer, the first structure indicating that a first double-bit quantum gate may be included in the N quantum gates, and the number of qubits acting on the first double-bit quantum gate may be two. The number of the first double-bit quantum gates may be one, two or more, and is not particularly limited herein. The N qubits may also include a single-bit qubit gate, and the qubits acting on the single-bit qubit gate may be one.

In the case that the first quantum circuit includes at least two dibit quantum gates, both of the at least two dibit quantum gates may be used as the first dibit quantum gate, or one of the at least two dibit quantum gates may be selected as the first dibit quantum gate. In an alternative embodiment, the dibit quantum gate with the largest label distance of the two qubits acting on the at least two dibit quantum gates may be determined as the first dibit quantum gate, for example, a plurality of entanglement gates act on the qubits (1, 2), (2, 3), (3, 4), (4, 1), respectively, and the plurality of entanglement gates form a ring structure, and the entanglement gate acting on (4, 1) may be determined as the first dibit quantum gate to be used as the quantum gate to be decomposed, so that the ring structure formed by the plurality of entanglement gates may be broken, and thus, as few decomposition times as possible may be used, and the purpose of reducing the difficulty of quantum circuit simulation may be achieved.

The first two-bit quantum gate may be a control Z gate, i.e., a CZ gate, or may be other two-bit quantum gates, which is not specifically limited herein. The first dual bit quantum gate will be described in detail below with the CZ gate as an example, and the decomposition principle of the other dual bit quantum gates is similar.

The qubits acted on by the N qubits may be numbered starting from 0, e.g., 0, 1, …, N-1, or may be otherwise numbered, and are not specifically limited herein.

In an alternative embodiment, the qubits acted on by the N quantum gates may be numbered starting from 0, and the information of the N quantum gates may be ordered in the first information according to the order of action of the quantum gates in the quantum circuit, i.e. the first information may be an ordered list of structures as shown in formula (1) above.

The first information may be obtained in a plurality of manners, for example, in a case where the first quantum circuit is designed based on a quantum computing task, the quantum circuit diagram of the first quantum circuit may be stored according to an action order of the quantum gate, so as to obtain the first information. Or an ordered list corresponding to a first quantum circuit capable of realizing quantum computing tasks and stored in advance can be obtained, and the ordered list is used as first information. And receiving an ordered list corresponding to a first quantum circuit which is capable of realizing quantum computing tasks and sent by other electronic equipment, and taking the ordered list as first information. Or receiving an ordered list corresponding to the first quantum circuit input by the user, and taking the ordered list as the first information.

In addition, the first information may also be acquired as follows:

obtaining fourth information, the fourth information being used to characterize a fourth structure of a fourth quantum circuit, the fourth structure indicating that the fourth quantum circuit includes a second dual-bit quantum gate;

based on the fourth information, performing conversion processing on the fourth quantum circuit to obtain the first information;

wherein the first quantum circuit is equivalent to the fourth quantum circuit;

the conversion process includes: converting the second dual-bit quantum gate into at least two quantum gates equivalent to the second dual-bit quantum gate, the at least two quantum gates including the first dual-bit quantum gate.

The fourth information may be obtained in the same or similar manner as the first information, and the first information representing the first quantum circuit structure equivalent to the fourth quantum circuit may be obtained by performing equivalent conversion on the second dual-bit quantum gate in the fourth quantum circuit to convert the second dual-bit quantum gate into the first dual-bit quantum gate and the other quantum gates. For example, the double-bit quantum gate CNOT gate can be equivalently converted into a double-bit quantum gate CZ gate and an H gate, so that the CNOT gate can be decomposed in a CZ gate decomposition mode, and the decomposition difficulty of other double-bit quantum gates can be reduced.

Step S302: decomposing the first quantum circuit based on the first information to obtain M pieces of second information and M weight coefficients corresponding to the M pieces of second information, wherein the M pieces of second information are used for representing a second structure of M second quantum circuits equivalent to the first quantum circuit, and the second structure indicates that the second quantum circuit comprises a single-bit quantum gate obtained by performing qubit decomposition on the first double-bit quantum gate.

Wherein M is an integer greater than 1.

In this step, the first dual-bit quantum gate may be used as a quantum gate to be decomposed based on the first information, the first quantum circuit may be decomposed, and the first dual-bit quantum gate may be subjected to qubit decomposition in at least two decomposition manners for the first dual-bit quantum gate, so as to decompose the first quantum circuit, thereby obtaining M second information representing M second quantum circuit structures equivalent to the first quantum circuit, and a weight coefficient of each second quantum circuit. Each second information is used to characterize a second structure of a second quantum circuit.

The weighting coefficients are used for representing the decomposition weights of the second quantum circuits for the effect of the first quantum circuit, and the sum of the weighting coefficients of the M second quantum circuits is 1, that is, the weighting effect of the M second quantum circuits can be equivalent to that of the first quantum circuit.

Each decomposition method may obtain a decomposition result of the first dual-bit quantum gate, and performing qubit decomposition on the first dual-bit quantum gate may refer to: the two qubits acting on the first two-bit qubit gate are decomposed, i.e. the entanglement of the two qubits is broken. The qubit decomposition method may include at least one of the following:

respectively acting two qubits on different single-bit qubits;

one qubit acts on a single-bit qubit gate and an intermediate measurement is performed on the other qubit, which may be a computationally-based measurement on the qubit.

The equivalence of the first quantum circuit and the M second quantum circuits may refer to: by simulating the M second quantum circuits multiple times, a sampling result equivalent to the first quantum circuit can be obtained. That is to say, the equivalence means that the M second quantum circuits are equivalent to the first quantum circuit in terms of the effect of the evolution result of the quantum algorithm, where the evolution result of the M second quantum circuits in terms of the quantum algorithm means the weighted evolution result of the M second quantum circuits, that is, the weighting of the weighting coefficient and the evolution result of the second quantum circuit.

The second information characterizes the second quantum circuit structure in the same or similar manner as the first information characterizes the first quantum circuit structure, i.e., the second information may also be an ordered list of structures as shown in equation (1) above.

The qubit decomposition may be performed only on the first dual-bit quantum gate, while the other quantum gates in the first quantum circuit remain unchanged, or may be performed on both the first dual-bit quantum gate and the other dual-bit quantum gates in the first quantum circuit, which is not particularly limited herein.

Step S303: and determining M pieces of third information based on the M pieces of second information, wherein the M pieces of third information are used for respectively representing third structures of M pieces of third quantum circuits which are equivalent to the second quantum circuits one by one, and the third structures indicate that the preparation of quantum states in the third quantum circuits is positioned before the operation of the quantum gates, and the measurement of the quantum bits based on calculation is positioned after the operation of the quantum gates.

In this step, each of the third information is used to characterize a third structure of a third quantum circuit, which may be a standard quantum circuit. The standard quantum circuit can mean that the preparation of the qubit, the operation of the quantum gate and the quantum measurement are all independent operations, and the preparation of the qubit is positioned before the operation of the quantum gate, and the quantum measurement is positioned after the operation of the quantum gate. The quantum measurement refers to the measurement based on the calculation of a qubit.

As shown in fig. 1, the quantum circuit diagram is a standard quantum circuit diagram, qubits are all initially prepared as initial quantum states, which are zero states, the initial quantum states are subjected to quantum gate operation to complete the evolution of the quantum states, and after the evolution, measurement results are extracted through quantum measurement.

In an alternative embodiment, each of the M second quantum circuits may be a standard quantum circuit, that is, the M second information may be determined as the M third information. In another alternative embodiment, the third information is the second information when the second quantum circuit is a standard quantum circuit. In the case where the second quantum circuit is not a standard quantum circuit, if the second quantum circuit includes intermediate measurement of a qubit, the second quantum circuit may be normalized based on second information corresponding to the second quantum circuit to obtain third information. As such, the determination of the M third information may be implemented based on the M second information.

The intermediate measurement refers to measurement under a calculation basis on a quantum state, and the measurement is positioned between two different qubit operations, namely, a first quantum gate operation is firstly carried out according to an initial quantum state, quantum measurement is carried out on the qubit subjected to quantum state evolution by the first quantum gate operation, a measurement result is obtained, then a second quantum gate operation is carried out according to the measurement result, and quantum state evolution is continuously carried out.

Normalizing the second quantum circuit may refer to: it is equivalently deformed to obtain a standard quantum circuit, i.e., a third quantum circuit. The purpose of carrying out equivalent deformation is to postpone quantum measurement to the end of the whole quantum circuit and to advance preparation of quantum states to the front of the whole quantum circuit, and the quantum circuit after equivalent deformation is a standard quantum circuit. In an alternative embodiment, an auxiliary qubit may be introduced, splitting the two processes of quantum measurement and quantum state preparation into two independent operations acting on different qubits, deferring the quantum measurement to the end of the overall quantum circuit, and advancing the preparation of the quantum state to the very front of the overall quantum circuit.

Step S304: and simulating the M third quantum circuits based on the M third information to obtain M probability information, wherein the probability information is used for representing the result probability distribution after quantum state evolution is carried out based on one third quantum circuit.

After obtaining the M pieces of third information, a third quantum circuit may be built based on each piece of third information, and the third quantum circuit may be simulated based on a 1WQC model or other simulation methods.

The M third quantum circuits may be simulated for L times, and the sampling result may be equivalent to the sampling result obtained by simulating the first quantum circuit for L times. The sampling frequency of each third quantum circuit is set according to actual conditions, and the total sampling frequency is ensured to be L when the sampling frequency is set.

Wherein, one simulation may refer to: the evolution of the quantum state is completed from the quantum state of the quantum bit to the operation of the quantum gate, and the measurement result is extracted through the process of quantum measurement, the measurement result is the simulation result of one-time simulation, and the system setting of each simulation is consistent.

Under the condition that a plurality of simulation results are obtained by simulating the third quantum circuit for a plurality of times, the plurality of simulation results can be subjected to statistical processing to obtain the result probability distribution after the quantum state evolution.

Where the second quantum circuit itself is a standard quantum circuit, the probability information may include a probability distribution vector and a weight (weight is 1) of the simulation result. Where the second quantum circuit is not a standard quantum circuit and an ancillary qubit is introduced in the normalization process, the probability information may include an edge probability that the measurement of the ancillary qubit is an intermediate measurement of the quantum state and a conditional probability distribution vector for the remaining quantum states where the measurement of the ancillary qubit is an intermediate measurement of the quantum state. And the probability distribution of the third quantum circuit to the result of quantum state evolution can be obtained through the probability information corresponding to the third quantum circuit.

Step S305: and determining a task result of the quantum computing task based on the M pieces of probability information and the M pieces of weight coefficients.

In this step, the M pieces of probability information and the M pieces of weight coefficients may be weighted to obtain the comprehensive sampling result (which may be a probability distribution vector) of the M pieces of third quantum circuits, which may be equivalent to the sampling result obtained after the simulation of the first quantum circuit, so that the task result of the quantum computing task may be determined based on the comprehensive sampling result of the M pieces of third quantum circuits. For example, the measurement result with the highest probability in the probability distribution vector is determined as the evolution result of the quantum algorithm, so that the task result of the quantum computing task executed based on the quantum algorithm can be obtained.

In this embodiment, the first two-bit quantum gate in the first quantum circuit is equivalently replaced with a single-bit quantum gate to decompose the first quantum circuit, so as to break the entangled structure of the first quantum circuit, thereby reducing the simulation difficulty of the quantum circuit and further reducing the processing difficulty of the quantum computing task.

Optionally, the step S302 specifically includes:

decomposing the first double-bit quantum gate into two parts by an M decomposition mode based on the first information and a first position of the first double-bit quantum gate in the first quantum circuit to obtain M pieces of second information and M pieces of weight coefficients;

wherein the quantum gates in the second quantum circuit acting before the first location are the same as the quantum gates in the first quantum circuit acting before the first location, and the quantum gates in the second quantum circuit acting after the first location are the same as the quantum gates in the first quantum circuit acting after the first location;

wherein, at least one part of two parts obtained by different decomposition modes is different, and the two parts comprise at least one of the following parts:

two single-bit quantum gates;

a single-bit qubit gate and a computationally-based measurement of a first qubit, the first qubit being one of the qubits acting on the first dual-bit qubit gate;

a single-bit qubit gate and a computationally-based measurement of a second qubit, the second qubit being the other qubit acting on the first dual-bit qubit gate.

In this embodiment, when the first quantum circuit is decomposed, taking CZ gate as an example, the first quantum circuit may be abstracted to the form shown in fig. 4 based on the first position of the first two-bit quantum gate in the first quantum circuit, that is, the quantum gate operation in the first quantum circuit is divided into three parts: all quantum gates acting before the first two-bit quantum gate, the first two-bit quantum gate acting on the ith, j-th qubit, and all quantum gates acting after the first two-bit quantum gate, respectively.

The CZ gate is used as a quantum gate to be decomposed, the CZ gate is decomposed in an M decomposition mode according to a first position of the CZ gate in a first quantum circuit based on first information, the CZ gate is equivalently replaced by a single-bit quantum gate, each decomposition mode can be used for decomposing the CZ gate into two parts, at least one of the two parts obtained by decomposition in different decomposition modes is different, and the other parts are kept unchanged.

The first quantum circuit shown in fig. 4 can be decomposed into 10 second quantum circuits, and the circuit diagrams of the 10 second quantum circuits are shown in fig. 5 to 14, which are numbered as a1, a2, … and a 10.

As shown in fig. 5, the CZ door is disassembled in the following manner: the quantum circuit is decomposed into two rotating gates around the z axis, the rotating angle is-pi/2, namely, the rotating gates around the z axis are respectively acted on the ith and jth quantum bits, the rotating angle is-pi/2, a second quantum circuit A1 is obtained through decomposition, and the corresponding weight coefficient of the second quantum circuit is 1/2.

As shown in fig. 6, the CZ door is disassembled in the following manner: the first quantum circuit is decomposed into two rotating gates around the z-axis, the rotating angle is pi/2, namely the rotating gates around the z-axis are respectively acted on the ith and jth quantum bits, the rotating angle is pi/2, the second quantum circuit A2 is obtained through decomposition, and the corresponding weight coefficient of the second quantum circuit is 1/2.

As shown in fig. 7, the CZ door is disassembled in the following manner: and performing calculation-based measurement on the ith quantum bit, wherein the measurement result is 0, preparing a zero state in the ith quantum bit, applying a rotating gate around the z axis to the jth quantum bit, and decomposing by a rotating angle of-pi to obtain a second quantum circuit A3, wherein the corresponding weight coefficient of the second quantum circuit is-1/2.

As shown in fig. 8, the CZ door is disassembled in the following manner: and (3) carrying out calculation-based measurement on the j-th qubit, wherein the measurement result is 0, preparing a zero state in the j-th qubit, applying a rotating gate around the z-axis to the i-th qubit, and decomposing to obtain a second quantum circuit A4, wherein the corresponding weight coefficient of the second quantum circuit is-1/2.

As shown in fig. 9, the CZ door is disassembled in the following manner: and (3) carrying out calculation-based measurement on the ith quantum bit, wherein the measurement result is 0, preparing a zero state in the ith quantum bit, applying a unit gate to the jth quantum bit, and decomposing to obtain a second quantum circuit A5, wherein the corresponding weight coefficient of the second quantum circuit is 1/2.

As shown in fig. 10, the CZ door is disassembled in the following manner: and (3) carrying out calculation-based measurement on the j-th qubit, wherein the measurement result is 1, preparing a state in the j-th qubit, applying a rotating gate around the z-axis to the i-th qubit, and decomposing the state by a rotating angle of-pi to obtain a second quantum circuit A6, wherein the corresponding weight coefficient of the second quantum circuit is 1/2.

As shown in fig. 11, the CZ door is disassembled in the following manner: and (3) carrying out calculation-based measurement on the ith quantum bit, wherein the measurement result is 1, preparing a state in the ith quantum bit, applying a rotating gate around the z axis to the jth quantum bit, and decomposing by a rotating angle of-pi to obtain a second quantum circuit A7, wherein the corresponding weight coefficient of the second quantum circuit is 1/2.

As shown in fig. 12, the CZ door is disassembled in the following manner: and (3) performing calculation-based measurement on the j-th quantum bit, wherein the measurement result is 0, preparing a zero state in the j-th quantum bit, applying a unit gate to the i-th quantum bit, and decomposing to obtain a second quantum circuit A8, wherein the corresponding weight coefficient of the second quantum circuit is 1/2.

As shown in fig. 13, the CZ door is disassembled in the following manner: and (3) carrying out calculation-based measurement on the ith quantum bit, wherein the measurement result is 1, preparing a state in the ith quantum bit, applying a unit gate to the jth quantum bit, and decomposing to obtain a second quantum circuit A9, wherein the corresponding weight coefficient of the second quantum circuit is-1/2.

As shown in fig. 14, the CZ door is disassembled in the following manner: and (3) carrying out calculation-based measurement on the jth qubit, wherein the measurement result is 1, preparing a state in the jth qubit, applying a unit gate to the ith qubit, and decomposing to obtain a second quantum circuit A10, wherein the corresponding weight coefficient of the second quantum circuit is-1/2.

In this embodiment, based on the first information, the first two-bit quantum gate is subjected to the equivalent conversion of the single-bit quantum gate by the M decomposition method at the first position of the first two-bit quantum gate in the first quantum circuit, so as to obtain M pieces of second information and M pieces of weight coefficients. In this way, decomposition of the first quantum circuit can be achieved.

Optionally, step S303 specifically includes:

normalizing the second quantum circuit based on the second information to obtain the third information if the two parts include a computationally based measurement of a target qubit acting in the first dual-bit quantum gate;

determining the second information as the third information in case the two parts comprise two single-bit quantum gates;

wherein the target qubit is the first qubit or the second qubit.

As shown in fig. 5 to 14, in a1 and a2, the CZ gate is decomposed into two revolving gates around the z axis, so that the CZ gate is a standard quantum circuit and does not need to be standardized, while in A3 to a10, because intermediate measurement is carried out on the quantum bit, and then the evolution of the quantum state is continuously carried out according to the measurement result, the CZ gate is not a standard quantum circuit and needs to be standardized to equivalently transform A3 to a10 into a standard quantum circuit, so that the subsequent simulation of the quantum circuit can be facilitated.

Optionally, the normalizing the second quantum circuit based on the second information to obtain the third information includes:

introducing a third qubit at a second position in the second quantum circuit, the third qubit replacing the target qubit acted on by a target qubit in the second quantum circuit, the second position being a position arranged below and adjacent to the target qubit, the target qubit being a qubit acting on the target qubit and acting after the first position;

and preparing the quantum state of the third qubit into a quantum state matched with a target measurement result to obtain the third information, wherein the target measurement result is a measurement result based on calculation of the target qubit.

In this embodiment, the normalization process may be to introduce an auxiliary qubit, i.e., a third qubit, to divide the two processes of quantum measurement and quantum state preparation into two independent operations acting on different qubits, to postpone the quantum measurement to the end of the whole quantum circuit, and to advance the preparation of the quantum state to the front of the whole quantum circuit.

Taking A3 to a10 as an example, the normalization process for A3 may be performed by introducing an auxiliary qubit i' below the ith qubit, keeping the operation modes of the series of quantum gates on the left unchanged, and operating the quantum gate originally operated on the ith qubit in the series of quantum gates on the right on the ith qubit, to prepare the initial quantum state of the ith qubit to be a zero state. The third quantum circuit number obtained after the normalization process is B3, as shown in fig. 15.

The normalization process of a4 may be to introduce an auxiliary qubit j' below the jth qubit, keep the action of the left series of quantum gates unchanged, and apply the quantum gate, which originally acted on the jth qubit, of the right series of quantum gates to the jth qubit, thereby preparing the initial quantum state of the jth qubit to be a zero state. The third quantum circuit number obtained after the normalization process is B4, as shown in fig. 16.

The normalization process of a5 may be to introduce an auxiliary qubit i' below the ith qubit, to maintain the action of the left series of quantum gates unchanged, to act the ith qubit on the ith quantum gate of the right series of quantum gates, and to prepare the initial quantum state of the ith qubit to be zero. The third quantum circuit number obtained after the normalization process is B5, as shown in fig. 17.

The normalization process of a6 may be to introduce an auxiliary qubit j' below the jth qubit, to maintain the action of the left series of quantum gates unchanged, to act on the jth qubit from the right series of quantum gates, and to prepare the initial quantum state of the jth qubit as a state. The third quantum circuit number obtained after the normalization process is B6, as shown in fig. 18.

The normalization process of a7 may be to introduce an auxiliary qubit i' below the ith qubit, keep the action of the left series of qubit gates unchanged, and apply the qubit gate originally acting on the ith qubit in the right series of qubit gates to the ith qubit, thereby preparing the initial quantum state of the ith qubit as a state. The third quantum circuit number obtained after the normalization process is B7, as shown in fig. 19.

The normalization process of A8 may be to introduce an auxiliary qubit j' below the jth qubit, keep the action of the left series of quantum gates unchanged, and apply the quantum gate, which originally acted on the jth qubit, of the right series of quantum gates to the jth qubit, thereby preparing the initial quantum state of the jth qubit to be a zero state. The third quantum circuit number obtained after the normalization process is B8, as shown in fig. 20.

The normalization process of a9 may be to introduce an auxiliary qubit i ' below the ith qubit, to maintain the action of the left series of quantum gates unchanged, to act on the ith ' qubit with the quantum gate of the right series of quantum gates that originally acted on the ith qubit, and to prepare the initial quantum state of the ith ' qubit as one state. The third quantum circuit number obtained after the normalization process is B9, as shown in fig. 21.

The normalization process of a10 may be to introduce an auxiliary qubit j' below the jth qubit, to maintain the action of the left series of quantum gates unchanged, to act on the jth qubit from the right series of quantum gates, and to prepare the initial quantum state of the jth qubit as a state. The third quantum circuit number obtained after the normalization process is B10, as shown in fig. 22.

In this embodiment, the target qubit of the target qubit gate effect in the second quantum circuit is replaced by a third qubit by introducing the third qubit at a second position in the second quantum circuit; and preparing the quantum state of the third quantum bit into a quantum state matched with the target measurement result to obtain third information. In this way, a standardization process for non-standard quantum circuits can be achieved.

In addition, it is consistent with a1 for the third quantum circuit B1, and with a2 for the third quantum circuit B2.

Optionally, the step S304 specifically includes:

simulating the third quantum circuit for K times based on the third information to obtain K first simulation results, wherein K is an integer larger than 1;

and carrying out statistical processing on the first simulation result to obtain the probability information.

Optionally, the performing statistical processing on the first simulation result to obtain the probability information includes:

under the condition that the third quantum circuit comprises the third qubit, performing first statistical processing on the first simulation result to obtain the marginal probability that the measurement result of the target qubit is the target measurement result;

screening the first simulation result to obtain a second simulation result, wherein the second simulation result is a simulation result of the target measurement result of the target qubit in the first simulation result;

performing second statistical processing on the second simulation result to obtain a conditional probability distribution vector, where the conditional probability distribution vector is used to represent the result probability distribution of the remaining qubits in the third quantum circuit except the target qubit when the measurement result of the target qubit is the target measurement result;

wherein the probability information comprises the edge probability and the conditional probability distribution vector.

In this embodiment, M third quantum circuits may be built based on M third information, for example, 10 standard quantum circuits B1 to B10 may be built.

The third quantum circuit may be simulated based on a 1WQC model or other simulation means. And uniformly sampling each third quantum circuit, for example, the total sampling time is L, and 10 third quantum circuits are built, that is, each third quantum circuit samples L/10 times, and K is equal to L/10.

When the third quantum circuit is simulated for multiple times to obtain multiple first simulation results, the multiple first simulation results may be subjected to statistical processing to obtain probability information corresponding to the third quantum circuit.

Taking B1 to B10 as an example, a plurality of first simulation results can be obtained by simulating B1 for a plurality of times, and the first sampling results, i.e., probability information, are obtained by statistically processing the plurality of first simulation results. The first sampling result may include a probability distribution vector of the first simulation result, which may be denoted as p _ { B1}, and since no auxiliary qubit is introduced in B1, the measurement result of the qubit always matches the prepared quantum state of the qubit, recording a weight of w _ { B1} ═ 1.

And B2 is simulated for multiple times to obtain multiple first simulation results, and the multiple first simulation results are subjected to statistical processing to obtain a second sampling result. The second sample result may include a probability distribution vector of the first simulation result, which may be denoted as p _ { B2}, and since no auxiliary qubit is introduced in B2, the measurement result of the qubit always matches the prepared quantum state of the qubit, recording a weight of w _ { B2} ═ 1.

And simulating B3 for multiple times to obtain multiple first simulation results, and performing statistical processing on the multiple first simulation results to obtain a third sampling result. The third sample result may include the probability of occurrence of a measurement 0 on the ith qubit, denoted w _ { B3}, and the probability distribution vectors for the remaining qubits, denoted p _ { B3}, when the measurement 0 on the ith qubit, denoted as w _ { B3 }.

And simulating B4 for multiple times to obtain multiple first simulation results, and performing statistical processing on the multiple first simulation results to obtain a fourth sampling result. The fourth sample result may include the probability of occurrence of a measurement of 0 on the jth qubit, denoted as w _ { B4}, and the probability distribution vectors of the remaining qubits, denoted as p _ { B4}, when the measurement of 0 on the jth qubit is 0.

And simulating B5 for multiple times to obtain multiple first simulation results, and performing statistical processing on the multiple first simulation results to obtain a fifth sampling result. The fifth sample result may include the probability of occurrence of a measurement of 0 on the ith qubit, denoted w _ { B5}, and the probability distribution vectors of the remaining qubits, denoted p _ { B5}, when the measurement of 0 on the ith qubit is 0, denoted as p _ { B5 }.

And simulating B6 for multiple times to obtain multiple first simulation results, and performing statistical processing on the multiple first simulation results to obtain a sixth sampling result. The sixth sample result may include the probability of occurrence of a measurement 1 on the jth qubit, denoted as w _ { B6}, and the probability distribution vectors for the remaining qubits, denoted as p _ { B6}, when the measurement 1 on the jth qubit.

And simulating B7 for multiple times to obtain multiple first simulation results, and performing statistical processing on the multiple first simulation results to obtain a seventh sampling result. The seventh sample result may include the probability of occurrence of a measurement 1 on the ith qubit, denoted w _ { B7}, and the probability distribution vectors for the remaining qubits, denoted p _ { B7}, when the measurement 1 on the ith qubit, denoted as p _ { B7 }.

A plurality of first simulation results can be obtained by simulating B8 for a plurality of times, and the plurality of first simulation results are statistically processed to obtain an eighth sampling result. The eighth sample result may include the probability of occurrence of a measurement 0 on the jth qubit, denoted as w _ { B8}, and the probability distribution vectors for the remaining qubits, denoted as p _ { B8}, when the measurement on the jth qubit is 0.

And simulating B9 for multiple times to obtain multiple first simulation results, and performing statistical processing on the multiple first simulation results to obtain a ninth sampling result. The ninth sample result may include the probability of occurrence of a measurement 1 on the ith qubit, denoted w _ { B9}, and the probability distribution vectors for the remaining qubits, denoted p _ { B9}, when the measurement 1 on the ith qubit, denoted as w _ { B9 }.

A plurality of first simulation results can be obtained by simulating B10 for a plurality of times, and the tenth sampling result is obtained by statistically processing the plurality of first simulation results. The tenth sample result may include the probability of occurrence of a measurement 1 on the jth qubit, denoted w _ { B10}, and the probability distribution vectors for the remaining qubits, denoted p _ { B10}, when the measurement 1 on the jth qubit, denoted as w _ { B10 }.

It should be noted that, when calculating the conditional probability distribution vector, if the qubit measurement result of the delayed measurement does not match the quantum state prepared by the advanced auxiliary qubit (for example, the result on the qubit of the delayed measurement is 1, but a zero state is prepared in advance on the auxiliary qubit), the measurement result is discarded, and the conditional probability distribution vector is obtained based on statistical analysis of the remaining measurement results.

Specifically, when the third qubit, i.e., the auxiliary qubit, is introduced into the third quantum circuit relative to the second quantum circuit, the conditional probability distribution vectors of the remaining qubits are calculated when the measurement result of the target qubit is the target measurement result. Correspondingly, the statistical processing of the plurality of first simulation results may include two steps, where the first step is: performing a first statistical process on the plurality of first simulation results to calculate an edge probability that the measurement result of the target qubit is the target measurement result, and a second step of: and discarding the measurement result of the qubit with delayed measurement in the plurality of first measurement results and the measurement result of the quantum state mismatch prepared by the advanced auxiliary qubit to obtain a second measurement result, and performing a second statistical process on the second measurement result to calculate the conditional probability distribution vector of the rest qubits when the measurement result of the target qubit is the target measurement result.

In the embodiment, the third quantum circuits are respectively built, and are respectively simulated for multiple times, and the simulation result is counted, so that the high-efficiency simulation of the M third quantum circuits can be realized.

Optionally, the step S305 specifically includes:

determining a target probability distribution vector corresponding to the first quantum circuit based on the M weight coefficients and the M probability information;

determining the task result based on the target probability distribution vector.

In the present embodiment, a target probability distribution vector corresponding to the first quantum circuit may be calculated based on the M weight coefficients and the M probability information using the following expression (2).

Wherein, in the above formula (2), p is a target probability distribution vector corresponding to the first quantum circuit, a _k Is numbered as B _k The corresponding weight coefficient of the third quantum circuit,

is numbered as B _k The corresponding weight or edge probability of the third quantum circuit,

number B _k The third quantum circuit of (1) is associated with a probability distribution vector.

And then determining a task result of the quantum computing task according to the target probability distribution vector. For example, the measurement result with the highest probability in the target probability distribution vector is determined as the evolution result of the quantum algorithm, so that the task result of the quantum computing task executed based on the quantum algorithm can be obtained.

Optionally, the first structure indicates that the first quantum circuit includes at least two-bit quantum gates, and the method further includes:

determining a target dual-bit quantum gate in the first quantum circuit as the first dual-bit quantum gate, the target dual-bit quantum gate being a dual-bit quantum gate with the largest label distance of two qubits acted in the at least two dual-bit quantum gates.

In this embodiment, when the first quantum circuit includes at least two dibit quantum gates, one of the dibit quantum gates may be selected as the first dibit quantum gate.

Specifically, the dibit quantum gate with the largest label distance of two qubits acting on at least two dibit quantum gates may be determined as the first dibit quantum gate, and if a plurality of entanglement gates act on qubits (1, 2), (2, 3), (3, 4), (4, 1), respectively, and the plurality of entanglement gates form a ring structure, the entanglement gate acting on (4, 1) may be determined as the first dibit quantum gate to be used as a quantum gate to be decomposed, so that the ring structure formed by the plurality of entanglement gates may be broken, and thus, as few decomposition times as possible may be used, and the purpose of reducing the simulation difficulty of the quantum circuit may be achieved.

Optionally, step S301 specifically includes:

wherein the first quantum circuit is equivalent to the fourth quantum circuit;

In this embodiment, the fourth information may be obtained in the same or similar manner as the first information, and the first information representing the first quantum circuit structure equivalent to the fourth quantum circuit may be obtained by performing equivalent conversion on the second dual-bit quantum gate in the fourth quantum circuit to convert the second dual-bit quantum gate into the first dual-bit quantum gate and the other quantum gates. For example, the double-bit quantum gate CNOT gate can be equivalently converted into a double-bit quantum gate CZ gate and an H gate, so that the CNOT gate can be decomposed in a CZ gate decomposition mode, and the decomposition difficulty of other double-bit quantum gates can be reduced.

The following describes the quantum computing processing method in this embodiment in detail with a specific example.

Fig. 23 is a schematic structural diagram of a specific example quantum circuit diagram, which is a graphical representation of a strongly entangled quantum circuit commonly used in a variation quantum algorithm, as shown in fig. 23. Setting the circuit width as S, initializing S quantum bits to be a zero state, acting a layer of rotation gate (Ry gate) around the y axis on all the quantum bits, and randomly selecting rotation angle parameters; applying a control Z-gate (CZ-gate) to two adjacent qubits in the circuit, and applying a control Z-gate to the first and last qubits, thus forming a strongly entangled structure; applying a layer of rotation gate (Rx gate) around the x axis to all the qubits, and randomly selecting the rotation angle parameters; z measurements are made for all qubits.

When the width S of such a quantum circuit is larger than 25, it is difficult to perform efficient simulation in a common circuit simulation method due to the memory limitation of a computer. In addition, even if the depth of the circuit is small, the 1WQC model is not suitable for simulation due to a strong entangled structure in the circuit.

Therefore, the quantum circuit is decomposed by using the control Z gate 2301 acting on the qubit (S-1, 0) as a quantum gate to be decomposed to break the strongly entangled structure of the quantum circuit, resulting in a1 to a10, and resulting in weight coefficients of a1 to a 10. And normalizing the A1-A10 to obtain B1-B10, performing efficient simulation on the B1-B10 by adopting a 1WQC model, and performing statistical simulation to obtain probability information corresponding to the B1-B10. Then weighting the weighting coefficients of a1 to a10 and the probability information corresponding to B1 to B10 to obtain the comprehensive sampling results of B1 to B10, wherein the comprehensive sampling results are equivalent to the sampling results corresponding to the quantum circuit shown in fig. 23, so that the quantum circuit with the strong entanglement structure can be efficiently simulated, and the processing difficulty of quantum computation can be reduced.

With the quantum circuit shown in fig. 23, quantum circuits with widths S of 8, 9, 10, 11, 12, 16, 20, 25, 30, and 40 were selected in sequence for performance testing. For each circuit, the circuit was simulated 10 times in its entirety and the running time t1 was recorded in seconds. Thereafter, the same quantum circuit was simulated using the quantum computing processing method of the present embodiment, and the operating time t2 was recorded in seconds. The performance comparison table for the two simulations is shown in table 2 below.

Table 2 performance comparison table for two simulation modes

Width S of circuit	8	9	10	11	12	16	20	25	30	40
											Run time t1	4.62	17.91	70.32	297.2	1195.2	NAN	NAN	NAN	NAN	NAN
Run time t2	0.285	0.261	0.306	0.311	0.359	0.642	0.92	0.98	1.37	1.68

Wherein, NaN means that the memory limit of the computer is exceeded, and analog sampling cannot be performed. As can be seen from table 2 above, when the same quantum circuit is simulated by using the quantum computing processing method of this embodiment, the performance is significantly improved in terms of circuit simulation efficiency.

Second embodiment

As shown in fig. 24, the present disclosure provides a quantum computation processing device 2400 including:

an obtaining module 2401, configured to obtain first information, where the first information is used to characterize a first structure of a first quantum circuit, where the first structure indicates that the first quantum circuit includes a first double-bit quantum gate, and the first quantum circuit is used to perform a quantum computation task;

a decomposition module 2402, configured to decompose the first quantum circuit based on the first information to obtain M pieces of second information and M weight coefficients corresponding to the M pieces of second information, where the M pieces of second information are used to characterize a second structure of M second quantum circuits equivalent to the first quantum circuit, the second structure indicates that the second quantum circuit includes a single-bit quantum gate obtained by performing qubit decomposition on the first two-bit quantum gate, and M is an integer greater than 1;

a first determining module 2403, configured to determine M pieces of third information based on the M pieces of second information, where the M pieces of third information are used to respectively characterize a third structure of M third quantum circuits that are one-to-one equivalent to the second quantum circuits, where the third structure indicates that preparation of a quantum state in the third quantum circuit is before a quantum gate operation and a measurement based on computation of a qubit is after the quantum gate operation;

the simulation module 2404 is configured to simulate, based on the M pieces of third information, the M pieces of third quantum circuits to obtain M pieces of probability information, where the probability information is used to represent a result probability distribution after quantum state evolution is performed based on one third quantum circuit;

a second determining module 2405, configured to determine a task result of the quantum computing task based on the M pieces of probability information and the M pieces of weight coefficients.

Optionally, the decomposition module 2402 is specifically configured to:

two single-bit quantum gates;

Optionally, the first determining module 2403 includes:

a normalization processing unit configured to normalize the second quantum circuit based on the second information to obtain the third information, in a case where the two parts include measurement based on a calculation of a target qubit acting in the first dual-bit quantum gate;

a determination unit configured to determine the second information as the third information in a case where the two parts include two single-bit quantum gates;

wherein the target qubit is the first qubit or the second qubit.

Optionally, the normalization processing unit is specifically configured to:

Optionally, the simulation module 2404 includes:

the simulation unit is used for simulating the third quantum circuit for K times based on the third information to obtain K first simulation results, wherein K is an integer larger than 1;

and the statistical processing unit is used for performing statistical processing on the first simulation result to obtain the probability information.

Optionally, the statistical processing unit is specifically configured to:

Optionally, the second determining module 2405 is specifically configured to:

Optionally, wherein the first structure indicates that the first quantum circuit includes at least two-bit quantum gates, the apparatus further comprising:

a third determining module, configured to determine, if the first quantum circuit includes at least two dibit quantum gates, a target dibit quantum gate in the first quantum circuit as the first dibit quantum gate, where the target dibit quantum gate is a dibit quantum gate in which labels of two qubits acted in the at least two dibit quantum gates are the largest in distance.

Optionally, the obtaining module 2401 is specifically configured to:

wherein the first quantum circuit is equivalent to the fourth quantum circuit;

The quantum computing processing device 2400 provided in the present disclosure can implement each process implemented by the quantum computing processing method embodiment, and can achieve the same beneficial effects, and for avoiding repetition, details are not repeated here.

In the technical scheme of the disclosure, the collection, storage, use, processing, transmission, provision, disclosure and other processing of the personal information of the related user are all in accordance with the regulations of related laws and regulations and do not violate the good customs of the public order.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to embodiments of the present disclosure.

FIG. 25 shows a schematic block diagram of an example electronic device that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 25, the apparatus 2500 includes a computing unit 2501, which can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM)2502 or a computer program loaded from a storage unit 2508 into a Random Access Memory (RAM) 2503. In the RAM 2503, various programs and data required for the operation of the device 2500 can also be stored. The calculation unit 2501, ROM 2502, and RAM 2503 are connected to each other via a bus 2504. An input/output (I/O) interface 2505 is also connected to bus 2504.

A number of components in the device 2500 are connected to the I/O interface 2505, including: an input unit 2506 such as a keyboard, a mouse, or the like; an output unit 2507 such as various types of displays, speakers, and the like; a storage unit 2508 such as a magnetic disk, an optical disk, or the like; and a communication unit 2509 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 2509 allows the device 2500 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.

Computing unit 2501 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 2501 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The calculation unit 2501 executes the respective methods and processes described above, such as the quantum calculation processing method. For example, in some embodiments, the quantum computing processing methods may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 2508. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 2500 via the ROM 2502 and/or the communication unit 2509. When the computer program is loaded into RAM 2503 and executed by computing unit 2501, one or more steps of the quantum computing processing method described above may be performed. Alternatively, in other embodiments, the computing unit 2501 may be configured to perform the quantum computing processing method by any other suitable means (e.g., by way of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel or sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A quantum computation processing method, comprising:

obtaining first information characterizing a first structure of a first quantum circuit, the first structure indicating that the first quantum circuit includes a first dual-bit quantum gate, the first quantum circuit to perform a quantum computation task;

2. The method of claim 1, wherein the decomposing the first quantum circuit based on the first information to obtain M second information and M weight coefficients corresponding to the M second information comprises:

two single-bit quantum gates;

3. The method of claim 2, wherein the determining M third information based on M of the second information comprises:

determining the second information as the third information in case the two parts comprise two single bit quantum gates;

wherein the target qubit is the first qubit or the second qubit.

4. The method of claim 3, wherein the normalizing the second quantum circuit based on the second information to obtain the third information comprises:

5. The method of claim 4, wherein the simulating the M third quantum circuits based on the M third information to obtain M probability information comprises:

6. The method of claim 5, wherein the statistically processing the first simulation result to obtain the probability information comprises:

7. The method of claim 1, wherein the determining a task result for the quantum computing task based on the M pieces of probability information and the M pieces of weight coefficients comprises:

8. The method of claim 1, wherein the first structure indicates that the first quantum circuit includes at least two-bit quantum gates;

the method further comprises the following steps:

9. The method of claim 1, wherein the obtaining first information comprises:

wherein the first quantum circuit is equivalent to the fourth quantum circuit;

10. A quantum computation processing apparatus comprising:

11. The apparatus of claim 10, wherein the decomposition module is specifically configured to:

two single-bit quantum gates;

12. The apparatus of claim 11, wherein the first determining means comprises:

wherein the target qubit is the first qubit or the second qubit.

13. The apparatus according to claim 12, wherein the normalization processing unit is specifically configured to:

14. The apparatus of claim 13, wherein the simulation module comprises:

15. The apparatus according to claim 14, wherein the statistical processing unit is specifically configured to:

16. The apparatus of claim 10, wherein the second determining module is specifically configured to:

17. The apparatus of claim 10, wherein the first structure indicates that the first quantum circuit includes at least two-bit quantum gates, the apparatus further comprising:

18. The apparatus according to claim 10, wherein the obtaining module is specifically configured to:

obtaining fourth information characterizing a fourth structure of a fourth quantum circuit, the fourth structure indicating that the fourth quantum circuit includes a second dual-bit quantum gate;

wherein the first quantum circuit is equivalent to the fourth quantum circuit;

19. An electronic device, comprising:

at least one processor; and

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

20. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-9.

21. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-9.