CN114841109B - Equivalent noise charge model design method based on Hooge noise model - Google Patents

Equivalent noise charge model design method based on Hooge noise model Download PDF

Info

Publication number
CN114841109B
CN114841109B CN202210356404.9A CN202210356404A CN114841109B CN 114841109 B CN114841109 B CN 114841109B CN 202210356404 A CN202210356404 A CN 202210356404A CN 114841109 B CN114841109 B CN 114841109B
Authority
CN
China
Prior art keywords
representing
noise
model
mos transistor
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210356404.9A
Other languages
Chinese (zh)
Other versions
CN114841109A (en
Inventor
高武
王建文
高天龙
徐秋双
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northwestern Polytechnical University
Original Assignee
Northwestern Polytechnical University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northwestern Polytechnical University filed Critical Northwestern Polytechnical University
Priority to CN202210356404.9A priority Critical patent/CN114841109B/en
Publication of CN114841109A publication Critical patent/CN114841109A/en
Application granted granted Critical
Publication of CN114841109B publication Critical patent/CN114841109B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/10—Noise analysis or noise optimisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides an equivalent noise charge model design method based on a Hooge noise model. The invention has the advantages that the model accuracy is high, the error of the theoretical ENC model and the actually measured ENC performance can be reduced, the invention can be applied to the low-noise design of the detector front-end readout integrated circuit, and important theoretical guidance is provided for the design of the ultra-low-noise front-end readout integrated circuit.

Description

Equivalent noise charge model design method based on Hooge noise model
Technical Field
The invention belongs to the field of nuclear electronics, and particularly relates to an equivalent noise charge model design method based on a Hooge noise model, which is suitable for a semiconductor radiation detector analog front end readout integrated circuit.
Background
In detector systems such as space radiation detection spectrometers, X-ray diffractometers, electronic personal dosimeters, etc., it is necessary to use high performance radiation detectors and low noise readout electronics to achieve detection of low energy X-rays with energies in the range of 1 to 30 keV. The use of application specific integrated circuits (ASICs for short) to implement all or part of the functionality of the detector front-end readout electronics has become a common solution. Currently, the best noise level is obtained with an analog front end readout circuit that combines a charge sensitive amplifier and an active shaping amplifier. The topology of the common analog front end readout circuit is shown in fig. 1, and mainly comprises a Charge Sensitive Amplifier (CSA), a pole zero cancellation circuit (PZC) and an active shaper (CRRC) based on a folded cascode amplifier structure. The parameter that measures the noise performance of the analog front end readout ASIC is the Equivalent Noise Charge (ENC), which is defined as:
wherein,representing the total noise voltage power at the output of the shaper, v o For amplitude of AC output signal, Q in To input an amount of charge. The smaller the value of ENC, the better the noise performance of the readout electronics system.
A noise model of the detector analog front end readout system is shown in fig. 2. The input noise source consists essentially of current noise and voltage noise, their noise power spectral densityAnd->The following equations respectively give:
the equivalent noise charge ENC can be obtained by noise operation tot The method comprises the following steps:
wherein e represents the electron basic charge amount, t p Represents the shaping time of the shaper, q represents the input charge amount, I det Indicating detector leakage current, R bias Representing detector bias resistance, R f Represents feedback resistance, k is Boltzmann constant, T is absolute temperature, C T Representing the total input capacitance, C f Represents feedback capacitance, gamma represents tunneling coefficient of trap, g m0 Representing the transconductance of an input MOS tube, C ox Representing the transistor gate capacitance density, W 0 And L 0 Representing the gate width and gate length of an input MOS transistor, K is one AND processRelated constants. Depending on the source of the noise, the above formula may be expressed as a combination of ENC components contributing to different noise sources, namely:
wherein ENC i Representing equivalent noise charge components contributed by current noise, ENC w Representing equivalent noise charge component contributed by CSA input transistor thermal noise, ENC f Representing the equivalent noise charge component contributed by the CSA input transistor flicker noise.
The noise model can finish system-level noise performance evaluation, but has the problem that noise modeling is not accurate enough, so that a large error exists between the system-level ENC and the actual ENC.
In the charge-sensitive amplifier circuit shown in fig. 1, ENC f At ENC tot The largest ratio of (c) has an important effect on the overall noise level, resulting in no further reduction of ENC noise floor. In the prior literature, there are two scintillation noise power spectral density models, one is the mcworld scintillation noise model, and the physical explanation of the model is scintillation noise caused by digital fluctuation caused by trap capture and carrier release at the interface of silicon and silicon dioxide. The noise power spectral density of this model is:
wherein N is T Representing the oxide interface trap density per unit volume, W and L represent the gate width and gate length of MOS transistors other than the input MOS transistor. Another model of Hooge noise, the physical explanation, is to assume that the mobility of carriers changes randomly due to photon scattering and lattice interactions, which in turn affects the drain current of the transistor, thereby creating flicker noise. The noise power spectral density of this model is:
wherein μ represents carrier mobility, α H Is a Hooge constant, I denotes the drain current of other MOS transistors than the input MOS transistor. For the NMOS tube working in the strong inversion region, the experimental measured noise result is closer to the McWorther noise model, and for the PMOS tube working in the strong inversion region, the flicker noise experimental result is closer to the Hooge noise model.
Therefore, for the charge-sensitive amplifier shown in fig. 1, since a PMOS transistor is used as an input, modeling it using the mcworld flicker noise model in the prior art is not suitable, resulting in that the noise model is not accurate enough to accurately guide the low noise circuit design. In order to meet the requirements of low detection threshold, high signal to noise ratio of incident photons and particles in some applications, a new equivalent noise model needs to be built for guiding the design of low noise readout circuits.
Disclosure of Invention
In order to overcome the defect that the existing equivalent noise charge model is inaccurate, so that the system-level noise modeling deviates from the actual situation, and the equivalent noise charge substrate cannot be further reduced when a circuit is designed, the invention provides an equivalent noise charge model design method based on a Hooge noise model. The invention has the advantages that the model accuracy is high, the error of the theoretical ENC model and the actually measured ENC performance can be reduced, the invention can be applied to the low-noise design of the detector front-end readout integrated circuit, and important theoretical guidance is provided for the design of the ultra-low-noise front-end readout integrated circuit.
The method for designing the equivalent noise charge model based on the Hooge noise model is characterized by comprising the following steps:
step 1: the equivalent noise charge model based on the Hooge noise model is established as follows:
wherein ENC tot Representing the equivalent noise charge at the system level, e representing the electron fundamental charge quantity, t p Represents the shaping time of the shaper, q represents the input charge amount, I det Represents detector leakage current, k represents Boltzmann constant, T is absolute temperature, R bias Representing detector bias resistance, R f Represents feedback resistance, C det Representing the capacitance of the detector, C in Representing parasitic capacitance of input MOS transistor, C f Represents feedback capacitance, gamma represents tunneling coefficient of trap, g m0 Representing the transconductance, K, of the input MOS transistor fa Representing process parameters, C ox Representing the transistor gate capacitance density, W 0 Represents the gate width, mu of the input MOS transistor p Representing carrier mobility of the PMOS transistor;
according to the simplified model of the MOS transistor, the transconductance g of other PMOS transistors working in the saturation region m And input MOS transistor parasitic capacitance C in The method comprises the following steps of:
wherein L is 0 The gate length of the input MOS transistor is represented, I represents the drain current of other MOS transistors, and W and L represent the gate width and gate length of other MOS transistors; the other MOS transistors refer to MOS transistors except the input MOS transistor;
substituting formula (2) and formula (3) into (1) can result in:
wherein k is 0 、k 1 And k 2 Are constants and are calculated according to the following formulas:
wherein alpha is H Represents the Hooge constant;
step 2: order theObtaining the equivalent noise charge ENC tot Forming time t of former when taking minimum value p The method comprises the following steps:
step 3: order theAnd->Obtaining the equivalent noise charge ENC tot Parasitic capacitance C of input MOS transistor when taking minimum value in And input MOS transistor drain current I D0 The values of (2) are as follows:
C in ＝C det +C f (21)
the beneficial effects of the invention are as follows: the equivalent noise charge model is more accurate, and can more effectively guide the low-noise design of the front-end reading circuit.
Drawings
FIG. 1 is a schematic diagram of a charge integration front-end readout circuit topology;
IN the figure, CSA is a charge sensitive amplifier module, PZC is a zero cancellation circuit, CRRC is an active shaper, IN is an input signal, R pzc For zeroing resistance, OUT is an output signal, VDDA is an analog positive power supply, VSSA is an analog negative power supply, GNDA is an analog ground, M0-M11 are transistors, VB1 and VB2 are voltage biases, R1 and R2 are resistors, and C1 and C2 are capacitors;
FIG. 2 is a schematic diagram of a conventional noise model circuit;
in the figure, V out,CSA For CSA output, V out,CR_RC The CR-RC output is CR-RC Shaper is an active Shaper;
FIG. 3 is a graph comparing simulation results of different equivalent noise models and SPICE models ENC with detector capacitance changes;
FIG. 4 is a graph comparing simulation results of different equivalent noise models and SPICE models ENC over forming time;
FIG. 5 shows the differential equivalent noise model and SPICE model ENC versus capacitanceRatio C in /C det And (5) comparing the simulation results.
Detailed Description
The invention will be further illustrated with reference to the following figures and examples, which include but are not limited to the following examples.
Aiming at the charge integration front end readout circuit structure shown in fig. 1, the invention improves an input tube flicker noise model (shown in fig. 2) in a charge sensitive preamplifier, provides an equivalent noise charge model based on a Hooge noise model, replaces a McWorcher noise model in a formula (3) with a formula (11), and obtains the contribution of flicker noise to total ENC as follows:
thus, a new ENC is obtained tot The model is as follows:
wherein ENC tot Representing the equivalent noise charge at the system level, e representing the electron fundamental charge quantity, t p Represents the shaping time of the shaper, q represents the input charge amount, I det Represents detector leakage current, k represents Boltzmann constant, T is absolute temperature, R bias Representing detector bias resistance, R f Represents feedback resistance, C det Representing the capacitance of the detector, C in Representing parasitic capacitance of input MOS transistor, C f Represents feedback capacitance, gamma represents tunneling coefficient of trap, g m0 Representing the transconductance, K, of the input MOS transistor fa Representing process parameters, C ox Representing the transistor gate capacitance density, W 0 Representing the width, μ of the input MOS transistor p The carrier mobility of the PMOS transistor is represented.
From equation (24), it can be seen that the electrical parameters associated with the circuit are:
(1) Detector parameters: detector capacitance C det Bias power of detectorR resistance bias ；
(2) Charge sensitive preamplifier parameters: input MOS transistor M 0 Is of the gate width W 0 Input MOS transistor M 0 Gate length L of (2) 0 Transconductance g of input MOS transistor m0 Feedback resistor R f Feedback capacitor C f ；
(3) Shaper parameters: forming time t of former p ；
To obtain ENC tot Is essentially a multi-parameter optimization combination problem. With reference to the reduced model of the MOS transistor, the transconductance g of other PMOS transistors operating in the saturation region m And input MOS transistor parasitic capacitance C in The method comprises the following steps of:
wherein L is 0 The gate length of the input MOS transistor is shown, and I represents the drain current of the other MOS transistor.
Substituting equation (25) and equation (26) into equation (24) yields:
wherein k is 0 、k 1 And k 2 Are all constants, respectively:
wherein L is 0 Representing the gate length, alpha, of an input MOS transistor H Representing the Hooge constant.
In the design of the detector readout system, after the detector model is selected, the detector capacitance C det Is determined; when the incident particle energy range is determined, the input range of the charge-sensitive preamplifier can also be determined, C f Is also determined. At ENC tot In the minimum optimization, only the drain current I of the input MOS transistor is finally existed D0 Forming time t of former p And the parasitic capacitance of the input MOS transistor is C in Three unknowns.
ENC tot The optimization process of the minimum value is as follows:
first, let theObtaining ENC tot Forming time t of former when taking minimum value p The method comprises the following steps:
similarly, let theAnd->Obtaining ENC tot Parasitic capacitance C of input MOS transistor when taking minimum value in And input MOS transistor drain current I D0 The optimum values of (2) are as follows:
C in ＝C det +C f (32)
ENC according to formulas (28) to (30) tot The condition of minimum value is taken, relevant circuit parameters are related, the method can be used for low-noise design of the front end readout integrated circuit of the detector, and specific calculation processes and steps are given in table 1.
TABLE 1
Wherein Q is in,max Represents the maximum input charge amount, A Q Representing the system output gain, W 0,6 Representing the width, L, of transistors M0 and M6 0,6 Representing the lengths of transistors M0 and M6, L min Represents the minimum value of transistor length, g m1,7 Representing the transconductance, r, of transistors M1 and M7 ds0,6 Represents the drain-source resistance of transistors M0 and M6, lambda represents the channel modulation factor, I 0,6 Representing drain currents, W, of transistors M0 and M6 1,7 Representing the width, L, of transistors M1 and M7 1,7 Represents the length, μ of transistors M1 and M7 n Indicating carrier mobility of NMOS transistor, I 1,7 Representing the drain currents, W, of transistors M1 and M7 4,11 Representing the width, L, of transistors M4 and M11 4,11 Represents the length, g, of transistors M4 and M11 m4,11 Representing the transconductance of transistors M4 and M11, I 4,11 Representing drain currents, W, of transistors M4 and M11 5,10 Representing the width, L, of transistors M5 and M10 5,10 Represents the length, g, of transistors M5 and M10 m5,10 Representing the transconductance, W, of transistors M5 and M10 2,9 Representing the width, L, of transistors M2 and M9 2,9 Represents the length, g, of transistors M2 and M9 m2,9 Representing the transconductance, A, of transistors M2 and M9 v Representing the voltage gain of CSA, r ds3,8 Representing the drain-source resistance, W, of transistors M3 and M8 3,8 Representing the width, L, of transistors M3 and M8 3,8 Indicating the length of transistors M3 and M8. By calculation in the third column of the tableThe formula can obtain the design parameters of the devices in the second column of the table.
FIGS. 3-5 show the use of the literature "Y, duan, Y, et al SENSROC12: A Four-Channel Binary-Output Front-End Readout ASIC for Si-PIN-Based Personal Dosimeters [ J ]]The simulation results of the ENC noise model in 1976-1983 and the equivalent noise charge model using the present invention were compared with the simulation results of the circuit SPICE. Wherein, the stippled line represents the comparison of the simulation result of the ENC noise model of the literature and the simulation result of the SPICE circuit, the solid line represents the comparison of the simulation result of the equivalent noise model of the invention and the simulation result of the SPICE model, the simulation result of ENC along with the change of the capacitance of the detector is shown in FIG. 3, the simulation result of ENC along with the change of the forming time is shown in FIG. 4, and the simulation result of ENC along with the change of the capacitance C is shown in FIG. 5 in /C det And (5) a variable simulation result. As can be seen from fig. 3, the noise model of the present invention has a smaller difference between the simulation result of the noise model and the simulation result of SPICE, and has a smaller slope of both the base noise and the noise; the noise model simulation result and the SPICE simulation result in the literature are large in difference in base noise or noise slope. As can be seen from fig. 4 and fig. 5, the noise model simulation result and the SPICE simulation result of the present invention keep the same variation trend, but the simulation result of the noise model in the literature has a larger variation trend than the SPICE simulation result, and the noise model in the literature cannot accurately guide the design of the low noise readout integrated circuit. Therefore, the equivalent noise charge model provided by the invention is more accurate, and can more effectively guide the low-noise design of the front-end reading circuit.

Claims (1)

1. The method for designing the equivalent noise charge model based on the Hooge noise model is characterized by comprising the following steps:
step 1: the equivalent noise charge model based on the Hooge noise model is established as follows:
wherein ENC tot Representing the equivalent noise charge at the system level, e representing the electron fundamental charge quantity, t p Represents the shaping time of the shaper, q represents the input charge amount, I det Represents detector leakage current, k represents Boltzmann constant, T is absolute temperature, R bias Representing detector bias resistance, R f Represents feedback resistance, C det Representing the capacitance of the detector, C in Representing parasitic capacitance of input MOS transistor, C f Represents feedback capacitance, gamma represents tunneling coefficient of trap, g m0 Representing the transconductance, K, of the input MOS transistor fa Representing process parameters, C ox Representing the transistor gate capacitance density, W 0 Represents the gate width, mu of the input MOS transistor p Representing carrier mobility of the PMOS transistor;
according to the simplified model of the MOS transistor, the transconductance g of other PMOS transistors working in the saturation region m And input MOS transistor parasitic capacitance C in The method comprises the following steps of:
wherein L is 0 The gate length of the input MOS transistor is represented, I represents the drain current of other MOS transistors, and W and L represent the gate width and gate length of other MOS transistors; the other MOS transistors refer to MOS transistors except the input MOS transistor;
substituting formula (2) and formula (3) into (1) can result in:
wherein k is 0 、k 1 And k 2 Are constants and are calculated according to the following formulas:
wherein alpha is H Represents the Hooge constant;
step 2: order theObtaining the equivalent noise charge ENC t o t Forming time t of former when taking minimum value p The method comprises the following steps:
step 3: order theAnd->Obtaining the equivalent noise charge ENC tot Parasitic capacitance C of input MOS transistor when taking minimum value in And input MOS transistor drain current I D0 The values of (2) are as follows:
C in ＝C det +C f (9)
。
CN202210356404.9A 2022-03-29 2022-03-29 Equivalent noise charge model design method based on Hooge noise model Active CN114841109B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210356404.9A CN114841109B (en) 2022-03-29 2022-03-29 Equivalent noise charge model design method based on Hooge noise model

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210356404.9A CN114841109B (en) 2022-03-29 2022-03-29 Equivalent noise charge model design method based on Hooge noise model

Publications (2)

Publication Number Publication Date
CN114841109A CN114841109A (en) 2022-08-02
CN114841109B true CN114841109B (en) 2024-02-23

Family

ID=82564158

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210356404.9A Active CN114841109B (en) 2022-03-29 2022-03-29 Equivalent noise charge model design method based on Hooge noise model

Country Status (1)

Country Link
CN (1) CN114841109B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110208676A (en) * 2019-05-20 2019-09-06 西北工业大学 Front end reads the equivalent noise charge test circuit and test method of integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19930194A1 (en) * 1999-06-30 2001-01-18 Siemens Ag Process for designing low noise integrated amplifier circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110208676A (en) * 2019-05-20 2019-09-06 西北工业大学 Front end reads the equivalent noise charge test circuit and test method of integrated circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
低噪声CMOS电荷灵敏前置放大器;邓智;康克军;程建平;刘以农;;清华大学学报(自然科学版);20051225(12);全文 *
基于迁移率波动的MOSFET线性区域1/f噪声模型;徐建生, 周求湛, 张新发;电子学报;20020825(08);全文 *

Also Published As

Publication number Publication date
CN114841109A (en) 2022-08-02

Similar Documents

Publication Publication Date Title
Gao et al. Design and Characterization of a Low-Noise Front-End Readout ASIC in 0.18-$\mu $ m CMOS Technology for CZT/Si-PIN Detectors
Manghisoni et al. Submicron CMOS technologies for low-noise analog front-end circuits
Kmon et al. Active feedback with leakage current compensation for charge sensitive amplifier used in hybrid pixel detector
Manghisoni et al. Low-noise analog channel for the readout of the Si (Li) detector of the GAPS experiment
Manghisoni et al. Instrumentation for noise measurements on CMOS transistors for fast detector preamplifiers
Noulis et al. Advanced low-noise X-ray readout ASIC for radiation sensor interfaces
CN114841109B (en) Equivalent noise charge model design method based on Hooge noise model
Noulis et al. Noise optimised charge-sensitive CMOS amplifier for capacitive radiation detectors
Gao et al. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager
Yannick Hertz et al. A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications
Kmon et al. Design of analog pixels front-end active feedback
Binkley et al. A low-noise, wideband, integrated CMOS transimpedance preamplifier for photodiode applications
Beikahmadi et al. A low-power continuous-reset CMOS charge-sensitive amplifier for the readout of solid-state radiation detectors
Gogolou et al. CMOS Folded-Cascode versus Inverter-based CSA towards Noise Performance and Speed
Zubrzycka et al. Optimization of low-noise read-out electronics for high energy resolution X-ray strip detectors
Gogolou et al. Charge-Sensitive Amplifiers: Technology Scaling Impact on Noise Performance
Hu et al. A very low power consumption, low noise analog readout chip for capacitive detectors with a power supply of 3.3 V
Noulis et al. SiGe BiCMOS CSA-shaper radiation detection front end: Noise performance and noise modelling
Evariste et al. Noise optimization of readout front ends in CMOS technology with PS circuit
Diba Design of a programmable low-noise and low-power readout channel for solid-state detectors
Britton et al. PATARA: solid-state neutron detector readout electronics with pole-zero and complex shaping and gated baseline restorer for the SNS
Hao Design of microelectronic system based on front-end readout circuit
Cheng et al. A Low-power, Low-Noise Readout ASIC for Gamma-ray Dosimeter Based on CdZnTe Detector
Heanue et al. CMOS detector readout electronics for an emission-transmission medical imaging system
Kaplon et al. Front end electronics for SLHC semiconductor trackers in CMOS 90 nm and 130 nm processes

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant