CN114840149B

CN114840149B - Method and system for analyzing timing stability of super flash memory

Info

Publication number: CN114840149B
Application number: CN202210786669.2A
Authority: CN
Inventors: 李庭育; 陈育鸣; 王展南
Original assignee: Jiangsu Huacun Electronic Technology Co Ltd
Current assignee: Jiangsu Huacun Electronic Technology Co Ltd
Priority date: 2022-07-06
Filing date: 2022-07-06
Publication date: 2022-09-23
Anticipated expiration: 2042-07-06
Also published as: CN114840149A

Abstract

The invention discloses a method and a system for analyzing the timing stability of a super flash memory, wherein the method comprises the following steps: obtaining first data to be written; obtaining first data scale information; detecting and collecting a first flash memory to obtain a plurality of written information and erased information; presetting a plurality of writing schemes; global optimization is carried out to obtain an optimal writing scheme; writing the first data to be written by adopting the optimal writing scheme; and analyzing the stability of the first flash memory after the first data to be written is written. The method solves the technical problems that when data are written into the flash memory in the prior art, the limitation of the erasing times of the blocks is not considered, and the random and disordered writing of the data causes the unbalanced erasing times of each block, thereby influencing the use stability of the flash memory and even influencing the service life. By writing data in according to the global optimal writing scheme, the technical effects of improving the ordering of data writing and further improving the stability of the flash memory are achieved.

Description

Method and system for analyzing timing stability of super flash memory

Technical Field

The invention relates to the technical field of computers, in particular to a method and a system for analyzing the timing stability of a super flash memory.

Background

Flash memory has come to be used in response to the user's need to store and transfer electronic data information temporarily, quickly, and in small quantities. Compared with a mobile hard disk, the flash memory can store electronic data, wherein the mobile hard disk has large data storage capacity and higher price, so the flash memory is not suitable for user groups with small space capacity, the data reading speed of the flash memory is higher than that of the mobile hard disk, the flash memory has no noise and small heat dissipation, is very suitable for users with small capacity requirements, and in addition, the flash memory can be directly and quickly deleted after temporarily storing and using the data. A flash memory in the related art includes a plurality of blocks, and deletion of each block, that is, the number of times of erasing data, is limited, and once the limit of the number of times of erasing is exceeded, a corresponding block can no longer store data. For example, a certain block in a certain flash memory has ten thousand times of erasing opportunities, and when the number of times of erasing data reaches ten thousand times, the data cannot be stored, that is, the service life of the flash memory is ended. In the prior art, when a user stores data information into a flash memory, the flash memory writes into blocks randomly by default, and the technical problems that some blocks store more data and further erase more times, and some blocks are not used yet, so that the stability of the flash memory is influenced exist. The research of controlling the order of writing data in the flash memory and the priority order of the blocks during storage by using a computer technology has important significance for keeping the stability of the flash memory, prolonging the service life and the like.

However, when data is written into the flash memory in the prior art, the limitation of the number of times of erasing blocks is not considered, and random and disordered writing of the data causes unbalance of the number of times of erasing each block, so that the technical problems that the use stability of the flash memory is influenced, and even the service life is influenced exist.

Disclosure of Invention

The invention aims to provide a method and a system for analyzing the timing stability of a super flash memory, which are used for solving the technical problems that the use stability of the flash memory is influenced and even the service life of the flash memory is influenced because the limit of the erasing times of blocks is not considered when data are written into the flash memory in the prior art and the erasing times of each block are unbalanced due to random and disordered writing of the data.

In view of the foregoing problems, the present invention provides a method and a system for analyzing timing stability of a super flash memory.

In a first aspect, the present invention provides a method for analyzing timing stability of a super flash memory, where the method is implemented by a system for analyzing timing stability of a super flash memory, and the method includes: obtaining first data to be written, wherein the first data to be written is data needing to be written into a first flash memory; acquiring size information of the first data to be written to obtain first data scale information; detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information and erase information; presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, wherein the writing schemes are used for writing the first data to be written into the first flash memory; global optimization is carried out in various writing schemes by taking the balance of the erasing information of a plurality of blocks and the ordered writing as optimization purposes, so as to obtain an optimal writing scheme; writing the first data to be written by adopting the optimal writing scheme; and analyzing the stability of the first flash memory after the first data to be written is written.

In another aspect, the present invention further provides a timing stability analysis system of a super flash memory, configured to execute the timing stability analysis method of the super flash memory according to the first aspect, where the system includes: a first obtaining unit: the first obtaining unit is used for obtaining first data to be written, and the first data to be written is data needing to be written into the first flash memory; a second obtaining unit: the second obtaining unit is used for collecting the size information of the first data to be written to obtain first data scale information; a third obtaining unit: the third obtaining unit is used for detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory, and obtaining a plurality of write-in information and erase information; a first setting unit: the first setting unit is used for presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, and the writing schemes are used for writing the first data to be written into the first flash memory; a fourth obtaining unit: the fourth obtaining unit is used for carrying out global optimization in a plurality of writing schemes by taking the balance of the erasing information and the ordered writing of the plurality of blocks as optimization purposes to obtain an optimal writing scheme; a first writing unit: the first writing unit is used for writing the first data to be written by adopting the optimal writing scheme; a first analysis unit: the first analysis unit is used for analyzing the stability of the first flash memory after the first data to be written is written.

In a third aspect, an electronic device comprises a processor and a memory;

the memory is used for storing;

the processor is configured to execute the method according to any one of the first aspect through calling.

In a fourth aspect, a computer program product comprises a computer program and/or instructions which, when executed by a processor, performs the steps of the method of any of the first aspect described above.

One or more technical schemes provided by the invention at least have the following technical effects or advantages:

1. acquiring the data scale of the data to be written and the writing and erasing information of the flash memory to be written so as to obtain various writing schemes for writing the data to be written into the flash memory to be written; then carrying out global optimization in the obtained multiple writing schemes, and writing the data to be written into the flash memory to be written in the obtained optimal writing scheme; and finally evaluating the stability of the data to be written in the flash memory after the data to be written in is written in. By writing data in according to the overall optimal writing scheme, the technical aim of balancing the times of erasing information of each block in the flash memory to be written is achieved on the basis of ensuring the current data writing requirement, and meanwhile, the technical effect of improving the ordering of data writing and further improving the stability of the flash memory is achieved.

2. By analyzing the use and erasure conditions of each block in the quantized memory and combining the preset erasure time threshold of each block in the flash memory, the current writable and erasable block is obtained, and the technical effects of shortening the optimization range and improving the optimization efficiency are achieved.

3. The optimal writing scheme is determined through a tabu algorithm, so that the local optimal solution is jumped, the quality of the optimal solution is improved, the data writing is ensured to be reasonable and ordered, and the technical effect of erasing balance of each block in the memory after the data writing is ensured.

4. The stability of the model is analyzed based on the group stability index algorithm idea, and the stability of the model is quantized based on data, so that the reliability of the model is visually evaluated, and the technical effect of providing an intelligent model with high accuracy and high reliability for subsequent evaluation of the stability of a storage is achieved.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

In order to more clearly illustrate the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only exemplary, and for those skilled in the art, other drawings can be obtained according to the provided drawings without inventive effort.

FIG. 1 is a schematic flow chart illustrating a method for analyzing timing stability of a super flash memory according to the present invention;

FIG. 2 is a schematic flow chart illustrating an optimal write scheme obtained in the method for analyzing timing stability of a super flash memory according to the present invention;

FIG. 3 is a schematic flow chart illustrating an optimal write scheme according to the historical optimal solution obtained in the method for analyzing timing stability of a super flash memory according to the present invention;

FIG. 4 is a schematic flow chart illustrating a stability analysis result of a first flash memory according to a method for analyzing timing stability of a super flash memory according to the present invention;

FIG. 5 is a schematic structural diagram of a timing stability analysis system of a super flash memory according to the present invention;

FIG. 6 is a schematic diagram of an exemplary electronic device of the present invention;

description of reference numerals:

a first obtaining unit 11, a second obtaining unit 12, a third obtaining unit 13, a first setting unit 14, a fourth obtaining unit 15, a first writing unit 16, a first analyzing unit 17, a bus 300, a receiver 301, a processor 302, a transmitter 303, a memory 304, and a bus interface 305.

Detailed Description

The invention provides a method and a system for analyzing the timing stability of a super flash memory, and solves the technical problems that in the prior art, when data are written into a flash memory, the limitation of the erasing times of blocks is not considered, and the random and disordered writing of the data causes the unbalanced erasing times of each block, so that the use stability of the flash memory is influenced, and even the service life is influenced. By writing data in through a globally optimal writing scheme, the technical goal of balancing the times of erasing information of each block in the flash memory to be written is achieved on the basis of ensuring the current data writing requirement, and meanwhile, the technical effect of improving the ordering of data writing and further improving the stability of the flash memory is achieved.

In the technical scheme of the invention, the data acquisition, storage, use, processing and the like all conform to relevant regulations of national laws and regulations.

The technical solutions in the present invention will be described below clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments of the present invention, and it should be understood that the present invention is not limited by the exemplary embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention. It should be further noted that, for the convenience of description, only some but not all of the elements associated with the present invention are shown in the drawings.

The invention provides a method for analyzing the timing stability of a super flash memory, which is applied to a system for analyzing the timing stability of the super flash memory, wherein the method comprises the following steps: obtaining first data to be written, wherein the first data to be written is data needing to be written into a first flash memory; acquiring size information of the first data to be written to obtain first data scale information; detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information and erase information; presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, wherein the writing schemes are used for writing the first data to be written into the first flash memory; global optimization is carried out in various writing schemes by taking the balance of the erasing information of a plurality of blocks and the ordered writing as optimization purposes, so as to obtain an optimal writing scheme; writing the first data to be written by adopting the optimal writing scheme; and analyzing the stability of the first flash memory after the first data to be written is written.

Having described the general principles of the invention, reference will now be made in detail to various non-limiting embodiments of the invention, examples of which are illustrated in the accompanying drawings.

Example one

Referring to fig. 1, the present invention provides a method for analyzing timing stability of a super flash memory, wherein the method is applied to a system for analyzing timing stability of a super flash memory, and the method specifically includes the following steps:

step S100: obtaining first data to be written, wherein the first data to be written is data needing to be written into a first flash memory;

specifically, the method for analyzing the stability of the time sequence of the super flash memory is applied to the system for analyzing the stability of the time sequence, and the writing position of data can be comprehensively coordinated based on the storage space, the using condition of each block and the like of the super flash memory, so that the stability of the super flash memory can be ensured, and the service life of the super flash memory can be prolonged. The first data to be written refers to data information to be written into the first flash memory, such as various electronic data information such as pictures, texts, videos, and the like. The first flash memory is any flash memory to be used for performing coordination control of data writing, storage and the like by using the timing stabilization system. The flash memory is a memory form capable of repeatedly reading, storing and erasing electronic data information, and is often applied to electronic data transmission and exchange between various electronic devices such as mobile phones and computers, computers and computers. For example, a memory card, a usb flash drive, etc. are flash memories. By obtaining the first data to be written and the first flash memory, the technical effect of providing data and equipment foundation for writing the subsequent data into the flash memory is achieved.

Step S200: acquiring size information of the first data to be written to obtain first data scale information;

specifically, by analyzing the electronic data information to be written into the first flash memory, that is, the first data to be written, the size of the capacity of the memory occupied by the data of the first data to be written, that is, the first data size information can be determined. For example, if the electronic data information to be written into the flash memory is a picture in a jpg format, and the memory size occupied by the picture is 7.18M, the data size of the data to be written is 7.18M. By obtaining the first data scale information, a data basis is provided for a follow-up system to match the storable blocks based on the actual memory size of the data to be written, and the technical effect of improving the adaptability of the system personalized coordination storage blocks is achieved.

Step S300: detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information and erase information;

specifically, the use condition of the flash memory to which the data information is to be written, including the basic parameter information and the use condition of each internal block and page, etc., is statistically analyzed, so as to obtain the use condition of each block of the first flash memory, the capacity of the page, etc., and other parameter information. For example, a certain flash memory has a total page capacity of 8G and 2KB and a block capacity of 256KB, and currently, data information can be written and erased 10000 times per block in the flash memory, wherein a first block is written and erased 5845 times, a second block is written and erased 2655 times, a third block is written and erased 8932 times, and the like, so that the historical writing and erasing information of each block in the flash memory can be clarified. In addition, the data information in the first flash memory is analyzed, so that whether the data information is the garbage data information or not is judged. By obtaining a plurality of writing information and erasing information, the technical effects of determining the used writing and erasing times information of each block in the flash memory and providing a foundation for the system to coordinate the subsequent data writing are achieved.

Step S400: presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, wherein the writing schemes are used for writing the first data to be written into the first flash memory;

specifically, according to the detected and collected historical writing information of the first flash memory, and in combination with the scale information of the space occupied by the data to be written, that is, a plurality of writing schemes for writing the first data to be written into the first flash memory, are obtained in advance. The writing scheme comprises the number of blocks written by data, the corresponding information proportion and other related information. For example, the total video data information is 1.6GB, based on the historical write data information of the flash memory, a plurality of blocks in which data is not written or blocks in which garbage data is stored are erased, and then the video data information is written in different combination manners. By means of the method and the device, multiple writing schemes are generated intelligently based on the scale of the data to be stored and the writing information of the memory, and the technical effects of providing selection and analysis bases and ranges for subsequent comparison analysis and determination of the optimal writing scheme are achieved.

Step S500: global optimization is carried out in various writing schemes by taking the balance of the erasing information of a plurality of blocks and the ordered writing as optimization purposes, so as to obtain an optimal writing scheme;

step S600: writing the first data to be written by adopting the optimal writing scheme;

specifically, historical erased data information of each block in the first flash memory, including relevant information such as data erasing time, data erasing amount, data erasing frequency and the like, is obtained based on historical storage and erased data records of the first flash memory, and further based on existing used data information of the first flash memory, the erased information of each block is balanced, and meanwhile, ordered writing of first data to be written is ensured, traversing and screening are performed in multiple preset writing schemes, and an optimal writing scheme which can balance data erasing of each block and enables the first data to be written to be better in order after writing is obtained. Further, the first data to be written is written into the first flash memory based on an optimal writing scheme obtained through global optimization. For example, the data to be written is written into the flash memory according to the data access sequence or the storage space logic sequence, so that the instability of data reading, modification, erasing and the like caused by random writing is avoided. In this way, after the current data is written, the current data is defaulted to be erased in the future and is preferentially stored in the blocks with less erasing times, so that the erasing times of all the blocks are balanced, and the purpose of ordered writing is also achieved.

And obtaining an optimal writing scheme for writing the first data to be written through global optimization, and further writing the data, thereby achieving the technical effects of balancing the erasing information of each block of the flash memory, ensuring the ordered writing of the data and further prolonging the service life of the flash memory.

Step S700: and analyzing the stability of the first flash memory after the first data to be written is written.

Specifically, after the first data to be written is subjected to data writing in the optimal writing scheme, stability detection analysis is performed on the first flash memory in which the first data to be written is written. By analyzing the actual stability of the flash memory after data is written in and comparing the actual stability with the theory and the preset stability based on the optimal writing scheme, the verification target of the optimal writing scheme is realized, and the technical effect of ensuring the effectiveness and the rationality of the optimal data writing scheme is achieved.

Further, step S300 of the present invention further includes:

step S310: detecting and acquiring whether write-in data exists in a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information;

step S320: judging whether the written data in the block and the page with the written data is garbage data or not, and obtaining a plurality of judgment results;

step S330: adding a plurality of judgment results into a plurality of written information;

step S340: and detecting and collecting the erasing times of the blocks in the previous using process to obtain a plurality of erasing information.

Specifically, before determining the writing scheme for writing the first data to be written into the first flash memory, relevant data such as historical usage of the first flash memory is analyzed. Firstly, data such as the relevant performance and the current use condition of each block and page in the first flash memory are collected, whether data information exists in each current block is further judged, and the data information of the current data, the information of the corresponding storage block and the like are counted. Then, data information analysis is sequentially performed on each block having data information, that is, the data information stored in each block is sequentially analyzed and determined, and it is determined whether the data information of each block is spam or not. Furthermore, a plurality of the written information can be obtained based on the judgment result condition of the data information of each block. And finally, sequentially detecting the times, frequency and the like of erasing data information in the historical use process of each block of the first flash memory before, so as to obtain the plurality of erasing information.

The method has the advantages that the multiple pieces of erasing information are obtained by sequentially analyzing the blocks of the flash memory, and the erasing information of the blocks is determined based on historical actual use conditions, so that the use and erasing conditions of the blocks are visually quantized, and a reference is provided for reasonably formulating a data writing scheme based on the existing erasing use conditions of the blocks.

Further, as shown in fig. 2, step S500 of the present invention further includes:

step S510: setting optimization constraint conditions according to a plurality of writing information and erasing information;

step S520: setting an optimization space according to the optimization constraint condition;

step S530: setting an optimization evaluation parameter according to the erasure information and the ordered writing of the balanced blocks;

step S540: and carrying out global optimization in the optimization space according to the optimization evaluation parameters to obtain the optimal writing scheme.

Further, as shown in fig. 3, step S540 of the present invention further includes:

step S541: randomly selecting and obtaining a writing scheme in the optimizing space as a first writing scheme and as a historical optimal solution;

step S542: calculating and obtaining a first optimizing parameter of the first writing scheme according to the optimizing evaluation parameter;

step S543: according to the writing mode and the erasing mode in the first writing scheme, a first neighborhood of the first writing scheme is constructed in a preset writing scheme conversion mode, and the first neighborhood comprises a plurality of writing schemes;

step S544: calculating and obtaining optimization parameters of all writing schemes in the first neighborhood, and selecting a writing scheme with the optimal optimization parameters as a second writing scheme;

step S545: judging whether a second optimizing parameter of the second writing scheme is superior to the first optimizing parameter, if so, taking the second writing scheme as the historical optimal solution, and if not, not adjusting the historical optimal solution;

step S546: adding the transformation mode of the second writing scheme into a tabu table, wherein the tabu table comprises a tabu iteration number, and deleting the transformation mode of the second writing scheme from the tabu table after the optimization iteration number reaches the tabu iteration number;

step S547: continuously adopting the preset writing scheme conversion mode to construct a second neighborhood of the first writing scheme, and performing iterative optimization;

step S548: and after the iteration optimization reaches a preset iteration number, taking the obtained historical optimal solution as the optimal writing scheme.

Specifically, the scheme that the current first data to be written is written into the first flash memory is analyzed and determined in advance based on the actual situation of the current data to be written and the actual situation of historical use of the data to be stored in the flash memory. And then analyzing all the writing schemes to obtain a writing scheme which enables the erasing times of each block in the first flash memory to be balanced and enables the writing sequence of the first data to be written to be reasonable. When all the writing schemes are analyzed and the optimal writing scheme is determined, optimizing constraint conditions are set on the basis of historical writing data and erasing data information of the first flash memory. And further setting an optimization space according to the optimization constraint condition, namely determining the optimization range of the optimal writing scheme. Wherein the optimization space includes a plurality of writing schemes. And finally, optimizing in an optimizing space based on the optimizing evaluation parameters to obtain an optimal writing scheme. The optimization evaluation parameters are set according to the optimization target, that is, the optimization evaluation parameters include the balance degree of each block in the flash memory after the writing is executed according to the writing scheme, the order degree of the data writing process, the balance degree of the erasing times of each block after the writing, and the like. For example, the number of times of historical erasure data of each block in the memory is arranged in an ascending order, and the data is preferentially written into the block with the smaller number of times of historical erasure.

In the process of global optimization in an optimization space based on optimization evaluation parameters, any scheme is randomly selected based on a plurality of writing schemes in the optimization space, and the selected scheme is used as a historical optimal solution, namely a first writing scheme is randomly selected as an optimal writing scheme for writing the first data to be written into the first flash memory. A first optimization parameter of the first writing scheme is then determined based on the optimization evaluation parameter. Further, a first neighborhood of the first writing scheme is constructed based on historical usage of the first writing scheme, i.e. historical write data information and erasure data information. The method for constructing the first neighborhood, namely the preset writing scheme transformation mode, is determined after comprehensive analysis of the system based on design purposes, actual writing execution and other conditions. For example, when there are X writable blocks in a flash memory, the first data needs to be written into Y blocks, and Y < X, but the selection of the blocks is completely random, the transformation method may be to transform and select m blocks not selected in the first writing scheme for writing, and then obtain the neighborhood, and when m blocks are transformed and selected, the m blocks may be randomly selected from the blocks not selected in the first writing scheme, so that there are multiple schemes in the neighborhood. Further, the optimizing parameters of each writing scheme in the first neighborhood are sequentially calculated, and a group with the optimal optimizing parameters and a corresponding writing scheme are used as a second writing scheme. And when the second optimizing parameter of the second writing scheme is more optimal than the first optimizing parameter of the first writing scheme, replacing the first writing scheme with the second writing scheme, namely taking the second writing scheme as a history optimal solution. Meanwhile, the transformation mode of the second writing scheme is added into the tabu table, and the transformation mode is not adopted in the next neighborhood construction process, namely the transformation of the writing scheme is not carried out by adopting m blocks in the transformation mode, so that the optimization process can be prevented from falling into local optimization. And deleting the transformation mode of the second writing scheme from the tabu table after the optimizing iteration times reach certain tabu iteration times. The taboo iteration times refer to the iteration times determined by the system based on multi-party comprehensive analysis and are stored in a taboo table. And then, continuously adopting the preset writing scheme conversion mode to construct a second neighborhood of the first writing scheme, carrying out iterative optimization, and taking the obtained historical optimal solution as the optimal writing scheme after the iterative optimization reaches a preset iteration number.

The optimal writing scheme is obtained by utilizing the tabu algorithm to carry out global iterative optimization, so that the local optimal solution is jumped off, the quality of the optimal solution is improved, the reasonable and ordered data writing is ensured, and the technical effect of erasing balance of each block in the memory after the data writing is ensured.

Further, step S530 of the present invention further includes:

step S531: obtaining a plurality of writable blocks and a plurality of writable pages according to a plurality of writing information;

step S532: setting a first constraint condition according to a plurality of writable blocks and a plurality of writable pages;

step S533: setting a threshold value of the erasing times of a plurality of blocks according to a plurality of erasing information;

step S534: setting a second constraint condition according to a plurality of erasure time thresholds;

step S535: and taking the first constraint condition and the second constraint condition as the optimizing constraint condition.

Specifically, before global optimization is performed, optimization evaluation parameters for evaluating each writing scheme are comprehensively analyzed and determined based on historical use conditions of the first flash memory, including historical writing data, erasing data and other information, and writing conditions of the first data to be written and the like.

Firstly, determining the information of the currently writable blocks and pages based on the historical write data information of the first flash memory, and taking the writable blocks and pages as first constraint conditions, wherein only the part of the blocks and pages can be written in different write schemes. And then setting the erasing times threshold of each block based on the historical erasing data information of the first flash memory, and writing blocks of which the erasing times are about to exceed the erasing times threshold as far as possible in the writing process, so as to avoid short service life caused by excessive erasing times of a certain block. And finally, combining the first constraint condition and the second constraint condition to obtain the optimizing constraint condition.

The current erasable blocks can be obtained by writing and erasing data information based on the history of the flash memory and combining the preset erasing times threshold of each block in the flash memory, so that the technical effects of restricting, determining the optimizing range and improving the optimizing accuracy and efficiency are achieved.

Further, as shown in fig. 4, step S700 of the present invention further includes:

step S710: acquiring and acquiring a historical writing information set and a historical storage state information set based on big data;

step S720: setting and obtaining a stability analysis result information set based on supervised learning;

step S730: dividing the historical write information set, the historical storage state information set and the stability analysis result information set according to a preset division rule to obtain a training sample, a verification sample and a test sample;

step S740: constructing a stability analysis model based on the neural network model;

step S750: carrying out supervision training, verification and testing on the stability analysis model by adopting the training sample, the verification sample and the testing sample, and obtaining the stability analysis model when the accuracy of the output result of the stability analysis model reaches a preset requirement;

step S760: evaluating the stability of the stability analysis model, and if the stability meets the preset stability requirement, putting the stability analysis model into use;

step S770: after the first data to be written is written, acquiring and acquiring writing information of the first data to be written and storage state information of the first flash memory;

step S780: and inputting the writing information and the storage state information into the stability analysis model to obtain an output result, wherein the output result comprises a stability analysis result of the first flash memory.

Specifically, historical write-in data and erase data of a plurality of flash memories and information such as stability of the flash memories after the data are written correspondingly are collected by utilizing big data, and therefore the intelligent evaluation model of the stability of the flash memories is trained.

Firstly, based on historical write data of each flash memory and a storage state information record after the data is written, a historical write information set and a storage state set of the memory after the data is written corresponding to the history are obtained. And then obtaining a stability analysis result set consisting of various storage stability analysis results based on computer supervised learning. And finally, dividing each data set based on a preset division rule to respectively obtain a training sample, a verification sample and a test sample. The training sample is used for intelligent training of the stability analysis model based on the neural network model, the verification sample is used for intelligent verification of the stability analysis model based on the neural network model, and the test sample is used for intelligent detection of the stability analysis model based on the neural network model. And finally determining the stability analysis model.

Furthermore, stability intelligent analysis is carried out on the stability analysis model obtained through training. The verification sample is used for intelligent verification of the stability analysis model based on the neural network model, and when the accuracy of the verification result display model output result reaches the preset requirement, the stability analysis model is determined to have sufficient precision and can be used for actual application of stability analysis. Therefore, after the first data to be written is written, the writing information of the first data to be written and the storage state information of the first flash memory are collected, so that the stability analysis result of the first flash memory is obtained by using the stability analysis model.

The stability analysis model is obtained through training based on use data such as writing-in and erasing of a historical memory and in combination with data such as memory state change after historical writing-in, model accuracy is further verified, when the accuracy reaches a preset requirement, the stability analysis model is put into use, and the state of a first flash memory, namely the stability condition of the first flash memory, is intelligently obtained after the first information to be written is written into the first flash memory based on an optimal writing scheme. The technical effects of intelligently analyzing the stability of the memory and verifying the reasonability and reliability of the writing scheme are achieved.

Further, step S760 of the present invention further includes:

step S761: inputting the training sample into the stability analysis model to obtain a first output result set;

step S762: obtaining a predictive stability analysis distribution according to the first output result set;

step S763: inputting the verification sample and/or the test sample into the stability analysis model to obtain a second output result set;

step S764: obtaining actual stability analysis distribution according to the second output result set;

step S765: calculating and evaluating the stability of the stability analysis model according to the predicted stability analysis distribution and the actual stability analysis distribution, and calculating by the following formula:

step S766: wherein the ratio of the ith stability analysis result grade in the actual stability distribution, the ratio of the ith stability analysis grade in the predicted stability distribution, and the number of stability analysis grades in the actual stability distribution and the actual stability distribution are provided.

Specifically, before the stability analysis model is put into use, the stability of the model itself, the accuracy of intelligent analysis, and the like are analyzed and determined.

Firstly, inputting a training sample into a stability analysis model to obtain a corresponding output result. And then carrying out stability distribution analysis on the analysis result. And then inputting the verification sample and/or the test sample into a stability analysis model to obtain a corresponding output result, and performing stability distribution analysis on the output result. And the output result obtained based on the training sample is a first output result, and the output result obtained based on the verification sample and/or the test sample is a second output result. Wherein the second output result includes three output possibilities: the first is an output result based on the validation sample only, the second is an output result based on the test sample only, and the third is an output result based on both the validation sample and the test sample. Further, the predicted stability analysis distribution of the stability analysis model obtained based on the first output result is compared with the actual stability analysis distribution of the stability analysis model obtained based on the second output result, and the difference between the two distributions is calculated, wherein the calculation formula is as follows:

wherein the ratio of the ith stability analysis result grade in the actual stability distribution, the ratio of the ith stability analysis grade in the predicted stability distribution, and the number of stability analysis grades in the actual stability distribution and the actual stability distribution are provided.

By calculating the difference between the model predicted stability distribution and the actual stability distribution based on the group stability index algorithm idea and obtaining the model stability analysis result, the technical effect of quantifying the model stability based on data so as to visually evaluate the model reliability is achieved.

In summary, the method for analyzing timing stability of a super flash memory provided by the present invention has the following technical effects:

1. acquiring the data scale of the data to be written, and the writing and erasing information of the flash memory to be written, so as to obtain various writing schemes for writing the data to be written into the flash memory to be written; then, global optimization is carried out in the obtained multiple writing schemes, and the data to be written is written into the flash memory to be written according to the obtained optimal writing scheme; and finally evaluating the stability of the data to be written in the flash memory after the data to be written in is written in. By writing data in through a globally optimal writing scheme, the technical goal of balancing the times of erasing information of each block in the flash memory to be written is achieved on the basis of ensuring the current data writing requirement, and meanwhile, the technical effect of improving the ordering of data writing and further improving the stability of the flash memory is achieved.

4. The stability of the model is analyzed based on the group stability index algorithm idea, and the stability of the model is quantized based on data, so that the reliability of the model is visually evaluated, and the technical effect of providing an intelligent model with high accuracy and high reliability for the subsequent evaluation of the stability of the memory is achieved.

Example two

Based on the same inventive concept as the timing stability analysis method of the super flash memory in the foregoing embodiment, the present invention further provides a timing stability analysis system of a super flash memory, referring to fig. 5, where the system includes:

a first obtaining unit 11, where the first obtaining unit 11 is configured to obtain first data to be written, where the first data to be written is data that needs to be written in a first flash memory;

a second obtaining unit 12, where the second obtaining unit 12 is configured to collect size information of the first data to be written, and obtain first data scale information;

a third obtaining unit 13, where the third obtaining unit 13 is configured to detect and collect write information and erase information of a plurality of blocks and pages in the first flash memory, and obtain a plurality of write information and erase information;

a first setting unit 14, where the first setting unit 14 is configured to set multiple writing schemes in advance according to the first data size information and multiple pieces of the writing information, where the writing schemes are used to write the first data to be written into the first flash memory;

a fourth obtaining unit 15, where the fourth obtaining unit 15 is configured to perform global optimization in multiple writing schemes to obtain an optimal writing scheme, with the purpose of balancing erase information and ordered writing of multiple blocks as optimization goals;

a first writing unit 16, where the first writing unit 16 is configured to write the first data to be written by using the optimal writing scheme;

and the first analysis unit 17 is used for analyzing the stability of the first flash memory after the first data to be written is written.

Further, the system further comprises:

a fifth obtaining unit, configured to detect whether write data exists in a plurality of blocks and pages in the first flash memory, and obtain a plurality of pieces of write information;

a sixth obtaining unit, configured to determine whether write data in the block and the page where the write data exists is garbage data, and obtain a plurality of determination results;

a first adding unit, configured to add the plurality of determination results to the plurality of pieces of written information;

a seventh obtaining unit, configured to detect and collect erasing times of the multiple blocks in a previous use process, and obtain multiple pieces of erasing information.

Further, the system further comprises:

a first setting unit configured to set a seek constraint condition according to a plurality of the write information and the erase information;

a second setting unit for setting an optimization space according to the optimization constraint condition;

a third setting unit configured to set an optimization evaluation parameter according to the erasure information and the ordered writing of the equalized plurality of blocks;

an eighth obtaining unit, configured to perform global optimization in the optimization space according to the optimization evaluation parameter, and obtain the optimal writing scheme.

Further, the system further comprises:

a ninth obtaining unit configured to obtain a plurality of writable blocks and a plurality of writable pages according to a plurality of the write information;

a fourth setting unit configured to set a first constraint condition according to a plurality of the writable blocks and a plurality of the writable pages;

a fifth setting unit configured to set an erase count threshold of the plurality of blocks according to the plurality of pieces of erase information;

a sixth setting unit configured to set a second constraint condition according to the plurality of erasure number thresholds;

a seventh setting unit configured to take the first constraint condition and the second constraint condition as the optimization constraint condition.

Further, the system further comprises:

an eighth setting unit, configured to randomly select and obtain one of the write schemes in the optimization space as a first write scheme and as a historical optimal solution;

a tenth obtaining unit, configured to calculate and obtain a first optimization parameter of the first writing scheme according to the optimization evaluation parameter;

the first construction unit is used for constructing a first neighborhood of the first writing scheme by adopting a preset writing scheme conversion mode according to the writing mode and the erasing mode in the first writing scheme, and the first neighborhood comprises a plurality of writing schemes;

a ninth setting unit, configured to calculate and obtain optimization parameters of all write schemes in the first neighborhood, and select a write scheme with an optimal optimization parameter as a second write scheme;

a first determining unit, configured to determine whether a second optimization parameter of the second writing scheme is better than the first optimization parameter, if so, take the second writing scheme as the historical optimal solution, and if not, not adjust the historical optimal solution;

a second adding unit, configured to add the transformation mode of the second writing scheme into a tabu table, where the tabu table includes a tabu iteration number, and delete the transformation mode of the second writing scheme from the tabu table after an optimization iteration number reaches the tabu iteration number;

the first execution unit is used for continuously adopting the preset writing scheme transformation mode to construct a second neighborhood of the first writing scheme and carry out iterative optimization;

a tenth setting unit, configured to use the obtained historical optimal solution as the optimal writing scheme after the iteration optimization reaches a preset iteration number.

Further, the system further comprises:

an eleventh obtaining unit, configured to acquire and obtain a history write information set and a history storage state information set based on big data;

a twelfth obtaining unit configured to set to obtain a stability analysis result information set based on supervised learning;

a thirteenth obtaining unit, configured to divide the history write information set, the history storage state information set, and the stability analysis result information set according to a preset division rule, and obtain a training sample, a verification sample, and a test sample;

a second construction unit for constructing a stability analysis model based on a neural network model;

a fourteenth obtaining unit, configured to perform supervised training, verification, and testing on the stability analysis model by using the training sample, the verification sample, and the test sample, and obtain the stability analysis model when an accuracy of an output result of the stability analysis model meets a preset requirement;

the first evaluation unit is used for evaluating the stability of the stability analysis model, and if the stability meets the preset stability requirement, the stability analysis model is put into use;

a fifteenth obtaining unit, configured to acquire and obtain write information of the first data to be written and storage state information of the first flash memory after the first data to be written is written;

a sixteenth obtaining unit, configured to input the writing information and the storage state information into the stability analysis model, and obtain an output result, where the output result includes a stability analysis result of the first flash memory.

Further, the system further comprises:

a seventeenth obtaining unit, configured to input the training sample into the stability analysis model, and obtain a first output result set;

an eighteenth obtaining unit, configured to obtain a predictive stability analysis distribution according to the first output result set;

a nineteenth obtaining unit, configured to input the verification sample and/or the test sample into the stability analysis model, and obtain a second output result set;

a twentieth obtaining unit, configured to obtain an actual stability analysis distribution according to the second output result set;

a second evaluation unit for calculating and evaluating the stability of the stability analysis model based on the predicted stability analysis distribution and the actual stability analysis distribution, calculated by the following formula:

an eleventh setting unit, configured to, wherein, the ratio is the ratio of the ith stability analysis result level in the actual stability distribution, the ratio is the ratio of the ith stability analysis level in the predicted stability distribution, and the number of stability analysis levels in the actual stability distribution and the actual stability distribution.

In this specification, the embodiments are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the aforementioned timing stability analysis method and specific example of the first embodiment in fig. 1 are also applicable to the timing stability analysis system of the super flash memory of this embodiment, and through the foregoing detailed description of the timing stability analysis method of the super flash memory, those skilled in the art can clearly know the timing stability analysis system of the super flash memory in this embodiment, so for the brevity of the description, detailed description is not repeated here. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Exemplary electronic device

The electronic device of the present invention is described below with reference to fig. 6.

Fig. 6 illustrates a schematic structural diagram of an electronic device according to the present invention.

Based on the inventive concept of a timing stability analysis method of a super flash memory in the foregoing embodiments, the present invention further provides a timing stability analysis system of a super flash memory, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps of any one of the foregoing timing stability analysis methods of a super flash memory.

Where in fig. 6 a bus architecture (represented by bus 300), bus 300 may include any number of interconnected buses and bridges, bus 300 linking together various circuits including one or more processors, represented by processor 302, and memory, represented by memory 304. The bus 300 may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface 305 provides an interface between the bus 300 and the receiver 301 and transmitter 303. The receiver 301 and the transmitter 303 may be the same element, i.e., a transceiver, providing a means for communicating with various other apparatus over a transmission medium.

The processor 302 is responsible for managing the bus 300 and general processing, and the memory 304 may be used for storing data used by the processor 302 in performing operations.

The invention provides a time sequence stability analysis method of a super flash memory, which is applied to a time sequence stability analysis system of the super flash memory, wherein the method comprises the following steps: obtaining first data to be written, wherein the first data to be written is data needing to be written into a first flash memory; acquiring size information of the first data to be written to obtain first data scale information; detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information and erase information; presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, wherein the writing schemes are used for writing the first data to be written into the first flash memory; global optimization is carried out in various writing schemes by taking the balance of the erasing information of a plurality of blocks and the ordered writing as optimization purposes, so as to obtain an optimal writing scheme; writing the first data to be written by adopting the optimal writing scheme; and analyzing the stability of the first flash memory after the first data to be written is written. The method solves the technical problems that when data are written into the flash memory in the prior art, the limitation of the erasing times of the blocks is not considered, and the random and disordered writing of the data causes the unbalanced erasing times of each block, thereby influencing the use stability of the flash memory and even influencing the service life. By writing data in through a globally optimal writing scheme, the technical goal of balancing the times of erasing information of each block in the flash memory to be written is achieved on the basis of ensuring the current data writing requirement, and meanwhile, the technical effect of improving the ordering of data writing and further improving the stability of the flash memory is achieved.

The invention also provides an electronic device, which comprises a processor and a memory;

the memory is used for storing;

the processor is configured to execute the method according to any one of the first embodiment through calling.

The invention also provides a computer program product comprising a computer program and/or instructions which, when executed by a processor, performs the steps of the method of any of the above embodiments.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely software embodiment, an entirely hardware embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention is in the form of a computer program product that may be embodied on one or more computer-usable storage media having computer-usable program code embodied therewith. And such computer-usable storage media include, but are not limited to: various media capable of storing program codes, such as a usb disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk Memory, a Compact Disc Read-Only Memory (CD-ROM), and an optical Memory.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a system for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction system which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the present invention and its equivalent technology, it is intended that the present invention also include such modifications and variations.

Claims

1. A method for analyzing timing stability of a super flash memory is characterized by comprising the following steps:

obtaining first data to be written, wherein the first data to be written is data needing to be written into a first flash memory;

acquiring size information of the first data to be written to obtain first data scale information;

detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information and erase information;

presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, wherein the writing schemes are used for writing the first data to be written into the first flash memory;

global optimization is carried out in various writing schemes by taking the balance of the erasing information and the ordered writing of a plurality of blocks as optimization purposes, so as to obtain an optimal writing scheme;

writing the first data to be written by adopting the optimal writing scheme;

analyzing the stability of the first flash memory after the first data to be written is written;

the method for optimizing the erase information and the ordered writing of the plurality of blocks in the multiple writing modes to obtain the optimal writing scheme comprises the following steps:

setting optimizing constraint conditions according to a plurality of writing information and erasing information;

setting an optimization space according to the optimization constraint condition;

setting an optimization evaluation parameter according to the erasure information and the ordered writing of the balanced blocks;

and carrying out global optimization in the optimization space according to the optimization evaluation parameters to obtain the optimal writing scheme.

2. The method of claim 1, wherein the detecting collects write information and erase information of a plurality of blocks and pages in the first flash memory, comprising:

detecting and acquiring whether write-in data exists in a plurality of blocks and pages in the first flash memory to obtain a plurality of write-in information;

judging whether the written data in the block and the page with the written data is garbage data or not, and obtaining a plurality of judgment results;

adding a plurality of judgment results into a plurality of written information;

and detecting and collecting the erasing times of the blocks in the previous using process to obtain a plurality of erasing information.

3. The method of claim 1, wherein setting optimization constraints based on the plurality of write information and erase information comprises:

obtaining a plurality of writable blocks and a plurality of writable pages according to a plurality of writing information;

setting a first constraint condition according to a plurality of writable blocks and a plurality of writable pages;

setting a threshold value of the erasing times of a plurality of blocks according to a plurality of erasing information;

setting a second constraint condition according to a plurality of erasure time thresholds;

and taking the first constraint condition and the second constraint condition as the optimizing constraint condition.

4. The method of claim 1, wherein the global optimization in the optimization space according to the optimization evaluation parameters comprises:

randomly selecting and obtaining a writing scheme in the optimizing space as a first writing scheme and as a historical optimal solution;

calculating and obtaining a first optimizing parameter of the first writing scheme according to the optimizing evaluation parameter;

according to the writing mode and the erasing mode in the first writing scheme, a first neighborhood of the first writing scheme is constructed in a preset writing scheme conversion mode, and the first neighborhood comprises a plurality of writing schemes;

calculating and obtaining optimization parameters of all writing schemes in the first neighborhood, and selecting a writing scheme with the optimal optimization parameters as a second writing scheme;

judging whether a second optimizing parameter of the second writing scheme is superior to the first optimizing parameter, if so, taking the second writing scheme as the historical optimal solution, and if not, not adjusting the historical optimal solution;

adding the transformation mode of the second writing scheme into a tabu table, wherein the tabu table comprises a tabu iteration number, and deleting the transformation mode of the second writing scheme from the tabu table after the optimization iteration number reaches the tabu iteration number;

continuously adopting the preset writing scheme conversion mode to construct a second neighborhood of the first writing scheme, and performing iterative optimization;

and after the iteration optimization reaches a preset iteration number, taking the obtained historical optimal solution as the optimal writing scheme.

5. The method of claim 1, wherein analyzing the stability of the first flash memory after the first data to be written is written comprises:

acquiring and obtaining a historical writing information set and a historical storage state information set based on big data;

setting and obtaining a stability analysis result information set based on supervised learning;

dividing the historical writing information set, the historical storage state information set and the stability analysis result information set according to a preset division rule to obtain a training sample, a verification sample and a test sample;

constructing a stability analysis model based on the neural network model;

carrying out supervision training, verification and testing on the stability analysis model by adopting the training sample, the verification sample and the testing sample, and obtaining the stability analysis model when the accuracy of the output result of the stability analysis model reaches a preset requirement;

evaluating the stability of the stability analysis model, and if the stability meets the preset stability requirement, putting the stability analysis model into use;

after the first data to be written is written, acquiring and acquiring writing information of the first data to be written and storage state information of the first flash memory;

and inputting the writing information and the storage state information into the stability analysis model to obtain an output result, wherein the output result comprises a stability analysis result of the first flash memory.

6. The method of claim 5, wherein said evaluating the stability of said stability analysis model comprises:

inputting the training sample into the stability analysis model to obtain a first output result set;

obtaining a predictive stability analysis distribution according to the first output result set;

inputting the verification sample and/or the test sample into the stability analysis model to obtain a second output result set;

obtaining actual stability analysis distribution according to the second output result set;

calculating and evaluating the stability of the stability analysis model according to the predicted stability analysis distribution and the actual stability analysis distribution, and calculating by the following formula:

wherein the content of the first and second substances,

the ratio of the ith stability analysis result grade in the actual stability distribution,

for the proportion of the ith stability analysis grade within the predicted stability profile,

for actual stability distribution and practiceNumber of stability analysis classes within the stability profile.

7. A timing stability analysis system of a super flash memory, the system being applied to the method of any one of claims 1 to 6, the system comprising:

a first obtaining unit: the first obtaining unit is used for obtaining first data to be written, and the first data to be written is data needing to be written into the first flash memory;

a second obtaining unit: the second obtaining unit is used for collecting the size information of the first data to be written to obtain first data scale information;

a third obtaining unit: the third obtaining unit is used for detecting and collecting write-in information and erase information of a plurality of blocks and pages in the first flash memory, and obtaining a plurality of write-in information and erase information;

a first setting unit: the first setting unit is used for presetting a plurality of writing schemes according to the first data scale information and the plurality of writing information, and the writing schemes are used for writing the first data to be written into the first flash memory;

a fourth obtaining unit: the fourth obtaining unit is used for carrying out global optimization in a plurality of writing schemes by taking the balance of the erasing information and the ordered writing of the plurality of blocks as optimization purposes to obtain an optimal writing scheme;

a first writing unit: the first writing unit is used for writing the first data to be written by adopting the optimal writing scheme;

a first analysis unit: the first analysis unit is used for analyzing the stability of the first flash memory after the first data to be written is written;

the fourth obtaining unit is configured to perform global optimization in multiple writing schemes for optimization purposes of balancing erase information and ordered writing of multiple blocks, and obtain the optimal writing scheme, where the obtaining unit includes:

a third setting unit, configured to set an optimization evaluation parameter according to the erasure information and the ordered writing of the equalized plurality of blocks;

8. An electronic device comprising a processor and a memory;

the memory is used for storing;

the processor is used for executing the method of any one of claims 1-6 through calling.

9. A computer program product comprising a computer program and/or instructions, characterized in that the computer program and/or instructions, when executed by a processor, implement the steps of the method of any one of claims 1 to 6.