CN114826213B

CN114826213B - Method for constructing filter, computing device and storage medium

Info

Publication number: CN114826213B
Application number: CN202210475537.8A
Authority: CN
Inventors: 刘国柱
Original assignee: Xuanzhi Electronic Technology Shanghai Co ltd
Current assignee: Xuanzhi Electronic Technology Shanghai Co ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-11-22
Anticipated expiration: 2042-04-29
Also published as: CN114826213A

Abstract

Embodiments of the present disclosure relate to methods, filters, computing devices, and storage media for constructing filters. In the method, a discrete transfer function of a filter to be constructed is obtained; calculating a first difference between a non-integer polynomial coefficient in a denominator polynomial of the discrete transfer function and a reference integer; in response to determining that a first difference value is smaller than a preset threshold value, splitting a non-integer polynomial coefficient corresponding to the first difference value into a first gain coefficient and a second gain coefficient; and respectively constructing a first feedback branch and a second feedback branch based on the first gain coefficient and the second gain coefficient so as to form the target filter. The method can improve the quantization precision of the filter coefficient, remarkably reduce the quantization error and ensure that the target filter still keeps good performance under the condition of higher sampling frequency.

Description

Method for constructing filter, computing device and storage medium

Technical Field

Embodiments of the present disclosure relate generally to the field of digital filters, and more particularly, to a method, filter, computing device, and storage medium for constructing a filter.

Background

In actual control system engineering, a filter is usually used for signal processing. Conventional schemes for constructing filters include, for example: in the theoretical design process, a filter with a continuous structure is used for signal processing, and then the filter is discretized when the filter is applied to an actual system. For example, for first and second order continuous filters, discretization is often performed directly by a zero order keeper, and then the post-discretization filter is used in actual engineering. However, the filter after discretization may generate errors. The above errors mainly originate from three aspects: in a first aspect, compared with an ideal case, the input signal of the filter generates quantization error through analog-to-digital (a/D) conversion; in a second aspect, since the bit width used for representing the number in the computer is limited, the discretized filter coefficients may have quantization errors; in the third aspect, errors may also occur during computation due to limitations of the word size used for the operation. Quantization errors can cause the actual output result to be inconsistent with the theoretical design result. Further, as the sampling frequency of the filter increases, the influence of the quantization error of the filter coefficient becomes more prominent, which may cause the output of the filter to not converge and an unstable pole-zero to appear.

In summary, the conventional scheme of directly constructing the filter according to the coefficients in the discrete transfer function of the filter has the following disadvantages: as the sampling frequency of the filter to be constructed increases, the influence of the quantization error of the filter coefficient becomes more prominent, thereby affecting the performance of the filter.

Disclosure of Invention

In view of the above problems, the present disclosure provides a method, a filter, a computing device, and a storage medium for constructing a filter, which can significantly reduce quantization errors of filter coefficients and ensure performance of the filter.

According to a first aspect of the present disclosure, a method for constructing a filter is provided. The method comprises the following steps: obtaining a discrete transfer function of a filter to be constructed; calculating a first difference value between a non-integer polynomial coefficient in a denominator polynomial of the discrete transfer function and a reference integer, the reference integer being a non-zero integer closest to the non-integer polynomial coefficient, in order to determine whether the first difference value is smaller than a preset threshold value; in response to determining that a first difference value is smaller than a preset threshold value, splitting a non-integer polynomial coefficient corresponding to the first difference value into a first gain coefficient and a second gain coefficient; and respectively constructing a first feedback branch and a second feedback branch based on the first gain coefficient and the second gain coefficient so as to form a target filter, wherein the target filter at least comprises an adder and a target delay unit, the first feedback branch is a feedback branch of which the output end of the target delay unit feeds back to the input end of the adder, and the second feedback branch is a feedback branch of which the output end of the target delay unit feeds back to the input end of the adder. In some embodiments, constructing the first feedback branch and the second feedback branch of the target filter based on the first gain coefficient and the second gain coefficient, respectively, comprises: constructing a first feedback branch based on the first gain coefficient, and constructing a second feedback branch based on the second gain coefficient for constructing a pole network, wherein the pole network at least comprises the adder, and the target delay unit is a delay unit corresponding to the first gain coefficient and the second gain coefficient; constructing a zero network so that one input end of the adder of the pole network receives an output signal of the zero network; and forming a target filter based on the constructed zero network and pole network.

In some embodiments, splitting the polynomial coefficient corresponding to the first difference into a first gain coefficient and a second gain coefficient comprises: and enabling a polynomial coefficient corresponding to the first difference value to be the sum of the first gain coefficient and the second gain coefficient, and enabling the first gain coefficient to be a reference integer corresponding to the first difference value.

In some embodiments, the method for constructing a filter further comprises: in response to determining that the filter to be constructed is a second order filter, determining whether the discrete transfer function of the filter to be constructed can be split into a combination of two first order discrete transfer functions that respectively correspond to first order filters; and in response to determining that the discrete transfer function of the filter to be constructed can be split into a combination of two first-order discrete transfer functions respectively corresponding to first-order filters, respectively obtaining non-integer polynomial coefficients in a denominator polynomial of each split first-order discrete transfer function for respectively calculating first difference values between the non-integer polynomial coefficients and reference integers.

In some embodiments, forming the target filter comprises: aiming at each first-order discrete transfer function obtained by splitting, obtaining a first-order filter and a second first-order filter; and combining the first order filter and the second first order filter to obtain a second order target filter.

In some embodiments, combining the first order filter and the second first order filter to obtain the second order target filter comprises: in response to determining that the discrete transfer function of the filter to be constructed can be split into the multiplication of two first-order discrete transfer functions respectively corresponding to first-order filters, cascading a first-order filter and a second first-order filter to form a second-order target filter; and in response to determining that the discrete transfer function of the filter to be constructed can be split into the addition of two first order discrete transfer functions that respectively correspond to first order filters, connecting the first order filter and the second first order filter in parallel to form a second order target filter.

In some embodiments, forming the target filter further comprises: the output end of the adder is connected with the input end of the target delay unit; and taking the output end of the target delay unit as the output end of the target filter.

In some embodiments, calculating a first difference between a non-integer polynomial coefficient in a denominator polynomial of the discrete transfer function and a reference integer comprises: in response to determining that the filter to be constructed is a second-order filter, respectively calculating first difference values between first-order coefficients and constant coefficients in the denominator polynomial of the discrete transfer function and corresponding reference integers; wherein splitting the non-integer polynomial coefficient corresponding to the first difference into a first gain coefficient and a second gain coefficient comprises: the first-order coefficient is divided into a first-order first gain coefficient and a first-order second gain coefficient, and the constant coefficient is divided into a constant coefficient first gain coefficient and a constant coefficient second gain coefficient.

In some embodiments, constructing the first feedback branch and the second feedback branch to form the target filter based on the first gain coefficient and the second gain coefficient, respectively, comprises: constructing a first-order first feedback branch based on the first-order first gain coefficient, and constructing a first-order second feedback branch based on the first-order second gain coefficient, wherein the first-order first feedback branch is a feedback branch of which the output end of the first target delay unit is fed back to the input end of the adder, and the first-order second feedback branch is a feedback branch of which the output end of the first target delay unit is fed back to the input end of the adder; a constant coefficient first feedback branch is constructed based on a constant coefficient first gain coefficient, and a constant coefficient second feedback branch is constructed based on a constant coefficient second gain coefficient, wherein the constant coefficient first feedback branch is a feedback branch of which the output end of the second target delay unit feeds back to the input end of the adder, and the constant coefficient second feedback branch is a feedback branch of which the output end of the second target delay unit feeds back to the input end of the adder; and the output end of the adder is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the input end of the second delay unit, and the output end of the second delay unit is used as the output end of the target filter.

In some embodiments, obtaining the discrete transfer function of the filter to be constructed comprises: acquiring a continuous transfer function of a filter to be constructed; and generating a discrete transfer function of the filter to be constructed according to the obtained continuous transfer function.

In some embodiments, obtaining the discrete transfer function of the filter to be constructed from the obtained continuous transfer function comprises: and discretizing the obtained continuous transfer function based on a zero-order retainer to obtain a discrete transfer function of the filter to be constructed.

In some embodiments, the preset threshold is less than or equal to 1/2, and the sampling frequency corresponding to the filter to be constructed is greater than or equal to 1KHz (kilohertz).

According to a second aspect of the present disclosure, there is provided a filter constructed in accordance with the method of the first aspect of the present disclosure. The filter includes: a pole network; wherein the pole network comprises at least: an adder; a target delay unit; a first feedback branch, which is a feedback branch from an output end of the target delay unit to an input end of the adder, and corresponds to a first gain coefficient; and a second feedback branch, where the second feedback branch is a feedback branch where an output end of the target delay unit feeds back to an input end of the adder, and the second feedback branch corresponds to a second gain coefficient.

In some embodiments, the filter further comprises: a zero network, wherein an output of the zero network is connected to one input of said adder of the pole network.

According to a third aspect of the present disclosure, a computing device is provided. The computing device includes: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the first aspect of the disclosure.

According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium has stored thereon a computer program which, when executed by a machine, implements a method according to the first aspect of the disclosure. It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements.

Fig. 1 shows a schematic diagram of a discrete system formed by discretizing a continuous transfer function of a first-order low-pass filter based on a zero-order keeper in the prior art.

Fig. 2 shows a schematic structural diagram of a first-order low-pass filter constructed according to formula (4) in the prior art.

Fig. 3 shows a schematic structural diagram of a second-order filter constructed according to equation (6) in the prior art.

Fig. 4 shows a schematic diagram of a computing device for implementing a method for constructing a filter according to an embodiment of the present disclosure.

Fig. 5 shows a flow diagram of a method 500 for constructing a filter of an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a target filter constructed in accordance with a method 500 of an embodiment of the present disclosure.

Fig. 7 shows a flow diagram of a method 700 for constructing a second order target filter of an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of a second order target filter 800 constructed in accordance with the method 700 of an embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of another second order target filter 900 generated according to the method 700 construction of an embodiment of the present disclosure.

Fig. 10 shows a flow diagram of a method 1000 for constructing a filter of an embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a target filter 1100 constructed in accordance with a method 1000 of an embodiment of the disclosure.

Fig. 12 shows an optimization manner corresponding to the filter of the embodiment of the present disclosure.

FIG. 13 illustrates a schematic diagram of a corresponding frequency response amplitude curve for frequency domain amplitude result analysis in an embodiment of the present disclosure.

Fig. 14 shows a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of embodiments of the present disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, in the conventional filter structure directly constructed from the coefficients in the discrete transfer function of the filter, as the sampling period T is reduced, the quantization error of the filter coefficients has more significant influence, which can seriously affect the performance of the filter.

The following is a first order low pass filterFor example, the result derivation process of the discretization is described with reference to fig. 1. Fig. 1 shows a schematic diagram of a discrete system 100 formed by discretizing a first-order low-pass filter 112 based on a zero-order keeper 110 in the prior art. Wherein r (t) represents the input continuous signal, r ^* (t) characterizing the discrete signal obtained on the basis of r (t), c (t) characterizing the output continuous signal ^* (t) characterizing the output discrete signal. The transfer function of the zeroth order keeper 110 is:

wherein, G _k (s) a transfer function characterizing the zeroth order keeper 110, which represents the ratio of the laplace transform of the response (i.e., output) of the zeroth order keeper 110 to the laplace transform of the excitation (i.e., input) under zero initial conditions; s = j ω, where ω denotes angular frequency, j denotes imaginary unit, and T denotes sampling period.

It is assumed that the continuous transfer function expression of the first-order low-pass filter 112 is as shown in the following formula (1).

In the above formula (1), G(s) represents a continuous transfer function representing a ratio of laplace transform of a filter response amount to laplace transform of an excitation amount under a zero initial condition; a denotes the cut-off angular frequency.

It can be concluded that, in an actual system, the continuous transfer function of the first-order low-pass filter 112 is transformed into a discrete transfer function corresponding to the discrete system 100 based on the discretization performed by the zeroth-order keeper 110, and the expression of the discrete transfer function is shown in the following formula (2).

In formula (2), G (z) represents a discrete transfer function,

representative pair

Performing Z transformation, Z = e ^sT 。

From equation (2), further derivation, the discrete transfer function expression corresponding to the discrete system 100 can be transformed as shown in equation (3) below.

As a general form of expression, the formula (3) may be expressed as shown in the following formula (4).

Wherein the coefficients

b ₀ ＝-e ^-aT 。

Fig. 2 shows a schematic diagram of a first-order low-pass filter 200 constructed according to equation (4). Wherein the first order low pass filter 200 comprises a first network 210 and a second network 220, the input of the first order low pass filter 200 is characterized by Fi and the output of the first order low pass filter 200 is characterized by Fo. The first network 210 is a zero point network, and corresponds to the molecular polynomial of the discrete transfer function formula (4), and the specific structure thereof can be implemented by those skilled in the art according to the molecular polynomial of the discrete transfer function formula (4), so that the figure is only summarized and not specifically shown. The second network 220 is a pole network corresponding to the denominator polynomial of the discrete transfer function equation (4). The second network 220 is a feedback network and is composed of an adder 222, a delay unit 224, and a multiplier 226. The multiplier 226 has a coefficient of-b ₀ I.e. constant coefficient b in the denominator polynomial of the discrete transfer function equation (4) ₀ The opposite number of (c). Wherein the multiplier 226 constitutes a feedback branch. The output terminal of the delay unit 224 is fed back and added through the feedback branchAn input of the law 222. Specifically, the output terminal of the delay unit 224 is connected to the input terminal of the multiplier 226, and the output terminal signal of the multiplier 226 is fed back to the input terminal of the adder 222.

When the sampling period T is small, a ₀ ≈0，b ₀ And the value is approximately equal to-1. However, for a ₀ 、b ₀ The quantization error formed by quantization becomes severe as the sampling period T corresponding to the filter becomes smaller, thereby affecting the performance of the first order low pass filter.

Similarly, taking a second-order filter as an example, assume that the continuous transfer function expression of the second-order filter is as shown in the following equation (5).

Where G(s) characterizes the continuous transfer function, ξ characterizes the relative damping ratio, w _n Representing the natural angular frequency.

When the formula (5) is discretized, a discrete transfer function expression of the second order filter is obtained as shown in the following formula (6).

Wherein, a ₁ Is a first order coefficient in a molecular polynomial, a ₀ Is a constant coefficient in a molecular polynomial; b ₁ Is a first order coefficient in a denominator polynomial, b ₀ The second order coefficients in the denominator polynomial are normalized to 1 for the constant coefficients in the denominator polynomial.

Fig. 3 shows a schematic diagram of a second-order filter 300 constructed according to equation (6). The second order filter 300 comprises a first network 310 and a second network 320, the input of the second order filter 300 being characterized by Fi and the output of the second order filter 300 being characterized by Fo. The second network 320 is a feedback network and is composed of an adder 322, a first stage delay unit 324, a second stage delay unit 326, a first stage multiplier 328, and a second stage multiplier 330. Wherein the first stage of multiplier 328 isA number of-b ₁ I.e. first order coefficient b ₁ The opposite number of (c); the second stage multiplier 330 has a coefficient of-b ₀ I.e. constant coefficient b ₀ The opposite number of (c). The output of the first stage delay unit 324 is fed back to the adder 322 via a feedback branch. The output of the second stage delay unit 326 is fed back to the adder 322 via a feedback branch.

Accordingly, a quantization error is introduced in quantizing the filter coefficient in equation (6), and becomes severe as the sampling period T corresponding to the filter becomes smaller, thereby affecting the performance of the second order filter.

To at least partially address one or more of the above issues and other potential issues, example embodiments of the present disclosure provide a filter and a method for constructing a filter, in an aspect of the present disclosure, by obtaining a discrete transfer function of a filter to be constructed; when the non-integer polynomial coefficient in the denominator polynomial of the discrete transfer function is determined to be closer to a reference integer (the reference coefficient is a non-zero integer closest to the non-integer polynomial coefficient) (that is, a first difference value is smaller than a preset threshold), the non-integer polynomial coefficient is split into a first gain coefficient and a second gain coefficient, and a first feedback branch and a second feedback branch are respectively constructed based on the first gain coefficient and the second gain coefficient obtained through splitting so as to form a target filter. Therefore, the scheme provided by the exemplary embodiment of the disclosure can improve the quantization precision of the filter coefficient, significantly reduce the quantization error, and ensure that the target filter still maintains good performance under the condition of higher sampling frequency.

Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings.

Fig. 4 shows a schematic diagram of a computing device 400 for implementing a method for constructing a filter according to an embodiment of the present disclosure. The computing device 400 may have one or more Processing units, including special purpose Processing units such as a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), and general purpose Processing units such as a CPU (Central Processing Unit). Additionally, one or more virtual machines may also be running on each computing device 400. In some embodiments, the computing device 400 comprises, for example, a transfer function acquisition unit 410, a first difference acquisition unit 412, a polynomial coefficient splitting unit 414, a filter generation unit 416.

As regards the transfer function acquisition unit 410, it is used to acquire the discrete transfer function of the filter to be constructed.

Regarding the first difference obtaining unit 412, it is configured to calculate a first difference between a non-integer polynomial coefficient in a denominator polynomial of the discrete transfer function and a reference integer, so as to determine whether the first difference is smaller than a preset threshold. Wherein the reference integer is the nearest non-zero integer to the non-integer polynomial coefficient.

Regarding the polynomial coefficient splitting unit 414, in response to determining that the first difference is smaller than the preset threshold, the non-integer polynomial coefficient corresponding to the first difference is split into a first gain coefficient and a second gain coefficient.

The filter generating unit 416 is configured to respectively construct a first feedback branch and a second feedback branch based on the first gain coefficient and the second gain coefficient so as to form a target filter, where the target filter at least includes an adder and a target delay unit, the first feedback branch is a feedback branch in which an output end of the target delay unit is fed back to an input end of the adder, and the second feedback branch is a feedback branch in which an output end of the target delay unit is fed back to an input end of the adder.

A method 500 for constructing a filter according to an embodiment of the disclosure is described below with reference to fig. 5 and 6. Fig. 5 shows a flow diagram of a method 500 for constructing a filter of an embodiment of the present disclosure. The method 500 may be performed by the computing device 400 as shown in fig. 4, or may be performed at the electronic device 1400 shown in fig. 14. It should be understood that method 500 may also include additional steps not shown and/or may omit steps shown, as the scope of the present disclosure is not limited in this respect.

At step 510, the computing device 400 obtains the discrete transfer function of the filter to be constructed.

As to the method for obtaining the discrete transfer function of the filter to be constructed, it includes, for example: the computing device 400 receives the type and performance parameters of the filter to be constructed, which are input by a user; and generating a discrete transfer function corresponding to the filter to be constructed according to the type and the performance parameters of the filter to be constructed. For example, if the type of the filter to be constructed, which is received by the computing device 400 by the user input, is "low-pass filter", and the performance parameters include "cutoff frequency", "quality factor", and the like, then the computing device 400 generates the discrete transfer function corresponding to the filter to be constructed based on the performance parameters of "low-pass filter", such as "cutoff frequency", "quality factor", and the like. In some alternative embodiments, the computing device 400 may directly receive the discrete transfer function input by the user as the discrete transfer function corresponding to the filter to be constructed. For example, the computing device 400 accepts discrete transfer functions of user input based on a user interface.

In some optional embodiments, the computing device 400 receives a user input of a continuous transfer function corresponding to the filter to be constructed, and converts the continuous transfer function into a discrete transfer function. In particular, the computing device 400 discretizes the acquired continuous transfer function based on a zero-order keeper to obtain a discrete transfer function of the filter to be constructed. For example, the computing device 400 receives the filter to be constructed as a first order low pass filter having a continuous transfer function as shown in equation (7) below.

At step 510, the computing device 400 discretizes equation (7) to obtain a discrete transfer function of the filter to be constructed, which is shown below in equation (8).

According to equation (8), the term of the denominator polynomial of the discrete transfer function with the highest order is the first order term "z", and its corresponding coefficient is the first order coefficient. Where the first order coefficients are normalized to 1.

At step 512, the computing apparatus 400 calculates a first difference between the non-integer polynomial coefficients in the denominator polynomial of the discrete transfer function and the reference integer to determine whether the first difference is less than a preset threshold. Wherein the reference integer is the nearest non-zero integer to the non-integer polynomial coefficient.

As for the first difference, it is, for example, an absolute value of a difference between a non-integer polynomial coefficient in the denominator polynomial of the discrete transfer function and a reference integer. As for the non-integer polynomial coefficient, it is, for example, a coefficient which is not an integer among polynomial coefficients in the denominator polynomial of the discrete transfer function.

Taking equation (8) as an example, computing device 400 identifies the denominator polynomial of the discrete transfer function as "z + b ₀ ". It will be appreciated that the computing apparatus 400 may also identify a molecular polynomial of the discrete transfer function as "a ₀ ". Further, computing device 400 derives a denominator polynomial "z + b ₀ Identification in the sequence yields a first order coefficient "1" and a constant coefficient "b ₀ ". Assuming constant coefficient b ₀ Not an integer, the computing apparatus 400 obtains a constant coefficient b ₀ A corresponding first difference. The first difference is a constant coefficient b ₀ Absolute value of difference with reference integer, reference integer being constant coefficient b ₀ The nearest non-zero integer.

When the sampling frequency of the filter to be constructed is greater than a preset frequency, the constant coefficient b ₀ And the value is approximately equal to-1. Thus, -1 is a constant coefficient b ₀ Corresponding reference integer, the computing device 400 obtains the constant coefficient b ₀ The corresponding first difference is Δ = | b ₀ +1|. In some alternative implementationsIn this way, the predetermined frequency is 1KHz.

At step 514, if the computing device 400 determines that the first difference is less than the predetermined threshold, the non-integer polynomial coefficient corresponding to the first difference is split into a first gain coefficient and a second gain coefficient.

As to the first gain coefficient, it is, for example, equal to the reference integer to which the non-integer polynomial coefficient corresponds. As regards the second gain factor, it is for example equal to the difference of the non-integer polynomial factor and the reference integer (its absolute value is equal to the first difference). As regards the preset threshold, it is, for example, associated with the sampling frequency of the filter to be constructed.

Specifically, according to equation (8), when the sampling frequency of the filter to be constructed is greater than the preset frequency, -1<b ₀ <-1/2. An optional preset threshold Th =1/2. Thus, Δ<Th, i.e., when the computing device 400 determines that the first difference is less than the predetermined threshold, the non-integer polynomial coefficient (e.g., without limitation, constant coefficient b) is set ₀ ) Split into a sum of a first gain factor and a second gain factor. This splitting manner is shown in the following formula (9).

b ₀ ＝-1+r ₀ (9)

Wherein the first gain coefficient is-1, i.e. constant coefficient b ₀ A corresponding reference integer; the second gain coefficient is r ₀ . It can be known that r ₀ <1/2. As the sampling frequency becomes larger, r even appears ₀ ＜＜1/2。

To this end, the computing device 400 adjusts the discrete transfer function of the filter to be constructed from equation (8) to an optimized discrete transfer function. The optimized discrete transfer function is shown in the following equation (10).

At step 516, the computing device 400 constructs a first feedback branch and a second feedback branch, respectively, based on the first gain factor and the second gain factor, so as to form a target filter. The target filter at least comprises an adder and a target delay unit, the first feedback branch is a feedback branch of which the output end of the target delay unit feeds back to the input end of the adder, and the second feedback branch is a feedback branch of which the output end of the target delay unit feeds back to the input end of the adder.

For example, computing device 400 constructs a zero network and a pole network according to equation (10) to form the target filter. Fig. 6 shows a schematic diagram of a target filter 600 constructed in accordance with the method 500 of an embodiment of the present disclosure. Therein, the target filter 600 includes a zero network 610 and a pole network 620. The specific structure diagram of the zero point network 610 is only shown in a general way, and is not specifically shown. Pole network 620 includes at least one adder 622, where one input of adder 622 receives the output signal of zero network 610.

The process of computing device 400 building the pole network includes at least: the first feedback branch 624 is constructed according to a first gain factor (e.g., -1), and according to a second gain factor (e.g., r) ₀ ) A second feedback branch 628 is constructed.

The first feedback branch 624 is a feedback branch for feeding the output of the target delay unit 626 back to the input of the adder 622. The target delay unit 626 is a delay unit in which the first gain coefficient and the second gain coefficient correspond to each other. In some embodiments, the first feedback branch 624 corresponds to a coefficient of 1 (i.e., the inverse of the first gain coefficient-1). In a specific implementation, the first feedback branch 624 is implemented by using a feedback line, so that hardware resources are not additionally occupied.

A second feedback branch 628 is a feedback branch for feeding back the output of the target delay unit 626 to the input of the adder 622.

In an alternative embodiment, the second feedback branch 628 is implemented by a multiplier with a coefficient of-r ₀ . The output end of the target delay unit is connected to the input end of the multiplier; the output of the multiplier is connected to the input of adder 622.

In another alternative embodiment, the second feedback branch 628 is implemented using a multiplier and a sign inversion module. Wherein the multiplier has a coefficient r ₀ . Output terminal of target delay unitAn input terminal connected to the multiplier; the output of the multiplier is connected to a sign inversion module, which inverts the sign of the signal and transmits the inverted signal to the input of the adder 622.

As a first order filter, in the target filter 600, the output terminal of the target delay unit 626 also serves as the output terminal Fo of the target filter 600.

In the prior art, after a discrete transfer function formula (8) is obtained by discretizing a continuous transfer function corresponding to a filter, the filter is directly constructed based on the formula (8), wherein a filter coefficient comprises a constant coefficient b in a denominator polynomial ₀ The resulting coefficients are quantized. Whereas according to the method 500 of this embodiment, non-integer polynomial coefficients (e.g., without limitation, constant coefficients b) are applied ₀ ) Split into a first gain factor (e.g., without limitation, -1) and a second gain factor (e.g., without limitation, r) ₀ ) And constructing the target filter. Comparing the original constant coefficients b ₀ Introduced quantization error and second gain factor r ₀ The introduced quantization error can obtain the advantages and disadvantages of the two schemes. The following text refers to a detailed and rigorous mathematical reasoning, which is only described in general terms in terms of numerical representations. By constant coefficient b ₀ As an example, the normal coefficient b ₀ The quantization is performed and then characterized by a binary number with a predetermined bit width, because the mantissa, which is truncated by the limit of the bit width, corresponds to the quantization error. The more mantissas are rounded off, the larger the quantization error. Because of the constant coefficient b ₀ Close to-1 (larger amplitude), so, at a relatively constant coefficient b ₀ When the characterization is performed, in order to characterize the constant coefficient b ₀ Occupies a larger number of bits, and therefore, has a constant coefficient b ₀ When the representation is performed, the fraction is more rounded off, and the fraction is assumed to be rounded off after the 8 th bit. And inverse second gain coefficient r ₀ It is a small fraction of the magnitude, often 0 in the higher digits. Therefore, for the second gain coefficient r ₀ When quantization is performed and characterization is performed with a binary number having a predetermined bit width, more bits may correspond to the second gain coefficient r ₀ E.g. the 10 th, 11 th or even lower digits after the decimal point, are allAn efficient characterization can be obtained. That is, based on the second gain factor r ₀ And performing quantization characterization, wherein when binary numbers with the same preset bit width are used for characterization, the mantissa part is reduced. Therefore, according to the method 500 of the embodiment, the quantization precision of the filter coefficient can be effectively improved, the quantization error is significantly reduced, and the target filter still maintains good performance under the condition of high sampling frequency.

Accordingly, the present embodiment provides a filter. This filter is the target filter 600. Target filter 600 includes a zero network 610 and a pole network 620. Pole network 620 includes at least one adder 622, where one input of adder 622 receives the output signal of zero network 610. The pole network 620 further includes at least a first feedback branch 624, a second feedback branch 628, and a target delay unit 626.

The first feedback branch 624 is a feedback branch where the output end of the target delay unit 626 feeds back to the input end of the adder 622, and the coefficient corresponding to the first feedback branch 624 is an integer. In this first order filter, the first feedback branch 624 has a coefficient of 1 (i.e., the inverse of the first gain coefficient-1). In a specific implementation, the first feedback branch 624 is implemented by using a feedback line, so that hardware resources are not additionally occupied.

A second feedback branch 628 is a feedback branch for feeding back the output of the target delay unit 626 to the input of the adder 622. The gain coefficient corresponding to the second feedback branch 628 is r ₀ Wherein, | r ₀ And | is less than a preset reference value. An alternative preset reference value is 1/2. When the sampling frequency of the filter is high, | r ₀ |＜＜1/2。

In some optional embodiments, the sampling frequency corresponding to the target filter 600 is greater than the preset frequency, and in some optional embodiments, the preset frequency is 1KHz.

Fig. 7 shows a flow diagram of a method 700 for constructing a second order target filter in accordance with an embodiment of the present disclosure. The method 700 is used to construct a second order target filter. Method 700 is described in detail below.

At step S710, the computing device 400 obtains the discrete transfer function of the filter to be constructed.

It is assumed that the continuous transfer function of the filter to be constructed is as shown in the following equation (11).

The calculation device 400 performs discretization processing on the formula (11) to obtain a discrete transfer function corresponding to the filter to be constructed. The discrete transfer function is shown in the following equation (12).

According to equation (12), the term of the highest order in the denominator polynomial of the discrete transfer function is the quadratic term "z ² ", the corresponding coefficient is a second order coefficient. Where the second order coefficients are normalized to 1.

At step S712, if the computing device 400 determines that the filter to be constructed is a second order filter, it is determined whether the discrete transfer function of the filter to be constructed can be split into a combination of two first order discrete transfer functions, each corresponding to a first order filter.

In particular, the computing device 400 determines whether the discrete transfer function of the filter to be constructed can be split into a combination of two first-order discrete transfer functions that respectively correspond to first-order filters. Wherein, the combination form can be multiplication or addition. It is understood that the case where the coefficient included in one first-order filter is a negative number is included in the form of additive combination. The computing apparatus 400 is able to analyze whether the discrete transfer function can be split into a combination of two first-order discrete transfer functions respectively corresponding to first-order filters based on the numerator polynomial and the denominator polynomial of the discrete transfer function. A person skilled in the art can write a computer program to implement the numerator polynomial and the denominator polynomial based on the discrete transfer function to be able to analyze whether the discrete transfer function can be split, and the specific implementation manner is not described herein again.

If the discrete transfer function of the filter to be constructed can be split into two combinations of first-order discrete transfer functions respectively corresponding to first-order filters, at step 714, respectively obtaining non-integer polynomial coefficients in the denominator polynomial of each split first-order discrete transfer function for respectively calculating a first difference value between the non-integer polynomial coefficients and the reference integer, if the computing apparatus 400 determines that the discrete transfer function of the filter to be constructed can be split into two combinations of first-order discrete transfer functions respectively corresponding to first-order filters.

For example, the computing device 400 splits the discrete transfer function of the filter to be constructed into a combination of two first-order discrete transfer functions.

It is assumed that one of the first-order discrete transfer functions obtained by splitting according to equation (12) is shown in equation (13) below.

Wherein G1 (z) characterizes said one of the first order discrete transfer functions, a1 ₀ Characterizing the constant coefficient in a molecular polynomial, b1 ₀ Constant coefficients in the denominator polynomial are characterized.

Assume that another first-order discrete transfer function obtained by splitting according to equation (12) is shown in equation (14) below.

Wherein G2 (z) characterizes the further first-order discrete transfer function, a2 ₀ Characterizing the constant coefficients in a molecular polynomial, b2 ₀ Constant coefficients in the denominator polynomial are characterized.

If equation (12) can be broken down into a combined form of multiplication of equation (13) and equation (14), the discrete transfer function of the filter to be constructed is shown as equation (15) below.

G(z)＝G1(z)*G2(z) (15)

If equation (12) can be split into a combined form of adding equation (13) and equation (14), the discrete transfer function of the filter to be constructed is as shown in equation (16) below.

G(z)＝G1(z)+G2(z) (16)

At step 716, computing device 400 obtains a first order filter and a second order filter for each split first order discrete transfer function.

For example, computing device 400 derives a first order filter based on method 500 for equation (13) and a second first order filter based on method 500 for equation (14). The detailed process is not described herein.

At step 718, computing device 400 combines the first order filter and the second first order filter to obtain a target filter of second order.

For example, if the discrete transfer function of the filter to be constructed is as shown in equation (15), the computing device 400 cascades the first order filter and the second first order filter to form a second order target filter in response to determining that the discrete transfer function of the filter to be constructed can be split into the multiplication of two first order discrete transfer functions, each corresponding to a first order filter. Fig. 8 shows a schematic diagram of a second order object filter 800 constructed according to the method 700. The second-order target filter 800 is composed of a first-order filter 810 and a second first-order filter 820 in cascade.

If the discrete transfer function of the filter to be constructed is as shown in equation (16), then the computing device 400 connects the first-order filter and the second first-order filter in parallel to form a second-order target filter in response to determining that the discrete transfer function of the filter to be constructed can be split into an addition of two first-order discrete transfer functions that respectively correspond to first-order filters. Fig. 9 shows a schematic diagram of another second order object filter 900 generated according to the method 700. The second-order target filter 900 is formed by connecting a first-order filter 910 and a second first-order filter 920 in parallel.

In some alternative embodiments, the computing device 400 constructs a target filter that is second-order based on the discrete transfer function of the filter to be constructed in response to determining that the discrete transfer function of the filter to be constructed cannot be split into a combination of two first-order discrete transfer functions that respectively correspond to first-order filters.

In some optional embodiments, the computing device 400 does not perform the determination whether the discrete transfer function of the filter to be constructed is split into a combination of two first-order discrete transfer functions respectively corresponding to first-order filters, and constructs a second-order target filter based on the discrete transfer function of the filter to be constructed.

By adopting the means, the method and the device can obviously reduce the second-order filter coefficient quantization error and improve the performance of the second-order filter coefficient quantization error.

At step S1010, the computing device 400 obtains the discrete transfer function of the filter to be constructed.

It is assumed that the discrete transfer function of the filter to be constructed, which characterizes a second order filter, is shown in equation (12).

Thus, at step 1012, if the computing apparatus 400 determines that the filter to be constructed is a second order filter, first differences between first order coefficients, constant coefficients, and corresponding reference integers in the denominator polynomial of the discrete transfer function are calculated, respectively.

When the sampling frequency corresponding to the filter to be constructed is greater than the preset frequency, a ₀ ≈0，a ₁ ≈0，b ₀ ≈1，b ₁ And the value is approximately equal to-2. Thus, in equation (12), the first order coefficient b ₁ The corresponding reference integer is-2, constant coefficient b ₀ The corresponding reference integer is 1.

Then, at step 1014, the computing device 400 splits the first order coefficients into first order first gain coefficients and first order second gain coefficients, and splits the constant coefficients into constant coefficient first gain coefficients and constant coefficient second gain coefficients.

In particular, computing device 400 applies first order coefficients b ₁ Splitting according to the following formula (17) to obtain a constant coefficient b ₀ The resolution is performed according to the following equation (18):

b ₁ ＝-2+r ₁ (17)

b ₀ ＝1+r ₀ (18)

wherein, constant coefficient b ₀ Is divided into a constant coefficient first gain coefficient ' 1 ' and a constant coefficient second gain coefficient ' r ₀ "; coefficient of first order b ₁ Is split into a first order first gain factor "-2" and a first order second gain factor "r ₁ ”。

Then, equation (12) is adjusted to the optimized discrete transfer function. The optimized discrete transfer function is shown in the following equation (19).

Then, at step 1016, the computing device 400 constructs a first order first feedback branch based on the first order first gain factor and a first order second feedback branch based on the first order second gain factor; constructing a constant coefficient first feedback branch based on the constant coefficient first gain coefficient, and constructing a constant coefficient second feedback branch based on the constant coefficient second gain coefficient; and the output end of the adder is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the input end of the second delay unit, and the output end of the second delay unit is used as the output end of the target filter.

The first-order first feedback branch is a feedback branch of which the output end of the first target delay unit is fed back to the input end of the adder, and the first-order second feedback branch is a feedback branch of which the output end of the first target delay unit is fed back to the input end of the adder; the constant coefficient first feedback branch is a feedback branch in which an output end of the second target delay unit is fed back to an input end of the adder, and the constant coefficient second feedback branch is a feedback branch in which an output end of the second target delay unit is fed back to an input end of the adder.

Fig. 11 shows a schematic diagram of a target filter 1100 constructed in accordance with a method 1000 of an embodiment of the disclosure. The target filter 1100 includes a zero network 1110 and a pole network 1120. Pole network 1120 includes at least one adder 1122, and an input of adder 1122 receives the output signal of zero network 1110.

Computing device 400 constructs a pole network comprising at least: the constant coefficient first feedback branch 1124 is constructed based on a constant coefficient first gain coefficient (1), and the constant coefficient second gain coefficient (r) ₀ ) A constant coefficient second feedback branch 1126 is constructed.

The constant coefficient first feedback branch 1124 is a feedback branch from the output of the second delay unit 1128 to the input of the adder 1122. The second delay unit 1128 is a delay unit to which the first gain coefficient and the second gain coefficient correspond in common. In some embodiments, the constant coefficient first feedback branch 1124 has a coefficient of-1 (i.e., the inverse of the constant coefficient first gain coefficient of 1). The constant coefficient first feedback branch 1124 is implemented, for example, using a sign inversion module. The output terminal of the second delay unit 1128 is connected to the input terminal of the sign inversion module, and the output terminal of the sign inversion module is connected to the input terminal of the adder; and the sign inversion module is used for inverting the sign of the input end signal to obtain an inverted sign signal and outputting the inverted sign signal. In a binary scenario, the sign-inverted signal output by the sign inversion module is the complement of 1 of the signal at the input of the sign inversion module.

Constant coefficient second feedback branch 1126 is a feedback branch for feeding back the output of second delay unit 1128 to the input of adder 1122. In an alternative embodiment, the constant-coefficient second feedback branch 1126 is implemented, for example, using a multiplier having a coefficient of-r ₀ . The output of the second delay unit 1128 is connected to the input of the multiplier; the output of the multiplier is connected to the input of an adder 1122.

In another alternative embodiment, the constant coefficient second feedback branch 1126 is implemented, for example, with a multiplier having a coefficient r and a sign inversion module ₀ . The output of the second delay unit 1128 is connected to the input of the multiplier; the output of the multiplier is connected to a sign inversion block, which inverts the sign of the signal and inputs the inverted signal to the input of the adder 1122.

Computing device 400 constructs the pole network further comprising: the first-order feedback branch 1130 is constructed according to the first gain factor, the first-order gain factor (-2), and the second gain factor (r) according to the second gain factor, the first-order feedback branch ₁ ) A first order second feedback branch 1132 is constructed.

The first-order feedback branch 1130 is a feedback branch for feeding the output of the first delay unit 1134 back to the input of the adder 1122. The first delay unit 1134 is a delay unit corresponding to the first gain factor, and the second gain factor, the first gain factor and the second gain factor. In some embodiments, the first order first feedback branch 1130 has a coefficient of 2 (i.e., the first gain coefficient is the inverse of the first gain coefficient, first order first gain coefficient-2). For example, in a binary scenario, the first order first feedback branch 1130 is implemented using a left shift module. The output end of the first delay unit 1134 is connected to the input end of the left shift module, and the left shift module is configured to shift the output end signal of the first delay unit 1134 by one bit to the left and output the signal, so as to implement a first gain factor of 2 times corresponding to the first gain factor. The left shift module can be realized by adopting a feedback line without additionally occupying hardware resources. The signal output by the left shift module is a signal after the signal at the output end of the first delay unit 1134 is shifted left by one bit, and as for the lowest bit of the output signal of the left shift module, the lowest bit can be supplemented by 0 or 1, and specifically, the lowest bit can be reasonably set according to the requirement. The output signal of the left shift module is coupled to an input of an adder 1122.

A first-order second feedback branch 1132 feeds back the output of the first delay unit 1134 to the input of the adder 1122.

In an alternative embodiment, first-order second feedback branch 1132 is implemented using, for example, a multiplier having a coefficient of-r ₁ . The output of the first delay unit 1134 is connected to the input of the multiplier; the output of the multiplier is connected to the input of adder 1122.

In another alternative embodiment, the first-order second feedback branch 1132 is implemented, for example, by a multiplier with a coefficient r and a sign-inversion block ₁ . The output of the first delay unit 1134 is connected to the input of the multiplierAn input end; the output of the multiplier is connected to a sign inversion block, which inverts the sign of the signal and inputs the inverted signal to the input of the adder 1122.

In the target filter 1100, the output terminal of the second delay unit 1128 also serves as the output terminal Fo of the target filter 1100.

In some alternative embodiments, for a filter to be constructed characterized by equation (20) for a continuous transfer function, a corresponding target filter is constructed according to method 1000.

In particular implementation, at step 1010, the computing apparatus 400 discretizes the formula (20) to obtain a discrete transfer function of the filter to be constructed. This discrete transfer function is shown in the following equation (21).

Wherein, when the sampling frequency corresponding to the filter to be constructed is greater than the preset frequency,

a ₁ ＝a ₀ ≈0，b ₀ ≈1，b ₁ ≈-2。

for a specific construction process of the second-order filter represented by the formula (20), reference may be made to the method 1000, which is not described herein again.

In some alternative embodiments, for a filter to be constructed characterized by equation (22) for a continuous transfer function, a corresponding target filter is constructed according to method 1000.

In specific implementation, at step 1010, the computing device 400 discretizes the formula (22) to obtain a discrete transfer function of the filter to be constructed. This discrete transfer function is shown in the following equation (23).

When the sampling frequency corresponding to the filter to be constructed is greater than the preset frequency, a ₀ ≈1，a ₁ ≈-2，b ₀ ≈1，b ₁ ≈-2。

For a specific construction process of the second-order filter represented by the formula (22), reference may be made to the method 1000, which is not described herein again.

For ease of understanding, fig. 12 shows a corresponding optimization manner of the filter of the present embodiment. Wherein, the constraint condition corresponds to the value range of the related non-integer polynomial coefficient when the splitting mode can be adopted; the "splitting means" corresponds to an optional means for splitting the non-integer polynomial coefficients when the non-integer polynomial coefficients satisfy the "constraint condition".

Take the continuous transfer function as the filter to be constructed shown in equation (11) as an example. The discrete transfer function obtained by directly discretizing equation (11) is shown in equation (12). According to equation (12), the expression of the discrete transmission corresponding to the pole network of the filter to be constructed is shown in equation (24) below.

Wherein D is ₁ (z) represents the discrete transfer function of the pole network of the filter to be constructed. In the prior art, according to D directly ₁ (z) constructing a pole network of the filter to be constructed.

In some alternative implementations, according to the method 1000 of the embodiment of the present disclosure, an expression of the optimized discrete transfer function of the filter to be constructed, which is shown in formula (11) as a continuous transfer function, is shown in formula (25) below.

Wherein the first gain factor of the first order is-2 and the second gain factor of the first order is beta ₁ The first gain coefficient W of constant coefficient is 1, the second gain coefficient of constant coefficient is beta ₀ . Thus, according to the method 1000 of an embodiment of the present disclosure, the resulting discrete transfer function of the pole network of the target filter is shown in equation (26) below.

Wherein D is ₂ (z) a discrete transfer function, β, representing the pole network of the target filter ₁ ＝2+b ₁ ，β ₀ ＝b ₀ -1。

The ideal magnitude of a discrete transfer function of a pole network (e.g., characterized by D (z)) without quantization error is represented by M (ω) = | D (e) ^jωt ) And | characterizing. Accordingly, an expression defining the sensitivity of the ideal amplitude to the coefficient is as shown in the following equation (27).

Wherein Δ b represents a quantization error corresponding to the coefficient b; Δ M (ω) represents the amount of change in M (ω) caused by the quantization error Δ b, i.e., the influence of Δ b on M (ω). From the definition of the sensitivity shown in equation (27), the following equations (28) and (29) can be derived.

Wherein the content of the first and second substances,

represents the second gain coefficient beta of the constant coefficient in the formula (26) ₀ Corresponding sensitivity，

Represents the second gain factor of the first order in equation (26) as β ₁ A corresponding sensitivity;

represents the constant coefficient b in the formula (24) ₀ The corresponding sensitivity of the light source is determined,

represents a coefficient of the first order in the formula (24) as b ₁ Corresponding sensitivity. When the pole of the filter is close to the unit circle z =1, the error caused by the quantization of the coefficients to the output result is more obvious. At this time, b ₁ ≈-2,b ₀ 1, so, β ₀ ≈0，β ₁ 0, further available:

according to the storage mode of the floating point number, the error | Δ β can be known when the binary number with the same preset bit width is used for representation ₁ |<<|Δb ₁ |,|Δβ ₀ |<<|Δb ₀ L, wherein |. DELTA.beta ₁ I denotes a first-order second gain factor β ₁ Corresponding quantization error Δ β ₁ Absolute value of, | Δ b ₁ I denotes a first order coefficient of b ₁ Corresponding quantization error Δ b ₁ Absolute value of, | Δ β ₀ I represents a constant second gain coefficient beta ₀ Corresponding quantization error Δ β ₀ Absolute value of, | Δ b _0n | represents a constant coefficient b ₀ Corresponding quantization error Δ b ₀ The absolute value of (c). It can be seen that the method 1000 according to the embodiments of the present disclosure is constructed to result in a target filter with significantly reduced coefficient quantization error compared to the prior art.

Further, can obtain

And

wherein, Δ M ₁ Characterization in the case of a pole network according to the prior art in which the filter to be constructed is constructed directly on the basis of formula (24), since the first-order coefficient is b ₁ Corresponding quantization error Δ b ₁ And constant coefficient b ₀ Corresponding quantization error Δ b ₀ The resulting amount of change in the output amplitude,

characterizing the phase of variation Δ M ₁ The ratio for the ideal amplitude M; Δ M ₂ Characterizing method 1000 according to an embodiment of the present disclosure builds a pole network case of the target filter based on equation (26) because of the first order second gain factor β ₁ Corresponding quantization error Δ β ₁ And constant coefficient second gain coefficient beta ₀ Corresponding quantization error Δ β ₀ The resulting amount of change in the output amplitude,

characterizing the phase of variation Δ M ₂ For a ratio of the ideal amplitude M.

Compare to obtain, | Δ M ₂ |<|ΔM ₁ L. Therefore, the method 1000 according to the embodiment of the present disclosure is constructed to obtain the target filter, and the adverse effect of the coefficient quantization error on the output amplitude of the filter is significantly reduced compared to the prior art.

For b in discrete transfer function ₁ ＝e ^αT ,b ₀ ＝e ^βT (wherein, alpha, beta is the pole of the continuous transfer function, and is located on the left half plane of the polar coordinate system), and under the condition that the sampling frequency is more than or equal to 1KHz (the pole coordinate is designed not to be too far away from the coordinate axis, so alpha T, beta T are less than-0.5), b in the discrete transfer function ₁ ,b ₀ All the values of (A) can meet the conditions:

and-2<b ₁ <-1, therefore, a target filter can be constructed according to the method 1000 of the embodiment of the present disclosure, thereby achieving the effect of significantly reducing quantization error.

The technical effect of the present disclosure may be verified based on a time domain simulation result. Tables 1 to 4 provide four sets of time domain simulation results, wherein the verification object is a target filter obtained by four construction modes of a filter to be constructed (low-pass filter) with a continuous transfer function shown as formula (11). Wherein, the construction mode 1 corresponds to the target filter directly constructed based on the formula (12) according to the prior art; construction mode 2 corresponds to the target filter constructed by the method 1000 according to the embodiment of the present disclosure; construction mode 3 corresponds to the method 700 according to the embodiment of the present disclosure converting the corresponding discrete transfer function into the expression shown in formula (15), and then constructing the obtained target filter; construction mode 4 corresponds to the method 700 according to the embodiment of the present disclosure converting the corresponding discrete transfer function into the expression shown in formula (16), and then constructing the resultant target filter. The time domain simulation was performed based on MATLAB (a mathematical analysis software), where the input signal was a sinusoidal signal with a frequency of 2Hz and an amplitude of 1. The time domain simulation results include RMS (root mean square of error) and Inf norm (infinite norm of error). Wherein, w _n Each of =10 and ξ is a different value. In the time domain simulation result corresponding to table 1, ξ =1.5; in the time domain simulation results corresponding to table 2, ξ =5; in the time domain simulation results corresponding to table 3, ξ =10; in the time domain simulation results corresponding to table 4, ξ =100.

TABLE 1

TABLE 2

TABLE 3

TABLE 4

According to tables 1 to 4, the construction method 2, the construction method 3, and the construction method 4 are all superior to the construction method 1, that is, the method for constructing the filter according to the embodiment of the present disclosure is superior to the prior art, and can reduce the error by one to two orders of magnitude. As for the construction mode 2, the construction mode 3, and the construction mode 4, the construction mode 3 and the construction mode 4 are superior to the construction mode 2.

The results are also consistent for the band pass filter and the high pass filter. And are not shown in detail here.

FIG. 13 shows a schematic of a corresponding frequency response amplitude curve for frequency domain amplitude result analysis. The analysis object is a target filter obtained by three construction modes of a filter to be constructed, wherein the three construction modes are shown as a formula (11) by continuous transfer functions. Wherein, the construction mode 1 corresponds to the target filter directly constructed based on the formula (12) according to the prior art; construction mode 2 corresponds to the target filter constructed by the method 1000 according to the embodiment of the present disclosure; construction mode 3 corresponds to the method 700 according to the embodiment of the present disclosure converting the corresponding discrete transfer function into the expression shown in formula (15), and then constructing the resultant target filter. Wherein, w _n Each of =10 and ξ is a different value. Where the horizontal axis represents frequency in rad/s and the vertical axis represents Δ db (magnification difference). Wherein curve 1302 corresponds to construction mode 1; curve 1304 corresponds to construction mode 3; curve 1306 corresponds to build mode 2. It can be seen that the

construction modes

2 and 3 are superior to the construction mode 1, and the method for constructing the filter of the embodiment of the present disclosure is superior to the prior art.

For the band pass filter, the conclusion is consistent. And are not shown in detail here.

Fig. 14 shows a schematic block diagram of an example electronic device 1400 that can be used to implement embodiments of the present disclosure. For example, computing device 400 as shown in fig. 4 may be implemented by electronic device 1400. As shown, electronic device 1400 includes a Central Processing Unit (CPU) 1401 that can perform various suitable actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM) 1402 or computer program instructions loaded from a storage unit 1408 into a Random Access Memory (RAM) 1403. In the random access memory 1403, various programs and data necessary for the operation of the electronic device 1400 can also be stored. The central processing unit 1401, the read only memory 1402, and the random access memory 1403 are connected to each other via a bus 1404. An input/output (I/O) interface 1405 is also connected to bus 1404.

A plurality of components in the electronic device 1400 are connected to the input/output interface 1405, including: an input unit 1406 such as a keyboard, a mouse, a microphone, and the like; an output unit 1407 such as various types of displays, speakers, and the like; storage unit 1308, such as a magnetic disk, optical disk, or the like; and a communication unit 1409 such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1409 allows the electronic device 1400 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The various processes and processes described above, such as method 500, method 700, and method 1000, may be performed by central processing unit 1401. For example, in some embodiments, the

methods

500, 700, and 1000 may be implemented as computer software programs tangibly embodied on a machine-readable medium, such as the storage unit 1408. In some embodiments, some or all of the computer programs may be loaded and/or installed onto the electronic device 1400 via the read-only memory 1402 and/or the communication unit 1409. When the computer program is loaded into the random access memory 1403 and executed by the central processing unit 1401, one or more of the actions of the method 500, the method 700 and the method 1000 described above may be performed.

The present disclosure relates to methods, apparatuses, systems, electronic devices, computer-readable storage media and/or computer program products. The computer program product may include computer-readable program instructions for performing various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as a punch card or an in-groove protruding structure with instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge computing devices. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

Computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the disclosure are implemented by personalizing an electronic circuit, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA), with state information of computer-readable program instructions, which can execute the computer-readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the market, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for constructing a filter, comprising:

obtaining a discrete transfer function of a filter to be constructed;

calculating a first difference value between a non-integer polynomial coefficient in a denominator polynomial of the discrete transfer function and a corresponding reference integer to determine whether the first difference value is less than a preset threshold, the reference integer being a non-zero integer closest to the corresponding non-integer polynomial coefficient;

in response to determining that a first difference value is smaller than a preset threshold value, splitting a non-integer polynomial coefficient corresponding to the first difference value into a first gain coefficient and a second gain coefficient; and

based on a first gain coefficient and a second gain coefficient, a first feedback branch and a second feedback branch are respectively constructed so as to form a target filter, the target filter at least comprises an adder and a target delay unit, the first feedback branch is a feedback branch of which the output end of the target delay unit feeds back to the input end of the adder, and the second feedback branch is a feedback branch of which the output end of the target delay unit feeds back to the input end of the adder.

2. The method of claim 1, wherein constructing the first feedback branch and the second feedback branch of the target filter based on the first gain factor and the second gain factor, respectively, comprises:

constructing a first feedback branch based on the first gain coefficient, and constructing a second feedback branch based on the second gain coefficient for constructing a pole network, wherein the pole network at least comprises the adder, and the target delay unit is a delay unit corresponding to the first gain coefficient and the second gain coefficient;

constructing a zero network so that one input end of the adder of the pole network receives an output signal of the zero network; and

and forming a target filter based on the constructed zero network and the pole network.

3. The method of claim 1, wherein splitting a polynomial coefficient corresponding to the first difference value into a first gain coefficient and a second gain coefficient comprises:

and enabling a polynomial coefficient corresponding to the first difference value to be the sum of the first gain coefficient and the second gain coefficient, and enabling the first gain coefficient to be a reference integer corresponding to the first difference value.

4. The method of claim 1, further comprising:

in response to determining that the filter to be constructed is a second order filter, determining whether the discrete transfer function of the filter to be constructed can be split into a combination of two first order discrete transfer functions that respectively correspond to the first order filters; and

in response to determining that the discrete transfer function of the filter to be constructed can be split into a combination of two first-order discrete transfer functions respectively corresponding to first-order filters, respectively obtaining non-integer polynomial coefficients in a denominator polynomial of each split first-order discrete transfer function for respectively calculating first difference values between the non-integer polynomial coefficients and corresponding reference integers.

5. The method of claim 4, wherein forming a target filter comprises:

aiming at each first-order discrete transfer function obtained by splitting, obtaining a first-order filter and a second first-order filter; and

and combining the first-order filter and the second first-order filter to obtain a second-order target filter.

6. The method of claim 5, wherein combining the first order filter and the second first order filter to obtain a second order target filter comprises:

in response to determining that the discrete transfer function of the filter to be constructed can be split into the multiplication of two first-order discrete transfer functions respectively corresponding to first-order filters, cascading a first-order filter and a second first-order filter to form a second-order target filter; and

in response to determining that the discrete transfer function of the filter to be constructed can be split into the addition of two first order discrete transfer functions, each corresponding to a first order filter, the first order filter and the second first order filter are connected in parallel to form a second order target filter.

7. The method of claim 1, wherein forming the target filter further comprises:

the output end of the adder is connected with the input end of the target delay unit; and

and taking the output end of the target delay unit as the output end of the target filter.

8. The method of claim 1, wherein calculating a first difference between a non-integer polynomial coefficient in a denominator polynomial of the discrete transfer function and a corresponding reference integer comprises:

in response to determining that the filter to be constructed is a second-order filter, respectively calculating first difference values between first-order coefficients and constant coefficients in a denominator polynomial of the discrete transfer function and corresponding reference integers;

wherein splitting the non-integer polynomial coefficient corresponding to the first difference into a first gain coefficient and a second gain coefficient comprises:

the first-order coefficient is divided into a first-order first gain coefficient and a first-order second gain coefficient, and the constant coefficient is divided into a constant coefficient first gain coefficient and a constant coefficient second gain coefficient.

9. The method of claim 8, wherein constructing the first feedback branch and the second feedback branch to form the target filter based on the first gain factor and the second gain factor, respectively, comprises:

constructing a first-order first feedback branch based on the first-order first gain coefficient, and constructing a first-order second feedback branch based on the first-order second gain coefficient, wherein the first-order first feedback branch is a feedback branch of which the output end of the first target delay unit is fed back to the input end of the adder, and the first-order second feedback branch is a feedback branch of which the output end of the first target delay unit is fed back to the input end of the adder;

constructing a constant coefficient first feedback branch based on a constant coefficient first gain coefficient, and constructing a constant coefficient second feedback branch based on a constant coefficient second gain coefficient, wherein the constant coefficient first feedback branch is a feedback branch of which the output end of the second target delay unit is fed back to the input end of the adder, and the constant coefficient second feedback branch is a feedback branch of which the output end of the second target delay unit is fed back to the input end of the adder; and

and the output end of the adder is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the input end of the second delay unit, and the output end of the second delay unit is used as the output end of the target filter.

10. The method of claim 1, wherein obtaining a discrete transfer function of a filter to be constructed comprises:

acquiring a continuous transfer function of a filter to be constructed;

and generating a discrete transfer function of the filter to be constructed according to the obtained continuous transfer function.

11. The method of claim 10, wherein obtaining a discrete transfer function of a filter to be constructed from the obtained continuous transfer function comprises:

and discretizing the obtained continuous transfer function based on a zero-order retainer to obtain a discrete transfer function of the filter to be constructed.

12. The method according to claim 1, wherein the preset threshold is less than or equal to 1/2, and the sampling frequency corresponding to the filter to be constructed is greater than or equal to 1KHz.

13. A filter constructed in accordance with the method of any one of claims 1 to 12, comprising:

a pole network;

wherein the pole network comprises at least:

an adder;

a target delay unit;

a first feedback branch, which is a feedback branch from the output end of the target delay unit to the input end of the adder, and corresponds to a first gain coefficient; and

and the second feedback branch is a feedback branch which is fed back from the output end of the target delay unit to the input end of the adder, and corresponds to a second gain coefficient.

14. The filter of claim 13, further comprising: a zero network, wherein an output of the zero network is connected to one input of said adder of the pole network.

15. A computing device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor;

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-12.

16. A computer-readable storage medium having stored thereon a computer program which, when executed by a machine, implements the method of any of claims 1-12.