CN114824136A

CN114824136A - Display substrate, preparation method thereof, display device and packaging detection method

Info

Publication number: CN114824136A
Application number: CN202210443835.9A
Authority: CN
Inventors: 杨燕; 向炼; 任艳萍; 卢红婷; 陈星宇; 杨超
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-07-29

Abstract

A display substrate, a preparation method thereof, a display device and a packaging detection method are provided. The display substrate includes: at least one display area and a non-display area located at the periphery of the display area; the display substrate comprises at least one packaging test line positioned in the non-display area, and the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

Description

Display substrate and preparation method thereof, display device and packaging detection method

Technical Field

The embodiment of the disclosure relates to the technical field of display, in particular to a display substrate, a preparation method of the display substrate, a display device and a packaging detection method.

Background

In the field of display technology, the Organic Light Emitting Diode (OLED) panel display technology has been widely applied in the fields of mobile phone screens, computer monitors, vehicle displays, etc. by virtue of its advantages of flexible display, low power consumption, wide color gamut, etc., and is recognized as the flexible display technology with the most potential for the next generation.

The electrodes and the light-emitting materials of the OLED display panel are susceptible to electrochemical corrosion caused by atmospheric pollutants, water vapor and oxygen, resulting in failure of the OLED device. Therefore, the packaging technology of the OLED display panel is particularly important. In the field of vehicle-mounted OLED display, the working environment of an OLED car lamp is more easily corroded by water vapor, and the requirement on packaging reliability is severer. However, in some technologies, it is difficult to accurately capture the failure time of the package when testing the environmental reliability of the OLED display panel.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate, a preparation method thereof, a display device and an encapsulation detection method, and can solve the problem that the time of encapsulation failure is difficult to accurately capture when an OLED display panel is subjected to an environment reliability test.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including: at least one display area and a non-display area located at the periphery of the display area; the display substrate comprises at least one packaging test line positioned in the non-display area, and the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

In an exemplary embodiment, the display substrate includes: the light-emitting element is arranged on the display area, the substrate comprises at least one packaging test line, and the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the light-emitting element on the substrate; the orthographic projection of the packaging layer on the substrate covers the orthographic projection of the light-emitting element and the packaging test line on the substrate.

In an exemplary embodiment, an orthographic projection of the package test line on the substrate surrounds an orthographic projection of the display area on the substrate, including: orthographic projections of at least two packaging test lines on the substrate surround orthographic projections of a single display area on the substrate, and orthographic projections of the at least two packaging test lines surrounding the single display area on the substrate do not overlap.

In an exemplary embodiment, the substrate includes a substrate and a driving structure layer disposed on the substrate, the driving structure layer includes a plurality of stacked insulating layers, and the package test line is disposed between any two adjacent insulating layers or on a side of the driving structure layer close to the light emitting element.

In an exemplary embodiment, the light emitting device includes a first electrode layer, an organic light emitting layer, and a second electrode layer sequentially stacked on the substrate, and an orthogonal projection of the package test line on the substrate surrounds an orthogonal projection of the light emitting device on the substrate, and includes: the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the first electrode layer and the orthographic projection of the organic light emitting layer on the substrate, and the orthographic projection of the packaging test line on the substrate is located in the range of the orthographic projection of the second electrode layer on the substrate.

In an exemplary embodiment, the display substrate further includes a pixel defining layer including a plurality of pixel defining units, an opening area between adjacent pixel defining units, and the organic light emitting layer positioned in the opening area; the orthographic projection of the packaging test line on the substrate is positioned in the range of the orthographic projection of the pixel definition unit on the substrate.

In an exemplary embodiment, the display substrate further includes a passivation layer disposed on a side of the encapsulation test line close to the pixel defining unit, and an orthogonal projection of the encapsulation test line on the substrate is within an orthogonal projection range of the passivation layer on the substrate.

In an exemplary embodiment, the non-display area includes a plurality of bonding pins, and the head and the tail of the package test line are respectively connected to different bonding pins.

In an exemplary embodiment, the encapsulation test line is a single-layer metal structure or a multi-layer metal composite structure.

In a second aspect, embodiments of the present disclosure provide a method for manufacturing a display substrate, the method including: and forming at least one packaging test line on the substrate, wherein the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

In a third aspect, embodiments of the present disclosure provide a display device including the display substrate as described above.

In an exemplary embodiment, the display device further includes a driving circuit board and a connection unit; the connecting unit is arranged to connect the driving circuit board and the display substrate; the driving circuit board comprises a memory and a display chip, and is arranged to provide a test signal to the packaging test line and store a feedback signal from the packaging test line in the memory; the display chip is configured to read the feedback signal from the memory.

In an exemplary embodiment, the display chip is further configured to provide a display signal, and the display signal is used to drive the display substrate to display.

In an exemplary embodiment, the display chip is further configured to provide a first display signal to the display substrate when the feedback signal satisfies a first condition.

In a fourth aspect, an embodiment of the present disclosure further provides a package detection method, which is applied to package detection on the display device described above, where the method includes: the driving circuit board provides a test signal to a package test line and stores a feedback signal from the package test line in the memory; and the display chip reads the feedback signal from the memory.

The display substrate that this embodiment provided, through set up at least one encapsulation test line that encircles display area at the base plate, when carrying out the test of environment reliability to this display substrate, only need carry out real-time supervision to the resistance of encapsulation test line, just can obtain the time point that the encapsulation test line received the influence, and then can obtain the time of encapsulation inefficacy. The problem of OLED display panel when carrying out the test of environment reliability, be difficult to accurately grab the time that the encapsulation is invalid is solved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic view of a display substrate in an exemplary embodiment of the present disclosure;

FIG. 2 is a schematic diagram of two package test lines arranged around a single display area;

FIG. 3 is a schematic cross-sectional view of section AA in FIG. 1;

FIG. 4 is a schematic view of a display substrate in another exemplary embodiment of the present disclosure;

FIG. 5 is a schematic view of a display substrate in yet another exemplary embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a display device according to an exemplary embodiment of the disclosure;

fig. 7 is a schematic diagram illustrating an environment reliability test performed on a display device according to an exemplary embodiment of the disclosure.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical action" is not particularly limited as long as it can transmit an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which an angle is 85 ° or more and 95 ° or less.

In some technologies, in the process of testing the environmental reliability of the OLED display panel, the OLED display panel may be corroded by water and oxygen or may have a Crack (Crack) in the package layer, and if the package layer fails, for example, the package layer has a gap or breaks, moisture in the atmosphere may enter the light emitting element along the gap, so that the organic material in the light emitting element is oxidized and fails to form a failure region that cannot emit light. As the vapor continuously intrudes into the light emitting element along the slit, the failure region gradually expands, resulting in poor display of the display device, which is called as a continuously expanding Dark Spot (GDS). But due to the long duration of the environmental reliability test, it is difficult to precisely capture the time when the package fails.

An embodiment of the present disclosure provides a display substrate, including: at least one display area and a non-display area located at the periphery of the display area; the display substrate comprises at least one packaging test line positioned in the non-display area, and the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

In the scheme of the embodiment of the disclosure, at least one packaging test line surrounding the display area is arranged on the substrate, and when the display substrate is subjected to environment reliability test, if water and oxygen invade or cracks are generated, the packaging test line is influenced firstly, and then poor display is brought. No matter water oxygen invasion or crack generation lead to the encapsulation test wire fracture all can make the resistance increase of encapsulation test wire, consequently, only need carry out the environment when reliability is tested, carry out real-time supervision to the resistance of encapsulation test wire, just can obtain the time point that the encapsulation test wire received the influence, and then can obtain the time of encapsulation inefficacy. The display substrate provided by the embodiment of the disclosure can accurately capture the time of package failure when the environment reliability test is carried out, can provide a judgment basis for the quality of various package design effects, and is convenient for improving the packaging process.

In the embodiment of the present disclosure, the display substrate may include one or more display regions, the encapsulation test lines may be located in the non-display regions, the encapsulation test lines may be respectively disposed around each display region, and the encapsulation test lines may be as close as possible to the edges of the display regions. The design can test the packaging effect of each display area respectively, and the closer the packaging test line is to the display area, the more the packaging failure time point at the packaging test line can represent the packaging failure time point of the display area, which is beneficial to capturing more accurate packaging failure time of the display area. The distance between the package test line and the edge of the display area may be set according to practical situations, which is not limited by the present disclosure.

The display substrate provided by the embodiment of the disclosure can be applied to a vehicle lamp, and the display substrate provided by the embodiment of the disclosure can also be applied to other display devices, which is not limited by the disclosure.

In one exemplary embodiment, a display substrate includes: the packaging structure comprises a substrate, a light-emitting element and a packaging layer, wherein the light-emitting element is arranged on the substrate and is positioned in a display area; the substrate comprises at least one packaging test line, the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the light-emitting element on the substrate, and the orthographic projection of the packaging layer on the substrate covers the orthographic projection of the light-emitting element and the packaging test line on the substrate.

In this embodiment, a single display area may include one or more light emitting elements, and the encapsulation test line that sets up around this display area may encircle all light emitting elements that are located in this display area, and no matter which direction the invading water oxygen gets into the display area from, the homoenergetic is detected by the encapsulation test line the very first time to when carrying out the environment reliability test, can use single display area to test as the unit, simple audio-visual demonstration encapsulation effect. The corresponding relationship between the package test lines and the light emitting elements in the display region may be set as required, for example, the package test lines may be set for the light emitting elements near the edge of the display region, so as to know the orientation from which water and oxygen start to enter the display region, and more detailed package failure data can be obtained, which is not limited by the present disclosure.

In one exemplary embodiment, an orthographic projection of a package test line on a substrate surrounds an orthographic projection of a display area on the substrate, comprising: orthographic projections of the at least two packaging test lines on the substrate surround orthographic projections of a single display area on the substrate, and the orthographic projections of the at least two packaging test lines surrounding the single display area on the substrate do not overlap.

In this embodiment, two or more package test lines may be disposed around a single display area, and orthographic projections of the package test lines around the single display area on the substrate do not overlap. When carrying out the environmental reliability test, can carry out real-time supervision to the resistance of every encapsulation test line respectively, can set up first preset distance between the adjacent encapsulation test line, can set up the second preset distance between the encapsulation test line that is closest to the display area and the display area, can acquire the time that water oxygen invades to corresponding encapsulation test line according to the real-time supervision result of encapsulation test line resistance, then calculate the invasion speed of water oxygen between adjacent encapsulation test line according to first preset distance, and calculate the time point that water oxygen invaded to the display area according to the water oxygen invasion speed that obtains. The distance between different adjacent packaging test lines can be set to be different, and parameters such as the number, the interval and the like of the packaging test lines surrounding a single display area can be set according to needs, and the method is not limited by the disclosure.

In one exemplary embodiment, the package test line is positioned at a side of the substrate adjacent to the light emitting element in a direction perpendicular to the display substrate.

In one exemplary embodiment, the encapsulation test line is a single-layer metal structure or a multi-layer metal composite structure. For example, the material of the package test line may be Ti/Al/Ti, which is not limited by the present disclosure.

In one exemplary embodiment, a light emitting device includes a first electrode layer, an organic light emitting layer, and a second electrode layer sequentially stacked on a substrate, an orthogonal projection of an encapsulation test line on the substrate surrounds an orthogonal projection of the light emitting device on the substrate, including: the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the first electrode layer and the organic light emitting layer on the substrate, and the orthographic projection of the packaging test line on the substrate is located in the range of the orthographic projection of the second electrode layer on the substrate.

In this embodiment, the first electrode layer may be an anode layer, and the anode layer may include a plurality of anode units; the second electrode layer may be a cathode layer, which may be a complete film structure covering the entire display area. The present disclosure is not so limited. The orthographic projection of the packaging test line on the substrate is not overlapped with the orthographic projection of the first electrode layer and the organic light emitting layer on the substrate. In other embodiments, the orthographic projection of the package test line on the substrate may be outside the range of the orthographic projection of the second electrode layer on the substrate, which is not limited by the present disclosure.

In one exemplary embodiment, the display substrate further includes a pixel defining layer including a plurality of pixel defining units, an opening region between adjacent pixel defining units, and an organic light emitting layer in the opening region; the orthographic projection of the packaging test line on the substrate is positioned in the range of the orthographic projection of the pixel definition unit on the substrate.

In an exemplary embodiment, the display substrate further includes a passivation layer disposed on a side of the encapsulation test line adjacent to the pixel defining unit, and an orthogonal projection of the encapsulation test line on the substrate is within an orthogonal projection range of the passivation layer on the substrate.

In an exemplary embodiment, the non-display area includes a plurality of bonding pins, and the head and tail ends of the package test line are respectively connected to different bonding pins.

In this embodiment, a binding region may be disposed on one side of the non-display region on the display substrate, a plurality of binding pins may be disposed in the binding region, and the head and tail ends of the package test line may be connected to different binding pins respectively. Under the condition that at least two packaging test lines are arranged around a single display area, the head end and the tail end of the at least two packaging test lines can be respectively connected to the same two binding pins; or the head end and the tail end of the at least two packaging test lines can be respectively connected to different binding pins. The packaging test line can obtain a test signal from the binding pin and output a feedback signal from the binding pin, and the connection relationship between the packaging test line and the binding pin can be set according to requirements.

The technical contents of the present disclosure will be described in detail by specific embodiments with reference to the accompanying drawings.

Fig. 1 is a schematic view of a display substrate in an exemplary embodiment of the present disclosure. As shown in fig. 1, a display substrate 100 provided in the embodiment of the present disclosure includes a plurality of display regions and a non-display region located at a periphery of the display regions and surrounding the display regions, where the plurality of display regions are respectively: a first display area 1, a second display area 2 and a third display area 3, each of which may comprise one or more light emitting elements. The display regions shown in fig. 1 are all irregular shapes, and the number, shape and arrangement of the display regions may be set as required, for example, the display regions may be set as polygons of triangles, squares, rectangles, circles and other shapes. The package test line 4 is disposed in a non-display area adjacent to the display area, and a bonding area (not shown) may be disposed in the non-display area, and the bonding area may be located at one side of the display substrate 100, and a plurality of bonding pins (not shown) are disposed in the bonding area. In fig. 1, a single display region is surrounded by one package test line 4, and the head and tail ends of each package test line 4 can be connected to different binding pins, so that the package test lines can be conveniently connected with external signals, and signals of each package test line 4 can be conveniently detected when environment reliability detection is performed.

Fig. 2 is a schematic diagram of two package test lines arranged around a single display area. In fig. 2, the display substrate 100 includes a display region 101 and a non-display region located at the periphery of the display region 101, the non-display region includes a bonding region 102 located at one side of the display substrate 100, and the bonding region 102 includes a plurality of bonding pins. Two packaging test lines, namely a first packaging test line 103 and a second packaging test line 104, are arranged around the display area 101, and the orthographic projection of the first packaging test line 103 on the display substrate 100 is within the range of the orthographic projection of the second packaging test line 104 on the display substrate 100. As shown in fig. 2, the head and tail ends of the first package test line 103 and the head and tail ends of the second package test line 104 are respectively connected to different binding pins, in other embodiments, the head end of the first package test line 103 and the head end of the second package test line 104 may be connected to the same binding pin, and the tail end of the first package test line 103 and the tail end of the second package test line 104 may be connected to the same binding pin. That is, the first package test line 103 and the second package test line 104 may receive test signals from different bonding pins, respectively, and output feedback signals from different bonding pins, respectively; alternatively, the first package test line 103 and the second package test line 104 may receive a test signal from the same bonding pin and output a feedback signal from the other bonding pin. The distance between the first package test line 103 and the second package test line 104 may be set to d1, the distance between the second package test line 104 and the edge of the display region 101 may be set to d2, when performing the environmental reliability test, the time when the water oxygen invades to the corresponding package test line may be obtained according to the real-time monitoring result of the resistances of the first package test line 103 and the second package test line 104, then the invasion speed of the water oxygen between the first package test line 103 and the second package test line 104 may be calculated according to d1, and the time point when the water oxygen invades to the display region 101 may be calculated according to the obtained invasion speed of the water oxygen and the distance d2 between the second package test line 104 and the edge of the display region 101. A plurality of package test lines may be disposed around a single display area as needed, which is not limited by the present disclosure.

FIG. 3 is a schematic cross-sectional view of the AA section of FIG. 1. As shown in fig. 3, the display substrate 100 includes a substrate 20, a package test line 4 disposed on the substrate 20, a pixel defining layer 6, a light emitting element 7, and an encapsulation layer 9. The light emitting element 7 may include an anode layer 71, an organic light emitting layer 72, and a cathode layer 73, and an overlapping area where the anode layer 71, the organic light emitting layer 72, and the cathode layer 73 are orthographically projected on the substrate 20 may be referred to as a light emitting area. The pixel defining layer 6 includes a plurality of pixel defining units, an opening area is formed between adjacent pixel defining units, the organic light emitting layer 72 is located in the opening area, the first display region 1 may include one or more opening areas, and the first display region 1 includes one opening area as an example in fig. 3. The encapsulation test line 4 is disposed on a side of the substrate 20 close to the light emitting element 7, and an orthogonal projection of the encapsulation test line 4 on the substrate 20 is located within a range of an orthogonal projection of the pixel defining unit on the substrate 20. The orthographic projection of the encapsulation test line 4 on the substrate 20 is not overlapped with the orthographic projection of the anode layer 71 and the organic light emitting layer 72 on the substrate 20, the orthographic projection of the encapsulation test line 4 on the substrate 20 can surround the orthographic projection of the anode layer 71 and the organic light emitting layer 72 on the substrate 20, or the orthographic projection of the encapsulation test line 4 on the substrate 20 can surround the orthographic projection of the light emitting region on the substrate 20; the orthographic projection of the encapsulation test line 4 on the substrate 20 may be located within a range of the orthographic projection of the cathode layer 73 on the substrate 20. A passivation layer 5 is disposed on a side of the encapsulation test line 4 adjacent to the pixel defining unit, an orthogonal projection of the encapsulation test line 4 on the substrate 20 is within an orthogonal projection range of the passivation layer 5 on the substrate 20, and an orthogonal projection of the passivation layer 5 on the substrate 20 may be within an orthogonal projection range of the cathode layer 73 on the substrate 20. The adhesive layer 8 may be disposed on a side of the cathode layer 73 close to the encapsulation layer 9, and an orthographic projection of the adhesive layer 8 on the substrate 20 covers an orthographic projection of the cathode layer 73 on the substrate 20, so that the encapsulation layer 9 and the light emitting element 7 are tightly combined, which is helpful for obtaining a better encapsulation effect.

Fig. 4 is a schematic view of a display substrate in another exemplary embodiment of the present disclosure. As shown in fig. 4, the display substrate 100 includes a substrate 20, a conductive layer 30 disposed on the substrate 20, a pixel definition layer 6, a light emitting element 7, an adhesive layer 8, and an encapsulation layer 9. The light emitting element 7 includes an anode layer 71, an organic light emitting layer 72, and a cathode layer 73. The substrate 20, the pixel defining layer 6, the light emitting element 7, the adhesive layer 8 and the encapsulation layer 9 may be the same as those in fig. 2, and are not described herein again. As shown in fig. 4, a conductive layer 30 is disposed on the substrate 20, the conductive layer 30 includes a first power line 31, a package test line 4, a passivation layer 5 covering the package test line 4, and a first planarization layer 32, a connection via is disposed on the first planarization layer 32, the anode layer 71 is connected to the first power line 31 through the connection via, and the first power line 31 may be connected to a bonding pin configured to provide power to the light emitting element 7. The orthographic projection of the first power line 31 on the substrate 20 is within the range of the orthographic projection of the packaging test line 4 on the substrate 20 and has no overlap, the orthographic projection of the packaging test line 4 on the substrate 20 can be within the range of the orthographic projection of the passivation layer 5 on the substrate 20, the orthographic projection of the passivation layer 5 on the substrate 20 can be within the range of the orthographic projection of the pixel definition unit on the substrate 20, or the orthographic projections of the packaging test line 4 and the passivation layer 5 on the substrate 20 can be outside the range of the orthographic projection of the cathode layer 73 on the substrate 20, and the positions of the packaging test line 4 and the passivation layer 5 on the substrate 20 can be set as required. The bonding pin connected to the first power line 31 is different from the bonding pin connected to the package test line 4.

Fig. 5 is a schematic view of a display substrate in yet another exemplary embodiment of the present disclosure. As shown in fig. 5, the display substrate 100 includes a substrate 20, a package test line 4 disposed on the substrate 20, a passivation layer 5, a pixel defining layer 6, a light emitting element 7, an adhesive layer 8, and a packaging layer 9. The light emitting element 7 includes an anode layer 71, an organic light emitting layer 72, and a cathode layer 73. The same structure as that in fig. 3 will not be described again. The structure of the substrate 20 is illustrated in fig. 5. As shown in fig. 5, the substrate 20 includes a base 10 and a driving structure layer 102 disposed on the base 10. The driving structure layer 102 includes: a plurality of pixel circuits, and a first insulating layer 11, a second insulating layer 13, a third insulating layer 15, and a fourth insulating layer 16 provided between the pixel circuits. At least one pixel circuit includes a plurality of transistors and at least one capacitor. Fig. 3 illustrates an example of the first transistor and the first storage capacitor. The first transistor may include: the organic light emitting device includes an active layer 12, a gate electrode 14, a source electrode 17, and a drain electrode 18, wherein a first insulating layer 11 is provided between a base substrate 101 and the active layer 12, a second insulating layer 13 is provided between the active layer 12 and the gate electrode 14, and a third insulating layer 15 and a fourth insulating layer 16 are provided between the gate electrode 14 and the source electrode 17 and the drain electrode 18. The first storage capacitor may include: a first capacitive electrode 41 and a second capacitive electrode 42. The first capacitor electrode 41 is provided on the second insulating layer 13, and the third insulating layer 15 is provided between the first capacitor electrode 41 and the second capacitor electrode 42. The flat layer 103 is arranged on the driving structure layer 102, the pixel defining layer 6 and the light emitting element 7 are arranged on the flat layer 103, the second via hole is arranged on the flat layer 103, the anode 71 is connected with the drain electrode 18 of the first transistor through the second via hole arranged on the flat layer 103, the opening area of the pixel defining layer 6 is exposed out of the surface of the anode 301, the organic light emitting layer 72 is formed in the opening area and connected with the anode 71, and part of the cathode 73 is connected with the organic light emitting layer 72. In other embodiments, the encapsulation test line 4 may be disposed between any two adjacent insulating layers as needed, for example, the encapsulation test line 4 may be disposed on the same layer as any one of the active layer 12, the first capacitance electrode 41 or the second capacitance electrode 42, which is not limited by the present disclosure.

The embodiment of the disclosure provides a preparation method of a display substrate, which comprises the following steps: and forming at least one packaging test line on the substrate, wherein the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

According to the manufacturing method provided by the embodiment of the disclosure, at least one packaging test line surrounding the display area is formed on the substrate, and when the display substrate is subjected to an environment reliability test, if water and oxygen invade or cracks are generated, the packaging test line is affected first, and then poor display is brought. No matter water oxygen invasion or crack generation lead to the encapsulation test wire fracture all can make the resistance increase of encapsulation test wire, consequently, only need carry out the environment when reliability is tested, carry out real-time supervision to the resistance of encapsulation test wire, just can obtain the time point that the encapsulation test wire received the influence, and then can obtain the time of encapsulation inefficacy. The display substrate manufacturing method provided by the embodiment of the disclosure can accurately capture the time of package failure when the environment reliability test is performed, can provide a judgment basis for judging whether various package design effects are good or not, and is convenient for improving the packaging process.

In one exemplary embodiment, the method includes sequentially forming a light emitting element and an encapsulation layer on the substrate, wherein an orthographic projection of the encapsulation test line on the substrate surrounds an orthographic projection of the light emitting element on the substrate; the orthographic projection of the packaging layer on the substrate covers the orthographic projection of the light-emitting element and the packaging test line on the substrate.

In an exemplary embodiment, the substrate includes a substrate and a driving structure layer disposed on the substrate, the driving structure layer includes a plurality of stacked insulating layers, and the forming of the at least one package test line on the substrate includes: and forming the packaging test line between any two adjacent insulating layers, or forming the packaging test line on one side of the driving structure layer close to the light-emitting element.

The structure of the display substrate of the present disclosure is illustrated below by an example of a display substrate preparation process. The "patterning process" referred to in this disclosure includes processes of depositing a film layer, coating a photoresist, mask exposing, developing, etching, and stripping a photoresist. The deposition may employ any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more selected from spray coating and spin coating, and the etching may employ any one or more selected from dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. When the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "a and B are disposed in the same layer" in the present disclosure means that a and B are simultaneously formed by the same patterning process. "the orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

The following description will be made by taking as an example the preparation of a display substrate as shown in fig. 5:

(1) the substrate 10 is prepared on a glass carrier plate. In the present disclosure, the material of the base 10 may be selected according to the requirement, for example, the base 10 may be a flexible base or a rigid substrate.

(2) A pattern of driving structure layers 102 is formed on the substrate 10. In an exemplary embodiment, the driving structure layer 102 may include a first transistor and a first storage capacitor constituting a pixel driving circuit. In an exemplary embodiment, the preparation process of the driving structure layer 102 may include:

a first insulating film and an active layer film are sequentially deposited on the substrate 10, and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10 and an active layer pattern disposed on the first insulating layer 11.

Subsequently, a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 13 covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 13, the first gate metal layer pattern including a gate electrode 14 and a first capacitor electrode 41.

Subsequently, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 15 covering the first gate metal layer and a second gate metal layer pattern disposed on the third insulating layer 15, where the second gate metal layer pattern includes a second capacitor electrode 42, and the position of the second capacitor electrode 42 corresponds to the position of the first capacitor electrode 41.

And depositing a fourth insulating film, patterning the fourth insulating film by a patterning process to form a fourth insulating layer 16 pattern covering the second gate metal layer, wherein the fourth insulating layer 16 is provided with two first via holes, the positions of the two first via holes correspond to the positions of two ends of the first active layer 12, and the fourth insulating layer 16, the third insulating layer 15 and the second insulating layer 13 in the two first via holes are etched to expose the surface of the active layer 12.

And then, depositing a third metal film, patterning the third metal film through a patterning process, and forming a source-drain metal layer pattern on the fourth insulating layer 16, wherein the source-drain metal layer pattern comprises a source electrode 17 and a drain electrode 18 pattern, and the source electrode 17 and the drain electrode 18 are respectively connected with the active layer 12 through first via holes.

To this end, a pattern of the driving structure layer 102 is prepared on the substrate 10. The active layer 12, the gate electrode 14, the source electrode 17, and the drain electrode 18 constitute a first transistor, and the first capacitor electrode 41 and the second capacitor electrode 42 constitute a first storage capacitor. In an exemplary embodiment, the first Transistor may be a Thin Film Transistor (TFT).

(3) A planarization layer 103 is patterned on the substrate 10. And coating a first flat film on the substrate 10 with the pattern, forming a flat layer 103 covering the whole substrate base plate, and forming a second through hole on the flat layer 103 through a patterning process, wherein the second through hole exposes the surface of the drain electrode of the first transistor.

(4) A pattern of package test lines 4 is formed on the substrate 10. Depositing a packaging test film on the substrate 10 with the patterns, patterning the packaging test film through a patterning process to form patterns of packaging test lines 4, wherein the packaging test lines 4 are formed in a non-display area and are arranged around and closely attached to the display area, and the head end and the tail end of each packaging test line 4 are positioned on the same side of the display substrate.

Subsequently, an inorganic thin film is deposited on the substrate 10 formed with the aforementioned pattern, and the inorganic thin film is patterned through a patterning process to form a pattern of the passivation layer 5 covering the encapsulation test lines 4 as shown in fig. 4.

(5) An anode layer 71 is patterned on the substrate 10. Depositing a transparent conductive film on the substrate 10 with the patterns, patterning the transparent conductive film through a patterning process to form an anode layer 71 pattern, wherein the anode layer 71 is formed on the flat layer 103 of the display region and is connected with the drain electrode of the first transistor through a second via hole on the flat layer 103.

(6) A pixel defining layer 6 is patterned on a substrate 10. A pixel definition film is coated on the substrate 10 on which the patterns are formed, the patterns of the pixel definition layer 6 are formed through the processes of masking, exposing and developing, an opening area is arranged on the pixel definition layer 6, the pixel definition film in the opening area is developed to expose the surface of the anode 71, the remaining pixel definition film forms a pixel definition unit, and an opening area is arranged between the adjacent pixel definition units.

(7) The organic light emitting layer 72 is sequentially formed on the base substrate on which the aforementioned pattern is formed. On the substrate 10 on which the pattern is formed, an organic light emitting layer 72 is patterned by an evaporation method or an ink jet printing method, and the organic light emitting layer 72 is formed in an opening region between adjacent pixel defining units and connected to the anode layer 71. Since the anode layer 71 is connected to the drain electrode of the first transistor, light emission control of the light emitting layer 72 is achieved.

In an exemplary embodiment, the organic light emitting layer 72 may include an emission layer (EML), and any one or more of: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL).

In an exemplary embodiment, the organic light emitting layer 72 may be prepared in the following manner:

firstly, a hole injection layer, a hole transport layer and an electron blocking layer are sequentially formed by adopting an Open Mask (OPM) evaporation process or an ink-jet printing process, and a common layer of the hole injection layer, the hole transport layer and the electron blocking layer is formed on a display substrate.

And then, different light-emitting layers are formed on different sub-pixels by adopting an evaporation process of an open mask or an ink-jet printing process. The light emitting layers of adjacent sub-pixels may overlap by a small amount (for example, the overlapping portions occupy less than 10% of the area of the respective light emitting layer patterns), or may be isolated.

And then, sequentially forming a hole blocking layer, an electron transport layer and an electron injection layer by adopting an evaporation process of an open mask or an ink-jet printing process, and forming a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate.

In an exemplary embodiment, a microcavity adjusting layer may be included in the organic light emitting layer such that the thickness of the organic light emitting layer between the cathode and the anode satisfies the design of the microcavity length. In some exemplary embodiments, a hole transport layer, an electron blocking layer, a hole blocking layer, or an electron transport layer may be used as the microcavity adjusting layer, and the disclosure is not limited thereto.

In an exemplary embodiment, the light emitting layer may include a Host (Host) material and a guest (Host) material doped in the Host material, and the doping ratio of the guest material of the light emitting layer is 1% to 20%. In the range of the doping proportion, on one hand, the host material of the light-emitting layer can effectively transfer exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light, and on the other hand, the host material of the light-emitting layer carries out 'dilution' on the guest material of the light-emitting layer, thereby effectively improving the fluorescence quenching caused by the mutual collision among molecules and the mutual collision among energies of the guest material of the light-emitting layer, and improving the light-emitting efficiency and the service life of the device. In an exemplary embodiment, the doping ratio refers to a ratio of the mass of the guest material to the mass of the light emitting layer, i.e., mass percentage. In an exemplary embodiment, the host material and the guest material may be co-evaporated by a multi-source evaporation process to be uniformly dispersed in the light emitting layer, and the doping ratio may be controlled by controlling an evaporation rate of the guest material during evaporation, or by controlling an evaporation rate ratio of the host material and the guest material. In an exemplary embodiment, the thickness of the light emitting layer may be about 10nm to 50 nm.

In exemplary embodiments, the hole injection layer may employ an inorganic oxide such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may employ a p-type dopant of a strong electron-withdrawing system and a dopant of a hole-transporting material. In an exemplary embodiment, the thickness of the hole injection layer may be about 5nm to 20 nm.

In an exemplary embodiment, a material with high hole mobility, such as an arylamine compound, may be used for the hole transport layer, and the substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, furan, or the like. In an exemplary embodiment, the thickness of the hole transport layer may be about 40nm to 150 nm.

In exemplary embodiments, the hole blocking layer and the electron transport layer may employ aromatic heterocyclic compounds, for example, imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazolophenanthrin derivatives, and the like; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; and compounds containing a nitrogen-containing six-membered ring structure (including compounds having a phosphine oxide substituent on the heterocyclic ring) such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives. In an exemplary embodiment, the hole blocking layer may have a thickness of about 5nm to 15nm, and the electron transport layer may have a thickness of about 20nm to 50 nm.

In an exemplary embodiment, the electron injection layer may employ an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or a compound of these alkali metals or metals, or the like. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5nm to 2 nm.

(8) A cathode layer 73 is formed on the substrate 10 on which the aforementioned pattern is formed. On the substrate 10 on which the above-described pattern is formed, a cathode layer 73 pattern is formed by an open mask evaporation method. The cathode layer 73 covers the pixel defining layer 6, and a part of the cathode layer 73 is connected to the organic light emitting layer 72, so that the organic light emitting layer 72 is connected to both the anode layer 71 and the cathode layer 73.

(9) An adhesive layer 8 and a sealing layer 9 are formed on the substrate 10 on which the aforementioned pattern is formed. The substrate 10 on which the aforementioned pattern is formed is coated with an adhesive, and the adhesive layer 8 is formed through a patterning process. The adhesive layer 8 covers the light emitting element 7.

Subsequently, an encapsulation layer 9 is formed on the substrate 10 on which the aforementioned pattern is formed. In an exemplary embodiment, the preparation process of the encapsulation layer 9 may be: on the substrate 10 with the patterns, a first packaging film is deposited by an open type mask plate in a deposition mode to form a first layer of patterns, then a second packaging material is printed by the open type mask plate in an ink jet printing process to form a second layer of patterns, and then a third packaging film is deposited by the open type mask plate in a deposition mode to form a third layer of patterns. Thus, the packaging layer pattern is prepared. Other structures for the encapsulation layer 9 are also possible, and the disclosure is not limited thereto.

In an exemplary embodiment, the first encapsulation film and the third encapsulation film may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer, which may ensure that external water and oxygen cannot enter the light emitting element, and the deposition may be Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The second packaging film may be made of an organic material, such as resin, and serves to cover the layers of the display substrate, so as to improve structural stability and flatness.

The structure of the display substrate prepared as described above is shown in fig. 5. The display substrate may further include other film structures, such as a touch structure layer, a protection layer, and the like, and may be prepared according to actual needs, which is not described herein again. After the structure shown in fig. 4 is formed, the glass carrier can be peeled off.

In this example, the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is referred to as a Buffer (Buffer) layer for improving the water and oxygen resistance of the substrate, the second and third insulating layers are referred to as Gate Insulating (GI) layers, and the fourth insulating layer is referred to as an interlayer Insulating (ILD) layer. The first metal thin film, the second metal thin film, and the third metal thin film may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, or the like. The packaging test film can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti and the like. The planarization layer may employ an organic material. The cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. The active layer thin film may be made of various materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on Oxide technology, silicon technology, and organic technology. The transparent conductive film may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the pixel defining layer may be polyimide, acryl, or polyethylene terephthalate, etc.

An embodiment of the present disclosure provides a display device, including the display substrate described in any of the above embodiments. The display device may be: any product or component with a display function, such as a car lamp, a display, a digital photo frame, a navigator and the like.

In one exemplary embodiment, the display device further includes a driving circuit board and a connection unit; the connecting unit is arranged to connect the driving circuit board and the display substrate; the driving circuit board comprises a memory and a display chip, and is arranged to provide a test signal to the packaging test line and store a feedback signal from the packaging test line in the memory; the display chip is configured to read the feedback signal from the memory.

In an exemplary embodiment, a plurality of second bonding pins are disposed on the driving circuit board, and the connection unit is configured to connect the bonding pins on the display substrate with the corresponding second bonding pins.

In an exemplary embodiment, the driving circuit board may include a printed circuit board including a memory and a display chip, the package test line on the display substrate is connected to the printed circuit board through the bonding pin, and the printed circuit board is connected to the display chip.

In this embodiment mode, a test signal is supplied to a package test line on a display substrate by a Printed Circuit Board (PCB), a received feedback signal is stored in a memory, and the feedback signal is sampled and read from the memory by a display chip. When the display device is subjected to environment reliability test, the real-time change of the resistance value of the packaging test line can be judged according to the change of the feedback signal, so that the time point of the packaging test line affected can be obtained, and the packaging failure time can be further obtained. The display device provided in the embodiment can accurately capture the time of packaging failure when the environment reliability test is carried out, can provide a judgment basis for judging the good or bad effect of various packaging designs, and is convenient for improving the packaging process.

The display device provided by the embodiment of the disclosure can be applied to a vehicle lamp, and the display device provided by the embodiment of the disclosure can also be applied to other display devices, which is not limited by the disclosure.

In an exemplary embodiment, the test signal may be a voltage, a current, or the like signal, and the feedback signal may be a voltage, a current, or a resistance, or the like signal, which is not limited by the present disclosure.

In an exemplary embodiment, the display chip is further configured to provide a display signal, and the display signal is used for driving the display substrate to display.

In this embodiment, the display chip can be used to complete the environmental reliability test. The function of sending and receiving signals is equivalently added in the printed circuit board and the display chip corresponding to the display substrate, and the existing product is only required to be simply changed, so that the operation is convenient and the realization is easy.

In an exemplary embodiment, the memory may be a Flash memory, and the display chip may pass through I ² The C interface is connected with the Flash memory.

In one exemplary embodiment, the display chip is further configured to determine that the package is failed when the feedback signal satisfies a first condition, and provide a first display signal to the display substrate.

In this embodiment, when the feedback signal satisfies the first condition, it may be determined that the package is failed, and the display chip may provide the first display signal to the display substrate, and control the display substrate to display a specific image or a specific color, so as to remind a tester of the attention. Because the packaging test line surrounds the display device, the display area can still normally display at the time point when the water and oxygen erode the packaging test line, and at the time, a first display signal can be provided for the display substrate to control the display substrate to complete specific display, so that a tester can notice that the display device is subjected to packaging failure. The first condition may be set as required, for example, when the feedback signal is a voltage value, the first condition may be that the feedback signal is greater than a first predetermined value; when the feedback signal is a current value, the first condition may be that the feedback signal is smaller than a second predetermined value, and may be specifically set according to a type of the feedback signal, which is not limited in this disclosure. The first display signal may be set as required, for example, the display substrate may display a specific pattern (triangle, quadrangle, circle or other shapes) or a specific color (the display area displays a single color such as red, green, blue or a combination of different colors) under the first display signal, which is not limited by the present disclosure.

Fig. 6 is a schematic structural diagram of a display device in an exemplary embodiment of the present disclosure. As shown in fig. 6, the display device includes a display substrate M1, a driving circuit board M4, and a connection unit M3. The display substrate M1 includes a bonding region M2, the bonding region M2 includes a plurality of bonding pins, the driving circuit board M4 includes a plurality of second bonding pins, and the connection unit M3 connects the display substrate M1 and the driving circuit board M4 by connecting the bonding pins and the corresponding second bonding pins. The driving circuit board M4 comprises a display chip MCU and a Flash memory, a Power unit Power on the driving circuit board M4 can supply Power to the display chip MCU, and the driving circuit board M4 is provided with a Power interface M5 for being connected with an external Power supply. The display chip MCU may provide a display signal to the display substrate M1 for the display substrate M1 to display. The driving circuit board M4 can supply power to the display substrate M1 for normal operation of the display substrate M1. The package test line 4 (not shown) on the display substrate M1 is connected with the driving circuit board M4 through the connection unit M3, and the display chip MCU is connected with the Flash memory. When performing the environmental reliability test, the driver circuit board M4 may provide a real-time test signal to the package test line 4 and store a feedback signal returned by the package test line 4 in the memory. The display chip MCU can read the feedback signal from the Flash memory. When the environment reliability test is carried out, the display chip MCU can transmit a feedback signal into the test system, and the test system can analyze and display data.

The embodiment of the present disclosure further provides a package detection method, which is applied to package detection of the display device in any one of the embodiments, and the method includes: the driving circuit board provides a test signal to a package test line and stores a feedback signal from the package test line in the memory; and the display chip reads the feedback signal from the memory.

Fig. 7 is a schematic diagram illustrating an environment reliability test performed on a display device according to an exemplary embodiment of the disclosure. The packaging failure is caused after water vapor invades the packaging layer, the resistance of the packaging test line is increased, a real-time feedback signal is stored in a Flash memory of the driving circuit board M4, then the display chip MCU reads data from the Flash memory and transmits the data to the test system for displaying, and the test system reports errors and prompts the packaging failure.

In an exemplary embodiment, when the feedback signal satisfies a first condition, it may be determined that the package is failed, and the display chip MCU may provide a first display signal to the display substrate M1 to control the display substrate M1 to display a specific image or a specific color, so as to further remind the tester of the failure.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display substrate, comprising: at least one display area and a non-display area located at the periphery of the display area; the display substrate comprises at least one packaging test line positioned in the non-display area, and the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

2. The display substrate of claim 1, wherein the display substrate comprises: a substrate, a light emitting element disposed on the substrate, the light emitting element being located in the display region, and an encapsulation layer,

the substrate comprises at least one packaging test line, and the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the light-emitting element on the substrate; the orthographic projection of the packaging layer on the substrate covers the orthographic projection of the light-emitting element and the packaging test line on the substrate.

3. The display substrate of claim 2, wherein the orthographic projection of the encapsulation test line on the substrate surrounds the orthographic projection of the display area on the substrate, and comprises:

orthographic projections of at least two packaging test lines on the substrate surround orthographic projections of a single display area on the substrate, and orthographic projections of the at least two packaging test lines surrounding the single display area on the substrate do not overlap.

4. The display substrate according to claim 2, wherein the substrate comprises a substrate and a driving structure layer disposed on the substrate, the driving structure layer comprises a plurality of stacked insulating layers, and the package test line is disposed between any two adjacent insulating layers or on a side of the driving structure layer close to the light emitting element.

5. The display substrate according to claim 2, wherein the light emitting element includes a first electrode layer, an organic light emitting layer, and a second electrode layer stacked in this order on the substrate, and an orthogonal projection of the encapsulation test line on the substrate surrounds an orthogonal projection of the light emitting element on the substrate, and the method includes:

the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the first electrode layer and the orthographic projection of the organic light emitting layer on the substrate, and the orthographic projection of the packaging test line on the substrate is located in the range of the orthographic projection of the second electrode layer on the substrate.

6. The display substrate according to claim 5, further comprising a pixel defining layer including a plurality of pixel defining units, an opening region being between adjacent pixel defining units, the organic light emitting layer being located in the opening region; the orthographic projection of the packaging test line on the substrate is positioned in the range of the orthographic projection of the pixel definition unit on the substrate.

7. The display substrate of claim 6, further comprising a passivation layer disposed on a side of the encapsulation test line adjacent to the pixel defining unit, wherein an orthographic projection of the encapsulation test line on the substrate is within an orthographic projection of the passivation layer on the substrate.

8. The display substrate according to claim 1, wherein the non-display area comprises a plurality of bonding pins, and the head end and the tail end of the package test line are respectively connected with different bonding pins.

9. The display substrate of claim 1, wherein the encapsulation test line is a single-layer metal structure or a multi-layer metal composite structure.

10. A method for preparing a display substrate, the method comprising: and forming at least one packaging test line on the substrate, wherein the orthographic projection of the packaging test line on the substrate surrounds the orthographic projection of the display area on the substrate and is close to the edge of the display area.

11. A display device comprising the display substrate according to any one of claims 1 to 9.

12. The display device according to claim 11, further comprising a driver circuit board and a connection unit; the connecting unit is arranged to connect the driving circuit board and the display substrate; wherein,

the driving circuit board comprises a memory and a display chip, and is configured to provide a test signal to the packaging test line and store a feedback signal from the packaging test line in the memory; the display chip is configured to read the feedback signal from the memory.

13. The display device according to claim 12, wherein the display chip is further configured to provide a display signal for driving the display substrate to display.

14. The display device of claim 13, wherein the display chip is further configured to provide a first display signal to the display substrate when the feedback signal satisfies a first condition.

15. A method for inspecting a package of a display device as claimed in claims 11 to 14, the method comprising:

the driving circuit board provides a test signal to a package test line and stores a feedback signal from the package test line in the memory;

and the display chip reads the feedback signal from the memory.