CN114823895A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114823895A
CN114823895A CN202110071678.9A CN202110071678A CN114823895A CN 114823895 A CN114823895 A CN 114823895A CN 202110071678 A CN202110071678 A CN 202110071678A CN 114823895 A CN114823895 A CN 114823895A
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gate
layer
work function
barrier layer
semiconductor structure
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周真
王步雪
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor structure and a method of forming the same, comprising: the structure comprises a substrate and a plurality of fin parts, wherein the substrate is provided with a plurality of mutually-separated fin part structures; the gate structure is arranged on the surface of the substrate and stretches across the fin structures, the gate structure comprises a work function layer arranged on the substrate and a first barrier layer arranged on the surface of the work function layer, the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state. Thus, the performance and reliability of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
A Complementary Metal-Oxide-Semiconductor (CMOS) is one of the basic Semiconductor devices that constitute an integrated circuit. The Complementary Metal Oxide Semiconductor (CMOS) transistor includes a P-type metal oxide semiconductor (PMOS) and an N-type metal oxide semiconductor (NMOS).
In the prior art, in order to control short channel effect while reducing the size of a gate, a high-K dielectric material is generally used to replace a conventional material such as silicon oxide as a gate dielectric layer of a transistor, and a metal material is generally used to replace a conventional material such as polysilicon as a gate electrode layer of the transistor. Moreover, in order to adjust the threshold voltages of the PMOS transistor and the NMOS transistor, a work function layer (work function layer) is formed on the surface of the gate dielectric layer of the PMOS transistor and the NMOS transistor. The PMOS tube and the NMOS tube have different work function adjusting requirements, so that the work function layers are made of different materials to meet the respective work function adjusting requirements.
However, the existing gate structure still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance and the reliability of the semiconductor structure.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the structure comprises a substrate and a plurality of fins, wherein the plurality of fins are mutually separated; the gate structure is arranged on the surface of the substrate and spans the fin structures, the gate structure comprises a work function layer arranged on the substrate and a first barrier layer arranged on the surface of the work function layer, the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state.
Optionally, the second element is Si, and the third element is N.
Optionally, the second element atom and the third element atom form amorphous Si 3 Ni 4 。
Optionally, the material of the first barrier layer is TiSiN.
Optionally, the first barrier layer has a thickness in a range from 1 angstrom to 20 angstroms.
Optionally, the gate structure further includes: and the second barrier layer is positioned on the surface of the first barrier layer, and the material of the second barrier layer comprises TiN.
Optionally, the work function layer includes a P-type work function layer, and the P-type work function layer is made of one or both of titanium nitride and tantalum nitride.
Optionally, the work function layer further includes an N-type work function layer located on the P-type work function layer, and the N-type work function layer is made of titanium-aluminum alloy.
Optionally, the gate structure further includes: the gate dielectric layer is positioned between the work function layer and the substrate, and the metal gate is positioned on the surface of the first barrier layer.
Optionally, the gate structure further includes: and the third barrier layer is positioned between the gate dielectric layer and the work function layer.
Optionally, the gate structure further includes: and the etching stop layer is positioned between the third barrier layer and the work function layer.
Optionally, the material of the metal gate includes tungsten.
Optionally, the material of the gate dielectric layer includes a high-K dielectric material.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a plurality of fin part structures which are mutually separated; forming a plurality of gate structures on the surface of the substrate, wherein the gate structures cross the fin structures, each gate structure comprises a work function layer located on the substrate and a first barrier layer located on the surface of the work function layer, the material of the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state.
Optionally, the second element is Si, and the third element is N.
Optionally, the second element atom and the third element atom form amorphous Si 3 Ni 4 。
Optionally, the material of the first barrier layer is TiSiN.
Optionally, the gate structure further includes a second barrier layer located on the surface of the first barrier layer, and the material of the second barrier layer includes TiN.
Optionally, the process for forming the first barrier layer includes a chemical vapor deposition process, and the reaction gas adopted by the chemical vapor deposition process includes SiH 4 And SiH 2 Cl 2 And the flow rate of the reaction gas ranges from 10 to 1000 normal ml/min.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, because the material of the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state, the barrier capability of the first barrier layer is better, and the thinner first barrier layer can block elements diffused in the metal gate material in the gate structure, so that the thickness of the first barrier layer is reduced, thereby reducing the risk of merging the first barrier layers between adjacent gate structures, leaving more forming spaces for the metal gate in the gate structure, reducing the risk of insufficient filling of the metal gate, and improving the performance of the semiconductor structure. Specifically, the lattice gaps in the material of the first barrier layer are better filled by the amorphous crystal state, the second element atoms, or the second element atoms and the third element atoms, and the lattice gaps in the material of the first barrier layer are reduced, so that the first barrier layer has better blocking capability on the diffusion of elements in the metal gate material, and thus, the elements diffused in the metal gate material can be better blocked by the thinner first barrier layer.
Further, since the second element is Si and the third element is N, the second element atom, or the second element atom and the third element atom in the first barrier layer can be in an amorphous state (e.g., amorphous Si, or amorphous Si) 3 Ni 4 Etc.) to achieve a reduction in the thickness of the first barrier layer.
Correspondingly, in the forming method of the semiconductor structure provided by the technical scheme of the invention, because the material of the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state, the first barrier layer has better blocking capability, and the thinner first barrier layer can block elements diffused in the metal gate material in the gate structure, so that the thickness of the first barrier layer is reduced, the risk of merging the first barrier layers between the adjacent gate structures is reduced, more forming space is reserved for the metal gate in the gate structure, the risk of insufficient filling of the metal gate is reduced, and the performance of the semiconductor structure is improved.
Furthermore, the gate structure further comprises a second barrier layer located on the surface of the first barrier layer, and the material of the second barrier layer comprises TiN, so that the compatibility with a metal gate forming process is improved through the second barrier layer.
Drawings
FIGS. 1-5 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 6 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the existing gate structures still need to be improved. The following detailed description will be made in conjunction with the accompanying drawings.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to direct contact or not.
Fig. 1 to 5 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 has a plurality of fin structures 101 separated from each other; and forming an isolation dielectric layer 110 on the substrate 100, wherein the isolation dielectric layer 110 is also located on a part of the side wall surface of the fin structure 101.
Referring to fig. 2 and 3, fig. 3 is a schematic top view of fig. 2, fig. 2 is a schematic cross-sectional view taken along a direction a1-a2 in fig. 3, and a plurality of dummy gates 120 crossing over the fin structure 101 are formed on the isolation dielectric layer 110; forming a gate sidewall 121 on the sidewall surface of the dummy gate 120; after the gate spacers 121 are formed, a first dielectric layer 130 is formed on the isolation dielectric layer 110, and the top surface of the dummy gate 120 is exposed on the surface of the first dielectric layer 130.
Referring to fig. 4, the view directions of fig. 4 and fig. 3 are the same, the dummy gate 120 is removed, and a plurality of gate openings 131 are formed in the first dielectric layer 130.
Referring to fig. 5, in fig. 5, a gate dielectric film (not shown), a work function film (not shown) on the surface of the gate dielectric film, a barrier film (not shown) on the surface of the work function film, and a metal gate material layer (not shown) on the surface of the barrier film are formed in the gate opening 131 and on the surface of the first dielectric layer 130, and the metal gate material layer fills the gate opening 131; and flattening the metal gate material layer, the work function film, the barrier film and the gate dielectric film until the surface of the first dielectric layer 130 is exposed to form a gate structure, wherein the gate structure comprises a gate dielectric layer 151, a work function layer 152, a barrier layer 153 and a metal gate 154.
However, in the above embodiment, the work function layer 152 is thick, and at the same time, the thicker barrier layer 153 is formed to block the material diffusion of the metal gate 154, so that the adjacent barrier layers 153 in the region B (as shown in fig. 5) are merged, and thus, the metal gate material layer cannot fill between the adjacent fin structures 101, and the formed metal gate 154 cannot cover the sidewalls of the fin structures 101 on the isolation dielectric layer 110, thereby affecting the electrical characteristics of the gate structure, and resulting in poor performance and reliability of the semiconductor structure.
In order to solve the above technical problems, embodiments of the present invention provide a semiconductor structure and a forming method thereof, where a material of a first barrier layer includes a metal element atom, a second element atom, and a third element atom, and the second element atom is in an amorphous state, or the second element atom and the third element atom are in an amorphous state, so that a better barrier to an element diffused in the metal gate material can be achieved through a thinner first barrier layer, thereby reducing a risk of merging the first barrier layers between adjacent gate structures, leaving more formation space for a metal gate in the gate structure, reducing a risk of insufficient filling of the metal gate, and improving performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 6 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 6, a substrate 200 is provided, and the substrate 200 has a plurality of fin structures 201 separated from each other.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In other embodiments, the fin structure comprises: the fin structure comprises a plurality of fin sacrificial layers arranged in a direction vertical to the surface of the substrate, and nano sheets positioned between the adjacent fin sacrificial layers.
In this embodiment, before forming the dummy gate in the subsequent step, a first dielectric layer 210 is formed on the substrate 200, where the first dielectric layer 210 is also located on a portion of a sidewall surface of the fin structure 201. The first dielectric layer 210 can electrically insulate the adjacent fin structures 201 from each other and the semiconductor device from the substrate 200.
Referring to fig. 7 and 8, fig. 7 is a schematic cross-sectional view taken along a direction a1-a2 in fig. 8, fig. 8 is a schematic top view taken along a direction B in fig. 7, and a plurality of dummy gates 220 are formed on the surface of the substrate 200; and forming a gate sidewall 221 on the sidewall of the dummy gate 220.
In the present embodiment, the material of the dummy gate 220 includes amorphous silicon or polysilicon.
The dummy gate 220 is used to define the pattern of the gate structure during the subsequent formation of the gate structure.
In this embodiment, the method for forming the dummy gate 220 includes: forming a dummy gate material film (not shown) on the substrate 200 to cover the surface of the fin structure 201; patterning the dummy gate material film until the surface of the substrate 200 is exposed, so as to form a plurality of mutually discrete dummy gates 220 on the substrate 200, wherein the dummy gates 220 cross over the fin structure 201, and the top surface of the dummy gates 220 is higher than the top surface of the fin structure 201.
The forming process of the dummy gate material film comprises the following steps: an epitaxial growth process, or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, among others.
The gate sidewall 221 is used for defining the formation position of the source-drain structure.
In this embodiment, the material of the gate sidewall spacers 221 includes a combination of low-K dielectric materials (K is less than 3.9). The low-K dielectric material comprises SiOC, SiOCN, SiBCN and the like.
In this embodiment, the method for forming the gate sidewall spacers 221 includes: depositing a side wall material film (not shown) on the surface of the substrate 200 and the surface of the dummy gate 220; and etching the side wall material film back by adopting an anisotropic etching process until the side wall material film on the surface of the substrate 200 and the top surface of the pseudo gate 220 is removed, and forming a gate side wall 221 on the side wall of the pseudo gate 220.
In this embodiment, before forming the second dielectric layer, a plurality of source/drain structures (not shown) are formed in the substrate 200 on both sides of the dummy gate 220.
Specifically, the method for forming a plurality of source-drain structures comprises the following steps: after forming the gate sidewall 221, forming source-drain openings (not shown) in the fin structure 201 on both sides of the dummy gate 220; and forming a source-drain structure in the source-drain opening by adopting an epitaxial growth process.
With continued reference to fig. 7 and 8, after the source-drain structure is formed, a second dielectric layer 230 is formed on the surface of the substrate 200, the surface of the first dielectric layer 210, and the sidewall of the dummy gate 221.
In this embodiment, the material of the second dielectric layer 230 is silicon oxide.
In other embodiments, the material of the second dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
In this embodiment, the method for forming the second dielectric layer 230 includes: forming a second dielectric material layer (not shown) on the surfaces of the dummy gate 220 and the substrate 200, wherein the surface of the second dielectric material layer is higher than the top surface of the dummy gate 220; the second dielectric material layer is planarized until the top surface of the dummy gate 220 is exposed.
The forming process of the second dielectric material layer comprises the following steps: a spin coating process, a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.
The process for flattening the second medium material layer comprises the following steps: etch back process or chemical mechanical polishing process.
Referring to fig. 9, in the view direction of fig. 9 and fig. 8, a plurality of gate openings 222 are formed in the second dielectric layer 230.
The gate opening 222 provides space for the subsequent formation of a gate structure.
The method for forming the gate openings 222 in the second dielectric layer 230 includes: forming a first mask layer (not shown) on the surface of the second dielectric layer 230, wherein the first mask layer exposes the top surface of the dummy gate 220; and etching the dummy gate 220 by using the first mask layer as a mask until the dummy gate 220 is removed, and forming a plurality of gate openings 222 in the second dielectric layer 230.
The etching process for removing the dummy gate 220 includes at least one of a dry etching process and a wet etching process.
In the etching process of removing the dummy gate 220, the alignment precision of etching is improved by the gate sidewall 221.
Referring to fig. 10, in the view direction of fig. 10 and fig. 7, a plurality of gate structures 240 are formed on the surface of the substrate 200, and the gate structures 240 cross over the plurality of fin structures 201.
In this embodiment, the gate structure 240 includes: the gate dielectric layer 241 is located on the substrate 200, the work function layer 242 is located on the surface of the gate dielectric layer 241, the first barrier layer 243 is located on the surface of the work function layer 242, and the metal gate 244 is located on the surface of the first barrier layer 243.
Specifically, the work function layer 242 is located on the substrate 200, and the gate dielectric layer 241 is located between the work function layer 242 and the substrate 200.
The first barrier layer 243 is used to block the metal gate 244 material diffusing into the work function layer 242.
The material of the first barrier layer 243 includes metal element atoms, second element atoms, and third element atoms, and the second element atoms are in an amorphous state, or the second element atoms and the third element atoms are in an amorphous state.
Because the material of the first blocking layer 243 includes metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state, or the second element atoms and the third element atoms are in an amorphous state, the blocking capability of the first blocking layer 243 is better, and the thinner first blocking layer 243 can block elements diffused in the material of the metal gate 244 in the gate structure 240, so that the thickness of the first blocking layer 243 is reduced, thereby reducing the risk of merging the first blocking layers 243 between adjacent gate structures 240, leaving more forming spaces for the metal gate 244 in the gate structure 240, reducing the risk of insufficient filling of the metal gate 244, and improving the performance of the semiconductor structure.
Specifically, by the amorphous crystal state, the second element atoms, or the second element atoms and the third element atoms better fill the lattice gaps in the material of the first barrier layer 243, and the lattice gaps in the material of the first barrier layer 243 are reduced, so that the first barrier layer 243 has a better blocking capability for the diffusion of the elements in the material of the metal gate 244, and thus, the elements diffused in the material of the metal gate 244 can be better blocked by the thinner first barrier layer 243.
In this embodiment, the second element is Si, and the third element is N.
Since the second element is Si and the third element is N, the second element atoms, or the second element atoms and the third element atoms in the first barrier layer 243 can be in an amorphous state (e.g., amorphous Si, or amorphous Si) 3 Ni 4 Etc.) to achieve a reduction in the thickness of the first barrier layer 243.
In the present embodiment, the second element atom and the third element atom constitute amorphous Si 3 Ni 4 。
In this embodiment, the material of the first barrier layer 243 is TiSiN.
In the present embodiment, the thickness of the first barrier layer 243 ranges from 1 angstrom to 20 angstrom.
The thickness of the first barrier layer 243 is too large to allow enough space for the material filling the metal gate 224. Too small a thickness of the first barrier layer 243 increases the risk of diffusion of the material of the metal gate 244, resulting in an impaired performance and reliability of the semiconductor structure. Therefore, the thickness of the first barrier layer 243 is selected to be appropriate, i.e., the thickness of the first barrier layer 243 is in a range of 1 to 20 angstroms, i.e., enough space is left for the material filling the metal gate 224, and at the same time, the material of the metal gate 244 diffusing into the work function layer 242 is better blocked. Thus, the performance and reliability of the semiconductor structure is improved.
In this embodiment, the work function layer 242 includes a P-type work function layer (not shown).
Specifically, in this embodiment, the material of the P-type work function layer is one or both of titanium nitride and tantalum nitride.
Specifically, the semiconductor structure in this embodiment includes a P-type transistor, and the P-type work function layer is used for adjusting the work function of the P-type transistor.
Meanwhile, since the material of the first barrier layer 243 is TiSiN, the first barrier layer 243 can also assist in adjusting the work function of the P-type transistor.
In this embodiment, the material of the gate dielectric layer 241 includes a high-K dielectric material (K is greater than 3.9). The high-K dielectric material comprises: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
In the present embodiment, the material of the metal gate 244 includes tungsten.
In this embodiment, the method for forming the gate structure 240 includes: forming a gate dielectric film (not shown) on the surface of the substrate 200, the inner wall surface of the gate opening 222, and the surface of the second dielectric layer 230; forming a work function film (not shown) on the surface of the gate dielectric film; forming a first barrier film (not shown) on the work function film surface; forming a metal gate material layer (not shown) on the surface of the first barrier film, wherein the metal gate material layer fills the gate opening 222; and planarizing the metal gate material layer, the first barrier film, the work function film and the gate dielectric film until the surface of the second dielectric layer 230 is exposed, so as to form a gate structure 240 in the gate opening 222.
In this embodiment, the process of forming the first barrier film, i.e., forming the first barrier layer 243, includes a chemical vapor deposition process using a reaction gas including SiH 4 And SiH 2 Cl 2 And the flow rate of the reaction gas ranges from 10 to 1000 normal ml/min. Thus, the formation of the material of the first barrier layer 243 is achieved.
In this embodiment, the process of planarizing the metal gate material layer, the first blocking film, the work function film, and the gate dielectric film includes a back etching process or a chemical mechanical planarization process.
In this embodiment, the gate structure 240 further includes: a second barrier layer 245 positioned on the surface of the first barrier layer 243, and the material of the second barrier layer 245 comprises TiN.
Since the gate structure 240 further includes the second barrier layer 245 on the surface of the first barrier layer 243, the material of the second barrier layer 245 includes TiN, so that the compatibility with the formation process of the metal gate 244 is improved by the second barrier layer 245. Furthermore, the material of the second barrier layer 245 includes TiN, so that the second barrier layer 245 can assist in adjusting the work function of the P-type transistor.
The method of forming the second barrier layer 245 includes: forming a second barrier film (not shown) on the surface of the first barrier film before forming the metal gate material layer; in the process of planarizing the metal gate material layer, the first barrier film, the work function film, and the gate dielectric film, the second barrier film is also planarized to form the second barrier layer 245.
In other embodiments, the second barrier layer is not formed.
In this embodiment, the gate structure 240 further includes: and a third barrier layer 246 between the gate dielectric layer 241 and the work function layer 242.
The third blocking layer 246 is used for protecting the material of the gate dielectric layer 241, and avoids the change of the electrical characteristics of the semiconductor structure due to the influence of the process after the gate dielectric film is formed on the material of the gate dielectric layer 241, thereby improving the performance and reliability of the semiconductor structure.
The method of forming the third barrier layer 246 includes: forming a third barrier film (not shown) on the surface of the gate dielectric film before forming the work function film; in planarizing the metal gate material layer, the first barrier film, the work function film, and the gate dielectric film, a third barrier film is also planarized to form the third barrier layer 246.
In other embodiments, the third barrier layer is not formed.
In this embodiment, the work function layer 242 further includes an N-type work function layer (not shown) on the P-type work function layer. Therefore, when the semiconductor structure is provided with the N-type transistor and the P-type transistor which are adjacent and have small intervals, the work function of the N-type transistor can be adjusted by adjusting the thickness of the N-type work function layer, and the work function of the P-type transistor can be adjusted by adjusting the thickness of the P-type work function layer. The N-type work function layer is made of titanium-aluminum alloy.
Meanwhile, since the first barrier layer 243 is made of TiSiN, the first barrier layer 243 does not affect the work function of the N-type transistor.
In other embodiments, the work function layer does not include an N-type work function layer.
In this embodiment, the gate structure 240 further includes: an etch stop layer (not shown) located between the third barrier layer 246 and the work function layer 242.
In order to adjust the thickness of the N-type work function layer and the thickness of the P-type work function layer respectively, therefore, in the process of forming the work function film, an initial N-type work function film and an initial P-type work function film are formed, and the initial N-type work function film and the initial P-type work function film are respectively etched to be thinned according to design requirements, so as to form the P-type work function film which can meet the adjustment of the work function of the P-type transistor and the N-type work function film which can meet the adjustment of the work function of the N-type transistor. The etching stop layer is used for better stopping the etching process on the third barrier layer 246 in the etching process of forming the work function film, so that the gate dielectric film is better protected, the risk of damage to the gate dielectric film is reduced, and the performance and reliability of the semiconductor structure are improved.
In other embodiments, the work function layer comprises only a P-type work function layer, and no etch stop layer is formed.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 10, including: the structure comprises a substrate 200, wherein a plurality of fin structures 201 which are mutually separated are arranged on the substrate 200; a plurality of gate structures 240 located on the surface of the substrate 200, the gate structures 240 crossing over the plurality of fin structures 201, the gate structures 240 including a work function layer 242 located on the substrate, and a first barrier layer 243 located on the surface of the work function layer 242, the first barrier layer 243 including metal element atoms, second element atoms, and third element atoms in a material, the second element atoms being in an amorphous state, or the second element atoms and the third element atoms being in an amorphous state.
Because the material of the first blocking layer 243 includes metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state, or the second element atoms and the third element atoms are in an amorphous state, the blocking capability of the first blocking layer 243 is better, and the thinner first blocking layer 243 can block elements diffused in the metal gate material in the gate structure 240, so that the thickness of the first blocking layer 243 is reduced, thereby reducing the risk of merging the first blocking layers 243 between adjacent gate structures 240, leaving more formation spaces for the metal gate in the gate structure 240, reducing the risk of insufficient filling of the metal gate, and improving the performance of the semiconductor structure. Specifically, by the amorphous crystal state, the second element atoms, or the second element atoms and the third element atoms better fill the lattice gaps in the material of the first barrier layer 243, and the lattice gaps in the material of the first barrier layer 243 are reduced, so that the first barrier layer 243 has a better blocking capability for the diffusion of the elements in the metal gate material, and thus, the elements diffused in the metal gate material can be better blocked by the thinner first barrier layer 243.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In other embodiments, the fin structure comprises: the fin structure comprises a plurality of fin sacrificial layers arranged in a direction vertical to the surface of the substrate, and nano sheets positioned between the adjacent fin sacrificial layers.
In this embodiment, the gate structure 240 further includes: a gate dielectric layer 241 between the work function layer 242 and the substrate 200, and a metal gate 244 on the surface of the first barrier layer 243.
The first barrier layer 243 is used to block the metal gate 244 material diffusing into the work function layer 242.
In this embodiment, the second element is Si, and the third element is N.
Since the second element is Si and the third element is N, the second element atoms, or the second element atoms and the third element atoms in the first barrier layer 243 can be in an amorphous state (e.g., amorphous Si, or amorphous Si) 3 Ni 4 Etc.) to achieve a reduction in the thickness of the first barrier layer 243.
In the present embodiment, the second element atom and the third element atom constitute amorphous Si 3 Ni 4 。
In this embodiment, the material of the first barrier layer 243 is TiSiN.
In the present embodiment, the thickness of the first barrier layer 243 ranges from 1 angstrom to 20 angstrom.
The thickness of the first barrier layer 243 is too large to allow enough space for the material filling the metal gate 224. Too small a thickness of the first barrier layer 243 increases the risk of diffusion of the material of the metal gate 244, resulting in an impaired performance and reliability of the semiconductor structure. Therefore, the thickness of the first barrier layer 243 is selected to be appropriate, i.e., when the thickness of the first barrier layer 243 is in the range of 1 to 20 angstroms, sufficient space is left for forming the material for filling the metal gate 224, and at the same time, the material of the metal gate 244 diffusing into the work function layer 242 is better blocked. Thus, the performance and reliability of the semiconductor structure is improved.
In this embodiment, the work function layer 242 includes a P-type work function layer (not shown).
Specifically, in this embodiment, the material of the P-type work function layer is one or both of titanium nitride and tantalum nitride.
Specifically, the semiconductor structure in this embodiment includes a P-type transistor, and the P-type work function layer is used for adjusting the work function of the P-type transistor.
Meanwhile, since the material of the first barrier layer 243 is TiSiN, the first barrier layer 243 can also assist in adjusting the work function of the P-type transistor.
In this embodiment, the material of the gate dielectric layer 241 includes a high-K dielectric material (K is greater than 3.9). The high-K dielectric material comprises: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
In the present embodiment, the material of the metal gate 244 includes tungsten.
In this embodiment, the gate structure 240 further includes: a second barrier layer 245 positioned on the surface of the first barrier layer 243, and the material of the second barrier layer 245 comprises TiN.
Since the gate structure 240 further includes the second barrier layer 245 on the surface of the first barrier layer 243, the material of the second barrier layer 245 includes TiN, so that the compatibility with the formation process of the metal gate 244 is improved by the second barrier layer 245. Furthermore, the material of the second barrier layer 245 includes TiN, so that the second barrier layer 245 can assist in adjusting the work function of the P-type transistor.
In other embodiments, the semiconductor structure does not include a second barrier layer.
In this embodiment, the gate structure 240 further includes: and a third barrier layer 246 located between the gate dielectric layer 241 and the work function layer 242.
The third blocking layer 246 is used for protecting the material of the gate dielectric layer 241, and avoids the change of the electrical characteristics of the semiconductor structure due to the influence of the process after the gate dielectric film is formed on the material of the gate dielectric layer 241, thereby improving the performance and reliability of the semiconductor structure. Furthermore, the third blocking layer 246 also serves to block the material diffused from the work function layer 242 to the gate dielectric layer 241, thereby protecting the gate dielectric layer 241 to improve the performance and reliability of the semiconductor structure.
In other embodiments, the semiconductor structure does not include a third barrier layer.
In this embodiment, the work function layer 242 further includes an N-type work function layer (not shown) on the P-type work function layer. Therefore, when the semiconductor structure is provided with the N-type transistor and the P-type transistor which are adjacent and have small intervals, the work function of the N-type transistor can be adjusted by adjusting the thickness of the N-type work function layer, and the work function of the P-type transistor can be adjusted by adjusting the thickness of the P-type work function layer. The N-type work function layer is made of titanium-aluminum alloy.
Meanwhile, since the first barrier layer 243 is made of TiSiN, the first barrier layer 243 does not affect the work function of the N-type transistor.
In other embodiments, the work function layer does not include an N-type work function layer.
In this embodiment, the gate structure 240 further includes: an etch stop layer (not shown) located between the third barrier layer 246 and the work function layer 242.
In other embodiments, the work function layer comprises only a P-type work function layer, and the semiconductor structure does not comprise an etch stop layer.
In this embodiment, the semiconductor structure further includes: and the first dielectric layer 210 is positioned between the substrate 200 and the gate structure 240, and the first dielectric layer 210 is also positioned on a part of the side wall surface of the fin structure 201. The first dielectric layer 210 can electrically insulate the adjacent fin structures 201 from each other and the semiconductor device from the substrate 200.
In this embodiment, the semiconductor structure further includes: and the gate sidewall 221 is positioned on the sidewall of the gate structure 240.
In this embodiment, the material of the gate sidewall 221 includes a combination of a plurality of low K dielectric materials (K is less than 3.9). The low-K dielectric material comprises SiOC, SiOCN, SiBCN and the like.
In this embodiment, the semiconductor structure further includes: and a plurality of source and drain structures (not shown) in the substrate 200 at two sides of the gate structure 240.
In this embodiment, the semiconductor structure further includes: and the second dielectric layer 230 is positioned on the surface of the substrate 200, the surface of the first dielectric layer 210 and the side wall of the gate structure 240.
In this embodiment, the material of the second dielectric layer 230 is silicon oxide.
In other embodiments, the material of the second dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A semiconductor structure, comprising:
the structure comprises a substrate and a plurality of fins, wherein the plurality of fins are mutually separated;
the gate structure is arranged on the surface of the substrate and spans the fin structures, the gate structure comprises a work function layer arranged on the substrate and a first barrier layer arranged on the surface of the work function layer, the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state.
2. The semiconductor structure of claim 1, wherein the second element is Si and the third element is N.
3. The semiconductor structure of claim 2, wherein the second element atoms and the third element atoms form amorphous Si 3 Ni 4 。
4. The semiconductor structure of claim 2, wherein a material of the first barrier layer is TiSiN.
5. The semiconductor structure of claim 1, wherein the first barrier layer has a thickness in a range from 1 angstrom to 20 angstroms.
6. The semiconductor structure of claim 1, wherein the gate structure further comprises: and the second barrier layer is positioned on the surface of the first barrier layer, and the material of the second barrier layer comprises TiN.
7. The semiconductor structure of claim 1, wherein the work function layer comprises a P-type work function layer, and the material of the P-type work function layer is one or both of titanium nitride and tantalum nitride.
8. The semiconductor structure of claim 7, wherein the work function layer further comprises an N-type work function layer on the P-type work function layer, and the material of the N-type work function layer is titanium aluminum alloy.
9. The semiconductor structure of claim 1, wherein the gate structure further comprises: the gate dielectric layer is positioned between the work function layer and the substrate, and the metal gate is positioned on the surface of the first barrier layer.
10. The semiconductor structure of claim 9, wherein the gate structure further comprises: and the third barrier layer is positioned between the gate dielectric layer and the work function layer.
11. The semiconductor structure of claim 10, wherein the gate structure further comprises: and the etching stop layer is positioned between the third barrier layer and the work function layer.
12. The semiconductor structure of claim 9, wherein a material of the metal gate comprises tungsten.
13. The semiconductor structure of claim 9, wherein the material of the gate dielectric layer comprises a high-K dielectric material.
14. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of fin part structures which are mutually separated;
forming a plurality of gate structures on the surface of the substrate, wherein the gate structures cross the fin structures, each gate structure comprises a work function layer located on the substrate and a first barrier layer located on the surface of the work function layer, the material of the first barrier layer comprises metal element atoms, second element atoms and third element atoms, and the second element atoms are in an amorphous state or the second element atoms and the third element atoms are in an amorphous state.
15. The method of forming a semiconductor structure of claim 14, wherein the second element is Si and the third element is N.
16. The method of forming a semiconductor structure of claim 15, wherein the second element atoms and the third element atoms form amorphous Si 3 Ni 4 。
17. The method of forming a semiconductor structure of claim 15, wherein a material of the first barrier layer is TiSiN.
18. The method of forming a semiconductor structure of claim 14, wherein the gate structure further comprises a second barrier layer on a surface of the first barrier layer, and a material of the second barrier layer comprises TiN.
19. The method of claim 14, wherein the step of forming the first barrier layer comprises a chemical vapor deposition process using a reactant gas comprising SiH 4 And SiH 2 Cl 2 And the flow rate of the reaction gas ranges from 10 to 1000 normal ml/min.
CN202110071678.9A 2021-01-19 2021-01-19 Semiconductor structure and forming method thereof Pending CN114823895A (en)

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