CN114822653A - Data erasing method, storage device and storage system - Google Patents

Data erasing method, storage device and storage system Download PDF

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Publication number
CN114822653A
CN114822653A CN202210480085.2A CN202210480085A CN114822653A CN 114822653 A CN114822653 A CN 114822653A CN 202210480085 A CN202210480085 A CN 202210480085A CN 114822653 A CN114822653 A CN 114822653A
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memory
voltage
layer
word line
bias voltage
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宋雅丽
关蕾
赵向南
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

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Abstract

The embodiment of the application provides a data erasing method, a storage device and a storage system. The memory device includes a memory block having a plurality of memory strings, each memory string being connected between a bit line and a source and including a plurality of memory cells connected in series, the memory cells of the same memory layer being connected to the same word line. The data erasing method of the nonvolatile memory device includes: the method includes applying an erase voltage to a source, and sequentially applying a plurality of different voltages to a word line of at least one memory layer during a time when the erase voltage is applied, wherein the plurality of different voltages includes at least a first bias voltage, and a compensation voltage having a voltage value greater than the first bias voltage. Embodiments of the present application may mitigate memory device aging due to erase operations.

Description

Data erasing method, storage device and storage system
Technical Field
Embodiments of the present invention relate to the field of design and manufacture of semiconductor structures, and more particularly, to a data erasing method, a memory device, and a memory system.
Background
Scaling of planar memory cells is challenging due to process technology limitations and reliability issues as memory devices are scaled to smaller die sizes to reduce manufacturing costs and increase storage density. Three-dimensional memory architectures can handle density and performance limitations in planar memory cells.
In a three-dimensional memory, many layers of memory cells may be vertically stacked, so that the storage density per unit area may be greatly increased. To further increase storage density, multiple levels may be vertically stacked, with many vertically stacked memory cells in each level. For efficient reading, writing and erasing in a three-dimensional memory having multiple levels, each level may be treated as a separate memory block, i.e., each level may be erased independently of the other levels. However, as the requirement for the performance of the three-dimensional memory is higher and higher, the requirement for the erasing speed is higher and higher, and the reliability of the three-dimensional memory is extremely high risk.
Disclosure of Invention
Embodiments of the present application provide a data erasing method, a storage device, and a storage system that can at least partially solve the above-mentioned problems in the prior art.
In one aspect, the present invention provides a data erasing method for a nonvolatile memory device, where the memory device includes a memory block having a plurality of memory strings, each memory string is connected between a bit line and a source and includes a plurality of memory cells connected in series, the memory cells of a same memory layer are connected to a same word line, and for a memory block to be erased, the method includes: the method includes applying an erase voltage to a source, and sequentially applying a plurality of different voltages to a word line of at least one memory layer during a time when the erase voltage is applied, wherein the plurality of different voltages includes at least a first bias voltage, and a compensation voltage having a voltage value greater than the first bias voltage.
In some exemplary embodiments of the present application, a variation of the voltage values of the plurality of different voltages applied in sequence is trended to decrease from the compensation voltage to the first bias voltage.
In some exemplary embodiments of the present application, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is to increase after decreasing from the compensation voltage to the first bias voltage.
In some exemplary embodiments of the present application, a plurality of storage layers are divided into a plurality of storage regions in a direction perpendicular to the storage layers; sequentially applying a plurality of different voltages to the word lines of the at least one memory layer includes: sequentially applying a plurality of different voltages to word lines of the memory layer of the first memory region adjacent to the source among the plurality of memory regions; the method further comprises the following steps: and applying a second bias voltage to word lines of the memory layers of the other memory regions except the first memory region, the second bias voltage being less than the compensation voltage.
In some exemplary embodiments of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the compensation voltage and the first bias voltage are applied to the word lines of the memory layers of at least two memory regions, and the voltage values of the applied compensation voltages are different.
In some exemplary embodiments of the present application, a memory string includes a channel structure, and a memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein a voltage value of the compensation voltage applied to the word line of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation.
In some exemplary embodiments of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the word lines of the memory layers of at least two memory regions are applied with the compensation voltage and the first bias voltage, and the lengths of time the first bias voltage is applied are different.
In some exemplary embodiments of the present application, a memory string includes a channel structure, and a memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein a length of time that the word line of the memory layer is applied with the first bias voltage has a positive correlation with a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer.
In some exemplary embodiments of the present application, a voltage value of the first bias voltage is equal to or greater than 0V and equal to or less than 1V.
In some exemplary embodiments of the present application, the compensation voltage has a voltage value smaller than the erase voltage.
In some exemplary embodiments of the present application, the memory block further includes a bottom redundancy transistor between the memory cell and the source, and a top redundancy transistor between the memory cell and the bit line; during the time that the erase voltage is applied, the word lines connected to the top redundant transistor and the word lines connected to the bottom redundant transistor float.
In some exemplary embodiments of the present application, the memory block further includes a bottom select transistor between the memory cell and the source, and a top select transistor between the memory string and the bit line; during the time that the erase voltage is applied, the word lines connected to the top select transistors and the word lines connected to the bottom select transistors are floating.
Another aspect of embodiments of the present application provides a nonvolatile memory device including: a memory block including a plurality of memory strings, each of the memory strings being connected between a bit line and a source electrode and including a plurality of memory cells connected in series, the memory cells of the same memory layer being connected to the same word line; peripheral circuitry coupled to the memory block and performing an erase operation on memory cells in the memory block, the peripheral circuitry configured to: the method includes applying an erase voltage to a source, and sequentially applying a plurality of different voltages to a word line of at least one memory layer during a time when the erase voltage is applied, wherein the plurality of different voltages includes at least a first bias voltage, and a compensation voltage having a voltage value greater than the first bias voltage.
In some exemplary embodiments of the present application, a plurality of storage layers are divided into a plurality of storage regions in a direction perpendicular to the storage layers; the peripheral circuitry is configured to: sequentially applying a plurality of different voltages to word lines of the memory layer of the first memory region adjacent to the source among the plurality of memory regions; the peripheral circuitry is further configured to: and applying a second bias voltage to word lines of the memory layers of the other memory regions except the first memory region, the second bias voltage being less than the compensation voltage.
In some exemplary embodiments of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the compensation voltage and the first bias voltage are applied to the word lines of the memory layers of at least two memory regions, and the voltage values of the applied compensation voltages are different.
In some exemplary embodiments of the present application, a memory string includes a channel structure, and a memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein a voltage value of the compensation voltage applied to the word line of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation.
In some exemplary embodiments of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the word lines of the memory layers of at least two memory regions are applied with the compensation voltage and the first bias voltage for different lengths of time.
In some exemplary embodiments of the present application, a memory string includes a channel structure, and a memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein a length of time that the word line of the memory layer is applied with the first bias voltage has a positive correlation with a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer.
Another aspect of embodiments of the present application provides a nonvolatile memory system including: a nonvolatile memory device including a memory block having a plurality of memory strings and a peripheral circuit coupled to the memory block, each memory string being connected between a bit line and a source and including a plurality of memory cells connected in series, the memory cells of a same memory layer being connected to a same word line; and a controller coupled to the storage device and configured to control the storage device; wherein the peripheral circuitry is configured to: applying an erase voltage to the source, and sequentially applying a plurality of different voltages including at least a first bias voltage and a compensation voltage having a voltage value greater than the first bias voltage to the word line of the at least one memory layer during a time when the erase voltage is applied.
According to one embodiment of the application, in the process of applying the erasing voltage to the source electrode, the nonvolatile memory device applies the compensation voltage with a larger voltage value to the word line of the storage layer so as to reduce the electric field intensity at the channel structure, reduce the pressure on the storage layer, reduce the breakdown condition, further reduce the probability of programming failure or erasing failure, and improve the DPPM.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:
FIG. 1 is a block diagram of a non-volatile memory device according to an embodiment of the present application;
FIG. 2 is an equivalent circuit diagram of a memory block according to an embodiment of the present application;
FIG. 3 is an equivalent circuit diagram of a portion of the memory block shown in FIG. 2;
FIG. 4 is a schematic diagram of a portion of the structure of the memory string shown in FIG. 3;
FIG. 5 is a voltage waveform diagram of a method of erasing operations of a non-volatile memory device in some processes;
FIG. 6 is a graph of voltage waveforms for a non-volatile memory device according to some embodiments of the present application;
FIG. 7 is a voltage waveform diagram of a non-volatile memory device according to yet another embodiment of the present application;
FIG. 8 is a voltage waveform diagram of a non-volatile memory device according to another embodiment of the present application;
FIG. 9 is a voltage waveform diagram of a non-volatile memory device according to another embodiment of the present application;
FIG. 10 is a voltage waveform diagram of a non-volatile memory device according to another embodiment of the present application;
FIG. 11 is a graph of voltage waveforms for a non-volatile memory device according to another embodiment of the present application;
FIG. 12 is a voltage waveform diagram of a non-volatile memory device according to another embodiment of the present application;
FIG. 13 is a voltage waveform diagram of a non-volatile memory device according to another embodiment of the present application;
FIG. 14 is a voltage waveform diagram of a non-volatile memory device according to another embodiment of the present application;
FIG. 15 is a flow chart of a method of erasing data from a non-volatile memory device according to one embodiment of the present application;
FIG. 16 is a block diagram of a non-volatile storage system according to an embodiment of the present application;
FIG. 17 is a schematic block diagram of a non-volatile storage system according to an exemplary embodiment of the present application;
FIG. 18 is a block diagram of another non-volatile storage system according to an example embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that in this specification the expressions first, second, third etc. are only used to distinguish one feature from another, and do not indicate any limitation of features, in particular any order of precedence.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than merely individual elements of the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.
Fig. 1 is a schematic block diagram of a nonvolatile memory device 10 according to an embodiment of the present application, fig. 2 is an equivalent circuit diagram of a memory block BLK1 according to an embodiment of the present application, fig. 3 is an equivalent circuit diagram of a portion of a memory block BLK1 shown in fig. 2, and fig. 4 is a partial structural diagram of a memory string MS shown in fig. 3.
In some embodiments of the present application, referring to fig. 1, a non-volatile memory device 10 may comprise, for example: memory blocks BLK 1-BLKz and peripheral circuit 120. One or more memory blocks BLK 1-BLKz may form memory cell array 110. Referring to fig. 2, the memory blocks BLK1 to BLKz have a plurality of memory strings MS11 to MSnm, each of which is connected between a bit line BL and a source (e.g., a common source line CSL of fig. 2) and includes a plurality of memory cells (e.g., MC1 to MCk) connected in series, and the memory cells MC of the same memory layer are connected to the same word line. The peripheral circuits 120 are coupled to the memory blocks BLK 1-BLKz and perform erase operations, program operations, etc. on the memory cells (e.g., MC 1-MCk) in the memory blocks BLK 1-BLKz.
In some embodiments of the present application, referring to fig. 1 and 2, the peripheral circuit 120 may include, for example, an address decoder 121, a page buffer 122, a control logic circuit 123, an I/O circuit 124, and a voltage generator 125.
The memory cell array 110 may be connected to the address decoder 121 through, for example, memory layer word lines WL, top redundancy word lines TRL, bottom redundancy word lines BRL, top selection word lines TSL, and bottom selection word lines BSL, and connected to the page buffer 122 through, for example, bit lines BL. Each memory block of the memory cell array 110 may include a plurality of pages (pages). Exemplarily, the nonvolatile memory device 10 performs an erase operation in units of a memory block BLK, and performs a program operation or a read operation in units of a page.
The address decoder 121 may control word lines connected to the memory cell array 110, for example, a memory layer word line WL connected to the memory layer, a top redundancy word line TRL connected to the top redundancy layer, a bottom redundancy word line BRL connected to the bottom redundancy layer, a top selection word line TSL connected to the top selection layer, and a bottom selection word line BSL connected to the bottom selection layer, in response to the control logic circuit 123. In other words, address decoder 121 may receive and decode address ADDR from control logic 123, and select one of the plurality of memory blocks BLK1 through BLKz in memory cell array 110 according to the decoded address ADDR. Illustratively, one of a plurality of pages in the selected memory block may be selected. Each memory layer word line WL may be used to control one page. The address decoder 121 may provide a voltage required for the storage layer word line WL from the voltage generator 125 to the selected storage layer word line WL in the selected memory block BLK.
The page buffer 122 may function as a write driver or a sense amplifier depending on the operation mode. For example, in a program operation, the page buffer 122 may supply a bit line voltage corresponding to DATA that needs to be programmed to the bit line BL of the memory cell array 110. The DATA may be multi-bit DATA that requires programming. In a read operation, the page buffer 122 may sense DATA stored in a selected memory cell through the bit line BL and output the sensed DATA to the I/O circuit 124. The page buffer 122 may include a plurality of page buffers respectively connected to the bit lines BL.
The control logic circuit 123 may control the address decoder 121, the page buffer 122, and the voltage generator 125 in response to commands CMD (e.g., program commands and read commands) and addresses ADDR from the I/O circuit 124. In addition, the control logic circuit 123 may control the nonvolatile memory device 10 to perform a program operation through a multi-step method. The multi-step method may perform a programming operation a plurality of times to configure a desired program state, and may include a pre/main programming method, a reprogramming method, a shadow programming method, and the like.
The voltage generator 125 may generate voltages to be supplied to the memory layer including the memory layer word line WL, the top redundancy word line TRL, the bottom redundancy word line BRL, the top selection word line TSL, and the bottom selection word line BSL under the control of the control logic circuit 123.
It will be understood by those skilled in the art that the operations performed by the address decoder 121, the page buffer 122, the control logic circuit 123, and the voltage generator 125 described herein may be performed by a processing circuit. The processing circuitry may include, but is not limited to, hardware of logic circuitry or a hardware/software combination of a processor executing software.
In one embodiment of the present application, referring to FIG. 2, the memory block BLK1 includes a plurality of memory strings MS11 MSnm. The memory strings MS11 Mnm may be arranged in a two-dimensional array on the xy plane. Each memory string MS may extend in the z-axis direction. The memory string MS, taking MS11 as an example, may include top select transistors TST 11-TST 12, top redundant transistors TRT 1-TRT 4, memory cells MC 1-MCk, bottom redundant transistors BRT 1-BRT 4, and bottom select transistors BST 11-BST 12, for example. That is, the memory string MS may include a plurality of memory cells MC connected in series between the bit line BL and the source. Storing the string MS may further include: a bottom redundancy transistor BRT between the memory cell MC and the source, a top redundancy transistor TRT between the memory cell MC and the bit line BL, a bottom select transistor BST between the memory cell MC and the source, and a top select transistor TST between the memory cell MC and the bit line. Memory cells MC of the same memory layer are connected to the same word line (e.g., memory layer word line WL). The number of the select transistors TST/BST, the redundancy transistors TRT/BRT, and the memory cells MC in each memory string MS is not specifically limited in this application. The redundancy transistor TRT/BRT and the memory cell MC may be charge trap MOS transistors capable of changing their threshold voltages by tunneling effect so that the memory cell MC and/or the redundancy transistor TRT/BRT are in different memory states. The selection transistor TST/BST may be a conventional MOS transistor or a charge trap type MOS transistor, which is not particularly limited in this application. In addition, since the top redundancy transistor TRT and the bottom redundancy transistor BRT are connected in the same manner, the reference numerals of the bottom redundancy transistor BRT and the corresponding structures are omitted from fig. 2 in this application.
The plurality of memory strings MS 11-MSnm on the memory block BLK1 may be connected to a common source line CSL. For example, the source terminals of the plurality of bottom select transistors BST at the ends of the plurality of memory strings MS 11-MSnm may be connected to the common source line CSL.
The gate terminals of the memory cells MC 1-MCk of the plurality of memory strings MS 11-MSnm located at the same height or a similar height from the common source line CSL may be connected to the same memory layer word lines WL 1-WLk. According to the description of the above structure, memory cells MC connected to the same memory layer word line WL to be simultaneously programmed may constitute one page, and one memory block BLK may include a plurality of pages. Similarly, the gate terminals of the redundancy transistors TRT/BRT located at the same height or at a similar height from the common source line CSL in the plurality of memory strings MS 11-MSnm may be connected to the same redundancy word line TRL/BRL.
Gate terminals of top select transistors TST (e.g., TST2) located at the same height or a similar height from the common source line CSL in a plurality of memory strings (e.g., MS11 to MS1m) arranged in the y-axis direction may be connected to the same top select word line TSL 21. Similarly, the gate terminals of the bottom select transistors BST located at the same height or at a similar height from the common source line CSL in the plurality of memory strings (e.g., MS11 through MS1m) arranged in the y-axis direction may be connected to the same bottom select word line BSL. Alternatively, as shown in fig. 2, a plurality of bottom select word lines BSL located at the same height or a similar height from the common source line CSL may be connected to each other. In other words, like the memory layer word line WL and the redundancy word line TRL/BRL, the gate terminals of the bottom select transistors BST (e.g., BST2) located at the same height or a similar height from the common source line CSL in the plurality of memory strings MS 11-MSnm may be connected to the same bottom select word line BSL.
A plurality of memory strings MS 11-MSnm on the memory block BLK1 may be connected to a plurality of bit lines BL 1-BLm. Specifically, the drain terminals of the top select transistors TST at the ends of the plurality of memory strings (e.g., MS11 to MSn1) arranged in the x-axis direction may be connected to the same bit line BL at the same height or at a similar height from the common source line CSL.
It should be understood that the memory block BLK1 may be the same as or similar to the other memory blocks BLK 2-BLKz in the memory cell array 110, which is described in detail herein with reference to the memory block BLK1 as an example.
In one embodiment of the present application, FIG. 3 shows a plurality of memory strings MS11 MS71 connected to the same bit line BL 1. The gate terminals of the top select transistors TST11 to TST71 in the memory strings MS11 to MS71 may be connected to the top select word lines TSL11 to TSL71, respectively, and the gate terminals of the top select transistors TST12 to TST72 in the memory strings MS11 to MS71 may be connected to the top select word lines TSL12 to TSL72, respectively.
Fig. 4 is a cross-sectional view of an exemplary memory string MS, according to some embodiments of the present application, which is an example of the memory string MS shown in fig. 3. As shown in fig. 4, the nonvolatile memory device 10 further includes a well region (not shown) as a source of the memory string MS, the well region being located in the semiconductor layer 200. The memory string MS extends above the semiconductor layer 200 in a direction substantially perpendicular to the semiconductor layer 200. Semiconductor layer 200 may be a semiconductor substrate, which may include, for example, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. The semiconductor layer 200 may include a well region, for example, and the well region of the semiconductor layer 200 may be a P-well or an N-well, for example, which is not limited in this application.
The memory string MS may include, for example, a channel structure 220, and the channel structure 220 may include, for example, a functional layer 221, a channel layer 222, and a channel fill layer 223. The functional layer 221 may include a blocking layer (not shown) blocking outflow of charges, a charge trap layer (not shown) on a surface of the blocking layer to store charges during operation of the semiconductor structure, and a tunnel insulating layer (not shown) on a surface of the charge trap layer. The functional layer 221 may include an oxide-nitride-oxide (ONO) structure. The channel layer 222 can be used to transport desired charges (electrons or holes). The trench fill layer 223 may include a dielectric layer of oxide, such as silicon oxide, etc.
In some embodiments, the channel structure 220 of the memory string MS extends vertically through a memory stack layer (not shown) having interleaved conductive layers (e.g., 210) and dielectric layers (not shown). The conductive layers (e.g., 210) can be divided, for example, into a top selection layer, a top redundancy layer, a memory layer, a bottom redundancy layer, a bottom selection layer. According to some embodiments, the storage layer of the channel structure 220 surrounding the memory string MS is a control gate of the memory cell MC in the memory string MS. In the memory string MS, the memory cells MC may be arranged in series, for example, vertically. In some embodiments, each memory cell MC may, for example, include a control gate (i.e., a portion of the memory layer) and a portion of the channel structure 220 surrounded by the control gate. Similarly, the top select transistor TST includes a top select layer surrounding the channel structure 220 of the memory string MS, which is a control gate of the top select transistor TST, and a portion of the channel structure 220 surrounded by the top select layer. The top redundancy transistor TRT includes a top redundancy layer surrounding the channel structure 220 of the memory string MS, which is a control gate of the top redundancy transistor TRT, and a portion of the channel structure 220 surrounded by the top redundancy layer. The bottom selection transistor BST includes a bottom selection layer surrounding the channel structure 220 of the memory string MS, which is a control gate of the bottom selection transistor BST, and a portion of the channel structure 220 surrounded by the bottom selection layer. The bottom redundancy transistor BRT includes a bottom redundancy layer surrounding the channel structure 220 of the memory string MS, which is a control gate of the bottom redundancy transistor BRT, and a portion of the channel structure 220 surrounded by the bottom redundancy layer. The conductive layer (e.g., 210) forming the control gates, also referred to as word lines (e.g., the storage layer word line WL, the top select word line TSL, the top redundant word line TRL, the bottom select word line BSL, and the bottom redundant word line BRL in fig. 1) coupled to the memory strings MS, are capable of receiving word line bias voltages for controlling the operation of the memory cells MC, for example, by read, erase, and program operations. The conductor layer 210 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
It should be understood that the structures of the nonvolatile memory devices illustrated in fig. 1 to 4 are schematically illustrated by taking the example that the nonvolatile memory devices include a 2-layer top selection layer, a 4-layer top redundancy layer, a 4-layer bottom redundancy layer, and a 2-layer bottom selection layer, and the number of the layers can be adjusted as needed without departing from the present application, which is not limited by the present application.
When programming the memory cell MC, electrons are stored in the portion of the charge trapping layer associated with the memory cell MC. These electrons are pulled into the charge trapping layer from the channel in the semiconductor layer 200 and through the tunneling layer. The threshold value (Vth) of the memory cell MC increases in proportion to the amount of stored charge. When erasing the memory cell MC, electrons are driven back to the channel in the semiconductor layer 200. In some processes, a voltage waveform diagram of an erase operation method of a nonvolatile memory device is shown in fig. 5. During an erase operation, an erase voltage V may be applied to the source, e.g., through the common source line CSL erase The top redundancy layer, the bottom redundancy layer, the top selection layer, and the bottom selection layer are floated, that is, the top redundancy word line TRL, the bottom redundancy word line BRL, the top selection word line TSL, and the bottom selection word line BSL are floated, and all the memory layer word lines WL are grounded.
However, due to the limitations of the current process conditions, the channel structure 220 of the memory string MS may for example comprise a non-uniform lateral dimension (e.g. diameter) in the y-direction as a result of the deep hole etch process. In some embodiments, the diameter of the channel structure 220 of the memory string MS increases from bottom to top. With the increasing requirements on the performance of the three-dimensional memory and the increasing requirements on the erasing speed, the erasing voltage also needs to be increased continuously. The increase of the erase voltage affects the performance of the three-dimensional memory, for example, the functional layer of the bottom word line is easily degraded, and the memory block BLK is failed due to the leakage current. In addition, the reliability and read window of the three-dimensional memory are also degraded, which poses a very high risk to reliability. Illustratively, due to the small bottom dimension of the channel structure 220, the electric field strength is large, the pressure on the bottom memory layer is large, after ten thousand program-erase operations, a three-dimensional memory burning-out condition is easy to occur, which causes program or erase failure, resulting in a part Per Million defect rate (DPPM) degradation.
In some embodiments of the present application, the peripheral circuitry 120 is configured to: an erase voltage is applied to the source electrode, and a plurality of different voltages are sequentially applied to the word line of at least one memory layer during the time when the erase voltage is applied. The plurality of different voltages at least comprise a first bias voltage and a compensation voltage with a voltage value larger than the first bias voltage.
According to the embodiment of the application, in the process of applying the erasing voltage, the nonvolatile memory device applies the compensation voltage with a larger voltage value to the word line of the memory layer so as to reduce the electric field intensity at the channel structure, reduce the pressure on the memory layer, reduce the breakdown condition, further reduce the probability of programming failure or erasing failure, and improve DPPM.
In some embodiments of the present application, the peripheral circuitry 120 may be configured to: while applying an erase voltage to the source (e.g., well region of the semiconductor layer 200) of the memory string MS, a plurality of different voltages are applied to the word line of the memory layer.
It should be understood that the peripheral circuitry 120 may also be configured to: a plurality of different voltages are sequentially applied to the word lines of the memory layer for a preset time after the application of the erase voltage to the source electrode (e.g., the well region of the semiconductor layer 200) of the memory string MS, wherein the level of the preset time may be, for example, in milliseconds. Since it takes a certain time for the voltage of the semiconductor layer 200 to rise, the peripheral circuit 120 may be configured to: a plurality of different voltages are applied to the word line of the memory layer before or after the erase voltage is applied to the semiconductor layer 200, which is not limited in the present application.
In one embodiment of the present application, a voltage value of the first bias voltage is equal to or greater than 0V and equal to or less than 1V to improve a data erasing speed.
In one embodiment of the present application, the compensation voltage has a voltage value greater than the first bias voltage and less than the erase voltage V erase . Illustratively, the voltage value range of the compensation voltage is (0V, 3V)]Or the voltage value range of the compensation voltage is [1V, 3V ]]. By applying a compensation voltage to the word line of the memory layer, a voltage difference between the word line of the memory layer and the semiconductor layer 200 is reduced, and damage of the nonvolatile memory device due to a large voltage difference applied to the memory layer at an initial stage of data erase can be reduced. After the compensation voltage is applied, the first bias voltage having a small voltage value is applied, so that a voltage difference between the word line of the memory layer and the semiconductor layer 200 is increased, and the erase efficiency is enhanced.
It is understood that the voltage value of the compensation voltage can be adjusted according to practical situations without departing from the teachings of the present application, for example, according to the design of the peripheral circuit of the non-volatile memory, and the like, and the present application does not limit the present application.
In one embodiment of the present application, the difference between the voltage value of the compensation voltage and the first bias voltage may be, for example, (0V, 3V) — however, it is understood that the magnitude of the difference between the voltage value of the compensation voltage and the first bias voltage may be determined according to the capability of voltage switching of the nonvolatile memory device and the capability of the peripheral circuit, and the present application does not limit this.
In one embodiment of the present application, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is decreased from the compensation voltage to the first bias voltage. The data erase efficiency can be improved by performing the data erase on the memory block BLK in a manner of gradually reducing the voltage applied to the word line of the memory layer.
In one embodiment of the present application, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is to be increased after decreasing from the compensation voltage to the first bias voltage. Wherein, the voltage value of the maximum voltage applied in the increment phase can be less than or equal to the compensation voltage. After the voltage applied to the word line of the memory layer is decreased to the first bias voltage, the voltage applied to the word line of the memory layer is increased, so that the voltage difference between the channel structure 220 and the semiconductor layer 200 can be reduced after the data erase operation, and the over-deep erase condition can be reduced.
In one embodiment of the present application, during the time that the erase voltage is applied, the word line connected to the top redundancy transistor TRT (i.e., the top redundancy word line TRL) and the word line connected to the bottom redundancy transistor BRT (i.e., the bottom redundancy word line BRL) float. It will be understood that when an element (or component, assembly, member, etc.) is referred to as being floating, it is intended to mean that the element (or component, assembly, member, etc.) does not form an electrical pathway with other elements (or components, assemblies, members, etc.).
In one embodiment of the present application, during the time when the erase voltage is applied, a word line connected to the top select transistor TST (i.e., the top select word line TSL) and a word line connected to the bottom select transistor BST (i.e., the bottom select word line BSL) float.
A process of applying the compensation voltage and the first bias voltage to the word line of the at least one memory layer, which is mentioned in the embodiments of the present application, is exemplified below.
Fig. 6 to 14 are voltage waveform diagrams of the nonvolatile memory device 10 according to the embodiment of the present application. It should be understood that fig. 6 to 6In the embodiment shown in fig. 14, the peripheral circuitry 120 is configured to: applying an erase voltage V to the source (i.e., well) region of a memory string erase And floats a word line connected to the top redundancy transistor TRT (i.e., top redundancy word line TRL), a word line connected to the bottom redundancy transistor BRT (i.e., bottom redundancy word line BRL), a word line connected to the top select transistor TST (i.e., top select word line TSL), and a word line connected to the bottom select transistor BST (i.e., bottom select word line BSL).
In one embodiment of the present application, a voltage waveform of the nonvolatile memory device 10 is as shown in fig. 6. As shown in fig. 6, the peripheral circuitry 120 is further configured to: when applying an erase voltage V erase Sequentially applying a compensation voltage V to the word lines WL of at least one memory layer offset And a first bias voltage V bias1 . Compensation voltage V applied to word line WL of each memory layer offset The voltage values of (a) may be the same.
It is understood that the first bias voltage V applied by the non-volatile memory device 10 to the word lines WL of each memory layer is not departing from the teachings of the present application bias1 The voltage values of (a) may be the same or different.
In still another embodiment of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, wherein a memory region near the source is the first memory region. The voltage waveform of the nonvolatile memory device 10 is shown in fig. 7. As shown in fig. 7, the peripheral circuit 120 is configured to: when applying an erase voltage V erase To the word line WL of the memory layer of the first memory area q1 Applying compensating voltages V in sequence offset And a first bias voltage V bias1 And to word lines WL of memory layers of memory regions other than the first memory region q3 Applying a second bias voltage V bias2 。
It should be appreciated that the second bias voltage V may be applied without departing from the teachings of the present application bias2 Which may be, for example, a low voltage that causes data stored by the storage layer of the other storage region to be stored. Illustratively, the second bias voltage may be, for example, [0V, 1V ]]Such as ground voltage 0V, for which the present application is not intendedAnd (4) making a limitation.
It should be understood that the number of memory layers in the first memory region and the number of memory layers in the other memory regions may be set according to the structure, size, etc. of the channel structure 220 in the nonvolatile memory device 10 without departing from the teachings of the present application, and the present application is not limited thereto.
It should be appreciated that the first bias voltage V may be applied without departing from the teachings of the present application bias1 And a second bias voltage V bias2 The voltages may be the same or different, and the application is not limited thereto.
In another embodiment of the present application, the peripheral circuit 120 is configured to: when applying an erase voltage V erase A plurality of compensation voltages and first bias voltages having different voltage values are sequentially applied to the word lines WL of at least one memory layer.
As one example, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is to decrease from the compensation voltage to the first bias voltage. For example, a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 8. The peripheral circuit 120 is configured to: at an erase voltage V erase To the word line WL of the memory layer of the first memory area in different sequential segments of the duration of q1 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 . Optionally, the peripheral circuitry 120 is further configured to: at the application of an erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 . The data erase efficiency can be improved by performing the data erase on the memory block BLK in a manner of gradually reducing the voltage applied to the word line of the memory layer.
Alternatively, the voltage value of the compensation voltage applied to the word lines WL of the respective memory layers of the first memory region is the same in the respective timing sections.
Optionally, a first bias voltage V is applied to the word lines WL of the memory layers of the first memory region bias1 The voltage values of (a) may be the same.
It should be understood that fig. 8 sequentially applies 2 compensation voltages (V) having different voltage values to the word lines WL of at least one memory layer offset1 And V offset2 ) For example, 3 or more than 3 compensation voltages with different voltage values can be applied without departing from the teachings of the present application, which is not limited in the present application.
As another example, the change tendency of the voltage values of the plurality of different voltages applied in sequence is to increase after decreasing from the compensation voltage to the first bias voltage. For example, a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 9. The peripheral circuit 120 is configured to: at an erase voltage V erase To the word line WL of the memory layer of the first memory area in different sequential segments of the duration of q1 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 A first bias voltage V bias1 And a third bias voltage V bias2 . Optionally, the peripheral circuitry 120 is further configured to: when applying an erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 . Wherein the maximum voltage applied in the increasing stage has a voltage value less than or equal to the compensation voltage, i.e. V bias3 ≤V offset1 . After the voltage applied to the word line of the memory layer is decreased to the first bias voltage, the voltage applied to the word line of the memory layer is increased, so that the voltage difference between the channel structure 220 and the semiconductor layer 200 can be reduced after the data erase operation, and the over-deep erase condition can be reduced.
Alternatively, the voltage value of the compensation voltage applied to the word lines WL of the respective memory layers of the first memory region is the same in the respective timing sections.
Optionally, a first bias voltage V is applied to the word lines WL of the memory layers of the first memory region bias1 The voltage values of (a) may be the same.
It should be understood that fig. 9 sequentially applies 2 compensation voltages (V) having different voltage values to the word lines WL of at least one memory layer offset1 And V offset2 ) The increasing phase including a third bias voltageV bias3 For example, 3 or more than 3 compensation voltages with different voltage values may be applied, or more than 3 bias voltages with different voltage values may be applied in the incremental step without departing from the teachings of the present application, and the present application is not limited thereto.
In another embodiment of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the compensation voltage and the first bias voltage are applied to the word lines WL of the memory layers of at least two memory regions, and the voltage values of the applied compensation voltages are different. It should be understood that the number of word lines of the memory layer of each memory block may be the same or different, and the present application is not limited thereto.
For example, the storage layer of the block BLK may be divided into 3 storage areas, respectively: a storage region 1, a storage region 2 and a storage region 3, the storage region 1 and the storage region 2 being the first storage region near the source. Fig. 10 shows a voltage waveform diagram of the nonvolatile memory device 10 in which the voltage value of the compensation voltage applied to the word line WL in the same memory layer is constant. The peripheral circuit 120 is configured to: when applying an erase voltage V erase To the word line WL of the memory area 1 q1 Applying a first compensation voltage V offset1 And a first bias voltage V bias1 Word line WL to memory area 2 q2 Applying a third compensation voltage V offset3 And a first bias voltage V bias1 。V offset1 And V offset3 Different. Illustratively, the memory string MS includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein a voltage value of the compensation voltage applied to the word line of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation. In this example, the transverse dimension of the storage region 1 is smaller than the transverse dimension, V, of the storage region 2 offset1 ＞V offset3 . The compensation voltage applied to the word line WL of the memory layer having a large lateral size of the channel structure 220 is smaller, and the compensation voltage applied to the word line WL of the memory layer having a small lateral size of the channel structure 220 is largerSo that data erasure of the respective memory layers is more uniform.
Optionally, the peripheral circuitry 120 is further configured to: when applying an erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 。
As another example, the storage layer of the storage block BLK may be divided into 3 storage areas, which are: a storage region 1, a storage region 2 and a storage region 3, the storage region 1 and the storage region 2 being the first storage region near the source. A plurality of offset voltages having different voltage values are applied to the word lines WL in the same memory layer, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 11. The peripheral circuit 120 is configured to: at the application of an erase voltage V erase To the word line WL of the memory area 1 q1 Applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 To the word line WL of the storage area 2 q2 Applying a third compensation voltage V offset3 A fourth compensation voltage V offset4 And a first bias voltage V bias1 。V offset1 And V offset2 、V offset3 Of different voltage values of V offset3 And V offset4 The voltage values of (a) are different. Optionally, the peripheral circuitry 120 is further configured to: when applying an erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 。
Alternatively, the voltage values of the first bias voltages applied to the word lines WL of the respective memory layers of the first memory region may be the same or different. This is not limited by the present application.
It should be understood that fig. 10 and fig. 11 exemplify the division of the storage layer of the storage block BLK into 3 storage areas, and may also be divided into 4 or more than 4 storage areas without departing from the teachings of the present application, which is not limited by the present application.
It is understood that the number of word lines WL for each memory region may be the same or different without departing from the teachings of the present application, and the present application is not limited thereto.
In one embodiment of the present application, the range of values of the difference between the voltage values of the compensation voltages applied to the word lines WL of the first storage region may be, for example, [0V, 3V ].
In one embodiment of the present application, a voltage value of the compensation voltage applied to the word line WL of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation. For example, the channel structure 220 at the storage region 1 has a smaller dimension in the x direction (hereinafter referred to as a lateral dimension), the channel structure 220 at the storage region 2 has a larger lateral dimension, and V offset1 ＞V offset3 。
Illustratively, in general, the lateral dimension of the channel structure 220 is large away from the semiconductor layer 200 and the lateral dimension of the channel structure 220 is small near the semiconductor layer 200. Due to the difference in the lateral dimensions of the channel structures 220, the electric field strength from the memory cell MC at different channel structures 220 may be different. For example, the electric field intensity of the memory cell MC with the large lateral dimension of the included channel structure 220 is smaller, and the electric field intensity of the memory cell MC with the small lateral dimension of the included channel structure 220 is larger. For the data erase operation of the memory block BLK, it is usually necessary to erase data of all memory cells MC of the whole memory block BLK, so that the memory layer partition of the memory block BLK can be controlled, i.e. the memory cells MC are partitioned. The compensation voltage applied to the word line WL of the memory layer having a large lateral size of the channel structure 220 is smaller, and the compensation voltage applied to the word line WL of the memory layer having a small lateral size of the channel structure 220 is larger, so that data erasure of the respective memory layers is more uniform.
In still another embodiment of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the word lines WL of the memory layers of at least two memory regions are applied with the compensation voltage and the first bias voltage, and the lengths of time for which the first bias voltage is applied are different. It should be understood that the number of word lines of the memory layer of each memory block may be the same or different, and the present application is not limited thereto.
The following storage layer in terms of a storage block BLK may be divided into 3 storage areas: the storage region 1, the storage region 2, and the storage region 3, the storage region 1 and the storage region 2 being the first storage region near the source are exemplified.
For example, a compensation voltage is applied to the word line WL of the memory layer of the first memory area, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 12. The peripheral circuit 120 is configured to: when applying an erase voltage V erase To the word line WL of the memory area 1 q1 And word line WL of memory area 2 q2 Applying a compensation voltage V offset And a first bias voltage V bias1 Applying a second bias voltage V to the word line of the memory area 3 bias2 . Wherein the peripheral circuit 120 is connected to the word line WL of the memory area 1 q1 And word line WL of memory area 2 q2 A first bias voltage V applied bias1 Respectively, is t 1 And t 2 . Illustratively, the memory string includes a channel structure, the memory cell including a control gate and a portion of the channel structure surrounded by the control gate; wherein the length of time that the word line of the memory layer is applied with the first bias voltage is in positive correlation with the dimension of the channel structure surrounded by the control gate in a section parallel to the memory layer, in this example, the lateral dimension of the memory region 1 is smaller than the lateral dimension of the memory region 2, t 1 ＜t 2 . The first bias voltage is applied for a longer time for the word line WL of the memory layer having a large lateral size of the channel structure 220, and the first bias voltage is applied for a shorter time for the word line WL of the memory layer having a small lateral size of the channel structure 220, so that data erasure of the respective memory layers is more uniform.
For another example, a plurality of compensation voltages having different voltage values are applied to the word line WL in the memory layer of the first memory area, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 13. The peripheral circuit 120 is configured to: when applying an erase voltage V erase To the word line WL of the memory area 1 q1 And word line WL of memory area 2 q2 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 Applying a second bias voltage V to the word line of the memory area 3 bias2 . Wherein, the word line WL to the memory area 1 q1 And word line WL of memory area 2 q2 The time lengths of the applied first bias voltages are t 1 And t 2 ，t 1 ＜t 2 . Word line WL to memory region 1 q1 And word line WL of storage area 2 q2 The lengths of time for applying the first compensation voltage and the second compensation voltage may be the same or different, and the example of different lengths of time is described here.
For another example, a plurality of offset voltages having different voltage values are applied to the word lines WL of the memory layers of at least two memory areas, and the voltage values applied to the word lines WL of the memory layers of different memory areas are different, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 14. When applying an erase voltage V erase For a time period, the peripheral circuit 120 is configured to: when applying an erase voltage V erase To the word line WL of the memory area 1 q1 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 Word line WL to memory area 2 q2 Sequentially applying a third compensation voltage V offset3 A fourth compensation voltage V offset4 And a first bias voltage V bias1 Applying a second bias voltage V to the word line of the memory area 3 bias2 。V offset1 And V offset2 、V offset3 Of different voltage values of V offset3 And V offset4 The voltage values of (a) are different. Word line WL to memory region 1 q1 And word line WL of memory area 2 q2 The time lengths of the applied first bias voltages are t 1 And t 2 ，t 1 ＜t 2 。
It should be understood that, for convenience of understanding, the embodiment of the present application is exemplified by the case where the voltage values of the first bias voltages applied to the word lines WL of the memory layers of the respective first memory regions are the same, and in other embodiments, the voltage values of the first bias voltages applied to the word lines WL of the memory layers of the respective first memory regions may be different.
Alternatively, the voltage values of the compensation voltages applied to the word lines WL of the respective memory layers of the first memory region may be the same or different. If the voltage values of the compensation voltages applied to the word lines WL of the respective memory layers are different, the difference range of the voltage values may be, for example, (0V, 3V).
It should be understood that fig. 12, 13 and 14 illustrate the storage layer of the memory block BLK being divided into 3 storage areas, and may also be divided into 4 or more than 4 storage areas without departing from the teachings of the present application, and the present application is not limited thereto.
It is understood that the number of word lines WL for each memory region may be the same or different without departing from the teachings of the present application, and the present application is not limited thereto.
In one embodiment of the present application, a length of time that the word line WL of the memory layer is applied with the first bias voltage has a positive correlation with a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer. For example, the lateral dimension of the channel structure 220 at storage region 1 is smaller, the lateral dimension of the channel structure 220 at storage region 2 is larger, t 1 ＜t 2 。
Illustratively, in general, the lateral dimension of the channel structure 220 is large away from the semiconductor layer 200 and the dimension of the channel structure 220 is small near the semiconductor layer 200. Due to the difference in lateral dimensions of the channel structures 220, the data erase speed of the memory cells MC at different channel structures 220 may be different. For example, the data erasing speed of the memory cell MC with the large lateral dimension of the included channel structure 220 is slow, and the data erasing speed of the memory cell MC with the small lateral dimension of the included channel structure 220 is fast. For the data erase operation of the memory block BLK, it is usually necessary to erase data of all memory cells MC of the whole memory block BLK, so that the memory layer partition of the memory block BLK can be controlled, i.e. the memory cells MC are partitioned. The first bias voltage is applied for a longer time for the word line WL of the memory layer having a large lateral size of the channel structure 220, and the first bias voltage is applied for a shorter time for the word line WL of the memory layer having a small lateral size of the channel structure 220, so that data erasure of the respective memory layers is more uniform.
Fig. 15 is a flowchart of a data erasing method 3000 of a nonvolatile memory device according to an embodiment of the present application. Referring to fig. 2, the memory device includes a memory block MLK having a plurality of memory strings MS connected between a bit line BL and a source and including a plurality of memory cells MC connected in series, the memory cells MC of the same memory layer being connected to the same word line. As shown in fig. 15, for a memory block MLK to be erased, the present application provides a data erasing method 3000 of a nonvolatile memory device, including:
s31, an erase voltage is applied to the source.
S32, sequentially applying a plurality of different voltages to the word line of at least one storage layer during the time when the erase voltage is applied. The plurality of different voltages at least comprise a first bias voltage and a compensation voltage with a voltage value larger than the first bias voltage.
According to the embodiment of the application, in the process of applying the erasing voltage, the compensation voltage with a larger voltage value is applied to the word line of the storage layer so as to reduce the electric field intensity at the channel structure, reduce the pressure on the storage layer, reduce the breakdown condition, further reduce the probability of programming failure or erasing failure, and improve DPPM.
In one embodiment of the present application, a plurality of different voltages may be sequentially applied to the word lines WL of the memory layer while applying an erase voltage to the source (e.g., the well region of the semiconductor layer 200) of the memory strings MS.
It is understood that, without departing from the teachings of the present application, considering that a certain time is required for the voltage of the semiconductor layer 200 to rise, a plurality of different voltages may be sequentially applied to the word lines WL of the memory layer within a preset time after the erase voltage is applied to the source (e.g., the well region of the semiconductor layer 200) of the memory strings MS, wherein the preset time may be in the order of milliseconds or seconds, for example. This is not limited by the present application.
In one embodiment of the present application, a voltage value of the first bias voltage is equal to or greater than 0V and equal to or less than 1V to improve a data erasing speed.
In one embodiment of the present application, the compensation voltage has a voltage value greater than the first bias voltage and less than the erase voltage V erase . Illustratively, the voltage value range of the compensation voltage is (0V, 3V)]Or the voltage value range of the compensation voltage is [1V, 3V ]]. By applying the compensation voltage to the word line WL of the memory layer, the voltage difference between the word line WL of the memory layer and the semiconductor layer 200 is reduced, and damage of the nonvolatile memory device due to a large voltage difference applied to the memory layer at the initial stage of data erase can be reduced. After the compensation voltage is applied, the first bias voltage having a smaller voltage value is applied, so that a voltage difference between the word line WL of the memory layer and the semiconductor layer 200 is increased, and the erase efficiency is enhanced.
It is understood that the voltage value of the compensation voltage can be adjusted according to practical situations without departing from the teachings of the present application, for example, according to the design of the peripheral circuit of the non-volatile memory, and the like, and the present application does not limit the present application.
In one embodiment of the present application, the difference between the voltage value of the compensation voltage and the first bias voltage may be, for example, (0V, 3V) — however, it is understood that the magnitude of the difference between the voltage value of the compensation voltage and the first bias voltage may be determined according to the capability of voltage switching of the nonvolatile memory device and the capability of the peripheral circuit, and the present application does not limit this.
In one embodiment of the present application, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is decreased from the compensation voltage to the first bias voltage. The data erase efficiency can be improved by performing the data erase on the memory block BLK in a manner of gradually reducing the voltage applied to the word line WL of the memory layer.
In one embodiment of the present application, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is to be increased after decreasing from the compensation voltage to the first bias voltage. Wherein, the voltage value of the maximum voltage applied in the increment phase can be less than or equal to the compensation voltage. After the voltage applied to the word line WL of the memory layer is decreased to the first bias voltage and then increased, the voltage applied to the word line WL of the memory layer may decrease the voltage difference between the channel structure 220 and the semiconductor layer 200 at the later stage of the data erase operation, thereby reducing the over-deep erase.
In one embodiment of the present application, during the time that the erase voltage is applied, the word line connected to the top redundancy transistor TRT (i.e., the top redundancy word line TRL) and the word line connected to the bottom redundancy transistor BRT (i.e., the bottom redundancy word line BRL) float.
In one embodiment of the present application, during the time when the erase voltage is applied, the word line connected to the top select transistor TST (i.e., the top select word line TSL) and the bottom select transistor BST (i.e., the bottom select word line BSL) float.
A process of applying the compensation voltage and the first bias voltage to the word line of the at least one memory layer, which is mentioned in the embodiments of the present application, is exemplified below.
Fig. 6 to 14 are voltage waveform diagrams of the nonvolatile memory device 10 according to the embodiment of the present application. It should be understood that in the embodiments shown in fig. 6-14, the non-volatile memory device 10 applies the erase voltage V to the source (i.e., well region) of the memory string erase And floats a word line connected to the top redundancy transistor TRT (i.e., the top redundancy word line TRL), a word line connected to the bottom redundancy transistor BRT (i.e., the bottom redundancy word line BRL), a word line connected to the top selection transistor TST (i.e., the top selection word line TSL), and a word line connected to the bottom selection transistor BST (i.e., the bottom selection word line BSL).
Voltage waveform diagram of nonvolatile memory device 10 in one embodiment of the present application referring to fig. 6, the nonvolatile memory device 10 applies an erase voltage V erase Sequentially applying a compensation voltage V to the word lines WL of at least one memory layer offset And a first bias voltage V bias1 . Compensation voltage V applied to word line WL of each memory layer offset The voltage values of (a) may be the same.
It is understood that the first bias voltage V applied by the non-volatile memory device 10 to the word lines WL of each memory layer is not departing from the teachings of the present application bias1 The voltage values of (a) may be the same or different.
In still another embodiment of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, wherein a memory region near the source is the first memory region. A voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 7. Non-volatile memory device 10 applying erase voltage V erase To the word line WL of the memory layer of the first memory area q1 Applying compensating voltages V in sequence offset And a first bias voltage V bias1 And to word lines WL of memory layers of memory regions other than the first memory region q3 Applying a second bias voltage V bias2 。
It should be appreciated that the second bias voltage V may be applied without departing from the teachings of the present application bias2 Which may be, for example, a low voltage that causes data stored by the storage layer of the other storage region to be stored. Illustratively, the second bias voltage may be, for example, [0V, 1V ]]Such as ground voltage 0V, which is not a limitation of the present application.
It is to be understood that the number of layers of the memory layer in the first memory region and the number of layers of the memory layers of the other memory regions may be set according to the structure, size, etc. of the channel structure 220 in the nonvolatile memory device 10 without departing from the teachings of the present application, and the present application is not limited thereto.
It is understood that the first bias voltage and the second bias voltage may be the same or different in voltage magnitude without departing from the teachings of the present application, which is not limited in this application.
In another embodiment of the present application, the nonvolatile memory device 10 applies the erase voltage V erase A plurality of compensation voltages and first bias voltages having different voltage values are sequentially applied to the word lines WL of at least one memory layer.
As one example, a variation tendency of the voltage values of the plurality of different voltages applied in sequence is to decrease from the compensation voltage to the first bias voltage. For example, a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 8. Non-volatile memory device 10 at erase voltage V erase To the first memory area in different sequential segments of the duration ofWord line WL of the memory layer q1 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 . Alternatively, non-volatile memory device 10 applies erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 . The data erase efficiency can be improved by performing the data erase on the memory block BLK in a manner of gradually reducing the voltage applied to the word line of the memory layer.
Alternatively, the voltage value of the compensation voltage applied to the word lines WL of the respective memory layers of the first memory region is the same in the respective timing sections.
Alternatively, the voltage value of the first bias voltage applied to the word lines WL of the respective memory layers of the first memory region may also be the same.
It should be understood that fig. 8 sequentially applies 2 compensation voltages (V) having different voltage values to the word lines WL of at least one memory layer offset1 And V offset2 ) For example, 3 or more than 3 compensation voltages with different voltage values can be applied without departing from the teachings of the present application, and the present application is not limited thereto.
As another example, the change tendency of the voltage values of the plurality of different voltages applied in sequence is to increase after decreasing from the compensation voltage to the first bias voltage. For example, a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 9. The peripheral circuitry 120 is configured to: at an erase voltage V erase To the word line WL of the memory layer of the first memory area in different sequential segments of the duration of q1 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 A first bias voltage V bias1 And a third bias voltage V bias2 . Optionally, the peripheral circuitry 120 is further configured to: at the application of an erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 . Wherein the maximum voltage applied in the increasing stage has a voltage value less thanAt a compensation voltage, i.e. V bias3 ≤V offset1 . After the voltage applied to the word line of the memory layer is decreased to the first bias voltage, the voltage applied to the word line of the memory layer is increased, so that the voltage difference between the channel structure 220 and the semiconductor layer 200 can be reduced after the data erase operation, and the over-deep erase condition can be reduced.
Alternatively, the voltage value of the compensation voltage applied to the word lines WL of the respective memory layers of the first memory region is the same in the respective timing sections.
Optionally, a first bias voltage V is applied to the word lines WL of the memory layers of the first memory region bias1 The voltage values of (a) may be the same.
It should be understood that fig. 9 sequentially applies 2 compensation voltages (V) having different voltage values to the word lines WL of at least one memory layer offset1 And V offset2 ) The increment phase comprises a third bias voltage V bias3 For example, 3 or more than 3 compensation voltages with different voltage values may be applied, or more than 3 bias voltages with different voltage values may be applied in the incremental step without departing from the teachings of the present application, and the present application is not limited thereto.
In another embodiment of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the compensation voltage and the first bias voltage are applied to the word lines WL of the memory layers of at least two memory regions, and the voltage values of the applied compensation voltages are different. It should be understood that the number of word lines of the memory layer of each memory block may be the same or different, and the present application is not limited thereto.
For example, the storage layer of the block BLK may be divided into 3 storage areas, respectively: a storage region 1, a storage region 2 and a storage region 3, the storage region 1 and the storage region 2 being the first storage region near the source of the memory string MS. The voltage value of the compensation voltage applied to the word line WL of the same memory layer is not changed, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 10. Non-volatile memory device 10 applying erase voltage V erase To the word line WL of the memory area 1 q1 Applying a first compensation voltage V offset1 And a first bias voltage V bias1 Word line WL to memory area 2 q2 Applying a third compensation voltage V offset3 And a first bias voltage V bias1 。V offset1 And V offset3 Different. Illustratively, the memory string MS includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein a voltage value of the compensation voltage applied to the word line of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation. In this example, the transverse dimension of the storage region 1 is smaller than the transverse dimension, V, of the storage region 2 offset1 ＞V offset3 . The compensation voltage applied to the word line WL of the memory layer having a large lateral size of the channel structure 220 is smaller, and the compensation voltage applied to the word line WL of the memory layer having a small lateral size of the channel structure 220 is larger, so that data erasure of the respective memory layers is more uniform.
Alternatively, non-volatile memory device 10 applies erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 。
As another example, the storage layer of the storage block BLK may be divided into 3 storage areas, which are: memory region 1, memory region 2 and memory region 3, memory region 1 and memory region 2 being the first memory region near the source of memory string MS. A plurality of compensation voltages having different voltage values are applied to the word lines WL in the same memory layer, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 11. Non-volatile memory device 10 applying erase voltage V erase To the word line WL of the memory area 1 q1 Applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 Word line WL to memory area 2 q2 Applying a third compensation voltage V offset3 Fourth compensation voltage V offset4 And a first bias voltage V bias1 。V offset1 And V offset2 、V offset3 Of different voltage values of V offset3 And V offset4 The voltage values of (a) are different. Alternatively, non-volatile memory device 10 applies erase voltage V erase To the word line WL of the memory layer of the memory region other than the first memory region q3 Applying a second bias voltage V bias2 。
Alternatively, the voltage values of the first bias voltages applied to the word lines WL of the respective memory layers of the first memory region may be the same or different. This is not limited by the present application.
It should be understood that fig. 10 and 11 illustrate the storage layer of the memory block BLK being divided into 3 storage areas, and may also be divided into 4 or more than 4 storage areas without departing from the teachings of the present application, and the present application is not limited thereto.
It is understood that the number of word lines WL for each memory region may be the same or different without departing from the teachings of the present application, and the present application is not limited thereto.
In one embodiment of the present application, the range of values of the difference between the voltage values of the compensation voltages applied to the word lines WL of the respective memory areas of the first memory area may be, for example, [0V, 3V ].
In one embodiment of the present application, a voltage value of the compensation voltage applied to the word line WL of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation. For example, the channel structure 220 at the storage region 1 has a smaller dimension in the x direction (hereinafter referred to as a lateral dimension), the channel structure 220 at the storage region 2 has a larger lateral dimension, and V offset1 ＞V offset3 。
Illustratively, in general, the lateral dimension of the channel structure 220 is large away from the semiconductor layer 200 and the lateral dimension of the channel structure 220 is small near the semiconductor layer 200. Due to the difference in the lateral dimensions of the channel structures 220, the electric field strength at the beginning of the memory cell MC may be different at different channel structures 220. For example, the electric field intensity of the memory cell MC with the large lateral dimension of the included channel structure 220 is smaller, and the electric field intensity of the memory cell MC with the small lateral dimension of the included channel structure 220 is larger. For the data erase operation of the memory block BLK, it is usually necessary to erase data of all memory cells MC of the whole memory block BLK, so that the memory layer partition of the memory block BLK can be controlled, i.e. the memory cells MC are partitioned. The compensation voltage applied to the word line WL of the memory layer having a large lateral size of the channel structure 220 is smaller, and the compensation voltage applied to the word line WL of the memory layer having a small lateral size of the channel structure 220 is larger, so that data erasure of the respective memory layers is more uniform.
In still another embodiment of the present application, the plurality of memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the compensation voltage and the first bias voltage are applied to the word lines WL of the memory layers of at least two memory regions, and the voltage values of the applied compensation voltages are different. It should be understood that the number of word lines of the memory layer of each memory block may be the same or different, and the present application is not limited thereto.
The following storage layer in terms of a storage block BLK may be divided into 3 storage areas: the memory region 1, the memory region 2, and the memory region 3, the memory region 1 and the memory region 2 being the first memory region near the source of the memory string MS are exemplified for illustration.
For example, a compensation voltage is applied to the word line WL of the storage layer of the first storage region, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 12. Non-volatile memory device 10 applying erase voltage V erase To the word line WL of the memory area 1 q1 And word line WL of memory area 2 q2 Applying a compensation voltage V offset And a first bias voltage V bias1 Applying a second bias voltage V to the word line of the memory area 3 bias2 . Wherein the nonvolatile memory device 10 is connected to the word line WL of the memory area 1 q1 And word line WL of memory area 2 q2 Applied first bias voltage V bias1 Respectively, is t 1 And t 2 . Illustratively, the memory string includes a channel structure, the memory cell including a control gate and a portion of the channel structure surrounded by the control gate; wherein the word line of the memory layer is applied with a first bias voltage for a time length and channel junctionThe portions of the structure surrounded by the control gate have a positive correlation with a dimension parallel to the cross-section of the memory layer, in this example the lateral dimension of the memory region 1 is smaller than the lateral dimension of the memory region 2, t 1 ＜t 2 . The first bias voltage is applied for a longer time for the word line WL of the memory layer having a large lateral size of the channel structure 220, and the first bias voltage is applied for a shorter time for the word line WL of the memory layer having a small lateral size of the channel structure 220, so that data erasure of the respective memory layers is more uniform.
For another example, a plurality of compensation voltages having different voltage values are applied to the word line WL of the memory layer of the first memory area, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 13. Non-volatile memory device 10 applying erase voltage V erase To the word line WL of the memory area 1 q1 And word line WL of storage area 2 q2 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 Applying a second bias voltage V to the word line of the memory area 3 bias2 . Wherein, the word line WL to the memory area 1 q1 And word line WL of memory area 2 q2 The time lengths of the applied first bias voltages are t 1 And t 2 ，t 1 ＜t 2 . Word line WL to memory region 1 q1 And word line WL of memory area 2 q2 The lengths of time for applying the first compensation voltage and the second compensation voltage may be the same or different, and the example of different lengths of time is described here.
For another example, a plurality of offset voltages having different voltage values are applied to the word lines WL of the memory layers of at least two memory areas, and the voltage values applied to the word lines WL of the memory layers of different memory areas are different, and a voltage waveform diagram of the nonvolatile memory device 10 is shown in fig. 14. Non-volatile memory device 10 applying erase voltage V erase To the word line WL of the memory area 1 q1 Sequentially applying a first compensation voltage V offset1 A second compensation voltage V offset2 And a first bias voltage V bias1 Word line WL to memory area 2 q2 Sequentially applying a third compensation voltage V offset3 The first stepFour compensation voltages V offset4 And a first bias voltage V bias1 Applying a second bias voltage V to the word line of the memory area 3 bias2 。V offset1 And V offset2 、V offset3 Of different voltage values of V offset3 And V offset4 The voltage values of (a) are different. Word line WL to memory region 1 q1 And word line WL of memory area 2 q2 The time lengths of the applied first bias voltages are t 1 And t 2 ，t 1 ＜t 2 。
It should be understood that, for convenience of understanding, the embodiment of the present application is exemplified by the case where the voltage values of the first bias voltages applied to the word lines WL of the memory layers of the respective first memory regions are the same, and in other embodiments, the voltage values of the first bias voltages applied to the word lines WL of the memory layers of the respective first memory regions may be different. This is not limited by the present application.
Alternatively, the voltage values of the compensation voltages applied to the word lines WL of the respective memory layers of the first memory region may be the same or different. If the voltage values of the compensation voltages applied to the word lines WL of the respective memory layers are different, the difference range of the voltage values may be, for example, (0V, 3V).
It should be understood that fig. 12, 13 and 14 illustrate the storage layer of the memory block BLK being divided into 3 storage areas, and may also be divided into 4 or more than 4 storage areas without departing from the teachings of the present application, and the present application is not limited thereto.
It is understood that the number of word lines WL for each memory region may be the same or different without departing from the teachings of the present application, and the present application is not limited thereto.
In one embodiment of the present application, a length of time that the word line WL of the memory layer is applied with the first bias voltage has a positive correlation with a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer. For example, the lateral dimension of the channel structure 220 at storage region 1 is smaller, the lateral dimension of the channel structure 220 at storage region 2 is larger, t 1 ＜t 2 。
Illustratively, in general, the lateral dimension of the channel structure 220 is large away from the semiconductor layer 200 and the dimension of the channel structure 220 is small near the semiconductor layer 200. Due to the difference in lateral dimensions of the channel structures 220, the data erase speed of the memory cells MC at different channel structures 220 may be different. For example, the data erasing speed of the memory cell MC with the large lateral dimension of the included channel structure 220 is slow, and the data erasing speed of the memory cell MC with the small lateral dimension of the included channel structure 220 is fast. For the data erase operation of the memory block BLK, it is usually necessary to erase data of all memory cells MC of the whole memory block BLK, so that the memory layer partition of the memory block BLK can be controlled, i.e. the memory cells MC are partitioned. The first bias voltage is applied for a longer time for the word line WL of the memory layer having a large lateral size of the channel structure 220, and the first bias voltage is applied for a shorter time for the word line WL of the memory layer having a small lateral size of the channel structure 220, so that data erasure of the respective memory layers is more uniform.
Fig. 16 is a block diagram of a non-volatile storage system according to an embodiment of the present application. As shown in fig. 16, the nonvolatile memory system 40 includes the nonvolatile memory device 10 and a controller 41.
The memory device 10 may be the same as the non-volatile memory device described in any of the above embodiments, and will not be described in detail herein.
The controller 41 may control the storage apparatus 10 through the channel CH, and the storage apparatus 10 may perform an operation based on the control of the controller 41 in response to a request from the host 50. The memory device 10 may receive a command CMD and an address ADDR from the controller 41 through a channel CH and access an area selected from the memory cell array in response to the address. In other words, the memory device 10 may perform an internal operation corresponding to the command on the area selected by the address. More specifically, the controller 41 transmits a command to execute the data erasing method 3000 described in any of the above embodiments and an address ADDR through the channel CH, causing the memory device 10 to execute the data erasing method 3000.
In the example shown in fig. 17, the controller 41 and the single nonvolatile memory device 10 may be integrated into a memory card. The memory card may include a PC card (PCMCIA, personal computer memory card international association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), and the like. The memory card may also include a memory card connector 42 that couples the memory card with the host 50.
In another example as shown in fig. 18, the controller 41 and the plurality of nonvolatile memory devices 10 may be integrated into a Solid State Drive (SSD). The solid state drive may also include an SSD connector 43 that couples the solid state drive with a host (not shown). In some embodiments, the storage capacity and/or operating speed of the solid state drive is higher than that of the memory card shown in fig. 17.
Although the structures of non-volatile memory device 10 and non-volatile memory system 40 are described herein, it will be appreciated that one or more features may be omitted, substituted, or added from non-volatile memory device 10 and non-volatile memory system 40.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (17)

1. A data erasing method of a nonvolatile memory device, wherein the memory device includes a memory block having a plurality of memory strings, each of the memory strings is connected between a bit line and a source electrode and includes a plurality of memory cells connected in series, and the memory cells of the same memory layer are connected to the same word line, the method comprising, for the memory block to be erased:
applying an erase voltage to the source, an
Sequentially applying a plurality of different voltages to word lines of at least one of the memory layers during the time when the erase voltage is applied,
wherein the plurality of different voltages at least include a first bias voltage, and a compensation voltage having a voltage value greater than the first bias voltage.
2. The method of claim 1, wherein a trend of a change in the voltage values of the plurality of different voltages applied in sequence is to decrease from the compensation voltage to the first bias voltage.
3. The method of claim 1, wherein the voltage values of the plurality of different voltages applied sequentially change in a trend of increasing after decreasing from the compensation voltage to the first bias voltage.
4. The method according to any one of claims 1 to 3, wherein a plurality of the storage layers are divided into a plurality of storage areas in a direction perpendicular to the storage layers;
sequentially applying a plurality of different voltages to a word line of at least one of the storage layers includes:
sequentially applying the plurality of different voltages to word lines of a memory layer of a first memory region adjacent to the source among the plurality of memory regions;
the method further comprises the following steps:
applying a second bias voltage to word lines of memory layers of the memory regions other than the first memory region, the second bias voltage being less than the compensation voltage.
5. The method according to any one of claims 1 to 3, wherein a plurality of the memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, the compensation voltage and the first bias voltage are applied to word lines of the memory layers of at least two of the memory regions, and voltage values of the applied compensation voltages are different.
6. The method of claim 5, wherein the memory string includes a channel structure, the memory cell including a control gate and a portion of the channel structure surrounded by the control gate;
wherein a voltage value of a compensation voltage applied to a word line of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation.
7. The method according to any one of claims 1 to 3, wherein a plurality of the memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, word lines of the memory layers of at least two of the memory regions are applied with the compensation voltage and the first bias voltage, and the lengths of time the first bias voltage is applied are different.
8. The method of claim 7, wherein the memory string includes a channel structure, the memory cell including a control gate and a portion of the channel structure surrounded by the control gate;
wherein a length of time that the word line of the storage layer is applied with the first bias voltage is in a positive correlation with a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the storage layer.
9. The method according to any one of claims 1 to 3, wherein the first bias voltage has a voltage value of 0V or more and 1V or less.
10. The method of any of claims 1-3, wherein the compensation voltage has a voltage value less than the erase voltage.
11. A non-volatile storage device, comprising:
the memory block comprises a plurality of memory strings, each memory string is connected between a bit line and a source electrode and comprises a plurality of memory cells connected in series, and the memory cells of the same memory layer are connected to the same word line;
peripheral circuitry coupled to the memory block and performing an erase operation on the memory cells in the memory block, the peripheral circuitry configured to:
applying an erase voltage to the source, an
Sequentially applying a plurality of different voltages to word lines of at least one of the memory layers during the time when the erase voltage is applied,
wherein the plurality of different voltages at least include a first bias voltage, and a compensation voltage having a voltage value greater than the first bias voltage.
12. The nonvolatile memory device according to claim 11, wherein a plurality of the memory layers are divided into a plurality of memory areas in a direction perpendicular to the memory layers;
the peripheral circuitry is configured to:
sequentially applying the plurality of different voltages to word lines of a memory layer of a first memory region adjacent to the source among the plurality of memory regions;
the peripheral circuitry is further configured to:
applying a second bias voltage to word lines of memory layers of the memory regions other than the first memory region, the second bias voltage being less than the compensation voltage.
13. The nonvolatile memory device according to claim 11, wherein a plurality of the memory layers are divided into a plurality of memory areas in a direction perpendicular to the memory layers, word lines of the memory layers of at least two of the memory areas are applied with the compensation voltage and the first bias voltage, and voltage values of the applied compensation voltages are different.
14. The non-volatile storage device of claim 13, wherein the memory string comprises a channel structure, the memory cells comprising control gates and portions of the channel structure surrounded by the control gates;
wherein a voltage value of a compensation voltage applied to a word line of the memory layer and a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the memory layer are in a negative correlation.
15. The nonvolatile memory device according to claim 11, wherein a plurality of the memory layers are divided into a plurality of memory regions in a direction perpendicular to the memory layers, word lines of the memory layers of at least two of the memory regions are applied with the compensation voltage and the first bias voltage, and lengths of time of the first bias voltage being applied are different.
16. The non-volatile storage device of claim 15, wherein the memory string comprises a channel structure, the memory cells comprising control gates and portions of the channel structure surrounded by the control gates;
wherein a length of time that the word line of the storage layer is applied with the first bias voltage is in a positive correlation with a dimension of a portion of the channel structure surrounded by the control gate in parallel with a cross section of the storage layer.
17. A non-volatile storage system, comprising:
a nonvolatile memory device including a memory block having a plurality of memory strings and a peripheral circuit coupled to the memory block, each of the memory strings being connected between a bit line and a source and including a plurality of memory cells connected in series, the memory cells of a same memory layer being connected to a same word line; and
a controller coupled to the storage device and configured to control the storage device;
wherein the peripheral circuitry is configured to:
applying an erase voltage to the source, an
And sequentially applying a plurality of different voltages to the word line of at least one storage layer within the time of applying the erasing voltage, wherein the plurality of different voltages at least comprise a first bias voltage and a compensation voltage with a voltage value larger than the first bias voltage.
CN202210480085.2A 2022-05-05 2022-05-05 Data erasing method, storage device and storage system Pending CN114822653A (en)

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