CN114822437A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114822437A CN114822437A CN202210406434.6A CN202210406434A CN114822437A CN 114822437 A CN114822437 A CN 114822437A CN 202210406434 A CN202210406434 A CN 202210406434A CN 114822437 A CN114822437 A CN 114822437A
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- film transistor
- control signal
- thin film
- demux
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
- G09G3/2025—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having all the same time duration
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
Abstract
The display panel and the display device provided by the embodiment of the application comprise a first scanning line group, a first DEMUX switch unit and a DEMUX control signal generating circuit, wherein the first scanning line group comprises at least two first scanning lines which are arranged at intervals along a first direction; the first DEMUX switch unit comprises a first scanning signal input port, at least two first DEMUX control signal input ports and at least two first scanning signal output ports; the DEMUX control signal generating circuit comprises at least two DEMUX control signal output ports; the DEMUX control signal generating circuit is used for sending a control signal to the first DEMUX switching unit, and the first DEMUX switching unit is used for controlling the connection or disconnection between the first scanning signal input port and the first scanning signal output port based on the control signal.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
Liquid crystal displays have the advantages of low radiation, small size, and low power consumption, and have gradually replaced conventional cathode ray tube displays and been widely used in flat panel televisions, personal computers, and mobile display panels.
Each sub-pixel in the existing liquid crystal display panel is controlled by one scan line and one data line. Therefore, for a liquid crystal display panel with resolution of M × N, M scan lines and N data lines need to be configured, wherein the output ports of the driving chips are connected with the scan lines in a one-to-one correspondence to form corresponding scan channels. In the driving method of cutting one frame image into a plurality of subfields, since the scanning time between each subfield is fixed, each subfield has the same number of scanning channels as the number of scanning lines at present, which causes the waste of the scanning channels.
Disclosure of Invention
An object of the embodiments of the present application is to provide a display panel and a display device, where the display panel can solve the problem of scan channel waste.
In one aspect, an embodiment of the present application provides a display panel, including: the DEMUX control circuit comprises a first scanning line group, a first DEMUX switch unit and a DEMUX control signal generating circuit, wherein the first scanning line group comprises at least two first scanning lines which are arranged at intervals along a first direction; the first DEMUX switch unit comprises a first scanning signal input port, at least two first DEMUX control signal input ports and at least two first scanning signal output ports; the DEMUX control signal generating circuit comprises at least two DEMUX control signal output ports; the at least two first DEMUX control signal input ports are electrically connected with the at least two DEMUX control signal output ports in a one-to-one corresponding mode, and the at least two first scanning signal output ports are electrically connected with the at least two first scanning lines arranged at intervals along the first direction in a one-to-one corresponding mode; the DEMUX control signal generating circuit is used for sending a control signal to the first DEMUX switch unit, and the first DEMUX switch unit is used for controlling the connection or disconnection between the first scanning signal input port and the first scanning signal output port based on the control signal.
Optionally, in some embodiments of the present application, the first DEMUX switch unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and an eighth thin film transistor; the gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor and the eighth thin film transistor are electrically connected with the eight DEMUX control signal output ports in a one-to-one correspondence manner; first electrodes of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, and the eighth thin film transistor are all electrically connected to the first scanning signal input port; second electrodes of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor and the eighth thin film transistor are electrically connected with eight first scanning lines in a one-to-one correspondence manner.
Optionally, in some embodiments of the present application, the DEMUX control signal generation circuit includes a first shunt control signal line, a second shunt control signal line, a third shunt control signal line, a fourth shunt control signal line, a fifth shunt control signal line, a sixth shunt control signal line, a seventh shunt control signal line, and an eighth shunt control signal line; the first shunt control signal line is electrically connected with a grid electrode of the first thin film transistor; the second shunt control signal line is electrically connected with the grid electrode of the second thin film transistor; the third shunt control signal line is electrically connected with a grid electrode of the third thin film transistor; the fourth shunt control signal line is electrically connected with a grid electrode of the fourth thin film transistor; the fifth branch control signal line is electrically connected with a grid electrode of the fifth thin film transistor; the sixth shunt control signal line is electrically connected with a gate of the sixth thin film transistor; the seventh shunt control signal line is electrically connected to a gate of the seventh thin film transistor; the eighth shunt control signal line is electrically connected to a gate of the eighth thin film transistor.
Optionally, in some embodiments of the present application, the display panel further includes a second scan line group, where the second scan line group includes at least two second scan lines arranged at intervals along the first direction; a second DEMUX switch unit including a second scan signal input port, at least two second DEMUX control signal input ports, and at least two second scan signal output ports; the at least two second DEMUX control signal input ports are electrically connected with the at least two second DEMUX control signal output ports in a one-to-one corresponding mode, and the at least two second scanning signal output ports are electrically connected with the at least two second scanning lines arranged at intervals along the first direction in a one-to-one corresponding mode; the DEMUX control signal generating circuit is further configured to send the control signal to the second DEMUX switch unit, and the second DEMUX switch unit is configured to control, based on the control signal, on or off between the second scanning signal input port and the second scanning signal output port.
Optionally, in some embodiments of the present application, the second DEMUX switching unit includes a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, and a sixteenth thin film transistor; first electrodes of the ninth thin film transistor, the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor and the sixteenth thin film transistor are all electrically connected with the second scan signal input port; second electrodes of the ninth thin film transistor, the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor and the sixteenth thin film transistor are electrically connected with eight second scanning lines in a one-to-one correspondence manner; the first shunt control signal line is electrically connected with a grid electrode of the ninth thin film transistor; the second shunt control signal line is electrically connected with a gate of the tenth thin film transistor; the third shunt control signal line is electrically connected with a gate of the eleventh thin film transistor; the fourth shunt control signal line is electrically connected with a grid electrode of the twelfth thin film transistor; the fifth branch control signal line is electrically connected with a grid electrode of the thirteenth thin film transistor; the sixth shunt control signal line is electrically connected with a gate of the fourteenth thin film transistor; the seventh shunt control signal line is electrically connected with a gate of the fifteenth thin film transistor; the eighth shunt control signal line is electrically connected to a gate of the sixteenth thin film transistor.
Optionally, in some embodiments of the present application, the display panel further includes a storage capacitor, one end of the storage capacitor is electrically connected to the first DEMUX switch unit, and the other end of the storage capacitor is connected to a ground terminal, and/or one end of the storage capacitor is electrically connected to the second DEMUX switch unit, and the other end of the storage capacitor is connected to the ground terminal.
Optionally, in some embodiments of the present application, the first to sixteenth thin film transistors are all transistors of the same type.
Optionally, in some embodiments of the present application, the control signal includes a first sub-control signal, a second sub-control signal, a third sub-control signal, a fourth sub-control signal, a fifth sub-control signal, a sixth sub-control signal, a seventh sub-control signal, and an eighth sub-control signal, wherein durations of active signals in the first sub-control signal, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal, and the eighth sub-control signal are equal.
Optionally, in some embodiments of the present application, intervals between the first sub-control signal, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal, and the eighth sub-control signal are equal.
In another aspect, the present application provides a display device, which includes a driving chip and the display panel as described above, wherein the driving chip is electrically connected to the display panel.
The application provides a display panel is through setting up first DEMUX switch element to make scanning signal output in grades, when guaranteeing normal display function, also can reduce the quantity of scanning passageway, and then solve the extravagant problem of scanning passageway.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate in a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a portion of a display panel according to a first embodiment of the present application;
fig. 3 is a timing diagram of driving a display panel according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a portion of a display panel according to a second embodiment of the present application;
FIG. 5 is a schematic circuit diagram of a portion of a display panel according to a third embodiment of the present application
Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a display panel and a display device, and provides the display panel and the display device. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms "first," "second," "third," and the like are used merely as labels to distinguish between different objects and not to describe a particular order.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, in order to distinguish two polarities of a transistor except for a gate, one of a source and a drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. The form in the drawing provides that the middle terminal of the switching transistor is a gate, the signal input terminal is a first electrode, and the output terminal is a second electrode. In addition, the transistors used in the embodiments of the present application are N-type transistors or P-type transistors, wherein the N-type transistors are turned on when the gate is at a high potential and turned off when the gate is at a low potential; the P-type transistor is turned on when the gate is at a low potential and turned off when the gate is at a high potential.
Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of an array substrate in a display panel according to an embodiment of the present disclosure; fig. 2 is a schematic circuit diagram of a portion of a display panel according to a first embodiment of the present disclosure; fig. 3 is a driving timing diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 1 and fig. 2, an embodiment of the present application provides a display panel 100, which includes a first scan line group 10, a first DEMUX switch unit 20, and a DEMUX control signal generating circuit 30, where the first scan line group 10 includes at least two first scan lines arranged at intervals along a first direction; the first DEMUX switch unit 20 includes one first scan signal input port, at least two first DEMUX control signal input ports, and at least two first scan signal output ports; the DEMUX control signal generating circuit 30 includes at least two DEMUX control signal output ports; the at least two first DEMUX control signal input ports are electrically connected with the at least two DEMUX control signal output ports in a one-to-one corresponding mode, and the at least two first scanning signal output ports are electrically connected with the at least two first scanning lines arranged at intervals along the first direction in a one-to-one corresponding mode; the DEMUX control signal generating circuit 30 is configured to send a control signal to the first DEMUX switching unit 20, and the first DEMUX switching unit 20 is configured to control the connection or disconnection between the first scan signal input port and the first scan signal output port based on the control signal.
The first scan signal input port on the display panel 100 may be electrically connected to a GOA cell in a gate driving circuit (not shown), or may be electrically connected to an output terminal of a driver chip.
In the embodiment of the present application, the display panel 100 includes an array substrate 110, a first scan line group 10 disposed on the array substrate 110, a first DEMUX switch unit 20, and a first DEMUX (Demultiplexer) control signal generating circuit 30. The array substrate 110 includes a plurality of data lines D and a plurality of scan lines that are interlaced with each other, and a plurality of pixel regions formed by interlacing the data lines and the scan lines with each other, and each pixel region is correspondingly formed with a sub-pixel 11. The first scan signal input port is connected to transmit a scan signal to the first DEMUX switch unit 20. The DEMUX control signal generating circuit 30 is connected to at least two first DEMUX control signal input ports, and transmits a control signal to the first DEMUX switching unit 20. The DEMUX control signal generating circuit 30 generates a control signal, further decomposes the scan signal into at least two signal channels, and writes the decomposed scan signal into the corresponding sub-pixel 11 through the first DEMUX switching unit 20 through at least two first DEMUX control signal input ports, respectively. At least two first scanning signal output ports are connected with the corresponding first scanning lines, and output scanning signals are loaded on the corresponding first scanning lines, so that pixels are charged. The first DEMUX switch unit 20 is configured to control on/off between the first scan signal input port and the first scan signal output port based on the control signal.
As shown in fig. 2, only one first DEMUX switching unit 20 is shown, but not limited thereto. One of the first scan signal input ports corresponds to one row of pixels, that is, a scan signal output by one of the first scan signal input ports scans eight rows of sub-pixels 11, for example, the first scan signal input port corresponds to a first scan line (G1, G2, G3, G4, G5, G6, G7, and G8), and the first scan signal sequentially scans rows of sub-pixels 11 corresponding to the first scan line (G1, G2, G3, G4, G5, G6, G7, and G8).
In this embodiment, eight first DEMUX control signal input ports and eight first scan signal output ports are taken as an example for description, but not limited to this, the first DEMUX switching unit 20 may further include ten first DEMUX control signal input ports and ten first scan signal output ports, or the first DEMUX switching unit 20 may further include six first DEMUX control signal input ports and six scan signal output ports.
In this embodiment, the DEMUX control signal generating circuit 30 includes a first shunt control signal line DEMUX _1, a second shunt control signal line DEMUX _2, a third shunt control signal line DEMUX _3, a fourth shunt control signal line DEMUX _4, a fifth shunt control signal line DEMUX _5, a sixth shunt control signal line DEMUX _6, a seventh shunt control signal line DEMUX _7, and an eighth shunt control signal line DEMUX _8, which are electrically connected to the first DEMUX switching unit 20. The eight shunt control signal lines of the DEMUX control signal generating circuit 30 are connected to the eight first DEMUX control signal input ports of the first DEMUX switch unit 20 in a one-to-one correspondence manner, so as to divide the first scanning signal into eight scanning signal channels, and the first scanning signal is input to the corresponding first scanning line through one of the first scanning signal output ports of the first DEMUX switch unit 20, so as to turn on the corresponding sub-pixel 11 switch, and charge the sub-pixel 11.
In the embodiment of the present application, the first DEMUX switching unit 20 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8.
In the embodiment of the present application, the gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8 are electrically connected to the eight DEMUX control signal output ports in a one-to-one correspondence. Specifically, the first shunt control signal line DEMUX _1 is electrically connected to a gate of the first tft T1, the second shunt control signal line DEMUX _2 is electrically connected to a gate of the second tft T2, the third shunt control signal line DEMUX _3 is electrically connected to a gate of the third tft T3, the fourth shunt control signal line DEMUX _4 is electrically connected to a gate of the fourth tft T4, the fifth shunt control signal line DEMUX _5 is electrically connected to a gate of the fifth tft T5, the sixth shunt control signal line DEMUX _6 is electrically connected to a gate of the sixth tft T6, the seventh shunt control signal line DEMUX _7 is electrically connected to a gate of the seventh tft T7, and the eighth shunt control signal line DEMUX _8 is electrically connected to a gate of the eighth tft T8.
In the embodiment of the present application, the first scan signal input port is electrically connected to the first electrodes of the first, second, third, fourth, fifth, sixth, seventh, and eighth thin film transistors T1, T2, T3, T4, T5, T6, T7, and T8 of the first DEMUX switching unit 20.
In the embodiment of the present application, as shown in fig. 3, the embodiment of the present application divides one frame image into eight subfields (SF1, SF2, SF3, SF4, SF5, SF6, SF7, and SF 8). The control signals generated by the DEMUX control signal generation circuit 30 include: the first sub-control signal, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal and the eighth sub-control signal, wherein the effective signal durations of the first sub-control signal, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal and the eighth sub-control signal are equal.
Specifically, the DEMUX control signal generation circuit 30 transmits the first sub-control signal to the gate of the first thin-film transistor T1 through the first branch control signal line DEMUX _ 1; transmitting the second sub-control signal to the gate of the second thin film transistor T2 through the second branch control signal line DEMUX _ 2; transmitting the third sub-control signal to the gate of the third thin film transistor T3 through the third branch control signal line DEMUX _ 3; transmitting the fourth sub-control signal to the gate of the fourth thin film transistor T4 through the fourth shunt control signal line DEMUX _ 4; the fifth sub-control signal is transmitted to the gate of the fifth thin film transistor T5 through the fifth shunt control signal line DEMUX _ 5; the sixth sub-control signal is transmitted to the gate of the sixth thin film transistor T6 through the sixth branch control signal line DEMUX _ 6; the seventh sub-control signal is transmitted to the gate of the seventh thin film transistor T7 through the seventh branch control signal line DEMUX _ 7; the eighth sub-control signal is transmitted to the gate of the eighth thin film transistor T8 through the eighth shunt control signal line DEMUX _ 8.
The first scan signal input port is connected to the first electrode of the first thin film transistor T1, the first electrode of the second thin film transistor T2, the first electrode of the third thin film transistor T3, the first electrode of the fourth thin film transistor T4, the first electrode of the fifth thin film transistor T5, the first electrode of the sixth thin film transistor T6, the first electrode of the seventh thin film transistor T7, and the first electrode of the eighth thin film transistor T8. A second electrode of the first thin film transistor T1 is connected to the first scan line G1, a second electrode of the second thin film transistor T2 is connected to the first scan line G2, a second electrode of the third thin film transistor T3 is connected to the first scan line G3, a second electrode of the fourth thin film transistor T4 is connected to the first scan line G4, a second electrode of the fifth thin film transistor T5 is connected to the first scan line G5, a second electrode of the sixth thin film transistor T6 is connected to the first scan line G6, a second electrode of the seventh thin film transistor T7 is connected to the first scan line G7, and a second electrode of the eighth thin film transistor T8 is connected to the first scan line G8.
Specifically, taking the nth frame as an example, when the sub-pixels 11 corresponding to the first scan line G1 need to be charged, the control signal is changed to an active signal of a high level, so that the first thin film transistor T1 in the first DEMUX switch unit 20 is turned on, at this time, the first scan signal input port and the first scan signal output port of the first thin film transistor T1 are communicated, the scan signal is output from the first thin film transistor T1 to the first scan line G1, the first scan line G1 is at a high level, the scan signal is written into the sub-pixels 11 corresponding to the first scan line G1, and the data lines D1 to D3 corresponding to the sub-pixels of the row charge the corresponding sub-pixels. At this time, the other control signals are at a low level.
In the subsequent scan period, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal, and the eighth sub-control signal sequentially become active signals of a high level, so that the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8 are sequentially turned on to charge the corresponding sub-pixel 11.
In the embodiment of the present application, the interval time t between the first sub-control signal, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal and the eighth sub-control signal 0 Equal but not limited thereto. In practical application, the skilled person can adjust the interval t according to actual requirements 0 Making adjustments to control the interval time t between signals 0 May not be equal.
The application provides a display panel is through setting up first DEMUX switch element 20 to make scanning signal output in grades, when guaranteeing normal display function, also can reduce the quantity of scanning passageway, and then solve the extravagant problem of scanning passageway.
As an embodiment of the present application, please refer to fig. 4, in which fig. 4 is a schematic circuit diagram of a portion of a display panel according to a second embodiment of the present application. As shown in fig. 4, the present application further provides a display panel 200, where the display panel 200 is different from the display panel 100 in that: the display panel 200 further includes a second scan line group 40 and a second DEMUX switch unit 50, where the second scan line group 40 includes at least two second scan lines arranged at intervals along the first direction; the second DEMUX switch unit 50 includes one second scan signal input port, at least two second DEMUX control signal input ports, and at least two second scan signal output ports; the at least two second DEMUX control signal input ports are electrically connected with the at least two second DEMUX control signal output ports in a one-to-one corresponding mode, and the at least two second scanning signal output ports are electrically connected with the at least two second scanning lines arranged at intervals along the first direction in a one-to-one corresponding mode; the DEMUX control signal generating circuit 30 is further configured to send a control signal to the second DEMUX switching unit 50, and the second DEMUX switching unit 50 is configured to control on/off between the second scan signal input port and the second scan signal output port based on the control signal.
In the embodiment of the present application, the second DEMUX switching unit 50 includes a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, and a sixteenth thin film transistor T16.
In the embodiment of the present application, the first electrodes of the ninth thin film transistor T9, the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, the thirteenth thin film transistor T13, the fourteenth thin film transistor T14, the fifteenth thin film transistor T15, and the sixteenth thin film transistor T16 are all electrically connected to the second scan signal input port; the second electrodes of the ninth thin film transistor T9, the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, the thirteenth thin film transistor T13, the fourteenth thin film transistor T14, the fifteenth thin film transistor T15, and the sixteenth thin film transistor T16 are electrically connected to the eight second scan lines in a one-to-one correspondence.
In the embodiment of the present application, the first shunt control signal line DEMUX _1 is electrically connected to the gate of the ninth tft T9; the second shunt control signal line DEMUX _2 is electrically connected to the gate of the tenth thin film transistor T10; the third shunt control signal line DEMUX _3 is electrically connected to the gate of the eleventh thin film transistor T11; the fourth branch control signal line DEMUX _4 is electrically connected to the gate of the twelfth thin film transistor T12; the fifth shunting control signal line DEMUX _5 is electrically connected to the gate of the thirteenth thin film transistor T13; the sixth branch control signal line DEMUX _6 is electrically connected to the gate of the fourteenth thin film transistor T14; the seventh branch control signal line DEMUX _7 is electrically connected to the gate of the fifteenth thin film transistor T15; the eighth shunt control signal line DEMUX _8 is electrically connected to the gate of the sixteenth thin film transistor T16.
In the embodiment of the present application, only one first DEMUX switching unit 20 and one second DEMUX switching unit 50 are shown, but not limited thereto. The first DEMUX switching unit 20 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8.
In the embodiment of the present invention, a first scan signal input port and a second scan signal input port respectively correspond to one row of pixels, that is, a scan signal output from the first scan signal input port and a scan signal output from the second scan signal input port respectively scan eight rows of sub-pixels 11, for example, the first scan signal input port corresponds to a first scan line (G1, G2, G3, G4 and G4), the first scan signal sequentially scans row sub-pixels 11 corresponding to the first scan line (G4, G4 and G4), the second scan signal corresponds to a second scan line (G4, G4 and G4), and the second scan signal sequentially scans row sub-pixels corresponding to the second scan line (G4, G4 and G4).
The application provides a display panel among display device is through setting up first DEMUX switch element 20 and second DEMUX switch element 50 to make scanning signal output in grades, when guaranteeing normal display function, also can reduce the quantity of scanning passageway, and then solve the extravagant problem of scanning passageway.
Note that the first to sixteenth thin film transistors T1 to T16 are all transistors of the same type.
As an embodiment of the present application, please refer to fig. 5, in which fig. 5 is a schematic circuit diagram of a portion of a display panel according to a third embodiment of the present application. As shown in fig. 5, the present application further provides a display panel 300, where the display panel 300 is different from the display panel 200 in that: one end of the storage capacitor is electrically connected to the first DEMUX switch unit 20 and the other end of the storage capacitor is connected to the ground terminal, and/or one end of the storage capacitor is electrically connected to the second DEMUX switch unit 50 and the other end of the storage capacitor is connected to the ground terminal.
In the embodiment of the present application, the display panel includes a first scan line group 10, a first DEMUX switching unit 20, a DEMUX control signal generating circuit 30, a second scan line group 40, a second DEMUX switching unit 50, and a storage capacitor c. The first DEMUX switching unit 20 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8. The second DEMUX switching unit 50 includes a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, and a sixteenth thin film transistor T16.
In the embodiment of the present application, preferably, the storage capacitor c includes a first storage capacitor c1, a second storage capacitor c2, a third storage capacitor c3, a fourth storage capacitor c4, a fifth storage capacitor c5, a sixth storage capacitor c6, a seventh storage capacitor c7, an eighth storage capacitor c8, a ninth storage capacitor c9, a tenth storage capacitor c10, an eleventh storage capacitor c11, a twelfth storage capacitor c12, a thirteenth storage capacitor c13, a fourteenth storage capacitor c14, a fifteenth storage capacitor c15, and a sixteenth storage capacitor c 16. Specifically, one end of the storage capacitor is connected between the first scan signal input port and the corresponding thin film transistor, and the other end of the storage capacitor is connected to the ground terminal. Taking the first storage capacitor as an example, one end of the first storage capacitor c1 is electrically connected to the first electrode of the first thin film transistor T1, and the other end is connected to the ground terminal.
In the embodiment of the application, the corresponding storage capacitor is added between each thin film transistor and the scanning signal input end, so that the potential of the scanning signal input end is kept stable, and further, the voltage change among different thin film transistors can be reduced and the potential holding capacity can be increased by adjusting the capacitance of the storage capacitor.
In the embodiment of the present invention, a first scan signal input port and a second scan signal input port correspond to one row of pixels, respectively, that is, a scan signal output from the first scan signal input port and a scan signal output from the second scan signal input port respectively scan eight rows of sub-pixels 11, for example, the first scan signal input port corresponds to a first scan line (G1, G2, G3, G4 and G4), the first scan signal sequentially scans first scan lines (G4, G4 and G4), the second scan signal sequentially scans second scan lines (G4, G4 and G4) corresponding to sub-pixels of the second scan lines (G4, G4 and G4).
Referring to fig. 6, fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 6, the present application provides a display device 400, where the display device 400 includes a driving chip 60 and the display panel, and the driving chip 60 is electrically connected to the display panel.
Specifically, the driving chip includes a plurality of output ports, each of which is electrically connected to one of the first DEMUX switch units 20 and/or the second DEMUX switch unit 50 in the display panel.
The application provides a display panel among display device is through setting up first DEMUX switch element 20, and/or, second DEMUX switch element 50 to make scanning signal output in grades, when guaranteeing normal display function, also can reduce the quantity of scanning passageway, and then solve the extravagant problem of scanning passageway.
The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel, comprising:
the scanning line set comprises at least two first scanning lines arranged along a first direction at intervals;
a first DEMUX switch unit including a first scanning signal input port, at least two first DEMUX control signal input ports, and at least two first scanning signal output ports;
a DEMUX control signal generating circuit including at least two DEMUX control signal output ports; wherein the content of the first and second substances,
the at least two first DEMUX control signal input ports are electrically connected with the at least two DEMUX control signal output ports in a one-to-one corresponding mode, and the at least two first scanning signal output ports are electrically connected with the at least two first scanning lines arranged at intervals along the first direction in a one-to-one corresponding mode; the DEMUX control signal generating circuit is used for sending a control signal to the first DEMUX switch unit, and the first DEMUX switch unit is used for controlling the connection or disconnection between the first scanning signal input port and the first scanning signal output port based on the control signal.
2. The display panel of claim 1, wherein the first DEMUX switch unit includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a sixth thin-film transistor, a seventh thin-film transistor, and an eighth thin-film transistor;
the gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor and the eighth thin film transistor are electrically connected with the eight DEMUX control signal output ports in a one-to-one correspondence manner;
first electrodes of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, and the eighth thin film transistor are all electrically connected to the first scanning signal input port;
second electrodes of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor and the eighth thin film transistor are electrically connected with eight first scanning lines in a one-to-one correspondence manner.
3. The display panel according to claim 2, wherein the DEMUX control signal generation circuit includes a first shunt control signal line, a second shunt control signal line, a third shunt control signal line, a fourth shunt control signal line, a fifth shunt control signal line, a sixth shunt control signal line, a seventh shunt control signal line, and an eighth shunt control signal line;
the first shunt control signal line is electrically connected with a grid electrode of the first thin film transistor; the second shunt control signal line is electrically connected with the grid electrode of the second thin film transistor; the third shunt control signal line is electrically connected with a grid electrode of the third thin film transistor; the fourth shunt control signal line is electrically connected with a grid electrode of the fourth thin film transistor; the fifth branch control signal line is electrically connected with a grid electrode of the fifth thin film transistor; the sixth shunt control signal line is electrically connected with a gate of the sixth thin film transistor; the seventh shunt control signal line is electrically connected to a gate of the seventh thin film transistor; the eighth shunt control signal line is electrically connected to a gate of the eighth thin film transistor.
4. The display panel according to claim 3, wherein the display panel further comprises a second scanning line group, the second scanning line group comprising at least two second scanning lines arranged at intervals along the first direction;
a second DEMUX switch unit including a second scan signal input port, at least two second DEMUX control signal input ports, and at least two second scan signal output ports;
the at least two second DEMUX control signal input ports are electrically connected with the at least two DEMUX control signal output ports in a one-to-one corresponding mode, and the at least two second scanning signal output ports are electrically connected with the at least two second scanning lines arranged at intervals along the first direction in a one-to-one corresponding mode; the DEMUX control signal generating circuit is further configured to send the control signal to the second DEMUX switch unit, and the second DEMUX switch unit is configured to control, based on the control signal, on or off between the second scanning signal input port and the second scanning signal output port.
5. The display panel according to claim 4, wherein the second DEMUX switching unit includes a ninth thin-film transistor, a tenth thin-film transistor, an eleventh thin-film transistor, a twelfth thin-film transistor, a thirteenth thin-film transistor, a fourteenth thin-film transistor, a fifteenth thin-film transistor, and a sixteenth thin-film transistor;
first electrodes of the ninth thin film transistor, the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor and the sixteenth thin film transistor are all electrically connected with the second scan signal input port;
second electrodes of the ninth thin film transistor, the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor and the sixteenth thin film transistor are electrically connected with eight second scanning lines in a one-to-one correspondence manner;
the first shunt control signal line is electrically connected with a grid electrode of the ninth thin film transistor; the second shunt control signal line is electrically connected with a gate of the tenth thin film transistor; the third shunt control signal line is electrically connected with a gate of the eleventh thin film transistor; the fourth shunt control signal line is electrically connected with a grid electrode of the twelfth thin film transistor; the fifth branch control signal line is electrically connected with a grid electrode of the thirteenth thin film transistor; the sixth shunt control signal line is electrically connected with a gate of the fourteenth thin film transistor; the seventh shunt control signal line is electrically connected with a gate of the fifteenth thin film transistor; the eighth shunt control signal line is electrically connected to a gate of the sixteenth thin film transistor.
6. The display panel according to claim 3 or 5, wherein the display panel further comprises a storage capacitor, one end of the storage capacitor is electrically connected to the first DEMUX switch unit, and the other end of the storage capacitor is connected to a ground terminal, and/or one end of the storage capacitor is electrically connected to the second DEMUX switch unit, and the other end of the storage capacitor is connected to the ground terminal.
7. The display panel according to claim 5, wherein the first to sixteenth thin film transistors are all of the same type.
8. The display panel according to claim 7, wherein the control signal comprises a first sub-control signal, a second sub-control signal, a third sub-control signal, a fourth sub-control signal, a fifth sub-control signal, a sixth sub-control signal, a seventh sub-control signal, and an eighth sub-control signal,
the effective signal durations in the first sub-control signal, the second sub-control signal, the third sub-control signal, the fourth sub-control signal, the fifth sub-control signal, the sixth sub-control signal, the seventh sub-control signal and the eighth sub-control signal are equal.
9. The display panel according to claim 8, wherein the interval time between the first sub control signal, the second sub control signal, the third sub control signal, the fourth sub control signal, the fifth sub control signal, the sixth sub control signal, the seventh sub control signal, and the eighth sub control signal is equal.
10. A display device comprising a driver chip and the display panel according to any one of claims 1 to 9, wherein the driver chip is electrically connected to the display panel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210406434.6A CN114822437A (en) | 2022-04-18 | 2022-04-18 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210406434.6A CN114822437A (en) | 2022-04-18 | 2022-04-18 | Display panel and display device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118430A (en) * | 2015-08-31 | 2015-12-02 | 上海和辉光电有限公司 | Pixel driving circuit, driving method thereof and display device |
| CN107564453A (en) * | 2017-09-15 | 2018-01-09 | 武汉华星光电技术有限公司 | Displaying panel driving method |
| CN108831392A (en) * | 2018-06-25 | 2018-11-16 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109637414A (en) * | 2018-12-28 | 2019-04-16 | 厦门天马微电子有限公司 | A kind of display panel, drive circuit and its driving method, display device |
| CN111048051A (en) * | 2019-12-23 | 2020-04-21 | 武汉华星光电技术有限公司 | Display panel |
| CN112530354A (en) * | 2020-12-29 | 2021-03-19 | 上海天马有机发光显示技术有限公司 | Display panel, display device and driving method of display panel |
| CN216118747U (en) * | 2021-11-08 | 2022-03-22 | 福建华佳彩有限公司 | Circuit structure for reducing Data Demux wiring load |
-
2022
- 2022-04-18 CN CN202210406434.6A patent/CN114822437A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118430A (en) * | 2015-08-31 | 2015-12-02 | 上海和辉光电有限公司 | Pixel driving circuit, driving method thereof and display device |
| CN107564453A (en) * | 2017-09-15 | 2018-01-09 | 武汉华星光电技术有限公司 | Displaying panel driving method |
| CN108831392A (en) * | 2018-06-25 | 2018-11-16 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109637414A (en) * | 2018-12-28 | 2019-04-16 | 厦门天马微电子有限公司 | A kind of display panel, drive circuit and its driving method, display device |
| CN111048051A (en) * | 2019-12-23 | 2020-04-21 | 武汉华星光电技术有限公司 | Display panel |
| CN112530354A (en) * | 2020-12-29 | 2021-03-19 | 上海天马有机发光显示技术有限公司 | Display panel, display device and driving method of display panel |
| CN216118747U (en) * | 2021-11-08 | 2022-03-22 | 福建华佳彩有限公司 | Circuit structure for reducing Data Demux wiring load |
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