CN114817092A - Multi-state ROM circuit with high storage density - Google Patents
Multi-state ROM circuit with high storage density Download PDFInfo
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- CN114817092A CN114817092A CN202210382971.1A CN202210382971A CN114817092A CN 114817092 A CN114817092 A CN 114817092A CN 202210382971 A CN202210382971 A CN 202210382971A CN 114817092 A CN114817092 A CN 114817092A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
The invention discloses a multi-state ROM circuit with high storage density, which comprises an internal memory, a ROM, a control processor, a bus, a host interface, a buffer memory and a memory interface, wherein the internal memory is communicated through the bus; the ROM comprises a first ROM storage unit, a second ROM storage unit, a third ROM storage unit and a fourth ROM storage unit, wherein the first ROM storage unit, the second ROM storage unit, the third ROM storage unit and the fourth ROM storage unit are all independent storage units. The invention provides a solution for multi-value storage of ROM memory cells, so that the ROM memory has the characteristic of high storage density.
Description
Technical Field
The invention relates to the related technical field of multi-state ROM circuits, in particular to a multi-state ROM circuit with high storage density.
Background
A Read-Only Memory (ROM) operates in a non-destructive Read mode, and Only information that cannot be written can be Read, and the structure of a Memory cell storing "0" and "1" is shown in fig. 9.
In general, when a certain cell is read by a ROM memory, as shown in fig. 10 (taking reading "0" as an example), the precharge signal charges the whole bit line BL where the cell is to be read to VDD, and then since the word line WL of the selected cell is in a gated state, therefore, the potential of the BL is pulled back from high level to low level by the unit under the effect of the conducting MOS transistor, and the time sequence change of the relevant signal in one complete read cycle is shown in fig. 11, as can be seen from the timing diagram, when the ROM memory reads once, the reading circuit firstly pulls up the potential of a whole bit line where the corresponding cell is located to the potential of the power supply, then the gating signal of the cell enables the cell to discharge (cell "0")/hold (cell "1"), then the SENSE signal of the amplifier releases the potential of the bit line after the cell is stabilized, and the final OUTPUT is obtained after the processing of other related circuits.
In the case of reading such a ROM memory cell with a conventional structure, the main difference between the cell "0" or "1" is whether the bit line BL is precharged and then the potential is pulled down again by the MOS transistor in the cell, and the final read result is "0" or "1" depending on the details of whether the potential of the bit line BL is dropped and the speed of dropping when the sense amplifier is enabled. In the read process of the ROM memory unit with the traditional structure, the speed of the bit line BL potential pulled down by the MOS tube is basically the same as that of a sensitive amplifier of a read circuit, so that only a single value can be stored, the relation between the actual storage capacity of the traditional ROM memory and the number of the memory units is very fixed, and the solution of the large-capacity ROM memory only increases the number of the memory units, thereby increasing the layout area and the read-write power consumption.
In summary, in the ROM memory cell with the conventional structure, in the reading process, the speed of the bit line BL potential pulled down by the MOS transistor is substantially the same for the sense amplifier of the reading circuit, and the difference of the bit line pull-down speeds between different cells cannot be sensed by the amplifier, so that only a single value can be stored, and the storage density of the ROM memory with the conventional structure is very low. However, the selection of the MOS tube in the memory cell is diversified, so that the pull-down speed of the potential of the bit line BL in the ROM cell with different memory '0' in the reading process has obvious difference due to the different speeds of the MOS tube, and the memory and the reading of different values are further realized.
Disclosure of Invention
It is an object of the present invention to provide a high storage density multi-state ROM circuit to solve the problems of the prior art.
In order to achieve the purpose, the invention provides the following technical scheme: a multi-state ROM circuit with high storage density comprises an internal memory, a ROM, a control processor, a bus, a host interface, a buffer memory and a memory interface, wherein the internal memory communicates through the bus, the ROM communicates through the bus, the control processor communicates through the bus, the host interface communicates through the bus, the buffer memory communicates through the bus, and the memory interface communicates through the bus;
the ROM comprises a first ROM storage unit, a second ROM storage unit, a third ROM storage unit and a fourth ROM storage unit, wherein the first ROM storage unit, the second ROM storage unit, the third ROM storage unit and the fourth ROM storage unit are all independent storage units.
Preferably, the first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS transistors of LVT, RVT and HVT.
Preferably, the first ROM memory cell, the second ROM memory cell and the third ROM memory cell respectively adopt MOS transistors of LVT, RVT and HVT to realize the storage of "00", "01" and "10".
Preferably, the system further comprises a boot ROM module and a storage element, wherein the boot ROM module comprises configuration instructions and patch data copying instructions; the internal memory includes a controller and patch data; the storage element includes patch data and configuration data.
Preferably, the design method comprises the following steps:
s1: providing 4 separate ROM memory cells;
s2: MOS transistors of LVT, RVT and HVT are adopted to realize storage of '00', '01' and '10', and a traditional storage unit is adopted to realize storage of '11'.
Preferably, the read current of the ROM cell in S2 is: "00" > "01" > "10" > "11".
Preferably, the ROM memory array can be programmed through a programming hole for each memory cell or through a threshold voltage, and a single bit is provided for two bits of information.
Preferably, for the implementation of different stored values, MOS tubes with various thresholds, the channel length of the MOS tube can be used for regulating the bit line potential change speed when the cell reads, or the width of the transistor can be used for forming the multi-bit.
Compared with the prior art, the invention has the beneficial effects that: 4 kinds of independent ROM memory cells are provided, MOS tubes of LVT, RVT and HVT are respectively adopted to realize the storage of '00', '01' and '10', and the cell storing '11' is the same as the traditional cell; thus, the read current of a ROM cell will be: "00" > "01" > "10" > "11"; in the common ROM memory array, each memory cell is programmed through a programming hole (VIA), and in addition, the memory cell can be programmed through the threshold voltage of a tube, so that two bits of information corresponding to a single bit are provided, and the requirement of high density is met; for the realization of different values, not only MOS tubes with various thresholds can be utilized, but also the channel Length (Length) of the MOS tube can be utilized to regulate and control the bit line potential change speed when the unit reads, and similarly, the Width (Width) of the transistor can also be used for forming a multi-bit; a solution is provided for multi-value storage of ROM memory cells, which enables the ROM memory to have the characteristic of high storage density.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of the structure of the read current "00" according to the present invention;
FIG. 3 is a schematic diagram of the structure of the read current "01" according to the present invention;
FIG. 4 is a schematic diagram of the structure of the read current "10" according to the present invention;
FIG. 5 is a schematic diagram of the structure of the read current "11" according to the present invention;
FIG. 6 is a schematic diagram of a read timing sequence of the ROM cell "00" according to the present invention;
FIG. 7 is a schematic diagram of a read timing sequence of a ROM cell "10" according to the present invention;
FIG. 8 is a schematic diagram of a Multi-state ROM read circuit according to the present invention;
FIG. 9 is a diagram of a prior art ROM cell;
FIG. 10 is a simplified diagram of a read point path of a ROM memory according to the prior art;
FIG. 11 is a timing diagram illustrating a prior art ROM read "0".
In the figure: 1. an internal memory; 2. a ROM; 3. a control processor; 4. a bus; 5. a host interface; 6. a buffer memory; 7. a memory interface.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example one
Referring to fig. 1-8, in an embodiment of the present invention, a high storage density multi-state ROM circuit includes an internal memory 1, a ROM2, a control processor 3, a bus 4, a host interface 5, a buffer memory 6, and a memory interface 7, and is characterized in that: the internal memory 1 communicates via a bus 4, the ROM2 communicates via the bus 4, the control processor 3 communicates via the bus 4, the host interface 5 communicates via the bus 4, the buffer memory 6 communicates via the bus 4, and the memory interface 7 communicates via the bus 4;
the ROM2 includes a first ROM storage unit, a second ROM storage unit, a third ROM storage unit, and a fourth ROM storage unit, which are all separate storage units.
The first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS transistors of LVT, RVT and HVT, and the first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS transistors of LVT, RVT and HVT to realize the storage of '00', '01' and '10'.
Also included are a boot ROM module and a storage element, the boot ROM module including configuration instructions and patch data copy instructions; the internal memory includes a controller and patch data; the storage element includes patch data and configuration data.
A method for designing a multi-state ROM circuit with high storage density comprises the following steps:
s1: providing 4 separate ROM memory cells;
s2: MOS transistors of LVT, RVT and HVT are adopted to realize storage of '00', '01' and '10', and a traditional storage unit is adopted to realize storage of '11'.
Read current of the ROM cell in S2: "00" > "01" > "10" > "11".
The ROM memory array can be programmed through programming holes or through tube threshold voltage, and single bit and corresponding two bits of information are provided.
For the implementation of different values, MOS tubes with various thresholds, the channel length of MOS are used to regulate the bit line potential variation speed when the cell reads, or the width of transistor is used to form multi-bit.
When multiple threshold MOS transistors are used for programming the multi-value cells, the difference between different stored value cells is mainly reflected in the pull-down speed of the bit line BL potential of the seed cell in the reading process. FIG. 6 shows the timing diagram of the ROM cell storing "00" during reading, FIG. 7 shows the timing diagram of the ROM cell storing "10" during reading, and the difference of BL potential drop speed during reading of two different value-stored cells can be seen by observing the two diagrams, and these obvious differences can be sensed by the sensitivity of the amplifier, thereby realizing the reading of the multi-valued ROM cell. Fig. 8 is a schematic diagram showing a reading circuit of a Multi-value (Multi-State) ROM, in which a difference in pull-down speed of the bit line BL potential of a memory cell is sensed as an output value of two bits by a sense amplifier, thereby realizing Multi-value reading.
The working principle of the invention is as follows: providing 4 separate ROM memory cells; MOS tubes of LVT, RVT and HVT are respectively adopted to realize the storage of '00', '01' and '10', and the storage of '11' is realized by adopting a traditional storage unit; read current of ROM cell: "00" > "01" > "10" > "11"; the ROM storage array can realize programming to each storage unit through a programming hole or program through a tube threshold voltage, and provides two bits of information corresponding to a single bit; for the implementation of different values, MOS tubes with various thresholds, the channel length of MOS are used to regulate the bit line potential variation speed when the cell reads, or the width of transistor is used to form multi-bit.
Example two
Referring to fig. 2-8, in an embodiment of the present invention, the ROM2 includes a first ROM storage unit, a second ROM storage unit, a third ROM storage unit, and a fourth ROM storage unit, and the first ROM storage unit, the second ROM storage unit, the third ROM storage unit, and the fourth ROM storage unit are all separate storage units.
The first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS transistors of LVT, RVT and HVT, and the first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS transistors of LVT, RVT and HVT to realize the storage of '00', '01' and '10'.
A method for designing a multi-state ROM circuit with high storage density comprises the following steps:
s1: providing 4 separate ROM memory cells;
s2: MOS transistors of LVT, RVT and HVT are adopted to realize storage of '00', '01' and '10', and a traditional storage unit is adopted to realize storage of '11'.
Read current of the ROM cell in S2: "00" > "01" > "10" > "11".
The ROM memory array can be programmed through programming holes or through tube threshold voltage, and single bit and corresponding two bits of information are provided.
For the implementation of different values, MOS tubes with various thresholds, the channel length of MOS are used to regulate the bit line potential variation speed when the cell reads, or the width of transistor is used to form multi-bit.
When multiple threshold MOS transistors are used for programming the multi-value cells, the difference between different stored value cells is mainly reflected in the pull-down speed of the bit line BL potential of the seed cell in the reading process. FIG. 6 shows the timing diagram of the ROM cell storing "00" during reading, FIG. 7 shows the timing diagram of the ROM cell storing "10" during reading, and the difference of BL potential drop speed during reading of two different value-stored cells can be seen by observing the two diagrams, and these obvious differences can be sensed by the sensitivity of the amplifier, thereby realizing the reading of the multi-valued ROM cell. Fig. 8 is a schematic diagram showing a reading circuit of a Multi-value (Multi-State) ROM, in which a difference in pull-down speed of the bit line BL potential of a memory cell is sensed as an output value of two bits by a sense amplifier, thereby realizing Multi-value reading.
The working principle of the invention is as follows: providing 4 separate ROM memory cells; MOS tubes of LVT, RVT and HVT are respectively adopted to realize the storage of '00', '01' and '10', and the storage of '11' is realized by adopting a traditional storage unit; read current of ROM cell: "00" > "01" > "10" > "11"; the ROM storage array can realize programming to each storage unit through a programming hole or program through a tube threshold voltage, and provides two bits of information corresponding to a single bit; for the implementation of different stored values, MOS tubes with various thresholds, the channel length of the MOS tube can be used for regulating and controlling the bit line potential change speed when the unit reads, or the width of the transistor is used for forming the multi-bit.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A high storage density multi-state ROM circuit comprising an internal memory (1), a ROM (2), a control processor (3), a bus (4), a host interface (5), a buffer memory (6) and a memory interface (7), characterized in that: the internal memory (1) communicates through a bus (4), the ROM (2) communicates through the bus (4), the control processor (3) communicates through the bus (4), the host interface (5) communicates through the bus (4), the buffer memory (6) communicates through the bus (4), and the memory interface (7) communicates through the bus (4);
the ROM (2) comprises a first ROM storage unit, a second ROM storage unit, a third ROM storage unit and a fourth ROM storage unit, wherein the first ROM storage unit, the second ROM storage unit, the third ROM storage unit and the fourth ROM storage unit are all independent storage units.
2. The high storage density, multi-state ROM circuit of claim 1, wherein: the first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS tubes of LVT, RVT and HVT.
3. The high storage density, multi-state ROM circuit of claim 2, wherein: the first ROM storage unit, the second ROM storage unit and the third ROM storage unit respectively adopt MOS transistors of LVT, RVT and HVT to realize storage of '00', '01' and '10'.
4. The high storage density, multi-state ROM circuit of claim 1, wherein: also included are a boot ROM module and a storage element, the boot ROM module including configuration instructions and patch data copy instructions; the internal memory includes a controller and patch data; the storage element includes patch data and configuration data.
5. The high storage density, multi-state ROM circuit of claim 1, wherein: the design method comprises the following steps:
s1: providing 4 separate ROM memory cells;
s2: MOS transistors of LVT, RVT and HVT are adopted to realize storage of '00', '01' and '10', and a traditional storage unit is adopted to realize storage of '11'.
6. The high storage density, multi-state ROM circuit of claim 5, wherein: read current of the ROM cell in S2: "00" > "01" > "10" > "11".
7. The high storage density, multi-state ROM circuit of claim 5, wherein: the ROM memory array can be programmed through programming holes or through tube threshold voltage, and single bit and corresponding two bits of information are provided.
8. The high storage density, multi-state ROM circuit of claim 5, wherein: for the implementation of different values, MOS tubes with various thresholds, the channel length of MOS are used to regulate the bit line potential variation speed when the cell reads, or the width of transistor is used to form multi-bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210382971.1A CN114817092A (en) | 2022-04-13 | 2022-04-13 | Multi-state ROM circuit with high storage density |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210382971.1A CN114817092A (en) | 2022-04-13 | 2022-04-13 | Multi-state ROM circuit with high storage density |
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| CN202210382971.1A Pending CN114817092A (en) | 2022-04-13 | 2022-04-13 | Multi-state ROM circuit with high storage density |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1102499A (en) * | 1993-07-12 | 1995-05-10 | 株式会社东芝 | Reading-only memory device |
| CN105336372A (en) * | 2014-05-29 | 2016-02-17 | 展讯通信（上海）有限公司 | ROM memory cell, storage array, memory and reading method |
| CN105448342A (en) * | 2014-05-29 | 2016-03-30 | 展讯通信（上海）有限公司 | ROM memory cell, memory array, memory and reading method |
| CN107045880A (en) * | 2016-02-08 | 2017-08-15 | 恩智浦有限公司 | With the high density ROM cell for being stored with the dibit of low-voltage at a high speed |
| CN110136767A (en) * | 2018-02-09 | 2019-08-16 | 展讯通信（上海）有限公司 | ROM array and its domain structure |
-
2022
- 2022-04-13 CN CN202210382971.1A patent/CN114817092A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1102499A (en) * | 1993-07-12 | 1995-05-10 | 株式会社东芝 | Reading-only memory device |
| CN105336372A (en) * | 2014-05-29 | 2016-02-17 | 展讯通信（上海）有限公司 | ROM memory cell, storage array, memory and reading method |
| CN105448342A (en) * | 2014-05-29 | 2016-03-30 | 展讯通信（上海）有限公司 | ROM memory cell, memory array, memory and reading method |
| CN107045880A (en) * | 2016-02-08 | 2017-08-15 | 恩智浦有限公司 | With the high density ROM cell for being stored with the dibit of low-voltage at a high speed |
| CN110136767A (en) * | 2018-02-09 | 2019-08-16 | 展讯通信（上海）有限公司 | ROM array and its domain structure |
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