CN114816747A - Multi-core load regulation and control method and device of processor and electronic equipment - Google Patents
Multi-core load regulation and control method and device of processor and electronic equipment Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
- G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
- G06F9/4862—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration the task being a mobile agent, i.e. specifically designed to migrate
- G06F9/4875—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration the task being a mobile agent, i.e. specifically designed to migrate with migration policy, e.g. auction, contract negotiation
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- G—PHYSICS
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
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Abstract
The embodiment of the invention relates to a multi-core load regulation and control method and device of a processor and electronic equipment, wherein the method comprises the following steps: determining the load level of each processor core in at least two processor cores of the processor according to a pre-configured level division rule; determining load regulation and control rules of at least two processor cores according to the difference value between the load grades of every two processor cores; and under the condition of determining to dynamically regulate and control the loads of the at least two processor cores according to the load regulation and control rule, completing the dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy. By monitoring the load condition of each core in real time, the task amount on each processor core can be flexibly and dynamically regulated and controlled, so that the processor can be ensured to operate in a better operating environment at every moment, and the time for testing whether the operating load of the processor meets the condition by using a static configuration trial and error in the prior art is saved.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to a multi-core load regulation and control method and device of a processor and electronic equipment.
Background
Currently, as a domain controller is the mainstream in a vehicle-mounted direction, more Electronic Control Units (ECUs) are used to complete the work on one controller, so that more tasks need to be run on a Micro Control Unit (MCU), and the MCU is also correspondingly changed from a single core to a multi-core. In a real-time processor of an existing vehicle-mounted MCU, a core is usually placed on the real-time performance of task processing, and the priority of task processing is often a priority point, and along with the development of domain control, not only the real-time performance of task processing but also the utilization rate of a processor core should be considered. Once the utilization rate of the processor core is too high, a pause phenomenon is easily caused when the task is processed, and further, a real-time task is overtime, the task is interrupted, and the like.
The real-time processor of the existing vehicle-mounted MCU adopts a static configuration mode to plan the utilization rate of each processor core in the processor, namely, the total number of tasks executed in the MCU, the execution period of each task, the priority of the tasks and the like are obtained in advance, and then all the tasks are classified and distributed to different processor cores to be executed. Tests show that in the real running process of a task, the static configuration mode easily causes the condition that one or more processor cores are overloaded and other processor cores have too few tasks, and if the running conditions of various tasks on different cores are re-planned at the moment, the execution of the tasks is delayed, time and labor are consumed, and whether the condition that one or more processor cores are overloaded and other processor cores have too few tasks at a certain subsequent moment can be known again or not.
Disclosure of Invention
The application provides a multi-core load regulation and control method and device of a processor and electronic equipment, and aims to solve part or all of technical problems in the prior art.
In a first aspect, the present application provides a method for multi-core load regulation of a processor, including:
determining the load level of each processor core in at least two processor cores of the processor according to a pre-configured level division rule, wherein the load level is obtained by division according to the utilization rate of the processor cores;
determining a load regulation rule for at least two processor cores according to the difference value between the load levels of every two processor cores;
and under the condition of determining to dynamically regulate and control the loads of the at least two processor cores according to the load regulation and control rule, completing the dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy.
In an optional embodiment, determining the load regulation rule for at least two processor cores according to the difference between the load levels of each two processor cores includes:
under the condition that the difference value between the load levels of any two processor cores is greater than or equal to a first preset difference value threshold value, determining that the load regulation and control rule is to dynamically regulate and control the loads of at least two processor cores;
or, when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold value and larger than or equal to a second preset difference threshold value, the situation lasts for a preset time period, and when the load levels of at least two processor cores are larger than or equal to the first load level, the load regulation rule is determined to dynamically regulate and control the loads of at least two processor cores.
In an optional implementation manner, in a case that a difference between load levels of any two processor cores is greater than or equal to a first preset difference threshold, the preset regulation and control policy includes:
sequencing at least two processor cores according to the size of the load grade;
determining the task adjustment times according to the total number of the processor cores;
and respectively adjusting the tasks of the processor cores ordered in the (n + 1) -i th time and the processor cores ordered as the i-th time at the ith time, and adjusting the tasks with preset number in the processor cores with high load grade to the processor cores with low load grade, wherein i is a positive integer, and n is the total number of the processor cores.
In an optional implementation manner, determining the number of task adjustments according to the total number of processor cores specifically includes:
and dividing the total number of the processor cores by 2 to obtain a module value, namely the task adjusting times.
In an optional implementation manner, before the ith time, respectively adjusting the tasks of the processor cores ordered at n +1-i and the processor core ordered as ith, the method further includes:
and determining the preset number of the tasks to be transferred by the processor core of the (n + 1) -th-i th order according to the load level of the processor core of the (n + 1) -th order and the load level of the processor core of the (i) th order.
In an optional implementation manner, when a difference between load levels of any two processor cores is smaller than a first preset difference threshold and greater than or equal to a second preset difference threshold for a preset time period, and the load levels of at least two processor cores are greater than or equal to the first load level, the preset regulation and control policy includes:
performing first-level optimization processing on codes corresponding to the processors under the condition that the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to a first load level and smaller than a second load level;
or, under the condition that the load levels of a preset number of processor cores in the at least two processor cores are greater than or equal to the second load level and less than the third load level, performing secondary optimization processing on codes corresponding to the processors, or replacing the processors;
or the processor is replaced when the load level of a preset number of processor cores in the at least two processor cores is greater than or equal to the third load level.
In an optional embodiment, before determining the load level of each of the at least two processor cores of the processor according to the preconfigured level-dividing rule, the method further comprises:
and traversing the utilization rate of each processor core in the at least two processor cores in sequence at fixed time intervals so as to determine the load level of each processor core according to the utilization rate of each processor core.
In an alternative embodiment, determining a load level of each of at least two processor cores of a processor according to a preconfigured level-dividing rule includes:
matching the utilization rate of each processor core in at least two processor cores with the utilization rate threshold range corresponding to each load level in the level division rule respectively;
and under the condition that the utilization rate of a first processor core in the at least two processor cores is determined to belong to the utilization rate threshold range corresponding to the ith load level, determining that the load level of the first processor core is the ith load level, wherein the first processor core is any one of the at least two processor cores, and i is a positive integer.
In a second aspect, the present application provides a multi-core load regulation device of a processor, the device comprising:
the system comprises a level determining module, a load determining module and a load determining module, wherein the level determining module is used for determining the load level of each processor core of at least two processor cores of a processor according to a preconfigured level dividing rule, and the load level is obtained by dividing according to the utilization rate of the processor cores;
the processing module is used for determining load regulation and control rules of at least two processor cores according to the difference value between the load grades of every two processor cores;
and the regulation and control module is used for finishing dynamic regulation and control of the loads of at least two processor cores according to a preset regulation and control strategy under the condition that the dynamic regulation and control of the loads of at least the processor cores are determined according to the load regulation and control rule.
In a third aspect, an electronic device is provided, which includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
the processor is configured to implement the steps of the multi-core load regulation method of the processor according to any one of the embodiments of the first aspect when executing the program stored in the memory.
In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for multicore load regulation of the processor according to any of the embodiments of the first aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
according to the method provided by the embodiment of the application, the load level of each of at least two processor cores of the processor is determined according to the pre-configured level division rule. And then, determining load regulation and control rules of the at least two processor cores according to the difference between the load grades of every two processor cores, and completing dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy under the condition that the load regulation and control rules are determined to dynamically regulate and control one or more loads of the at least two processor cores. By monitoring the load condition of each core in real time, the task amount on each processor core can be flexibly and dynamically regulated and controlled, so that the processor can be ensured to operate in a better operation environment at every moment, the time for repeatedly testing whether the load condition exists in the operation load of the processor by using static configuration in the prior art is saved, and the operation efficiency of the processor can be improved by the method.
Drawings
Fig. 1 is a schematic flowchart of a multi-core load control method for a processor according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for determining a load level of each of at least two processor cores of a processor according to a pre-configured hierarchical rule according to the present invention;
FIG. 3 is a flowchart illustrating a specific example of load level classification for each processor core according to the present invention;
fig. 4 is a schematic flowchart of a method for implementing a regulation and control strategy according to the present invention when a difference between load levels of any two processor cores is greater than or equal to a first preset difference threshold;
fig. 5 is a schematic structural diagram of a multi-core load control device of a processor according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained with reference to specific embodiments, which are not to be construed as limiting the embodiments of the present invention.
As introduced above, in the current vehicle MCU real-time operating system, the tasks in each processor core are configured in a static manner. That is, the total number of tasks to be executed in the MCU, the execution period of each task, and the priority of each task are known in advance. And distributing all tasks to different processor cores according to different characteristics of each task, the total amount of the tasks and the like. And writing specific configuration matters into the program codes, and judging whether the task allocation can cause the condition that one or more processor cores have overload, namely the condition that the utilization rate of the processor cores is too high, in a test mode. If one or more processor cores are overloaded, the task quantity and the task type corresponding to different processor cores are required to be re-planned. To ensure that each processor core is in a better operating environment (e.g., a more load balanced operating environment). The whole process consumes time and labor, and the situation that one or more processor cores are overloaded and other processor cores are under 'too few tasks' in a certain subsequent state or at certain time cannot be avoided.
Therefore, the embodiment of the application provides a multi-core load regulation and control method for a processor, which considers the requirement of current domain control, and dynamically adjusts the number of tasks on each processor core by monitoring the utilization rate of each processor core on the processor in real time under the condition of ensuring the real-time performance of a vehicle-mounted MCU operating system, so as to ensure that a CPU runs in a better running environment at every moment, and save a large amount of manpower, material resources, time cost and the like occupied by repeatedly testing whether the running load of the CPU is in the better running environment during static configuration. Moreover, because the number of tasks on each processor core is dynamically adjusted all the time, there is no need to worry about that after the adjustment, one or more processor cores are overloaded and other processor cores are in a condition of "too few tasks" in a subsequent operating state or at a certain time.
Specifically, a flow of a multi-core load regulation method for a processor provided in the embodiment of the present application may be shown in fig. 1. Before describing the method steps of the embodiments of the present application, the preparation work done before the method steps will be described first. See specifically below:
a real-time operating system is run first, and then corresponding tasks are executed on respective processor cores of a processor (e.g., CPU) in sequence in accordance with a static configuration. Then, the operation steps of the method are executed.
In an alternative example, the tasks executed on the respective processor cores may include, but are not limited to, the following, for example:
the system comprises a power management (external voltage monitoring) task, a storage management task, a calibration management task, a radar data acquisition task, a Controller Area Network (CAN) data-to-Ethernet transmission task, a state management task, an arbitration state machine management task, a Network management task and the like.
The method comprises the following steps:
And the load grades are obtained by dividing according to the utilization rate of the processor cores.
The processor core usage, which is actually the processor core resources (e.g., CPU usage) occupied by the running program, represents the situation of the machine running the program at a certain point in time.
In an alternative embodiment, before performing step 110, the method may further include the steps of:
and traversing the utilization rate of each of the at least two processor cores in turn at fixed time intervals.
In a specific example, it may be to traverse the utilization rate of the processor Core (Core _ loading) in the CPU by a timer, for example, every 5 milliseconds. The specific traversal order is, for example, traversal from processor core 1 to processor core n.
After the utilization rate of each processor core is obtained, the load level of each processor core can be determined according to the utilization rate of each processor core.
In an alternative example, the ranking rule is described in the following method steps, and in particular in fig. 2.
The first processor core is any one of the at least two processor cores, and i is a positive integer.
More specifically, for example, the load class includes 6 stages. Then, when the utilization rate of a first processor core in the at least two processor cores is smaller than a first preset utilization rate threshold value, determining the load level of the first processor core as a first load level;
or when the utilization rate of the first processor core is greater than or equal to a first preset utilization rate threshold and is less than a second preset utilization rate threshold, determining the load level of the first processor core as a second load level;
or when the utilization rate of the first processor core is greater than or equal to a second preset utilization rate threshold and is less than a third preset utilization rate threshold, determining the load level of the first processor core as a third load level;
or when the utilization rate of the first processor core is greater than or equal to a third preset utilization rate threshold and less than a fourth preset utilization rate threshold, determining the load level of the first processor core as a fourth load level;
or when the utilization rate of the first processor core is greater than or equal to a fourth preset utilization rate threshold and less than a fifth preset utilization rate threshold, determining the load level of the first processor core as a fifth load level;
or when the utilization rate of the first processor core is greater than or equal to a fifth preset utilization rate threshold value, determining that the load level of the first processor core is a sixth load level, wherein the first processor core is any one of the at least two processor cores.
Fig. 3 shows a flowchart for specifically dividing the load level of each processor core. See in particular the following:
a) when the utilization rate of the processor core is less than 30% (a first preset utilization threshold), determining the load level to be level 1;
b) when the processor core utilization rate is 30% < 50% (a second preset utilization threshold), determining the load level to be level 2;
c) when the processor core utilization rate is 50% < 60% (a third preset utilization threshold), determining the load level to be 3 levels;
d) when the processor core utilization rate is 60% < 70% (a fourth preset utilization threshold), determining the load level to be 4 levels;
e) when 70% <processorcore utilization rate < 80% (fifth preset utilization threshold), determining the load level as 5 level;
f) when the processor core usage > is 80%, the load level is determined to be 6 levels.
As described above, this is an exemplary implementation process for determining the load level of each of the at least two processor cores of the processor according to the preconfigured level division rule, and other exemplary processes are not described herein again.
And step 120, determining a load regulation rule for at least two processor cores according to the difference value between the load grades of every two processor cores.
Specifically, after determining the different load levels, the difference between the load levels of each two processor cores is determined. For example, a processor includes 3 processor cores. The load level of the first processor core is level 1, the load level of the second processor core is level 2, and the load level of the third processor core is level 4. Then, the difference between the load levels of the first processor core and the second processor core is 1, the difference between the load levels of the first processor core and the third processor core is 3, and the difference between the load levels of the second processor core and the third processor core is 2.
Based on the difference between the load grades of any two processor cores in the three processor cores, the corresponding load regulation and control rules are different.
In a specific example, the load regulation rule is determined to dynamically regulate the load leveling in at least two processor cores, for example, when a difference between the load levels of any two processor cores is greater than or equal to a first preset difference threshold.
Or when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold value and larger than or equal to a second preset difference threshold value continues for a preset time period, and the load levels of at least two processor cores are larger than or equal to the first load level, determining that the load regulation rule is to dynamically regulate and control the loads of at least two processor cores.
In another specific example, when the difference between the load levels of all the processor cores is smaller than the second preset difference threshold, or when the difference between the load levels of any two processor cores is smaller than the first preset difference threshold and greater than or equal to the second preset difference threshold and does not continue for the preset time period, it is determined that the load regulation and control rule does not perform any adjustment processing on the loads of the processor cores.
For example, the first preset difference threshold is 2, and the second threshold difference is preset to 1.
That is, if the load levels corresponding to any two processor cores are the same, no adjustment needs to be made to the tasks executed in the processor cores. Only when there is a certain difference between the load levels corresponding to any two processor cores, there may be a case of unbalanced load, and then a certain adjustment is made to the tasks of the processor cores.
And step 130, when determining to dynamically regulate and control the loads of the at least two processor cores according to the load regulation and control rule, completing the dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy.
Specifically, in a possible case, when the difference between the load levels of any two processor cores is greater than or equal to the first preset difference threshold, the preset regulation and control policy includes the following contents, which is specifically shown in fig. 4.
For example, when the difference between the load levels between any two of at least two processor cores in the processor exceeds 2, the following regulation strategy is executed. The method specifically comprises the following steps:
and step 410, sorting the at least two processor cores according to the size of the load level.
And step 420, determining the task adjustment times according to the total number of the processor cores.
And 430, respectively adjusting the tasks of the processor cores ordered at the (n + 1) -i) th time and the processor cores ordered as the i-th time, and adjusting the tasks with preset number in the processor cores with high load level to the processor cores with low load level.
Wherein i is a positive integer, and n is the total number of processor cores.
Specifically, assume that the number of processor cores is 3. The load grades corresponding to the processor cores 1 to 3 are respectively distributed into 1 grade, 2 grade and 4 grade. Then, the level difference between the processor core 1 and the processor core 3 is 3, the level difference between the processor core 1 and the processor core 2 is 1, and the level difference between the processor core 2 and the processor core 3 is 2.
Processor cores 1 through 3 are ordered. The specific sorting rule may be from large to small or from small to large. For example, in the present embodiment, the processor cores are sorted in the descending order, and then the sorted order is processor core 3, processor core 2, and processor core 1.
And then determining the task adjustment times according to the total number of the processor cores.
Optionally, when determining the number of times of adjustment, for example, the following method may be used to obtain:
and dividing the total number of the processor cores by 2 to obtain a module value, namely the task adjusting times.
As described above for the example, the total number of processor cores is 3, and the modulus value is 1 by dividing 3 by 2. Then the number of adjustment tasks is 1.
At the ith time, i is a positive integer and n is the total number of processor cores. And if the value is 1 for the first time, adjusting the tasks of the processor cores ordered as 3+1-1(n +1-i) and the processor cores ordered as 1(i) for the first time. During specific adjustment, the tasks with the preset number in the processor cores with high load levels are adjusted to the processor cores with low load levels.
In the example described above, the tasks of the first processor core and the 3 rd processor core are adjusted. The specific adjustment process is to adjust the tasks of the preset number in the processor core 3 into the processor core 1.
The number of specific adjustments is typically no greater than the difference between the number of tasks in processor core 3 and processor core 1. Otherwise, the adjustment is meaningless.
In an optional example, before the ith time, respectively adjusting tasks of the processor cores ordered at n +1-i and the processor core ordered as ith, the method further includes:
and determining the preset number of the tasks to be transferred by the processor core of the (n + 1) -th-i th order according to the load level of the processor core of the (n + 1) -th order and the load level of the processor core of the (i) th order.
Specifically, the preset number may be determined according to a difference between the load level of the processor core ordered as the (n + 1) -th and the load level of the processor core ordered as the (i) -th.
For example, 1, when the difference value is 5, 4 tasks in the processor cores ranked as n +1-i are transferred to the processor core ranked as i to run in the next execution cycle.
And 2, when the difference value is 4, transferring 3 tasks in the processor cores ranked as n +1-i to the processor core ranked as i to run in the next execution cycle.
3. When the difference is 3, transferring 2 tasks in the processor cores sequenced as the n +1-i to the processor core sequenced as the i for running in the next execution cycle;
4. and when the difference is 2, transferring 1 task in the processor cores sequenced as the n +1-i to the processor core sequenced as the i for running in the next execution cycle.
Of course, the task amount allocation may be accomplished in other manners besides the above-described manner of allocating the task amount. For example, counting the difference in the number of tasks on the two processor cores. And then distributing the difference quantity to determine the task quantity to be transferred according to a certain percentage. For example, the difference between the task amounts of the two processor cores is 50. Then selecting 10 percent of the task size to be transferred to the processor core with the smaller task size.
Optionally, when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold and is greater than or equal to a second preset difference threshold for a preset time period, and the load levels of at least two processor cores are greater than or equal to the first load level, the preset regulation and control policy includes:
when the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to a first load level and less than a second load level, performing primary optimization processing on codes corresponding to the processors;
or when the load levels of a preset number of processor cores in the at least two processor cores are greater than or equal to the second load level and less than the third load level, performing secondary optimization processing on codes corresponding to the processor, or replacing the processor; the optimization degree of the secondary optimization is higher than that of the primary optimization, and the secondary optimization can be understood as reinforced optimization.
Or when the load levels of a preset number of processor cores in the at least two processor cores are greater than or equal to the third load level, replacing the processor.
Further optionally, when the load levels of a preset number of processor cores of the at least two processor cores are smaller than the first load level, no processing is performed.
In one specific example, for example:
if the difference value of every two load levels in all the processor cores is less than or equal to 1, the task switching core processing is not carried out, but the level of the highest load in the label needs to be judged. The highest level is determined, which is primarily to determine that if the highest load level is also low, no load balancing operations are considered. That is, even if the difference between the load levels of any two processor cores is less than the first preset difference threshold and greater than or equal to the second preset difference threshold for the preset time period, no load imbalance is caused because the load levels of a preset number of processor cores of the at least two processor cores are less than the first load level, and the processor may not perform any processing because each processor core is in a high-speed operation state.
However, after the operation is performed for a period of time, the difference between the two load levels is still less than or equal to 1, and the load levels of a preset number of processor cores in the at least two processor cores are all greater than or equal to a first load level (the first load level is, for example, 4), then the following processing is performed:
a) if more than 50% of the processor cores are at load level 6, replacement of other processors is recommended.
b) If more than 50% of the processor cores are at load level 5, then it is recommended to enforce optimized code, or replace other processors.
c) If more than 50% of the processor cores are at load level 4, this indicates an unexpected chance that the code needs to be optimized at any time.
d) If more than 50% of the processor cores are at the load level of 3 or below, no processing is performed, and the current MCU running state is good.
According to the multi-core load regulation and control method of the processor, the load level of each processor core in at least two processor cores of the processor is determined according to the pre-configured level division rule. And then, determining load regulation and control rules of the at least two processor cores according to the difference between the load grades of every two processor cores, and completing dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy under the condition that the load regulation and control rules are determined to dynamically regulate and control one or more loads of the at least two processor cores. By monitoring the load condition of each core in real time, the task amount on each processor core can be flexibly and dynamically regulated and controlled, so that the processor can be ensured to operate in a better operation environment at every moment, the time for repeatedly testing whether the load condition exists in the operation load of the processor by using static configuration in the prior art is saved, and the operation efficiency of the processor can be improved by the method.
In the above, for several embodiments of the method for controlling the multi-core processor based on load monitoring provided by the present application, other embodiments of controlling the multi-core processor based on load monitoring provided by the present application are introduced and described below, specifically referring to the following.
Fig. 5 is a schematic structural diagram of a multi-core load control device of a processor according to an embodiment of the present invention, where the device includes: a grade determination module 501, a processing module 502, and a conditioning module 503.
A level determining module 501, configured to determine a load level of each of at least two processor cores of a processor according to a preconfigured level division rule, where the load level is obtained by dividing according to a utilization rate of the processor cores;
a processing module 502, configured to determine a load regulation rule for at least two processor cores according to a difference between load levels of every two processor cores;
the adjusting and controlling module 503 is configured to complete dynamic adjustment and control of the loads of the at least two processor cores according to a preset adjusting and controlling policy under the condition that it is determined according to the load adjusting and controlling rule that the loads of the at least two processor cores are dynamically adjusted and controlled.
Optionally, the processing module 502 is specifically configured to determine that the load regulation rule is to dynamically regulate and control the loads of at least two processor cores when the difference between the load levels of any two processor cores is greater than or equal to a first preset difference threshold;
or, when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold value and larger than or equal to a second preset difference threshold value, the situation lasts for a preset time period, and when the load levels of at least two processor cores are larger than or equal to the first load level, the load regulation rule is determined to dynamically regulate and control the loads of at least two processor cores.
Optionally, when the difference between the load levels of any two processor cores is greater than or equal to a first preset difference threshold, the preset regulation and control strategy includes:
sequencing at least two processor cores according to the size of the load grade;
determining the task adjustment times according to the total number of the processor cores;
and respectively adjusting the tasks of the processor cores ordered in the (n + 1) -i th time and the processor cores ordered as the i-th time at the ith time, and adjusting the tasks with preset number in the processor cores with high load grade to the processor cores with low load grade, wherein i is a positive integer, and n is the total number of the processor cores.
Optionally, the processing module 502 is specifically configured to divide the total number of the processor cores by 2 to obtain a module value, which is the task adjustment number.
Optionally, the processing module 502 is further configured to determine the preset number of tasks to be transferred by the processor core of the n +1 th-i according to the load level of the processor core of the n +1 th-i and the load level of the processor core of the i.
Optionally, when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold and greater than or equal to a second preset difference threshold, the preset regulation and control policy continues for a preset time period, and when the load levels of at least two processor cores are greater than or equal to the first load level, the preset regulation and control policy includes:
performing first-level optimization processing on codes corresponding to the processors under the condition that the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to a first load level and smaller than a second load level;
or, under the condition that the load levels of a preset number of processor cores in the at least two processor cores are greater than or equal to the second load level and less than the third load level, performing secondary optimization processing on codes corresponding to the processors, or replacing the processors;
or the processor is replaced when the load level of a preset number of processor cores in the at least two processor cores is greater than or equal to the third load level.
Optionally, when the load levels of a preset number of processor cores in the at least two processor cores are smaller than the first load level, no processing is performed.
Optionally, the apparatus further comprises: a traversal module 504;
and the traversing module 504 is configured to sequentially traverse the utilization rate of each of the at least two processor cores at fixed time intervals, so as to determine the load level of each processor core according to the utilization rate of each processor core in the following.
Optionally, the processing module 502 is specifically configured to match the utilization rate of each of the at least two processor cores with a utilization rate threshold range corresponding to each load level in the level division rule, respectively;
and under the condition that the utilization rate of a first processor core in the at least two processor cores is determined to belong to the utilization rate threshold range corresponding to the ith load level, determining that the load level of the first processor core is the ith load level, wherein the first processor core is any one of the at least two processor cores, and i is a positive integer.
The functions executed by each component in the multi-core processor regulation and control device based on load monitoring provided by the embodiment of the invention are described in detail in any method embodiment, and therefore, the detailed description is omitted here.
The multi-core load regulation and control device of the processor determines the load level of each processor core in at least two processor cores of the processor according to the pre-configured level division rule. And then, determining load regulation and control rules of the at least two processor cores according to the difference between the load grades of every two processor cores, and completing dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy under the condition that the load regulation and control rules are determined to dynamically regulate and control one or more loads of the at least two processor cores. By monitoring the load condition of each core in real time, the task amount on each processor core can be flexibly and dynamically regulated and controlled, so that the processor can be ensured to operate in a better operation environment at every moment, the time for repeatedly testing whether the load condition exists in the operation load of the processor by using static configuration in the prior art is saved, and the operation efficiency of the processor can be improved by the method.
As shown in fig. 6, an electronic device according to an embodiment of the present application includes a processor 111, a communication interface 112, a memory 113, and a communication bus 114, where the processor 111, the communication interface 112, and the memory 113 complete communication with each other through the communication bus 114.
A memory 113 for storing a computer program;
in an embodiment of the present application, when the processor 111 is configured to execute a program stored in the memory 113, the method for regulating and controlling a multi-core load of a processor according to any one of the foregoing method embodiments includes:
determining the load level of each processor core in at least two processor cores of the processor according to a pre-configured level division rule, wherein the load level is obtained by division according to the utilization rate of the processor cores;
determining load regulation and control rules of at least two processor cores according to the difference value between the load grades of every two processor cores;
and under the condition of determining to dynamically regulate and control the loads of the at least two processor cores according to the load regulation and control rule, completing the dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy.
Optionally, when the difference between the load levels of any two processor cores is greater than or equal to a first preset difference threshold, determining that the load regulation rule is to dynamically regulate and control the loads of at least two processor cores;
or, when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold value and larger than or equal to a second preset difference threshold value, the situation lasts for a preset time period, and when the load levels of at least two processor cores are larger than or equal to the first load level, the load regulation rule is determined to dynamically regulate and control the loads of at least two processor cores.
Optionally, when the difference between the load levels of any two processor cores is greater than or equal to a first preset difference threshold, the preset regulation and control strategy includes:
sequencing at least two processor cores according to the size of the load grade;
determining the task adjustment times according to the total number of the processor cores;
and respectively adjusting the tasks of the processor cores ordered in the (n + 1) -i th time and the processor cores ordered as the i-th time in the ith time, and adjusting the tasks with preset number in the processor cores with high load grade to the processor cores with low load grade, wherein i is a positive integer, and n is the total number of the processor cores.
Optionally, determining the task adjustment times according to the total number of the processor cores specifically includes:
and dividing the total number of the processor cores by 2 to obtain a module value, namely the task adjusting times.
Optionally, before the ith time, respectively adjusting the tasks of the processor cores ordered at n +1-i and the processor core ordered as ith, the method further includes:
and determining the preset number of the tasks to be transferred by the processor core of the (n + 1) -th-i th order according to the load level of the processor core of the (n + 1) -th order and the load level of the processor core of the (i) th order.
Optionally, when the difference between the load levels of any two processor cores is smaller than a first preset difference threshold and greater than or equal to a second preset difference threshold, the preset regulation and control policy continues for a preset time period, and when the load levels of at least two processor cores are greater than or equal to the first load level, the preset regulation and control policy includes:
performing first-level optimization processing on codes corresponding to the processors under the condition that the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to a first load level and smaller than a second load level;
or, under the condition that the load levels of a preset number of processor cores in the at least two processor cores are greater than or equal to the second load level and less than the third load level, performing secondary optimization processing on codes corresponding to the processors, or replacing the processors;
or the processor is replaced when the load level of a preset number of processor cores in the at least two processor cores is greater than or equal to the third load level.
Optionally, when the load levels of a preset number of processor cores of the at least two processor cores are smaller than the first load level, no processing is performed.
Optionally, before determining the load level of each of the at least two processor cores of the processor according to the preconfigured level division rule, the method further includes:
and traversing the utilization rate of each processor core in the at least two processor cores in sequence at fixed time intervals so as to determine the load level of each processor core according to the utilization rate of each processor core.
Optionally, determining a load level of each of at least two processor cores of the processor according to a preconfigured level division rule specifically includes:
matching the utilization rate of each processor core in at least two processor cores with the utilization rate threshold range corresponding to each load level in the level division rule respectively;
and under the condition that the utilization rate of a first processor core in the at least two processor cores is determined to belong to the utilization rate threshold range corresponding to the ith load level, determining that the load level of the first processor core is the ith load level, wherein the first processor core is any one of the at least two processor cores, and i is a positive integer.
The present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the multi-core load regulation and control method for the processor according to any one of the foregoing method embodiments.
It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. A method for multi-core load regulation of a processor, the method comprising:
determining the load level of each processor core of at least two processor cores of a processor according to a pre-configured level division rule, wherein the load level is obtained by division according to the utilization rate of the processor cores;
determining a load regulation and control rule for at least two processor cores according to the difference value between the load levels of every two processor cores;
and under the condition of determining to dynamically regulate and control the loads of the at least two processor cores according to the load regulation and control rule, completing the dynamic regulation and control of the loads of the at least two processor cores according to a preset regulation and control strategy.
2. The method of claim 1, wherein determining the load regulation rule for at least two processor cores according to a difference between load levels of each two processor cores comprises:
under the condition that the difference value between the load levels of any two processor cores is greater than or equal to a first preset difference value threshold value, determining that the load regulation and control rule is used for dynamically regulating and controlling the loads of at least two processor cores;
or, when the difference between the load levels of any two processor cores is smaller than the first preset difference threshold and larger than or equal to the second preset difference threshold, the situation lasts for a preset time period, and when the load levels of at least two processor cores are larger than or equal to the first load level, the load regulation rule is determined to dynamically regulate and control the loads of at least two processor cores.
3. The method of claim 2, wherein in the case that the difference between the load levels of any two processor cores is greater than or equal to a first preset difference threshold, the preset regulation and control strategy comprises:
sequencing at least two processor cores according to the size of the load grade;
determining the task adjustment times according to the total number of the processor cores;
and at the ith time, respectively adjusting the tasks of the processor cores ranked at the (n + 1) -i) th time and the tasks of the processor cores ranked as the ith time, and adjusting the preset number of tasks in the processor cores with high load level to the processor cores with low load level, wherein i is a positive integer, and n is the total number of the processor cores.
4. The method of claim 3, wherein determining the number of task adjustments according to the total number of processor cores specifically comprises:
and dividing the total number of the processor cores by 2 to obtain a module value, namely the task adjusting times.
5. The method of claim 3, wherein before adjusting the tasks of the processor cores ordered at n +1-i and the processor core ordered as i, respectively, at the i-th time, the method further comprises:
and determining the preset number of the tasks to be transferred by the processor core of the (n + 1) -th i-th order according to the load level of the processor core of the (n + 1) -th order and the load level of the processor core of the (i-th order).
6. The method of claim 2, wherein the preset regulation and control strategy comprises, when the difference between the load levels of any two processor cores is smaller than the first preset difference threshold and greater than or equal to a second preset difference threshold for a preset time period, and the load levels of at least two processor cores are greater than or equal to the first load level:
performing first-level optimization processing on codes corresponding to the processors under the condition that the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to a first load level and smaller than a second load level;
or, under the condition that the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to the second load level and less than a third load level, performing secondary optimization processing on a code corresponding to the processor, or replacing the processor;
or replacing the processor under the condition that the load levels of a preset number of processor cores in at least two processor cores are greater than or equal to the third load level.
7. The method of any of claims 1-6, wherein prior to determining the load level of each of the at least two processor cores of the processor according to the preconfigured levelization rule, the method further comprises:
and sequentially traversing the utilization rate of each processor core in at least two processor cores at fixed time intervals so as to determine the load level of each processor core according to the utilization rate of each processor core.
8. The method of claim 7, wherein determining a load level for each of at least two processor cores of a processor according to a preconfigured hierarchical classification rule comprises:
matching the utilization rate of each processor core in at least two processor cores with the utilization rate threshold range corresponding to each load level in the level division rule respectively;
and under the condition that the utilization rate of a first processor core in the at least two processor cores is determined to belong to the utilization rate threshold range corresponding to the ith load level, determining that the load level of the first processor core is the ith load level, wherein the first processor core is any one of the at least two processor cores, and i is a positive integer.
9. An apparatus for multi-core load regulation of a processor, the apparatus comprising:
the system comprises a level determining module, a load determining module and a load determining module, wherein the level determining module is used for determining the load level of each processor core of at least two processor cores of a processor according to a preconfigured level dividing rule, and the load level is obtained by dividing according to the utilization rate of the processor cores;
the processing module is used for determining load regulation and control rules of at least two processor cores according to the difference value between the load grades of every two processor cores;
and the regulation and control module is used for finishing the dynamic regulation and control of the loads of at least two processor cores according to a preset regulation and control strategy under the condition that the dynamic regulation and control of the loads of at least the processor cores are determined according to the load regulation and control rule.
10. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;
a memory for storing a computer program;
a processor for implementing the steps of the method for multi-core load regulation of a processor according to any one of claims 1 to 8 when executing a program stored in a memory.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for multicore load regulation by the processor of any one of claims 1 to 8.
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| CN116185582B (en) * | 2022-12-29 | 2024-03-01 | 国科础石(重庆)软件有限公司 | Multi-core scheduling method, device, vehicle, electronic equipment and medium |
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