CN114816254A

CN114816254A - Hard disk data access method, device, equipment and medium

Info

Publication number: CN114816254A
Application number: CN202210446406.7A
Authority: CN
Inventors: 董培强; 刘铁军; 韩大峰
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2022-07-29

Abstract

The application discloses a hard disk data access method, a device, equipment and a medium, which relate to the technical field of computers, and the method comprises the following steps: acquiring a target access request sent by a central processing unit aiming at target data; judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule; if the data type is large-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and a central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link; and if the data type is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to carry out data transmission so as to complete the access operation aiming at the target data through the second data transmission link. Therefore, the access speed of the hard disk is improved, and the time delay is reduced.

Description

Hard disk data access method, device, equipment and medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for accessing hard disk data.

Background

Currently, with the rapid development of electronic Technology and manufacturing process, in a computer system architecture, the operating frequency of a CPU (central processing unit) and a DDR (Double Data Rate, Double Data synchronous dynamic random access memory) is higher and higher, and the processing capability is stronger and stronger, while a large-capacity storage medium is also being developed, from a mechanical hard Disk to an SSD (Solid State Disk or Solid State Drive) based on SATA (Serial Advanced Technology Attachment, NVME (non-volatile memory Express, non-volatile memory host controller interface specification), the development speed of the large-capacity storage medium seriously lags behind the development speed of the CPU, how to improve the read/write access speed of the hard Disk IO (input \ output) becomes a key for affecting the performance of a computer system. Currently, in mass storage media devices, SSD solid state disks gradually replace traditional mechanical hard disks with their performance advantages. The SSD mainly includes SATA2.0\ SATA3.0\ pcie (peripheral Component Interconnect express) interface solid state disk, wherein the SSD based on NVME protocol specification has more excellent performance and gradually becomes a preferred design choice. But still remains a major bottleneck in computer system performance relative to CPU and DDR operating frequencies.

In summary, how to increase the access speed of the hard disk and reduce the latency is a problem to be solved urgently at present.

Disclosure of Invention

In view of this, the present invention provides a method, an apparatus, a device and a medium for accessing hard disk data, which can improve the access speed of the hard disk and reduce the time delay. The specific scheme is as follows:

in a first aspect, the present application discloses a hard disk data access method, including:

acquiring a target access request sent by a central processing unit of a host aiming at target data;

judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule;

if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link;

and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link.

Optionally, if the data type of the target data is large-capacity data, the data transmission is performed directly by using a first data transmission link between the double-data-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, so as to complete an access operation for the target data through the first data transmission link, where the method includes:

if the data type of the target data is high-capacity data and the operation type of the access operation in the target access request is a write operation, directly utilizing the first data transmission link to write the target data sent by the central processing unit into the double-rate synchronous dynamic random access memory;

writing the target data in the double-rate synchronous dynamic random access memory into the nonvolatile memory to complete the write operation of the target data.

if the data type of the target data is large-capacity data and the operation type of the access operation in the target access request is a read operation, transmitting the target data in the nonvolatile memory to the double-rate synchronous dynamic random access memory, so that the central processing unit can directly read the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link to complete the read operation of the target data.

Optionally, if the data type of the target data is small-capacity data, directly performing data transmission by using a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, so as to complete an access operation on the target data through the second data transmission link, where the data type of the target data is small-capacity data, and the method includes:

if the data type of the target data is small-capacity data and the operation type of the access operation in the target access request is a write operation, directly writing the target data sent by the central processing unit into the nonvolatile memory by using the second data transmission link to complete the write operation on the target data.

and if the data type of the target data is small-capacity data and the operation type of the access operation in the target access request is a read operation, sending the target data to the central processing unit by using the second data transmission link so as to complete the read operation of the target data.

Optionally, the sending the target data to the central processing unit by using the second data transmission link includes:

creating a data packet based on the target data in the non-volatile memory and sending the data packet to the central processor using the second data transmission link.

Optionally, the hard disk data access method further includes:

and realizing the communication between the host and the hard disk by utilizing a third target protocol.

In a second aspect, the present application discloses a hard disk data access device, including:

the request acquisition module is used for acquiring a target access request sent by a central processing unit of the host aiming at target data;

the judging module is used for judging the data type of the target data based on a preset large-capacity judging rule and a preset small-capacity judging rule;

the first access module is used for directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit which is established based on a first target protocol to carry out data transmission if the data type of the target data is high-capacity data, so as to complete the access operation aiming at the target data through the first data transmission link;

and the second access module is used for directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit which is established based on a second target protocol to carry out data transmission if the data type of the target data is the small-capacity data, so as to complete the access operation aiming at the target data through the second data transmission link.

In a third aspect, the present application discloses an electronic device comprising a processor and a memory; when the processor executes the computer program stored in the memory, the hard disk data access method disclosed in the foregoing is realized.

In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the hard disk data access method disclosed above.

Therefore, the target access request sent by the central processing unit of the host aiming at the target data is obtained; judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule; if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link; and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link. Therefore, the data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be carried out on the large-capacity data only through the first data link, and the double-rate synchronous dynamic random access memory in the host is not required any more, so that the data transmission speed is improved and the time delay is reduced when the large-capacity data is transmitted; according to the method and the device, for the small-capacity data, data transmission between the nonvolatile memory and the central processing unit can be carried out only through the second data link, and the double-rate synchronous dynamic random access memory in the host and the hard disk is not needed, so that the data transmission speed is improved and the time delay is reduced when the small-capacity data are transmitted; in summary, in the process of data transmission, the method and the device improve the data transmission speed, reduce the time delay, also improve the access speed of the hard disk, reduce the time delay, and also reduce the disturbance when accessing the double-rate synchronous dynamic random access memory.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a flow chart of a hard disk data access method provided in the present application;

FIG. 2 is a diagram illustrating a conventional hard disk data access method;

FIG. 3 is a flowchart of a specific hard disk data access method provided in the present application;

FIG. 4 is a flowchart of a specific hard disk data access method provided in the present application;

FIG. 5 is a diagram illustrating a hardware component of a hard disk data access method provided in the present application;

FIG. 6 is a diagram illustrating a firmware portion of a hard disk data access method provided in the present application;

FIG. 7 is a schematic flow chart of the CPU reading and writing a large-capacity data block provided by the present application;

FIG. 8 is a schematic flow chart of the CPU reading and writing small-capacity data blocks provided by the present application;

FIG. 9 is a block diagram of a hard disk data access device according to the present application;

fig. 10 is a block diagram of an electronic device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The current access speed of the SSD solid state disk is slow, which becomes a main bottleneck of computer performance. In order to overcome the problems, the application provides a hard disk data access scheme, which can improve the access speed of a hard disk and reduce the time delay.

Referring to fig. 1, an embodiment of the present application discloses a hard disk data access method, including:

step S11: and acquiring a target access request sent by a central processing unit of the host aiming at the target data.

In the embodiment of the application, there are two main methods for accessing hard disk data in the existing method. The first method is based on the SATA Interface, the SSD (solid state disk) of the AHCI (Advanced Host Controller Interface) protocol specification, and this method only has one queue between the computer and the storage device in the SATA on the hardware level, even if there are multiple CPUs, all requests can only pass through such a narrow road. Meanwhile, the external Controller (PCH) of the SATA and sas (serial Attached scsi) interfaces and the CPU also cause extra delay, and in terms of a software layer, each command of the AHCI needs to read 4 registers, which consumes 8000 CPU cycles, thereby causing delay of about 2.5 microseconds. The second method, as shown in fig. 2, is an SSD based on PCIe interface and NVME protocol specification, and in the hardware level, the NVME SSD uses PCIe bus for transmission, so that the bandwidth is significantly increased. Meanwhile, the NVMe protocol can have 64K queues at most, the multiple queues are responsible for exerting the parallel capability of the flash memory, each CPU or core can have one queue, the concurrency degree is greatly improved, and the throughput rate is greatly improved; specifically, the flow of accessing the NVME SSD by the CPU is as follows: the SSD is inserted into a PCIe slot of a HOST system in a PCIe card inserting mode, when a CPU accesses large-capacity data, the CPU sets NVME queue information to inform the SSD, then a controller on the SSD side reads the queue information to control a data management module and a DMA (Direct Memory Access), the data in NAND FLASH is transmitted to a HOST side RDIMM (registered DIMM) through the DMA (Direct Memory Access), an interrupt is generated to inform the CPU, and then the CPU accesses the RDIMM through a CACHE (CACHE Memory) to read the data. Data flow process NAND FLASH → board DDR4 → DMA → CPU DDR4 → CACHE. When the CPU performs small-capacity or IO data reading and writing, the NVME driver converts the read information into a PIO (programmable Input-Output) operation, sends a TLP (Transaction Layer Packet), and then the SSD side reads NAND FLASH data, sends the data to the CPU buffer in the form of a completion Packet, and reads the data. Therefore, the technical disadvantages of the above method are mainly that, firstly, the total delay time when the CPU accesses the SSD storage device is large, and the access efficiency is low; secondly, the CPU accesses CACHE and DDR, and the disturbance of the whole link is large, so that the access delay of the SSD is large; third, both CPU DMA frequent interrupts and PCIe NVME drivers impact performance. Therefore, the application provides a hard disk data access method.

In the embodiment of the present application, a cxl (computer Express link) protocol is used to perform communication between a host and a hard disk. The CXL protocol includes a cxl.mem sub-protocol, a cxl.cache sub-protocol, and a cxl.io sub-protocol, and further includes a CXL controller (CXL engine). The third target protocol, i.e. the cxl.io subprotocol, is used to enable communication between the host and the hard disk. It is noted that CXL is a new computing interconnect standard.

In the embodiment of the application, a total link is constructed first, the total link is initialized, then a target access request sent by a central processing unit of a host for target data is obtained, specifically, the central processing unit sends the target access request, generates an access request packet and sends the access request packet to a hard disk, after the hard disk obtains the access request packet, the access request packet is analyzed to obtain the target access request, more specifically, a CXL total link is constructed, the CXL total link is initialized, and the CXL. io request packet is sent out through a CXL controller (CXL engine) of the host. And then, receiving the CXL.io request packet by using a CXL controller (CXL engine) in the SSD and analyzing the CXL.io request packet to obtain a target access request. The target access request includes, but is not limited to, data source information, data type information, and a read-write flag.

Step S12: and judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule.

In the embodiment of the application, the data type of the target data is judged based on a preset large-capacity judgment rule and a preset small-capacity judgment rule, and then corresponding access operation is carried out on the target data based on the data type.

Step S13: and if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to perform data transmission so as to complete access operation aiming at the target data through the first data transmission link.

In the embodiment of the application, if the data type of the target data is large-capacity data, whether an access operation is a read operation or a write operation is judged based on a read-write flag, and then data transmission is performed directly by using a first data transmission link between a double-rate synchronous dynamic random access memory and a central processing unit, which is established based on a first target protocol, so that the read operation or the write operation for the target data is completed through the first data transmission link.

It should be noted that the first target protocol is cxl.mem subprotocol, cxl.mem implements direct management of MEM (memory) on the SSD by the CPU, and may also implement MEM as DDR (double data rate synchronous dynamic random access memory), so that the CPU can directly access the double data rate synchronous dynamic random access memory on the SSD through the first target protocol, thereby reducing the step of the CPU passing through the double data rate synchronous dynamic random access memory on the host, increasing the speed, and reducing the delay. Note that initialization of the CXL link is resumed after completion of a read operation or a write operation.

It should be noted that, when performing an access operation on large-capacity data, the first target protocol and the third target protocol, that is, the cxl.mem subprotocol and the cxl.io subprotocol, are mainly used.

Step S14: and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link.

In the embodiment of the application, if the data type of the target data is small-capacity data, whether an access operation is a read operation or a write operation is judged based on a read-write flag, and then a second data transmission link between a nonvolatile memory and the central processing unit, which is established based on a second target protocol, is directly used for data transmission, so that the read operation or the write operation aiming at the target data is completed through the second data transmission link.

It should be noted that the second target protocol is a cxl.cache subprotocol, the cxl.cache uses a firmware portion corresponding to a hard disk, that is, an FPGA (Field Programmable Gate Array), an internal RAM is used as a CPU CACHE, and is uniformly managed by a CPU CACHE consistency management module, and the CPU CACHE can be understood as a buffer area of a nonvolatile memory. Note that initialization of the CXL link is resumed after completion of a read operation or a write operation.

It should be noted that, when performing an access operation on large-capacity data, the second target protocol and the third target protocol, that is, the cxl.cache subprotocol and the cxl.io subprotocol, are mainly used.

Therefore, the target access request sent by the central processing unit of the host aiming at the target data is obtained; judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule; if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link; and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link. Therefore, the data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be carried out on the large-capacity data only through the first data link, and the double-rate synchronous dynamic random access memory in the host is not required any more, so that the data transmission speed is improved and the time delay is reduced when the large-capacity data is transmitted; according to the method and the device, for the small-capacity data, data transmission between the nonvolatile memory and the central processing unit can be carried out only through the second data link, and the double-rate synchronous dynamic random access memory in the host and the hard disk is not needed, so that the data transmission speed is improved and the time delay is reduced when the small-capacity data are transmitted; in summary, the present application improves the data transmission speed and reduces the delay, i.e. the access speed of the hard disk is improved, the delay is reduced, and the disturbance when accessing the double-rate synchronous dynamic random access memory is also reduced, in addition, because there is no DMA, there is no frequent interruption, and the access speed is improved.

Referring to fig. 3, an embodiment of the present application discloses a specific hard disk data access method, including:

step S21: and acquiring a target access request sent by a central processing unit of the host aiming at the target data.

For other more specific processing procedures in step S21, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Step S22: and judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule.

For other more specific processing procedures in step S22, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Step S23: if the data type of the target data is high-capacity data and the operation type of the access operation in the target access request is a write operation, directly utilizing the first data transmission link to write the target data sent by the central processing unit into the double-rate synchronous dynamic random access memory; writing the target data in the double-rate synchronous dynamic random access memory into the nonvolatile memory to complete the write operation of the target data.

In the embodiment of the present application, if the data type of the target data is large-capacity data, whether an access operation is a read operation or a write operation is determined based on a read-write flag, and if the operation type of the access operation in the target access request is a write operation, the target data sent by the central processing unit is written into the double-rate synchronous dynamic random access memory by directly using the first data transmission link; writing the target data in the double-rate synchronous dynamic random access memory into the nonvolatile memory to complete the write operation of the target data. It should be noted that the CXL protocol also includes a CXL controller (CXL engine) for making the read/write determination, and the CXL controller controls the use of the CXL protocol.

In this embodiment of the present application, the process of directly using the first data transmission link to write the target data sent by the central processing unit into the double-data-rate synchronous dynamic random access memory specifically includes: and generating an interrupt to inform a CPU (Central processing Unit) to send target data, writing the target data sent by the CPU into the double-rate synchronous dynamic random access memory through a first data transmission link by the CPU, and then utilizing a bus arbitration management module and a buffer area read-write module. Writing target data in the double-rate synchronous dynamic random access memory into the nonvolatile memory through the nonvolatile memory controller, then generating an interrupt again to inform the CPU that the writing operation is finished, and then initializing the CXL link again.

It should be noted that the first data transmission link is a data transmission link between the ddr sdram and the cpu, which is established based on a first target protocol; the first target protocol is a cxl.mem subprotocol; the generation of the interrupt to inform the CPU of sending the target data or inform the CPU of completing the write operation is completed by the CXL.io subprotocol; in the application, the double-rate synchronous dynamic random access memory is an MEM space of the SSD; the bus arbitration management module and the buffer area read-write module are positioned at a firmware part corresponding to the hard disk, namely FPGA firmware, and are responsible for transmitting data in the nonvolatile memory; the nonvolatile memory is FLASH.

Step S24: if the data type of the target data is large-capacity data and the operation type of the access operation in the target access request is a read operation, transmitting the target data in the nonvolatile memory to the double-rate synchronous dynamic random access memory, so that the central processing unit can directly read the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link to complete the read operation of the target data.

In this embodiment of the present application, if the data type of the target data is large-capacity data, whether an access operation is a read operation or a write operation is determined based on a read-write flag, and if the operation type of the access operation in the target access request is a read operation, the target data in the nonvolatile memory is transmitted to the double-rate synchronous dynamic random access memory, so that the central processing unit directly reads the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link to complete the read operation on the target data.

In the embodiment of the application, the target data is read from the nonvolatile memory and transmitted to the double-rate synchronous dynamic random access memory according to the address information of the target data in the nonvolatile memory, and then an interrupt is generated to inform the CPU to read the data, so that the CPU reads the data from the double-rate synchronous dynamic random access memory of the SSD by using the first data transmission link, and the read operation is completed.

It should be noted that the step of transferring the target data from the nonvolatile memory to the double-rate synchronous dynamic random access memory is completed by the bus arbitration management module and the buffer read-write module; the first data transmission link is a data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol.

Step S25: and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link.

For other more specific processing procedures in step S25, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Therefore, the method comprises the steps of obtaining a target access request sent by a central processing unit of a host aiming at target data; judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule; if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link; and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between the nonvolatile memory and the central processing unit, which is established based on a second target protocol, to perform data transmission so as to complete the access operation aiming at the target data through the second data transmission link. Therefore, the data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be carried out on the large-capacity data only through the first data link, and the double-rate synchronous dynamic random access memory in the host is not required any more, so that the data transmission speed is improved and the time delay is reduced when the large-capacity data is transmitted; according to the method and the device, for the small-capacity data, data transmission between the nonvolatile memory and the central processing unit can be carried out only through the second data link, and the double-rate synchronous dynamic random access memory in the host and the hard disk is not needed, so that the data transmission speed is improved and the time delay is reduced when the small-capacity data are transmitted; in summary, in the process of data transmission, the method and the device improve the data transmission speed, reduce the time delay, also improve the access speed of the hard disk, reduce the time delay, and also reduce the disturbance when accessing the double-rate synchronous dynamic random access memory.

Referring to fig. 4, an embodiment of the present application discloses a specific hard disk data access method, including:

step S31: and acquiring a target access request sent by a central processing unit of the host aiming at the target data.

For other more specific processing procedures in step S31, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Step S32: and judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule.

For other more specific processing procedures in step S32, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Step S33: and if the data type of the target data is high-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to perform data transmission so as to complete access operation aiming at the target data through the first data transmission link.

For other more specific processing procedures in step S33, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Step S34: if the data type of the target data is small-capacity data and the operation type of the access operation in the target access request is a write operation, directly writing the target data sent by the central processing unit into the nonvolatile memory by using the second data transmission link to complete the write operation on the target data.

In this embodiment of the present application, if the data type of the target data is small-capacity data, whether an access operation is a read operation or a write operation is determined based on a read-write flag, and if the operation type of the access operation in the target access request is a write operation, the target data sent by the central processing unit is directly written into the nonvolatile memory by using the second data transmission link, so as to complete the write operation on the target data.

In this embodiment of the application, the step of directly writing the target data sent by the central processing unit into the nonvolatile memory by using the second data transmission link is specifically to acquire a data packet generated by the CPU based on the target data, analyze the data packet to obtain the target data, write the target data into a buffer area of the nonvolatile memory, and write the target data in the buffer area of the nonvolatile memory into the nonvolatile memory by using the bus arbitration management module and the buffer area read-write module. Note that, before the CPU generates the data packet, the host generates a completion packet, and notifies the CPU of data transmission using the completion packet.

Note that the process of generating the data completion packet and notifying the CPU of data transmission is performed by the CXL controller (CXL engine); the data packet is a CXL.cache data packet; the process of parsing the packet is performed by a CXL controller (CXL engine).

Step S35: and if the data type of the target data is small-capacity data and the operation type of the access operation in the target access request is a read operation, sending the target data to the central processing unit by using the second data transmission link so as to complete the read operation of the target data.

In this embodiment of the application, if the data type of the target data is small-capacity data, whether an access operation is a read operation or a write operation is determined based on a read-write flag, if the operation type of the access operation in the target access request is a read operation, the target data is sent to the central processing unit by using the second data transmission link to complete the read operation on the target data, and specifically, a data packet is created based on the target data in the nonvolatile memory, and the data packet is sent to the central processing unit by using the second data transmission link.

It should be noted that the target data in the non-volatile memory may be written into a buffer of the non-volatile memory, and then the target data in the buffer is sent to the central processing unit by using the second data transmission link, so as to complete the read operation of the target data; specifically, the target data in the nonvolatile memory may be written into a buffer of the nonvolatile memory, then a data packet is created based on the target data in the buffer, and the data packet is sent to the central processing unit by using the second data transmission link.

It should be noted that the step of writing the target data in the nonvolatile memory into the buffer area of the nonvolatile memory is completed by the bus arbitration management module and the buffer area read-write module; the CXL controller (CXL engine) reads the target data from the buffer area and generates a data message; the data message is a CXL.

Therefore, the target access request sent by the central processing unit of the host aiming at the target data is obtained; judging the data type of the target data based on a preset large-capacity judgment rule and a preset small-capacity judgment rule; if the data type of the target data is large-capacity data, directly utilizing a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, which is established based on a first target protocol, to carry out data transmission so as to complete access operation aiming at the target data through the first data transmission link; and if the data type of the target data is small-capacity data, directly utilizing a second data transmission link between a nonvolatile memory and the central processing unit, which is established based on a second target protocol, to carry out data transmission so as to complete the access operation aiming at the target data through the second data transmission link. Therefore, the data transmission between the double-rate synchronous dynamic random access memory and the central processing unit can be carried out on the large-capacity data only through the first data link, and the double-rate synchronous dynamic random access memory in the host is not needed any more, so that the data transmission speed is improved and the time delay is reduced when the large-capacity data is transmitted; according to the method and the device, for the small-capacity data, data transmission between the nonvolatile memory and the central processing unit can be carried out only through the second data link, and the double-rate synchronous dynamic random access memory in the host and the hard disk is not needed, so that the data transmission speed is improved and the time delay is reduced when the small-capacity data are transmitted; in summary, in the process of data transmission, the method and the device improve the data transmission speed, reduce the time delay, also improve the access speed of the hard disk, reduce the time delay, and also reduce the disturbance when accessing the double-rate synchronous dynamic random access memory.

Referring to fig. 5, the hardware components disclosed in the present application are shown. The FPGA is used as a main processing chip to support 2 paths of DDR4, wherein one path of data management module is used for managing metadata, FLASH block mapping and the like, and the other path of data management module is used as a cache of FLASH array data and is accessed by the data management module and the CXL protocol together. The memory subsystem comprises a FLASH array, a FLASH controller, a data management module and a DDR 4. The interface adopts the CXL agreement, is compatible PCIe agreement in physical form, and the integrated circuit board can pass through golden finger disect insertion mainboard PCIe slot. It should be noted that the physical layer is compatible with the PCIe interface, and PCIe slots can be multiplexed without a new connector.

Referring to fig. 6, a firmware key module in the FPGA firmware portion includes a CXL subsystem (including cxl.io, cxl.cache, cxl.mem protocol layer, CXL coherence Engine, and CXL phy), a buffer read/write module, a bus arbitration management module, a control register, a status register, and NAND FLASH subsystems (FLASH controller, FLASH data management module), where cxl.io is used to implement IO communication between HOST and SSD, and includes functions of link training, command sending, msi interruption, etc., cxl.cache uses RAM inside FPGA as CPU CACHE, and is uniformly managed by the CPU CACHE consistency management module, and the CPU can access the CACHE on the SSD like accessing the local CACHE, thereby simplifying the path for the CPU to access the SSD, and reducing access delay. MEM enables CPU direct management of MEM on SSD. The buffer read-write module and the bus arbitration management module are responsible for transmitting FLASH data. The focus herein is to set forth how the overall time for a CPU to access an SSD is reduced by CXL, and therefore is not described in detail with respect to the storage subsystem.

Referring to fig. 7, a specific flow for reading and writing a large-capacity data block by a CPU is as follows:

s40: in the initial state, CXL link initialization is completed.

S41: the CPU sends out an IO request, and sends out a cxl.io request packet through a host-side CXL controller (CXL engine).

S42: the SSD side CXL engine receives a host CXL.io request packet, and the CXL.io subprotocol analyzes the packet to obtain relevant information of the IO request, such as information of a read-write mark, a data source, size and the like.

S43: and the CXL engine carries out reading, writing and interpretation according to the information analyzed by the CXL.io. If it is a write operation, it jumps to state S44, and if it is a read operation, it jumps to state S47.

S44: the CXL interrupt is generated by cxl.io to notify the CPU that data can be transmitted.

S45: the CPU side CXL directly writes data into the MEM space of the SSD through the cxl.mem protocol.

S46: the bus arbitration management module is matched with the buffer read-write module, data in the MEM space are written into the FLASH through the FLASH controller, and then interrupt is sent to the CPU, so that SSD write operation is realized. Return to the initial state S40.

S47: and when the IO is judged to be a read request, reading the data from the FLASH according to the address information.

S48: the bus arbitration management module is matched with the buffer area read-write module to move data to the MEM space of the SSD.

S49: and informing the CPU to read data, and reading the MEM space data of the SSD by the CPU through the HOST side CXL.

Referring to fig. 8, a specific process for reading and writing a small-capacity data block by a CPU is as follows:

s50: in an initial state, finishing CXL initialization, waiting for a CPU command, controlling a CPU to send an IO request, and sending a CXL.io packet request through a CXL controller at a host side.

S51: the SSD side CXL engine receives a host CXL.io request packet, and the CXL engine analyzes the CXL.io packet based on the CXL.io subprotocol and judges whether the CPU reads or writes. If the operation is a read operation, the state transition is made to S55, and if the operation is a write operation, the state transition is made to S52.

S52: and the CXL engine sends the CXL.io completion packet and informs the CPU to send data.

S53: CPU sends CXL.cache data packet, CXL.Engine analyzes data packet, writes data into FLASH buffer area

S54: and writing the data into the FLASH through the bus arbitration management module and the read-write buffer module.

S55: the CPU reads, the bus arbitration management module and the read-write buffer module read FLASH data and write the FLASH data into the buffer.

S56: and the CXL engine reads the data of the buffer area, generates a CXL.

S57: and (4) receiving the CXL (maximum likelihood) cache data message by the CPU side, and finishing the reading operation.

To sum up, the application provides a novel SSD solid state disk based on the CXL protocol from the angle of reducing the time delay on the CPU-CACHE-DDR-SSD whole link, the CXL.io, the CXL.cache and the CXL.mem subprotocols are realized on the solid state disk, the FPGA internal high-speed RAM or the REG is used as the SSD CACHE CACHE, and the CPU can directly access the CACHE on the SSD solid state disk, so that the IO storage speed is improved. And the transmission delay is reduced. Mainly, aiming at the problem that the access of the current CPU to the SSD is delayed relatively greatly through a DMA mode or an IO mode, a novel protocol CXL is realized to further improve the IO performance of the CPU to the SSD and reduce the access delay, and meanwhile, the scheme can also reduce the extra disturbance caused by the access of the CPU to the local DDR, thereby improving the performance of the whole computer system. Specifically, for large-capacity data transmission, a FLASH-local DDR-cxl.mem data path is formed by using the FPGA side MEM as the MEM of the HOST side CPU through the cxl.mem subprotocol, so that the transmission delay of FLASH data between the local DDR and the HOST side DDR is avoided. And secondly, small-capacity data transmission, namely, the FLASH data is directly read and written through the CXL.cache subprotocol, local DDR operation is bypassed, and meanwhile, compared with a PCIe IO packet, a CXL.IO protocol packet is simplified, so that delay is further reduced. And thirdly, a complete data path is formed by the CPU-CXL-local DDR-FLASH, the participation of the RDIMM at the HOST side is not needed, and the disturbance problem of the RDIMM access is avoided, wherein the HOST is the HOST.

Referring to fig. 9, an embodiment of the present application discloses a hard disk data access apparatus, including:

a request obtaining module 11, configured to obtain a target access request sent by a central processing unit of a host for target data;

the judging module 12 is used for judging the data type of the target data based on a preset large-capacity judging rule and a preset small-capacity judging rule;

a first access module 13, configured to, if the data type of the target data is large-capacity data, directly perform data transmission by using a first data transmission link between a double-rate synchronous dynamic random access memory and the central processing unit, where the first data transmission link is established based on a first target protocol, so as to complete an access operation on the target data through the first data transmission link;

and a second access module 14, configured to, if the data type of the target data is small-capacity data, directly perform data transmission by using a second data transmission link between the nonvolatile memory and the central processing unit, where the second data transmission link is established based on a second target protocol, so as to complete an access operation on the target data through the second data transmission link.

For more specific working processes of the modules, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Further, an electronic device is provided in the embodiments of the present application, and fig. 10 is a block diagram of an electronic device 20 according to an exemplary embodiment, which should not be construed as limiting the scope of the application.

Fig. 10 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, an input output interface 24, a communication interface 25, and a communication bus 26. The memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps of the hard disk data access method disclosed in any of the foregoing embodiments.

In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol followed by the communication interface is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited herein; the input/output interface 24 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.

In addition, the storage 22 is used as a carrier for resource storage, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, and the storage 22 is used as a non-volatile storage that may include a random access memory as a running memory and a storage purpose for an external memory, and the storage resources on the storage include an operating system 221, a computer program 222, and the like, and the storage manner may be a transient storage or a permanent storage.

The operating system 221 is used for managing and controlling each hardware device on the electronic device 20 on the source host and the computer program 222, and the operating system 221 may be Windows, Unix, Linux, or the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the hard disk data access method performed by the electronic device 20 disclosed in any of the foregoing embodiments.

In this embodiment, the input/output interface 24 may specifically include, but is not limited to, a USB interface, a hard disk reading interface, a serial interface, a voice input interface, a fingerprint input interface, and the like.

Further, the embodiment of the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the hard disk data access method disclosed above.

For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.

A computer-readable storage medium as referred to herein includes a Random Access Memory (RAM), a Memory, a Read-Only Memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic or optical disk, or any other form of storage medium known in the art. Wherein the computer program realizes the hard disk data access method when being executed by a processor. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the hard disk data access method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of an algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The hard disk data access method, device, equipment and medium provided by the invention are described in detail above, and a specific example is applied in the text to explain the principle and the implementation of the invention, and the description of the above embodiment is only used to help understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A hard disk data access method is characterized by comprising the following steps:

2. The method according to claim 1, wherein if the data type of the target data is large-capacity data, the data is directly transmitted by using a first data transmission link between a double-data-rate synchronous dynamic random access memory (ddr sdram) established based on a first target protocol and the central processing unit, so as to complete the access operation for the target data through the first data transmission link, including:

3. The method according to claim 1, wherein if the data type of the target data is large-capacity data, the data is directly transmitted by using a first data transmission link between a double-data-rate synchronous dynamic random access memory (ddr sdram) established based on a first target protocol and the central processing unit, so as to complete the access operation for the target data through the first data transmission link, including:

if the data type of the target data is large-capacity data and the operation type of the access operation in the target access request is a read operation, transmitting the target data in the nonvolatile memory to the double-rate synchronous dynamic random access memory, so that the central processing unit directly reads the target data from the double-rate synchronous dynamic random access memory by using the first data transmission link to complete the read operation on the target data.

4. The hard disk data access method according to claim 1, wherein if the data type of the target data is small-capacity data, directly performing data transmission by using a second data transmission link between the nonvolatile memory and the central processor, which is established based on a second target protocol, to complete an access operation for the target data through the second data transmission link, the method includes:

5. The hard disk data access method according to claim 1, wherein if the data type of the target data is small-capacity data, directly performing data transmission by using a second data transmission link between the nonvolatile memory and the central processor, which is established based on a second target protocol, to complete an access operation for the target data through the second data transmission link, the method includes:

6. The hard disk data access method of claim 5, wherein the sending the target data to the central processor using the second data transmission link comprises:

7. The hard disk data access method according to any one of claims 1 to 6, further comprising:

8. A hard disk data access device, comprising:

9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the hard disk data access method of any of claims 1 to 7.

10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements a hard disk data access method as claimed in any one of claims 1 to 7.