CN114785735A - FPGA-based network message current limiting method and device - Google Patents

FPGA-based network message current limiting method and device Download PDF

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CN114785735A
CN114785735A CN202210451930.3A CN202210451930A CN114785735A CN 114785735 A CN114785735 A CN 114785735A CN 202210451930 A CN202210451930 A CN 202210451930A CN 114785735 A CN114785735 A CN 114785735A
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packet
message
fpga
current limiting
clock period
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CN114785735B (en
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张子其
韩建奎
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Hangzhou DPtech Information Technology Co Ltd
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Hangzhou DPtech Information Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/14—Network analysis or design
    • H04L41/142—Network analysis or design using statistical or mathematical methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/20—Traffic policing

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Abstract

The invention relates to a network message current limiting method and a device based on FPGA, the method comprises: caching message packets in N network message input queues in N FIFO memories, wherein the message packets in each network message input queue are stored in the corresponding FIFO memory; scheduling the message packets stored in the N FIFO memories to form a continuous message packet sequence to be subjected to current limiting and arbitration, so that the message packets stored in each FIFO memory in the N FIFO memories can fairly enter the message packet sequence to be subjected to current limiting and arbitration; sequentially receiving the message packets contained in the message packet sequence to be subjected to current limiting and arbitration, accumulating and calculating the total packet length of the message packets contained in the message packet sequence to be subjected to current limiting and arbitration within 500 milliseconds in unit time based on an internal clock of the FPGA, and adding a current limiting identifier to the message packets outside the current limiting bandwidth if the total packet length is greater than the current limiting bandwidth V; and when the message is output, the message packet containing the current limiting identifier is discarded.

Description

FPGA-based network message current limiting method and device
Technical Field
The present disclosure relates to the field of network message current limiting technologies, and in particular, to a method and an apparatus for network message current limiting based on an FPGA.
Background
In modern network communication systems, the data traffic flowing in the network is increasing. In order to prevent the system from being unstable or down due to the overhigh traffic load, the traffic in a certain time window needs to be limited to maintain the stability of the system. In addition, due to the needs of operators and customers, sometimes in an application scenario, traffic in some specific lines or local area networks needs to be managed to ensure smooth and stable overall traffic of the priority lines or local area networks.
The leaky bucket algorithm is a common data flow limiting method, and the system controls the speed of the outgoing message through a corresponding algorithm, smoothly processes the burst flow in a short time and controls the flow to be output in order. Specifically, the leaky bucket algorithm first aggregates the message data stream into a data pool, then processes the output request according to the system requirements, and usually adopts a strategy of directly rejecting all requests exceeding the instantaneous upper limit of the flow or letting redundant requests enter a queue to wait, and the final result is that the message leaves the data pool at a fixed rate.
An FPGA (Field Programmable Gate Array) can process a large amount of data in parallel and transmit data contents at high speed. On the basis of fully utilizing the characteristics of the FPGA chip, the leakage bucket current limiting algorithm is used for realizing the current limiting function.
When the FPGA realizes the leakage bucket algorithm current limiting, the total packet length of the passing messages within 1s is usually counted. However, because the working frequency of the FPGA is high, the FPGA has the characteristic of transmitting data at a high speed, so that a large number of data packets are often passed through within 1s, and in this time precision, counting and entering the current-limiting arbitration module may cause the problem that the situation exceeding the expected flow limit occurs occasionally and the real-time rate fluctuation of the data stream is too large.
Therefore, a method and a device for limiting the flow of the network message are needed, which have high accuracy of the current-limiting output result and small real-time rate fluctuation of the data stream.
Disclosure of Invention
In view of this, the present disclosure provides a network message current limiting method and apparatus based on an FPGA. According to one aspect of the disclosure, a network message current limiting method based on an FPGA is provided, which includes: caching message packets in N network message input queues in N FIFO memories, wherein the message packets in each network message input queue are stored in the corresponding FIFO memory; scheduling the message packets stored in the N FIFO memories to form a continuous message packet sequence to be current-limited and arbitrated, so that the message packets stored in each FIFO memory in the N FIFO memories can fairly enter the message packet sequence to be current-limited and arbitrated; sequentially receiving the message packets contained in the message packet sequence to be subjected to current limiting and arbitration, accumulating and calculating the total packet length of the message packets contained in the message packet sequence to be subjected to current limiting and arbitration within 500 milliseconds in unit time based on an internal clock of the FPGA, and adding a current limiting identifier to the message packets outside the current limiting bandwidth if the total packet length is greater than the current limiting bandwidth V; and when the message is output, the message packet containing the current limiting identifier is discarded.
According to the network message current limiting method based on the FPGA, the method further comprises the following steps: presetting a fixed clock period T, a clock period upper limit M, a clock period statistical value and a packet total length statistical value N of an internal clock of the FPGA, wherein the fixed clock period T multiplied by the clock period upper limit M is 0.5, the initial values of the clock period statistical value and the packet total length statistical value N are both 0, when the internal clock of the FPGA within 500 milliseconds per unit time is updated once by the fixed clock period T, accumulating the clock period statistical value by 1 and accumulating the packet total length statistical value N by the packet length of a newly received message packet within the current fixed clock period T, when the packet total length statistical value N is greater than a current limiting bandwidth V, adding a current limiting identifier to the message packet exceeding the current limiting bandwidth in the newly received message packet until the clock statistical value is equal to the clock period upper limit M, and when the clock period statistical value is equal to the clock period upper limit M, the initial values of the reset clock cycle number statistic and the packet total length statistic N are both 0.
According to the network message current limiting method based on the FPGA, the method further comprises the following steps: and dynamically and synchronously reducing the upper limit value M of the clock period number and the current-limiting bandwidth V in proportion, wherein the upper limit value M of the clock period number and the current-limiting bandwidth V are respectively reduced values which are integer multiples of n on the premise that the current-limiting bandwidth Vx is larger than the minimum packet length of the FPGA after reduction.
According to the FPGA-based network message current limiting method disclosed by the invention, n can take the values of 2, 4 and 8.
According to the network message current limiting method based on the FPGA, the method further comprises the following steps: storing the length value of the part, which is not counted, of the message packet with the total packet length statistic value N in a memory; when the time unit is increased by 1 second every time, accumulating and calculating the length value of the part, which is not counted, of the message packet with the total length statistic N which is not counted in the unit time of 1 second to obtain the total length L of the non-counted packet, and when the total length L of the non-counted packet is longer than that of the whole packet, taking the L out of the memory and accumulating the total length statistic N of the packet of the judging module to make up the precision loss caused by the fact that the cut message packet is not counted.
According to another aspect of the present disclosure, there is provided a network message current limiting apparatus based on FPGA, the apparatus including: the buffer component is used for buffering the message packets in the N network message input queues in N FIFO memories, wherein the message packet in each network message input queue is stored in the corresponding FIFO memory; the fair scheduling component is used for scheduling the message packets stored in the N FIFO memories to form a continuous message packet sequence to be limited and arbitrated, so that the message packets stored in each FIFO memory in the N FIFO memories can fairly enter the message packet sequence to be limited and arbitrated; the arbitration component is used for sequentially receiving the message packets contained in the message packet sequence to be subjected to current limiting arbitration, accumulating and calculating the packet total length of the message packets contained in the message packet sequence to be subjected to current limiting arbitration within 500 milliseconds in unit time based on an internal clock of the FPGA, and adding a current limiting identifier to the message packets outside the current limiting bandwidth if the packet total length is greater than the current limiting bandwidth V; and the current limiting component is used for discarding the message packet containing the current limiting identifier when the message is output.
According to the network message current limiting device based on the FPGA of the present disclosure, wherein the arbitration component is further configured to: presetting a fixed clock period T, a clock period upper limit value M, a clock period statistical value and a packet total length statistical value N of an internal clock of the FPGA, wherein the clock period T multiplied by the clock period upper limit value M is 0.5, the initial values of the clock period statistical value and the packet total length statistical value N are both 0, when the internal clock of the FPGA in unit time within 1 second is updated once with the fixed clock period T, accumulating 1 for the clock period statistical value and accumulating N for the packet total length statistical value for the packet length of a newly received packet within the current fixed clock period T, when the packet total length statistical value N is greater than a current limiting bandwidth V, adding a current limiting identifier to a packet exceeding the current limiting bandwidth in the newly received packet until the clock period statistical value is equal to the clock period upper limit value M, and when the clock period statistical value is equal to the clock period upper limit value M, the initial values of the reset clock cycle number statistic and the packet total length statistic N are both 0.
According to this disclosed network message current limiting device based on FPGA, the sanction subassembly still is used for: dynamically synchronizing scaled down upper limit M of clock cycles and current-limited bandwidth V after scaling downxOn the premise of being longer than the minimum packet length of the FPGA, the upper limit value M of the clock cycle number and the current-limiting bandwidth V are reduced values which are respectively integer multiples of n.
According to the FPGA-based network message current limiting method disclosed by the invention, n can take the values of 2, 4 and 8.
According to the network message current limiting method based on the FPGA, the method further comprises the following steps: the packet total length adjusting component is used for storing the length value of the part which is not counted in of the message packet with the packet total length statistic value N which is not counted in the memory; when the time unit is increased by 1 second every time, accumulating and calculating the length value of the part, which is not counted, of the message packet with the total length value N which is not counted in the unit time of 1 second to obtain the total length L of the part, which is not counted, of the message packet, and when the total length L of the part, which is not counted, of the packet is longer than the length of the whole packet, taking the L out of the memory and accumulating the L in the total length value N of the packet of the judging module so as to make up the precision loss caused by the fact that the cut message packet is not counted.
Another aspect of the present invention provides a network message flow limiting method, which is applied to a network device, where the network device includes an arbitration unit and multiple cache units, where the multiple cache units are connected to the arbitration unit based on a data channel, and the network message flow limiting method includes: storing messages to be output to the plurality of cache units to be dispatched to the arbitration unit; reducing the statistical time of the message entering the arbitration unit to obtain target statistical time; counting the total packet length value of the message dispatched to the arbitration unit within each target counting time, and judging the size between the total packet length value and the target current-limiting bandwidth; and carrying out current limiting processing on the message of which the total packet length value is greater than the target current limiting bandwidth; and the target current limiting broadband is reduced in proportion to the target statistical time.
In the foregoing technical solution, preferably, the target limited bandwidth is greater than or equal to a minimum packet length of a data stream processed by the network device.
In any one of the above technical solutions, preferably, the method further includes: and caching the partial packet length of the messages which are not counted in the packet length statistic value when the preset statistic length is increased for the messages of which the time reaches the target statistic time and are not counted, and taking out statistics when the sum of the cached packet lengths is greater than the length of the whole packet.
In any one of the above counting schemes, preferably, the network device includes an FPGA (Field Programmable Gate Array), and the plurality of buffer units include FIFO (First Input First Output) storage units.
In order to solve the above technical problem, a further aspect of the present invention provides a network packet current limiting device, which is applied to a network device, where the network device includes an arbitration unit and multiple cache units, and the multiple cache units are connected to the arbitration unit based on a data channel, and the network packet current limiting device includes: the message cache component is used for storing the messages to be output into the plurality of cache units so as to be dispatched into the arbitration unit; the time adjusting component is used for reducing the statistical time of the message entering the arbitration unit so as to obtain target statistical time; the packet length counting component is used for counting the total packet length value of the message dispatched to the arbitration unit in each target counting time; the current-limiting judging component is used for judging the size between the total packet length value and the target current-limiting bandwidth; the current limiting processing component is used for performing current limiting processing on the message with the total packet length value larger than the target current limiting bandwidth; and the target current limiting broadband is reduced in proportion to the target statistical time.
In the foregoing technical solution, preferably, the target limited bandwidth is greater than or equal to a minimum packet length of a data stream processed by the network device.
In any one of the foregoing technical solutions, preferably, the packet length statistics component is further configured to, for a packet whose time reaches the target statistics time and is not counted, buffer packet lengths of a part of packets whose packet length statistics values are not counted each time a predetermined statistics length is added, and take out statistics when the sum of the buffered packet lengths is greater than the length of a whole packet.
In any one of the above technical solutions, preferably, the network device includes an FPGA, and the plurality of buffer units include FIFO storage units.
In summary, by adopting the network message current limiting method and device based on the FPGA, the internal clock of the FPGA can be adjusted according to application needs, and the adjusted internal clock of the FPGA is used for simulating real time to carry out flow statistics, so that the accuracy of current limiting and the stability of output flow are improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings described below are only some embodiments of the present application and other drawings may be derived by those skilled in the art without inventive effort.
Fig. 1 is a schematic flow diagram illustrating a method for limiting a flow of a network message based on an FPGA according to an embodiment of the present disclosure.
Fig. 2 is a detailed flowchart of a network message current limiting method based on an FPGA according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of an FPGA-based network message flow limiting apparatus according to an embodiment of the present disclosure.
Fig. 4 is a schematic flow chart of a network message flow limiting method according to another embodiment of the present invention.
Fig. 5 shows a schematic block diagram of a network message flow restriction apparatus according to another embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known methods, systems, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It is to be understood by those skilled in the art that the drawings are merely schematic representations of exemplary embodiments, and that the blocks or processes shown in the drawings are not necessarily required to practice the present disclosure and, therefore, are not intended to limit the scope of the present disclosure.
The FIFO memory is one of the basic buffer units in FPGA and features that the data stored first is read out first. When one FIFO memory is nearly full, a feedback signal of the FIFO memory is triggered, the signal guides the whole transmission of the queue to a certain extent, and the subsequent messages are stored temporarily; after a part of data in the FIFO memory is read out and data can be continuously filled into the FIFO memory, the feedback signal is invalid, and the system inputs a new message again, so that the data flow is ensured to stably enter the system, and the overflow problem is avoided.
Fig. 1 is a schematic flow diagram illustrating a network message current limiting method based on an FPGA according to an embodiment of the present disclosure. As shown in fig. 1, firstly, the traffic that needs to be output in a limited manner is buffered in an FIFO memory, in order to reduce the workload of the chip, a method of increasing the space occupied resources and reducing the time occupied resources is adopted, a plurality of FIFO memories are used for buffering data streams, and then, the traffic is taken out from each FIFO by using a scheduling link and enters a subsequent limited-flow arbitration module.
In order to improve the current limiting effect, the network message current limiting method based on the FPGA of the embodiment of the present disclosure enables the message to be output from the system according to the current limiting standard within a sufficiently long time on the premise of complying with the current limiting bandwidth condition and not causing data overflow; the fluctuation of data output is reduced, so that the smooth output can be realized when the burst flow is faced, and the precision of the current-limiting output result is improved.
Fig. 2 is a detailed flowchart of a network message current limiting method based on an FPGA according to an embodiment of the present disclosure.
As shown in fig. 2, in step S202, the packet in N network packet input queues is buffered in N FIFO memories, where the packet in each network packet input queue is stored in a corresponding FIFO memory. More specifically, the message flow is input into the system from a plurality of queues by using a single packet as a basic unit, and the message packet of each queue is stored in a FIFO memory.
In step S204, the packets stored in the N FIFO memories are scheduled to form a continuous pending current-limiting arbitration packet sequence, so that the packets stored in each FIFO memory of the N FIFO memories can fairly enter the pending current-limiting arbitration packet sequence.
More specifically, the network message current limiting method based on the FPGA of the embodiment of the present disclosure completes storing and shunting of data through step S202 and step S204. Specifically, as shown in fig. 1, the messages in the multiple queues enter the current-limiting arbitration module through one channel to perform the current-limiting calculation, so that it is necessary to perform shunt scheduling on the subsequent data read of each FIFO, thereby ensuring that the message flows in the multiple queues can fairly enter the arbitration module. And then, in steps S206 and S208, the arbitration and current limiting analysis and the specific current limiting operation are completed, specifically, the message is analyzed in the current limiting arbitration module, if the flag of the limited flow in the message identification is found, the message enters a current limiting link, and other messages which do not need to be limited flow are directly output to the outside through the system. The method comprises the steps that a user gives the current limiting capacity of a system, the current limiting capacity is in bytes, the FPGA counts and records the total length of the flow of messages passing through the system within a certain time, in order to guarantee the most basic current limiting effect, the FPGA generally counts the total packet length of the messages passing within 1s, and if the value exceeds the calibration capacity, the messages are subjected to output limiting processing. However, because the working frequency of the FPGA is high and the FPGA has a characteristic of transmitting data at a high speed, a large number of data packets are often passed through within 1s, and in this time precision, counting and entering the current limiting arbitration module may decrease the current limiting precision, which causes a problem that the real-time rate is not ideal, and thus it is necessary to reduce the time unit when counting the traffic.
As shown in fig. 2, according to the network packet current limiting method based on FPGA of the embodiment of the present disclosure, in step S206, the packet packets included in the to-be-current-limited and arbitrated packet sequence are sequentially received, the packet total length of the packet included in the to-be-current-limited and arbitrated packet sequence within 500 milliseconds is calculated based on the internal clock accumulation of the FPGA, and if the packet total length is greater than the current-limiting bandwidth V, a current-limiting identifier is added to the packet outside the current-limiting bandwidth.
In step S208, the packet including the flow limit identifier is discarded when the packet is output. The message entering the current limiting processing link in the steps can be marked with a current-limited mark, and the message can be discarded in the FPGA during output, so that the current limiting effect is achieved.
According to the FPGA-based network message current limiting method of the embodiment of the disclosure, the method further comprises the following steps: presetting a fixed clock period T, a clock period upper limit M, a clock period statistical value and a packet total length statistical value N of an internal clock of the FPGA, wherein the fixed clock period T multiplied by the clock period upper limit M is 0.5, the initial values of the clock period statistical value and the packet total length statistical value N are both 0, when the internal clock of the FPGA within 1 second of unit time is updated once by the fixed clock period T, accumulating the clock period statistical value by 1 and accumulating the packet total length statistical value N by the packet length of a newly received message packet within the current fixed clock period T, when the packet total length statistical value N is greater than a current limiting bandwidth V, adding a current limiting identifier to the message packet which exceeds the current limiting bandwidth in the newly received message packet until the clock statistical value is equal to the clock period upper limit M, and when the clock period statistical value is equal to the clock period upper limit M, the initial values of the reset clock cycle number statistic and the packet total length statistic N are both 0.
More specifically, in the process of current limiting analysis, by using an analog clock and a flow rate statistical system, for example, an FPGA chip with a fixed clock period of 4ns of an internal clock of the FPGA, in order to simulate a time flow of 1s inside the device, a counting register is required to be arranged inside the system for counting the clock period of the internal clock of the FPGA, wherein the upper limit value of the counting register is 250000000 decimal, that is, the upper limit value M of the clock period is 250000000. This register is incremented by 1 each time the FPGA internal clock is updated 1 time. 4ns M1 s is readily available, so whenever the count register reaches the upper limit, it represents that 1s has elapsed; when the analog clock counts are accumulated, the system can record and accumulate the packet length of each message entering the current-limiting arbitration module at the same time, compares the total packet length statistic value N with the current-limiting bandwidth V when the time reaches 1s, and sends the message to the current-limiting processing when the capacity is exceeded. And clearing the recorded value, and recording the total length of the passing message packet again in the new 1s, so as to carry out current limiting arbitration in the new 1 s.
According to the FPGA-based network message current limiting method, dynamic adjustable time configuration is added into the current limiting and judging module to reduce time precision, and meanwhile, the statistical value of the current limiting and judging module is reduced in the same proportion with the limiting bandwidth, so that current limiting and judging are carried out. More specifically, taking the case that the real-time traffic bandwidth is limited to V1000 Kb, when the time precision is equal to 1s, based on that the FPGA operating frequency is 250Mhz, the upper limit M of the clock cycle number of the internal counter of the FPGA is 250000000; and adding 1 to the counter every time one data packet is counted, and when the counting value of the number of clock cycles is greater than or equal to M, namely the real time reaches 1s, if the current-limiting judging module detects that the counting value N of the total length of the counted packets exceeds the current-limiting bandwidth V, judging that the data stream is subjected to current-limiting processing. The upper limit value M of the clock period number of the internal counter can be adjusted to 125000000, and the statistical time is changed to be 1/2 which is 500ms at the moment; simultaneously, the limited bandwidth V received by the system is reduced into V by half1When N exceeds V, 500Kb1And carrying out current limiting operation, discarding the message header of the output data, and finally reducing the output bandwidth to a required value.
According to the network message current limiting method based on the FPGA of the embodiment of the disclosure, the method further comprises the following steps: dynamically synchronizing scaled down upper limit M of clock cycles and current-limited bandwidth V after scaling downxOn the premise of being larger than the minimum packet length of the FPGA, the upper limit value M of the clock period number and the current-limiting bandwidth V are respectively reduced values which are integer multiples of n. In order to improve the output precision of the flow limiting rate, the value of the upper limit value M of the clock period number can be further adjusted to reduce the upper limit value M of the clock period number by integral multiple downwards. According to the FPGA-based network message current limiting method disclosed by the embodiment of the disclosure, n can take values of 2, 4 and 8.
More specifically, experiments have shown that when the number of clock cycles is above the upper limit value MxWhen the current limiting result is changed to 1/4, 1/8 of the upper limit value M of the clock cycle number M at 1 second in the original unit time, and until 1/16 (representing that the analog clock of the FPGA is changed to 250ms, 125ms or less), more accurate current limiting results can be obtained, but it should be noted that the upper limit value M of the clock cycle number is not infinitely reducible, and the current limiting result is more accurate and the scaled current limiting bandwidth V needs to be ensuredxThe minimum packet length of the data stream processed by the FPGA chip is larger than or equal to, otherwise, the data stream is directly transmitted through because the minimum packet length is smaller than.
According to the network message current limiting method based on the FPGA of the embodiment of the disclosure, the method further comprises the following steps: storing the length value of the part, which is not counted, of the message packet, which is not counted in the packet total length statistic value N, in a memory; when the time unit is increased by 1 second every time, accumulating and calculating the length value of the part, which is not counted, of the message packet with the total length statistic N which is not counted in the unit time of 1 second to obtain the total length L of the non-counted packet, and when the total length L of the non-counted packet is longer than that of the whole packet, taking the L out of the memory and accumulating the total length statistic N of the packet of the judging module to make up the precision loss caused by the fact that the cut message packet is not counted.
In particular, to further increase the accuracy of the output traffic and degrade the fluctuation of the output rate of the traffic, further processing of the packets at certain specific times is required. When the analog clock is further reduced, the actual packet length counted per unit time also becomes smaller, which may cause some packets to face the problem of being "cut" when the actual time reaches 1 s: the first half part of a complete data packet is within the upper 1s, the lower half part is within the lower 1s, and the result error is caused because the integer addition statistics in the FPGA causes that part of the data packet does not enter the statistical value; in order to process the partial data packet, when the time unit is increased by 1s every time, the partial data packet length which is not counted in the statistical value is recorded in the memory, and when the sum of the packet lengths in the memory is larger than the complete packet length, the partial data packet length is taken out and added into the statistical value, so that the precision loss caused by the fact that the 'cut' data packets are not counted is made up.
Fig. 3 is a schematic diagram of an FPGA-based network message flow limiting apparatus according to an embodiment of the present disclosure, and as shown in fig. 3, the apparatus includes a buffering component 302, a fairness scheduling component 304, an arbitration component 306, and a flow limiting component 308. The buffer group 302 is configured to buffer packet in N network packet input queues in N FIFO memories, where the packet in each network packet input queue is stored in a corresponding FIFO memory; a fairness scheduling component 304, configured to schedule the packets stored in the N FIFO memories to form a continuous pending current-limiting arbitration packet sequence, so that the packets stored in each FIFO memory of the N FIFO memories can fairly enter the pending current-limiting arbitration packet sequence; a arbitration component 306, configured to sequentially receive the packet packets included in the to-be-current-limited arbitration packet sequence, add and calculate a total packet length of the packet packets included in the to-be-current-limited arbitration packet sequence within 500 milliseconds per unit time based on an internal clock of the FPGA, and add a current-limiting identifier to the packet outside the current-limiting bandwidth if the total packet length is greater than the current-limiting bandwidth V; the current limiting component 308 is configured to discard a packet containing a current limiting identifier when outputting the packet.
According to the network message current limiting apparatus based on FPGA of the embodiment of the present disclosure, the arbitration component 306 is further configured to: presetting a fixed clock period T, a clock period upper limit value M, a clock period statistical value and a packet total length statistical value N of an internal clock of the FPGA, wherein the clock period T multiplied by the clock period upper limit value M is 0.5, the initial values of the clock period statistical value and the packet total length statistical value N are both 0, when the internal clock of the FPGA within 500 milliseconds per unit time is updated once with the fixed clock period T, accumulating 1 for the clock period statistical value and accumulating N for the packet total length statistical value for the packet length of a newly received packet within the current fixed clock period T, when the packet total length statistical value N is greater than a current limiting bandwidth V, adding a current limiting identifier to a packet exceeding the current limiting bandwidth in the newly received packet until the clock period statistical value is equal to the clock period upper limit value M, and when the clock period statistical value is equal to the clock period upper limit value M, the initial values of the reset clock cycle number statistic and the packet total length statistic N are both 0.
According to the network message current limiting apparatus based on FPGA of the embodiment of the present disclosure, the arbitration component 306 is further configured to: dynamically synchronizing scaled down upper limit M of clock cycles and current-limited bandwidth V after scaling downxOn the premise of being longer than the minimum packet length of the FPGA, the upper limit value M of the clock cycle number and the current-limiting bandwidth V are reduced values which are respectively integer multiples of n.
According to the FPGA-based network message current limiting method disclosed by the embodiment of the disclosure, n can be 2, 4 and 8.
According to the FPGA-based network message current limiting method of the embodiment of the disclosure, the method further comprises the following steps: a packet total length adjusting component 310, configured to store, in a memory, a length value of an unaccounted portion of a packet of the packet whose packet total length statistic N is unaccounted; when the time unit is increased by 1 second every time, accumulating and calculating the length value of the part, which is not counted, of the message packet with the total length statistic N which is not counted in the unit time of 1 second to obtain the total length L of the non-counted packet, and when the total length L of the non-counted packet is longer than that of the whole packet, taking the L out of the memory and accumulating the total length statistic N of the packet of the judging module to make up the precision loss caused by the fact that the cut message packet is not counted.
In summary, by adopting the network message current limiting method and device based on the FPGA, the internal clock of the FPGA can be adjusted according to application needs, and the adjusted internal clock of the FPGA is used for simulating real time to carry out flow statistics, so that the accuracy of current limiting and the stability of output flow are improved.
Fig. 4 is a schematic flow chart of a network message flow limiting method according to another embodiment of the present invention. As shown in fig. 4, the technical solution of this embodiment is applicable to a network device, where the network device includes an arbitration unit and multiple cache units, and the multiple cache units are connected to the arbitration unit based on a data channel, and the network packet current limiting method of this embodiment includes the following steps:
step S402, storing the message to be output to a plurality of buffer units to be scheduled to an arbitration unit.
In view of the fact that in the prior art, all messages are collected into one data pool and then are output in a current-limiting mode at a fixed rate, the requirement on the storage capacity of a system is high, and the corresponding workload is also high, in this embodiment, a plurality of cache units are used for caching the messages to be output, then the messages are taken out from each cache unit by utilizing a scheduling link and enter a subsequent arbitration unit, the storage pressure of the system is differentiated, in addition, the messages in each cache unit are scheduled according to the requirements, the data stream can be guaranteed to stably enter the system, and overflow is avoided.
Step S404, the statistical time of the message entering the arbitration unit is reduced to obtain the target statistical time.
Step S406, in each target counting time, counting the total packet length value of the message dispatched to the arbitration unit, and judging the size between the total packet length value and the target current-limiting bandwidth.
And step S408, carrying out flow limiting processing on the message of which the total packet length value is greater than the target flow limiting bandwidth.
Considering that the data processing capacity of network devices is high, for example, the FPGA has the capacity of processing a large amount of data in parallel and transmitting data at a high speed, if the statistical time is long, for example, the length of a message passing through a system is counted by taking the real time 1s as a unit, because the working frequency of the FPGA is high, a large number of data packets are often passed through within 1s, under the time precision, counting and entering a current limiting arbitration unit can reduce the current limiting precision, and cause the problem that the real-time rate is not ideal, therefore, the current limiting arbitration is realized by shortening the statistical time and adjusting the current limiting bandwidth at the same time, and the current limiting bandwidth is reduced in proportion to the statistical time. Specifically, an FPGA integrated with a plurality of FIFO memory units is taken as a network device for explanation:
1) firstly, message flow needing current-limiting output is cached into a plurality of FIFOs, and then the message flow is taken out from each FIFO by utilizing a scheduling link and enters a subsequent arbitration unit. The specific message flow is input into the system from a plurality of queues by taking a single packet as a basic unit, the message packet of each queue is stored in an FIFO memory, the FIFO memory is one of the basic cache units in the FPGA, and the method is characterized in that the data stored first is read out first, when the FIFO memory is nearly full of memory, a feedback signal of the FIFO memory is triggered, the signal guides the whole transmission of the queue to a certain extent, the subsequent messages are temporarily stored, after the data in the FIFO memory is read out to be partially and can be continuously filled with the data, the feedback signal is invalid, and the system inputs a new message, so that the data flow is ensured to stably enter the system, and the overflow problem is avoided.
2) The arbitration unit is added with dynamic adjustable time configuration to reduce time precision, and simultaneously, the statistical value of the arbitration unit and the current-limiting bandwidth are reduced in the same proportion, so as to carry out current-limiting arbitration. Generally, taking an example that the real-time traffic bandwidth is limited to V1000 Kb, when the time precision is equal to 1s, the working frequency is 250Mhz based on the FPGA, and the internal counter M of the FPGA is 250000000; adding 1 to a counter every time a data packet is counted, and when the counted value is greater than or equal to M, that is, the real time reaches 1s, if it is detected that the counted total packet length value N exceeds V, it is determined that the data stream should be limited, however, for an FPGA with high data processing and transmission capacity, the counted time of 1s has passed a large number of data packets, so in this example, the value of the internal counter M may be adjusted to 125000000, which represents that the counted time is changed to original 1/2, that is, 500ms (the target counted time, here, the value is only used for illustration and is not limited); meanwhile, the current-limiting bandwidth received by the system is halved into V1 ═ 500Kb (a target current-limiting bandwidth, the numerical value is only used for illustration and is not limited), when the total packet length value N exceeds V1, the current-limiting operation is performed, the message header of the output data is discarded, and finally the output bandwidth is reduced to the required numerical value;
in order to improve the output accuracy of the current-limiting flow, the value of M can be further adjusted to reduce the value by integral multiple downwards, experiments show that when the value becomes 1/4, 1/8 as before and reaches 1/16 (representing that the analog clock of the FPGA becomes 250ms, 125ms to less), a more accurate current-limiting result can be obtained, but it should be noted that M cannot be reduced infinitely, the current-limiting result is more accurate, and at the same time, it needs to be ensured that the scaled current-limiting bandwidth Vx is greater than or equal to the minimum packet length of the data stream processed by the FPGA chip, otherwise, the data stream is directly transmitted because the scaled current-limiting bandwidth Vx is smaller than the minimum packet length.
In view of reducing the statistical time, the actual packet length counted in unit time also becomes smaller, which may cause some data packets to be "cut" when the actual time reaches 1 s: that is, the first half of a complete packet is within the upper 1s, and the second half is within the lower 1s, and since integer addition statistics inside the FPGA will cause that part of the packet does not enter the statistical value, resulting in error, for this reason, further, when packet length statistics is performed: for the messages of which the time reaches the target statistical time and is not counted, caching partial message packet lengths of which the packet length statistical values are not counted when the preset statistical length is increased, and taking out statistics when the sum of the cached packet lengths is greater than the length of a complete packet, thereby greatly improving the statistical accuracy and reducing the fluctuation of message output.
The network device in this embodiment is not limited to the FPGA, and may also be another processing chip that integrates the cache unit and the arbitration unit.
Embodiments of apparatus of the present invention are described below, which may be used to perform method embodiments of the present invention. The details described in the device embodiments of the invention should be regarded as complementary to the above-described method embodiments; reference is made to the above-described method embodiments for details not disclosed in the apparatus embodiments of the invention.
Fig. 5 shows a schematic block diagram of a network message flow restriction apparatus according to another embodiment of the present invention. As shown in fig. 5, a network message flow limiting apparatus 500 according to an embodiment of the present invention is applied to a network device, the network device includes an arbitration unit and a plurality of cache units, the plurality of cache units are connected to the arbitration unit based on a data channel, the network message flow limiting apparatus 500 includes: a message buffer component 502, a time adjustment component 504, a packet length statistics component 506, a flow limit determination component 508, and a flow limit processing component 510.
The message buffer component 502 is configured to store a message to be output to a plurality of buffer units to be scheduled to an arbitration unit; the time adjustment component 504 is configured to reduce a statistical time of a packet entering the arbitration unit to obtain a target statistical time; the packet length counting component 506 is configured to count a total packet length value of the packet scheduled to the arbitration unit within each target counting time; the current limit determining component 508 is configured to determine a size between a total packet length value and a target current limit bandwidth; the current-limiting processing component 510 is configured to perform current-limiting processing on the packet whose total packet length value is greater than the target current-limiting bandwidth; the target current limiting broadband is reduced in proportion to the target statistical time, here, the network device includes an FPGA, the plurality of cache units include FIFO memory units, and certainly, the network device may also be other processing chips integrating the cache units and the arbitration unit.
Further, the target current limit bandwidth is greater than or equal to a minimum packet length of the data stream processed by the network device.
Further, the packet length counting component 506 is further configured to cache, for a packet whose time reaches the target counting time and is not counted, a part of packet lengths of the packet whose packet length counting value is not counted every time a predetermined counting length is added, and take out the counting when the sum of the cached packet lengths is greater than the entire packet length.
Those skilled in the art will appreciate that the modules in the above-described embodiments of the apparatus may be distributed as described in the apparatus, and may be correspondingly modified and distributed in one or more apparatuses other than the above-described embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
In the following, embodiments of the network device of the present invention are described, which may be regarded as specific entity implementations for the above-described embodiments of the method and apparatus of the present invention. The details described in the embodiments of the network device of the invention are to be regarded as supplementary to the embodiments of the method or the apparatus described above; for details not disclosed in the embodiments of the network device of the present invention, reference may be made to the above-described embodiments of the method or apparatus.

Claims (10)

1. A network message current limiting method based on FPGA comprises the following steps:
caching message packets in N network message input queues in N FIFO memories, wherein the message packets in each network message input queue are stored in the corresponding FIFO memory;
scheduling the message packets stored in the N FIFO memories to form a continuous message packet sequence to be current-limited and arbitrated, so that the message packets stored in each FIFO memory in the N FIFO memories can fairly enter the message packet sequence to be current-limited and arbitrated;
sequentially receiving the message packets contained in the message packet sequence to be flow-limited and arbitrated, accumulating and calculating the packet total length of the message packets contained in the message packet sequence to be flow-limited and arbitrated within 500 milliseconds in unit time based on an internal clock of the FPGA, and adding a flow-limiting identifier to the message packets outside a flow-limiting bandwidth if the packet total length is greater than the flow-limiting bandwidth V;
and when the message is output, the message packet containing the current limiting identifier is discarded.
2. The FPGA-based network message flow limiting method of claim 1, further comprising:
presetting a fixed clock period T, a clock period upper limit value M, a clock period statistical value and a packet total length statistical value N of an internal clock of the FPGA, wherein the fixed clock period T multiplied by the clock period upper limit value M is 0.5, the initial values of the clock period statistical value and the packet total length statistical value N are 0, when the internal clock of the FPGA within 500 milliseconds per unit time is updated once with the fixed clock period T, accumulating 1 for the clock period statistical value and accumulating N for the packet total length statistical value for the packet length of a newly received packet within the current fixed clock period T, when the packet total length statistical value N is greater than a current limiting bandwidth V, adding a current limiting identifier to a packet exceeding the current limiting bandwidth in the newly received packet until the clock period statistical value is equal to the clock period upper limit value M at that time, and when the clock period statistical value is equal to the clock period upper limit value M at that time, the initial values of the reset clock cycle number statistic and the packet total length statistic N are both 0.
3. The FPGA-based network message flow limiting method of claim 2, further comprising:
dynamic synchronization scaled down upper limit of clock cycles M and current limitingBandwidth V, limiting the current bandwidth V after reductionxOn the premise of being longer than the minimum packet length of the FPGA, the upper limit value M of the clock cycle number and the current-limiting bandwidth V are reduced values which are respectively integer multiples of n.
4. The FPGA-based network message flow limiting method of claim 3, wherein n can take on values of 2, 4, and 8.
5. The FPGA-based network message flow limiting method of claim 3, further comprising:
storing the length value of the part, which is not counted, of the message packet, which is not counted in the packet total length statistic value N, in a memory;
when the time unit is increased by 1 second every time, accumulating and calculating the length value of the part, which is not counted, of the message packet with the total length statistic N which is not counted in the unit time of 1 second to obtain the total length L of the non-counted packet, and when the total length L of the non-counted packet is longer than that of the whole packet, taking the L out of the memory and accumulating the total length statistic N of the packet of the judging module to make up the precision loss caused by the fact that the cut message packet is not counted.
6. A network message current limiting device based on FPGA comprises:
the buffer component is used for buffering the message packets in the N network message input queues in N FIFO memories, wherein the message packet in each network message input queue is stored in the corresponding FIFO memory;
the fair scheduling component is used for scheduling the message packets stored in the N FIFO memories to form a continuous message packet sequence to be limited and arbitrated, so that the message packets stored in each FIFO memory in the N FIFO memories can fairly enter the message packet sequence to be limited and arbitrated;
the arbitration component is used for sequentially receiving the message packets contained in the message packet sequence to be subjected to current limiting arbitration, accumulating and calculating the total packet length of the message packets contained in the message packet sequence to be subjected to current limiting arbitration within 500 milliseconds in unit time based on an internal clock of the FPGA, and adding a current limiting identifier to the message packets outside the current limiting bandwidth if the total packet length is greater than the current limiting bandwidth V;
and the current limiting component is used for discarding the message packet containing the current limiting identifier when the message is output.
7. The FPGA-based network message flow limiting device of claim 6, wherein the arbitration component is further configured to:
presetting a fixed clock period T, a clock period upper limit value M, a clock period statistical value and a packet total length statistical value N of an internal clock of the FPGA, wherein the clock period T multiplied by the clock period upper limit value M is 0.5, the initial values of the clock period statistical value and the packet total length statistical value N are both 0, when the internal clock of the FPGA within 500 milliseconds per unit time is updated once by the fixed clock period T, accumulating the clock period statistical value by 1 and accumulating the packet total length statistical value N by the packet length of a newly received message packet within the current fixed clock period T, when the packet total length statistical value N is greater than a current limiting bandwidth V, adding a current limiting identifier to the message packet which exceeds the current limiting bandwidth in the newly received message packet until the clock period statistical value is equal to the clock period upper limit value M, and when the clock period statistical value is equal to the clock period upper limit value M, the initial values of the reset clock cycle number statistic and the packet total length statistic N are both 0.
8. The FPGA-based network message current limiting apparatus of claim 7, the arbitration component further configured to:
dynamically synchronizing proportionally reducing the upper limit M of the number of clock cycles and the current-limiting bandwidth V after reductionxOn the premise of being longer than the minimum packet length of the FPGA, the upper limit value M of the clock cycle number and the current-limiting bandwidth V are reduced values which are respectively integer multiples of n.
9. The FPGA-based network message current limiting method of claim 8, wherein n can take on values of 2, 4, and 8.
10. The FPGA-based network message throttling method of claim 8, further comprising:
the packet total length adjusting component is used for storing the length value of the part, which is not counted, of the message packet which is not counted in the packet total length statistic value N in a memory; when the time unit is increased by 1 second every time, accumulating and calculating the length value of the part, which is not counted, of the message packet with the total length statistic N which is not counted in the unit time of 1 second to obtain the total length L of the non-counted packet, and when the total length L of the non-counted packet is longer than that of the whole packet, taking the L out of the memory and accumulating the total length statistic N of the packet of the judging module to make up the precision loss caused by the fact that the cut message packet is not counted.
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