CN114785699A

CN114785699A - Low-voltage distribution station physical topology identification method and high-speed power line carrier chip

Info

Publication number: CN114785699A
Application number: CN202210592584.0A
Authority: CN
Inventors: 郝岩; 周春良; 赵东艳; 陈永利; 迟海明; 张晓辉; 王连成
Original assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2022-05-27
Filing date: 2022-05-27
Publication date: 2022-07-22

Abstract

The invention discloses a physical topology identification method for a low-voltage distribution transformer area and a high-speed power line carrier chip. The low-voltage distribution station area comprises a Central Coordinator (CCO), an agent coordinator (PCO) and a Station (STA), and the method comprises the following steps: the CCO broadcasts phase information of all nodes, and performs point-to-neighbor time delay measurement according to the phase information to obtain distance parameters from the CCO to child nodes of the CCO under each phase; all PCOs with child nodes perform point-to-neighbor time delay measurement according to the phase information and the time measurement instruction to obtain distance parameters from the PCOs with the child nodes to the child nodes under each phase, and report the distance parameters to the CCO step by step, wherein the time measurement instruction is issued by a father node PCO or CCO of the PCO with the child nodes; and the CCO obtains the physical topology of the low-voltage power distribution area according to the logic topology among the nodes and the distance parameters among the nodes in each phase. The method can simply and efficiently acquire the physical topology.

Description

Low-voltage distribution station physical topology identification method and high-speed power line carrier chip

Technical Field

The invention relates to the technical field of power systems, in particular to a physical topology identification method for a low-voltage distribution area and a high-speed power line carrier chip.

Background

In an electric power system, a transformer area refers to a power supply range or area of a transformer, and a typical low-voltage distribution network user information acquisition topology is shown in fig. 1.

With the rapid increase of power users and the development of intelligent electric meter technology, the degree of automation and intelligence of power distribution network management is higher and higher. The topology of the distribution network is the basis for implementing various management functions. In the operation work of a distribution network, a newly-built intelligent substation, the reconstruction, the expansion and the maintenance of the intelligent substation can cause the change of a topological structure of a transformer area, the topological structure is generally updated by manually checking or depending on topological data input during initial installation, the workload is high, and the repeatability is high. Moreover, when the network is manually recorded, errors or line changes may occur to cause untimely updating, so that the updated topology structure is inconsistent with the master station. For this reason, the following schemes are proposed in the related art:

the first scheme is as follows: and carrying out topology identification by utilizing power line carrier communication. In the scheme, a signal generating device and a signal receiving terminal are designed, and are respectively installed at the incoming line or the outgoing line end of a branch box and an electric meter box and used for automatic topology identification. The signal receiving terminal has an ID number which is unique to the whole network, and the built-in wave trap can block 50Hz signals and can pass signals with specific frequencies. The signal generating device acquires the ID numbers of all the signal receiving terminals through power line carrier communication, then sends signals to enable the signal receiving terminals to detect the current trend, and judges father nodes of each branch box and the electric meter box according to the current trend, so that the topological structure of the whole platform area is obtained.

However, this solution requires that the trap has a very large resistance to both 50Hz and specific frequency passing signals, and is difficult to design. Moreover, the selection of the specific frequency is very relevant to the field electromagnetic interference environment, and when the interference of the specific frequency is large, the current flow direction can be misjudged. Meanwhile, the signal generating devices in the respective zones may cross talk with each other, and although a signal weakening circuit is added, the current signal from the signal generating device to the signal receiving terminal may be weakened. In addition, the measurement time point of the topological structure in the scheme is related to the load of the transformer, and the topological identification cannot be carried out when the load of the transformer is large.

Scheme II: and generating a measurement topological relation based on the signal-to-noise ratio information between the communication nodes and the phase information. According to the scheme, the physical topological relation of a low-voltage distribution area is obtained by judging the signal-to-noise ratio according to the maximum signal-to-noise ratio between adjacent communication nodes, and the interconversion corresponding relation recognition is completed. The scheme can cause misjudgment under the conditions of complex electromagnetic interference environment and low signal to noise ratio, because the low signal to noise ratio is possibly caused by strong electromagnetic interference around. Therefore, the problem of misjudgment of extremely low signal-to-noise ratio under the condition of strong electromagnetic interference cannot be solved.

And a third scheme is as follows: topological relation based on time delay measurement. The scheme carries out cluster analysis on the measured time delay information, adds the measured time delay information into clusters, and generates a topological structure according to the result of a fitting equation. The scheme adopts a statistical analysis method, a training set and a test set of time delay measurement data are needed, and the accuracy of a model is based on the training set and the test set, so that a large amount of accurate actual measurement data is needed, and the difficulty is high. In addition, the measurement data can be generated only in the process of topology identification, so that the measurement of the topology is completed while a large number of actual measurement data sets are provided. And different platform district site environment is different, and when the test data set migrated other platform district, also can not guarantee the accuracy degree of cluster analysis.

Moreover, the above solutions all require special measuring equipment, and for a platform area where a topology structure has been completed or needs to be updated, the installation manpower, material resources and time costs of the special measuring equipment are very high, and the integration level is not high and is not flexible.

Disclosure of Invention

The present invention is directed to solving, at least in part, one of the technical problems in the related art. Therefore, a first object of the present invention is to provide a method for identifying a physical topology of a low-voltage distribution substation, so as to easily and efficiently obtain the physical topology of the low-voltage distribution substation.

The second objective of the present invention is to provide a high-speed power line carrier chip.

In order to achieve the above object, an embodiment of a first aspect of the present invention provides a method for identifying a physical topology of a low-voltage power distribution substation, where the low-voltage power distribution substation includes a central coordinator CCO, a proxy coordinator PCO, and a station STA, and the method includes: the CCO broadcasts phase information of all nodes, and performs point-to-neighbor time delay measurement according to the phase information to obtain distance parameters from the CCO to child nodes of the CCO under each phase; all PCOs with child nodes carry out point-to-neighbor time delay measurement according to the phase information and the time measurement instruction to obtain distance parameters from all PCOs with child nodes to child nodes under each phase, and the distance parameters are reported to the CCO step by step, wherein the time measurement instruction is issued by a father node PCO or CCO of the PCO with child nodes; and the CCO obtains the physical topology of the low-voltage power distribution area according to the logic topology among the nodes and the distance parameters among the nodes in each phase.

According to the physical topology identification method for the low-voltage distribution transformer area, the CCO can broadcast the phase information of all nodes, point-to-neighbor time delay measurement is firstly carried out according to the phase information, the distance parameter from the CCO to the child node of the CCO under each phase is obtained, then the PCO with the child node carries out point-to-neighbor time delay measurement, the distance parameter from the PCO with the child node to the child node of the PCO under each phase is obtained, the CCO can obtain the physical topology according to the logical topology and the measured distance parameter, and therefore the physical topology can be obtained simply and efficiently.

In order to achieve the above object, a second embodiment of the present invention provides a high-speed power line carrier chip, where the chip includes: the analog front end is connected to an external node through a power line channel and used for sending a first pseudo-random sequence to the external node and receiving a second pseudo-random sequence sent by the external node; the topology identification sending module is connected with the analog front end and used for sending the first pseudorandom sequence to the analog front end; a topology identification receiving module, connected to the analog front end, for performing demodulation operation on the second pseudo random sequence, performing correlation operation on a demodulation result and a local correlation sequence to find a peak value, and generating an interrupt when the peak value is found; the timer is connected with the topology identification receiving module, the power carrier layer is connected with the topology identification sending module and the timer, when the node where the chip is located is a father node of the external node, the timer is triggered to perform timing under the interruption, and the power carrier layer is used for starting the topology identification sending module, controlling the timer to perform timing simultaneously and obtaining a distance parameter between the node where the chip is located and the external node according to two timing moments of the timer; and when the node where the chip is located is a child node of the external node, the power carrier layer is used for starting the topology identification sending module under the triggering of the interruption.

The high-speed power line carrier chip provided by the embodiment of the invention can integrate the low-voltage distribution area physical topology identification method into the chip by arranging the analog front end, the topology identification sending module, the topology identification receiving module, the timer and the power carrier layer in the HPLC chip, thereby obtaining the physical topology of the low-voltage distribution area with lower cost.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a topological diagram of user information collection of a low voltage distribution network in the related art;

FIG. 2 is a flow chart of a method of identifying a physical topology of a low voltage distribution substation according to one embodiment of the invention;

fig. 3 (a), (b) are schematic diagrams of the logical topology of the low voltage distribution substation of one example of the present invention;

FIG. 4 is a schematic diagram of a logical topology of another example low voltage distribution panel of the present invention;

FIG. 5 is a flow chart of a method of identifying a physical topology of a low voltage distribution substation according to another embodiment of the invention;

fig. 6 is a schematic structural diagram of a high-speed power line carrier chip according to an embodiment of the present invention;

FIG. 7 is a flow chart of the operation of an exemplary receiver of the present invention;

FIG. 8 is a diagram illustrating the results of an exemplary correlation operation of the present invention;

FIG. 9 is a flow chart illustrating delay measurements according to an exemplary embodiment of the present invention;

fig. 10 is a block diagram of a high-speed power line carrier chip according to an embodiment of the invention.

Detailed Description

The low voltage distribution substation physical topology identification method and the high speed power line carrier chip of the embodiments of the present invention are described below with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the drawings are illustrative and should not be construed as limiting the invention.

Fig. 2 is a flowchart of a method for identifying a physical topology of a low voltage distribution substation according to an embodiment of the present invention.

In an embodiment of the invention, the low voltage distribution substation comprises a central coordinator CCO, a proxy coordinator PCO and a station STA. The logical topology of the low voltage distribution substation may be in the shape of a radial as shown in (a) of fig. 3, or in the shape of a tree as shown in (b) of fig. 3, or in other possible shapes. The radial topology is centralized in the electric well boxes on the same floor of the same building in the urban area to distribute power supply for the users on the floor; other cases preferably dominate the tree topology, especially the trunk lines. The CCO is a master station as shown in fig. 1, and is a center of a low-voltage distribution substation, and executes a gateway program; the agent coordinator PCO is a concentrator as shown in fig. 1, and is a relay agent of a low-voltage distribution station area, and executes a node program, so that the central coordination area CCO may connect to all stations STA through the agent coordination area PCO, as an example, see a logical topology shown in fig. 4; the STA is the collector shown in fig. 1, and executes a node program; the central coordination area CCO, the proxy coordination area PCO, and the station STA communicate with each other by using a power line in the power system corresponding to the logical topology as a communication channel, and a data frame transmitted in the power line channel may include, for example, a data type having a byte number of 1 and a data content having a byte number of n, where a default value of the data type is 0 and a value range of the data content is 0 to 65535. The agent coordination area PCO and the station STA may be, for example, a smart meter/I type collector communication unit or a broadband carrier II type collector.

It should be noted that before the method of the embodiment of the present invention is used to identify the physical topology of the low voltage distribution substation, the logical topology of the low voltage distribution substation is known.

As shown in fig. 2, the method for identifying the physical topology of the low-voltage distribution substation comprises the following steps:

and S21, broadcasting the phase information of all nodes by the CCO, and measuring the time delay from the point to the neighbor according to the phase information to obtain the distance parameter from the CCO to the child node of each phase.

Specifically, before the CCO broadcasts the phase information of all nodes, the CCO needs to broadcast a global measurement parameter first, where the global measurement parameter includes at least one of a communication timeout time, a maximum retransmission number of delay measurement communication, a node information validity time, an average number of delay measurements, a delay measurement signal-to-noise ratio threshold, and a delay measurement communication success rate threshold. The global measurement parameter is an initialization measurement parameter of each node of topology identification, and defines parameters required by delay measurement required by all transmitting and receiving nodes. The communication timeout time is used for determining the waiting time of the two nodes during communication, and if the waiting time is longer than the communication timeout time, retransmission is required; the maximum retransmission times are used for measuring the exit condition when the abnormal condition exists; the node information effective time is used for determining the frequency of updating the node information; the average time of the time delay measurement is used for averaging the measurement time delay so as to eliminate partial measurement errors; the time delay measurement noise signal-to-noise ratio threshold and the time delay measurement communication success rate threshold determine the starting threshold of time delay measurement, and the time delay measurement is meaningful only when the signal-to-noise ratio and the communication success rate are larger than certain values.

Specifically, after the power system in the low-voltage distribution area is powered on, a communication network in the power system is initialized first. After initialization is completed, the upper computer starts a CCO (central processing unit), sends a Global measurement parameter Global _ Parameters to the CCO, after the CCO receives the Global measurement parameter Global _ Parameters, the Global measurement parameter is sent to each node (including a PCO and an STA) in a broadcast mode, and the broadcast address is full AA, namely after each node receives a data frame, the destination address of the data frame can be judged firstly, if the destination address is AA, the content in the data frame is judged to be the Global measurement parameter Global _ Parameters, and then initialization of the Global measurement parameter of the cost node is completed by saving the Global measurement parameter.

The content of the Global parameter Global _ Parameters can be shown in table 1 below.

TABLE 1

Further, after the CCO completes broadcasting the Global measurement parameter Global _ Parameters, the CCO may broadcast the phase information of all nodes. The CCO broadcasts Phase information of all nodes by broadcasting Phase information frame data Net _ Phase _ List _ bord, where the Phase information frame data Net _ Phase _ List _ bord includes a report frame identifier, a number of report nodes, identifiers of each node, and a Phase thereof, and specifically, the CCO may be as shown in table 2 below.

TABLE 2

It should be noted that, since the Net _ Phase _ List _ Borad of the Phase information frame data includes the Phase information of all nodes, after receiving the Phase information frame data, each node can determine the Phase of itself and the Phase of the child node according to the data, thereby completing the Phase information in the List information of its internal node. The above-mentioned present report frame identification is used for receiving node to determine whether there is frame loss condition, if the report frame identification is the accumulated result in a continuous period of time, it proves that there is no frame loss, and there is no need for CCO retransmission, if there is frame loss, the position of the frame loss can be determined according to the discontinuous value, and CCO can be required to initiate retransmission of the frame.

Further, after the node list information in each node is perfected, the CCO performs delay measurement from the CCO to the neighbor PCO one by one according to the phase information and a preset phase sequence, and performs delay measurement from the CCO to the neighbor STA one by one according to the phase information after the delay measurement from the CCO to the neighbor PCO is finished, wherein the neighbor PCO and the neighbor STA of the CCO are child nodes of the CCO. For example, the CCO may proceed with vehicles one by one in A, B, C facies order, i.e., the CCO may first transmit Req _ DM frame data to PCOs in children nodes of the CCO one by one in A, B, C facies order for delay measurement thereof; after the time delay measurement of the PCO in the sub-node of the CCO is completed, Req _ DM frame data is sent to the STAs in the sub-node of the CCO one by one in the order of A, B, C to perform the time delay measurement.

The Req _ DM frame is a delay measurement frame, and the delay measurement frame data may be, for example, as shown in table 3 below.

TABLE 3

Therefore, the delay measurement of the sub-nodes of the CCO can be realized.

And S22, performing point-to-neighbor time delay measurement on all PCOs with child nodes according to the phase information and the time delay measurement instruction to obtain distance parameters from all PCOs with child nodes to child nodes under each phase, and reporting the distance parameters to the CCO step by step, wherein the time delay measurement instruction is issued by a father node PCO or CCO of the PCO with child nodes.

Specifically, after the CCO completes the measurement of its child Node, the CCO sends a Node2Neighbor _ DM info frame to each PCO in its child Node according to a preset phase sequence (e.g., according to the A, B, C phase sequence).

For each PCO in the child Node of the CCO, after receiving the Node2Neighbor _ DM information frame, it needs to feed back the Node2Neighbor rdm _ ACK data frame to the CCO, and then first sends a delay measurement frame to the PCO in the child Node of the PCO according to the preset phase sequence for delay measurement, and then sends a delay measurement frame to the STV in the child Node of the PCO according to the preset phase sequence for delay measurement. Therefore, time delay measurement of PCO child nodes in CCO child nodes can be realized.

The Node2Neighbor _ DM info frame data may be shown in table 4 below, and the Node2Neighbor _ rdm _ ACK data frame data may be shown in table 5 below.

TABLE 4

TABLE 5

Content providing method and apparatus	Number of bytes		Remarks for note
				Number of neighbor nodes	2

Further, each PCO in the child Node of the CCO needs to send a Node2Neighbor _ DM information frame to each PCO in the child Node thereof, receive a Node2Neighbor _ rdm _ ACK data frame fed back by the PCO in the child Node thereof, and repeat the above process to implement the delay measurement on the child Node of the PCO in the child Node of the CCO. And further repeating the process continuously to realize that the time delay measurement is carried out on the child nodes … of the PCO in the child nodes of the PCO in the CCO child nodes and the child nodes … of the PCO in the child nodes of the CCO until all the child nodes of the PCO currently carrying out the measurement have only STV, and at the moment, the PCO currently carrying out the measurement needs to send a Return _ STA _ Neighbor _ List data frame to the CCO.

It should be noted that, a Global measurement parameter monitoring variable Global _ Parameters _ initiated may also be set inside each node, where a variable of 0 indicates that the node has not initialized the Global measurement parameter, and a variable of 1 indicates that the node has completed initializing the Global measurement parameter. And after receiving the delay measurement frame, each node may first determine a condition of a global measurement parameter monitoring variable inside the node, perform delay measurement if the value of the variable is 1, and request the CCO for the global measurement parameter and store the parameter if the value of the variable is 0. Or, instead of broadcasting the global measurement parameter, the CCO may be configured to directly broadcast the phase information of all nodes, and then perform the point-to-neighbor delay measurement according to the phase information to obtain the distance parameter from the CCO to its child node in each phase, and then perform the point-to-neighbor delay measurement on all PCOs having child nodes according to the phase information and the delay measurement instruction, and when each node receives the delay measurement frame, determine the value of its own global measurement parameter monitoring variable, and if 0, request the global measurement parameter from the CCO and store the parameter.

And S23, the CCO obtains the physical topology of the low-voltage distribution station area according to the logic topology among the nodes and the distance parameters among the nodes in each phase.

Specifically, the CCO summarizes all distance parameters obtained by the time delay measurement, and combines the logical topology between the nodes, thereby obtaining the physical topology of the low-voltage distribution substation area.

In an embodiment of the present invention, a specific flow of the delay measurement may be as shown in fig. 5.

In the embodiment of the present invention, for convenience of describing the above latency measurement, it is assumed that CCO is node a and any child node of CCO is node B, or it is assumed that PCO existing in child node is node a and any child node of PCO existing in child node is node B, and node a and node B are connected through power line channel communication. At this time, referring to fig. 5, the node a to node B delay measurement procedure includes:

s51, node a sends the first pseudo-random sequence to node B, and records the sending time t _ tx.

Specifically, the node a initiates delay measurement frame data to the node B; the node B returns response information according to the time delay measurement frame data; the node A receives response information, wherein the response information is used for triggering the node A to send the first pseudo-random sequence to the node B. The node B enters a "requested delay measurement" state when returning the response information, for example, a preset requested delay measurement function may be run; after receiving the response message, the node a starts delay measurement and enters a delay measurement state, for example, a preset delay measurement function may be run. After the node A enters a time delay measurement function, the modulated first pseudorandom sequence m0 is sent to a power line through a digital-to-analog converter, and the sending time t _ tx is recorded.

When the node A is CCO, the time delay measurement frame data comprises an information source address and a carrier frequency, and the response information comprises the number of the sub-nodes of the node B; when the node A is a PCO, the delay measurement frame data comprises a Flag of the node A, the response information comprises the number of child nodes of the node B, and the Flag of the node A is used for identifying the level of the node A.

S52, the node B performs a demodulation operation after the first pseudo-random sequence, and performs a correlation operation between the demodulation result and the local first correlation sequence to find a peak position, and when the peak position is found, transmits a second pseudo-random sequence to the node a.

Specifically, after receiving the first pseudo-random sequence m0 through the analog-to-digital converter, the node B performs a demodulation operation on the first pseudo-random sequence, and performs a correlation operation on the demodulation result and the local first correlation sequence to find a peak position, and when finding the peak position, sends a second pseudo-random sequence m1 to the node a through the digital-to-analog converter, and the node a can receive the second pseudo-random sequence m1 through the analog-to-digital converter.

S53, node a performs demodulation operation after the second pseudo-random sequence, correlates the demodulation result with the local second correlation sequence to find the peak position, and records the peak time t _ rx when finding the peak position.

And S54, the node A obtains the distance parameter between the node A and the node B according to the t _ rx and the t _ tx.

Specifically, the node a obtains the distance parameter by the following formula:

d-ttransmit v,

where d is a distance parameter, t _ transmission is (t _ rx-t _ tx)/2-t _ operation, t _ operation is an operation time of demodulation operation and correlation operation, and v is a speed at which an electromagnetic wave is transmitted in the power line channel.

Thereby, obtaining the distance between node a and node B may be achieved.

In an embodiment of the present invention, if a node in the low-voltage distribution grid is added with a new sub-node, the previously received Phase information frame data Net _ Phase _ List _ Borad may be queried first, and if the Phase information of the new node exists in the previously received Phase information frame data, the Phase information of the new node is used to complete the internal node List information of the node. If the node does not exist, the CCO is notified so that the CCO can send the phase information of all the nodes to the new node, or the new node can request the CCO for the phase information of all the nodes.

In an embodiment of the present invention, an HPLC (High speed Power Line Carrier) chip is installed in each of the node a and the node B, that is, the chip is used for the central coordinator CCO, the proxy coordinator PCO, and the station STA in the low-voltage distribution grid. The chip is additionally provided with components shown in fig. 6, including an AFE (analog front-end), a topo transmission (topology identification transmission module), a topo reception (topology identification reception module), an NTB (Network Time Base) timer, and a PLC (Power line Communication) layer, and further including a physical layer transmitter and a physical layer receiver. The topology identification receiving module comprises a demodulator and a relevant peak searching submodule. The topology identification receiving module further comprises an acquisition submodule and a low-pass filter. The analog front end comprises an analog-to-digital converter, a digital-to-analog converter and a programmable gain controller, and the programmable gain controller is used for dynamically adjusting the amplification factor of the analog front end when the chip outputs through the analog front end.

The analog front end is connected to an external node through a power line channel and used for sending a first pseudo-random sequence to the external node and receiving a second pseudo-random sequence sent by the external node; the topology identification sending module is connected with the analog front end and used for sending the first pseudorandom sequence to the analog front end; the topology identification receiving module is connected with the analog front end and used for demodulating the second pseudo-random sequence, correlating a demodulation result with a local correlation sequence to search a peak value and generating an interrupt when the peak value is searched; the timer is connected with the topology identification receiving module, and the power carrier layer is connected with the topology identification sending module and the timer. The physical layer transmitter and the physical layer receiver are connected with the power carrier layer and the analog front end.

By means of the components of the chips, a spread spectrum communication receiver can be integrated in each high-speed power line carrier chip, and the receiver is composed of a digital-to-analog converter, a demodulator, a low-pass filter, a related peak searching sub-module and a capturing sub-module. Specifically, after receiving a second pseudorandom sequence, the analog front end performs digital-to-analog conversion on the second pseudorandom sequence to obtain a corresponding modulated signal, a first input end of the demodulator is connected to the analog front end, a second input end of the demodulator is used for inputting a coherent carrier, and the demodulator is used for demodulating the modulated signal through the coherent carrier to obtain a demodulated signal; the input end of the low-pass filter is connected with the output end of the demodulator, and the low-pass filter is used for performing low-pass filtering on the demodulation signal; the first input end of the correlation peak searching submodule is connected with the output end of the low-pass filter, the second input end of the correlation peak searching submodule is used for inputting a local correlation sequence, and the correlation peak searching submodule is used for performing correlation operation on a demodulation signal and the local correlation sequence to search a peak value position; the input of the capture submodule is connected to the output of the associated peak finding submodule, and the capture submodule is arranged to generate an interrupt when the peak position is captured.

As an example, referring to fig. 7, the local correlation sequence is a local m-sequence, and the receiver may obtain a pseudorandom m-sequence of the baseband signal by means of digital down-conversion and filtering, and perform a correlation operation on the pseudorandom m-sequence to find a peak position. Suppose that the modulation signal output by DAC (digital-to-analog converter) is x_i＝a_isin(ω_ct), the signal is output after coherent carrier demodulation

Further, after passing the signal through a low-pass filter, only the baseband signal a is left_iAnd/2, performing correlation operation on the baseband signal and the local m sequence to obtain an autocorrelation peak as shown in fig. 8, and further obtaining a peak position according to the result, so that the capture submodule can generate an interrupt when capturing the peak position.

Therefore, the physical topology identification method for the low-voltage distribution transformer area in the embodiment of the invention can be integrated in a high-speed power line carrier chip, and adopts a zero intermediate frequency receiver scheme, so that the cost is low, and the design is flexible. And because the sensor is integrated in the high-speed power line carrier chip and is already integrated in various intelligent electric meter devices, repeated construction is not needed, and only the measurement is started as required. Moreover, the interference to a normal carrier communication network can be reduced by two multiplexing modes of frequency division multiplexing and time division multiplexing, and the scheme of the receiver can realize the demodulation and correlation of a complete pseudo-random sequence. Moreover, the strong anti-interference performance of spread spectrum communication and the strong autocorrelation characteristic of a pseudo-random sequence can be utilized, so that the strong interference in a power line channel is effectively resisted, and a high-precision measurement result is obtained under an extremely low signal-to-noise ratio.

Specifically, the process of measuring the time delay can be seen in fig. 9, which includes the following steps.

Step 1: and the power carrier layer in the chip on the node A sends the time delay measurement frame to the power line channel through the physical layer transmitter and the analog front end so as to send the time delay measurement frame data to the external node. And the power carrier layer in the chip on the node B receives the delay measurement frame through the physical layer receiver and the analog front end so as to receive the delay measurement frame data sent by the external node.

And2, step: and a power carrier layer in a chip on the node B generates response information according to the time delay measurement frame data, and then sends the response information to a power line channel through a physical layer transmitter and an analog front end. The power carrier layer in the chip on the node A receives response information returned by the external node through the physical layer receiver and the analog front end.

And 3, step 3: and the power carrier layer in the chip on the node A starts the topology identification sending module under the trigger of the response information, controls the timer to time and obtains the modulated first pseudorandom sequence m 0.

And 4, step 4: the chip on the node A sends the first pseudo-random sequence m0 to the power line channel by using the topology identification sending module and the analog front end, and records the sending time t _ tx.

And 5: the first pseudo-random sequence m0 is transmitted over the powerline channel to the node B.

Step 6: the chip on the node B receives the first pseudo-random sequence m0 and operates with the receiver to generate an interrupt, and a power carrier layer in the chip on the node B is used for starting a topology identification transmission module under the trigger of the interrupt and acquiring a second pseudo-random sequence m 1.

And 7: and the chip on the node B sends the second pseudo-random sequence m1 to the power line channel through the topology identification sending module and the analog front end on the chip.

And 8: the second pseudo-random sequence m1 is transmitted over the powerline channel to node a.

And step 9: and the chip on the node A receives the second pseudo-random sequence m1 and operates by using the receiver to generate an interrupt, and the timer performs timing under the triggering of the interrupt to obtain a peak time t _ rx. And then the topology identification receiving module obtains t _ transmission through the following formula:

t _ tx ═ t _ rx-t _ tx)/2-t _ operation,

where t _ rx is a preceding timing instant, t _ tx is a following second timing instant, and t _ operation is an operation time of the demodulation operation and the correlation operation.

Step 10: reporting the t _ transmission to a power carrier layer of the node A, and obtaining a distance parameter by the power carrier layer through the following formula:

d-ttransmit v,

wherein d is a distance parameter, and v is the speed of the electromagnetic wave transmitted in the power line channel. Therefore, the distance parameter can be obtained, and the distance parameter is reported to the CCO.

In an embodiment of the present invention, the modulation scheme of spread spectrum communication for topo sending and receiving adopts a BPSK modulation scheme; m0 and M1 adopt two orthogonal sequences with good autocorrelation performance and length of 31, the sampling rate is 100MHz, the code rate of the M sequence is determined to be 1Mbps, the occupied bandwidth is 2M, and the carrier frequency modulated by BPSK can be dynamically adjusted to the outside of the PLC communication bandwidth according to the bandwidth setting of a PLC layer so as to prevent interference to normal PLC communication.

In one embodiment of the invention, m-sequence length can be modified to select m-sequences with better performance and longer sequences to increase the spreading gain.

In an embodiment of the present invention, other more complex modulation schemes for spread spectrum communication may be adopted, such as QPSK (Quadrature Phase Shift Keying) modulation, so that longer m-sequence can be transmitted in a shorter time to achieve the advantage of increasing the spread spectrum gain and saving communication bandwidth. The operation related to the local correlation sequence may be performed in frequency operation, that is, after the operation of multiply-accumulate in time domain with the local correlation sequence is directly multiplied by fft (Fast Fourier Transform) converted to frequency domain, and then if (Inverse Fast Fourier Transform) converted to time domain for maximum value search. The advantage of this is a faster processing speed.

In one embodiment of the invention, multidimensional judgment basis can be added, current and voltage information acquisition is added, the distance between primary calibration nodes can be calibrated according to the signal-to-noise ratio and the impedance (the impedance is in direct proportion to the distance), and phase identification can correct phase parameters of the nodes in the logic topology, so that the distance parameters between the measurement nodes are more accurate. The CCO draws the physical topology by judging three dimensions of the signal-to-noise ratio, the impedance and the physical distance of the node, so that the obtained physical topology is more accurate.

In an embodiment of the invention, a software infinite electric receiving scheme can be preset in the chip, and then a modulation carrier and an m sequence can be flexibly configured by using the software radio receiving scheme, so that the design is flexible, and the measurement precision is high. For example, if the field electromagnetic environment is clean and the signal-to-noise ratio is high, the m sequence is 15 bits, the spread spectrum communication modulation mode adopts qpsk, so that the communication bandwidth is reduced to 500kHz, the communication bandwidth resource is saved, the frequency division multiplexing mode is adopted for the scene of the carrier communication service, and the center frequency point of the topology identification spread spectrum communication is arranged outside the carrier communication band, such as in the band2 frequency band; if the field electromagnetic environment is clean and the signal-to-noise ratio is high, 15 bits are selected for an m sequence, a qpsk is adopted as a spread spectrum communication modulation mode, the communication bandwidth is reduced to 500kHz, communication bandwidth resources are saved, a time division multiplexing mode is adopted for scenes with carrier communication services infrequently, topology identification is carried out at a time point when carrier communication is not carried out, a center frequency point of communication is arranged in a carrier communication band, for example, carrier communication is carried out at a band1 frequency band, and topology identification is started at a band1 frequency band when carrier services are not carried out; if under the more complicated strong interference condition, the signal-to-noise ratio is low, the modulation mode of the spread spectrum communication can be adjusted to be bpsk, the communication bandwidth is increased to 1MHz, the spread spectrum communication gain is improved, and different application scene requirements can be met by adopting a time division multiplexing mode and a frequency division multiplexing mode; if the signal-to-noise ratio is extremely low, a longer spreading sequence, such as 31bit, can be selected for the m sequence, and the bpsk is adopted as the modulation mode, so that the spreading communication gain is further improved, and the accuracy requirement of measurement topology identification is met.

To sum up, according to the method for identifying the physical topology of the low-voltage distribution substation area in the embodiment of the present invention, the CCO broadcasts the phase information of all nodes, and then performs the point-to-neighbor time delay measurement according to the phase information, to obtain the distance parameter from the CCO to the child node thereof in each phase, and then performs the point-to-neighbor time delay measurement according to the PCO having the child node, to obtain the distance parameter from the PCO having the child node to the child node thereof in each phase, and the CCO can obtain the physical topology according to the logical topology and the measured distance parameter, thereby achieving the simple and efficient acquisition of the physical topology. In addition, the invention combines the power line carrier communication and spread spectrum communication time delay measurement technology to carry out physical topology identification on the distribution network of the low-voltage distribution area. The method can be completed through an HPLC chip, namely, the real-time topological structure updating can be completed only through an electricity information acquisition chip, and meanwhile, the time delay measurement technology based on spread spectrum communication can also complete accurate topological identification and measurement even under a complex electromagnetic environment. In addition, the invention does not need to install a special topology recognition device, has high integration level, adopts power line carrier communication, has low cost and high measurement precision, and can solve the problems of noise interference, insufficient analysis precision, incapability of being flexibly suitable for various power distribution transformer areas and the like under strong electromagnetic environment. Moreover, the invention has low complexity and high accuracy. The data training set and the test set which are actually measured do not need to be prepared in advance, and the receiver spread spectrum communication time delay measuring method based on the software radio scheme has the advantages of high flexibility, high measuring precision and high anti-interference strength. Different configurations may be implemented in different zones. The invention provides an integration scheme based on a PLC carrier communication chip, can be seamlessly integrated in chips of an intelligent electric meter and other PLC communication modules, can carry out frequency division and time division transmission with normal HPLC communication, does not influence the normal HPLC communication, does not need to repeatedly install equipment, has low cost, does not need to newly add installation hardware, and has low construction cost and excellent performance.

Further, the invention provides a high-speed power line carrier chip.

As shown in fig. 10, the high-speed power line carrier chip 100 includes: the system comprises an analog front end 101, a topology identification transmitting module 102, a topology identification receiving module 103, a timer 104 and a power carrier layer 105.

Specifically, the analog front end 101 is connected to an external node through a power line channel, and is configured to send a first pseudo-random sequence to the external node and receive a second pseudo-random sequence sent by the external node; the topology identification sending module 102 is connected to the analog front end 101, and configured to send the first pseudorandom sequence to the analog front end 101; the topology identification receiving module 103 is connected to the analog front end 101, and configured to perform a demodulation operation on the second pseudorandom sequence, perform a correlation operation on a demodulation result and a local correlation sequence to find a peak value, and generate an interrupt when the peak value is found; the timer 104 is connected to the topology identification receiving module 103, and the power line carrier layer 105 is connected to the topology identification transmitting module 102 and the timer 104, where when the node where the chip is located is a parent node of the external node, the timer 104 performs timing under the trigger of the interrupt, and the power line carrier layer 105 is configured to start the topology identification transmitting module 102, control the timer 104 to perform timing at the same time, and obtain a distance parameter between the node where the chip is located and the external node according to two timing moments of the timer 104; when the node where the chip is located is a child node of the external node, the power carrier layer 105 is configured to start the topology identification sending module 102 under the trigger of the interrupt.

According to the high-speed power line carrier chip, the simulation front end, the topology identification sending module, the topology identification receiving module, the timer and the power carrier layer are arranged in the HPLC chip, so that the physical topology identification method of the low-voltage power distribution area is integrated in the chip, and the physical topology of the low-voltage power distribution area is obtained at low cost.

In an embodiment of the present invention, the power carrier layer 105 is specifically configured to obtain the distance parameter by the following formula:

d-ttransmit v,

where d is a distance parameter, t _ transmission is (t _ rx-t _ tx)/2-t _ operation, t _ rx is a preceding timing instant, t _ tx is a second following timing instant, t _ operation is an operation time of a demodulation operation and a correlation operation, and v is a speed at which an electromagnetic wave is transmitted in the power line channel.

In an embodiment of the present invention, the high-speed power line carrier chip 100 further includes: the physical layer transmitter and the physical layer receiver are connected with the power carrier layer 105 and the analog front end 101; when the node where the chip is located is a father node of an external node, the power carrier layer 105 is further configured to send delay measurement frame data to the external node through the physical layer transmitter, receive response information returned by the external node through the physical layer receiver, and start the topology identification sending module 102 under the trigger of the response information; when the node where the chip is located is a child node of the external node, the power carrier layer 105 is further configured to send response information to the external node through the physical layer transmitter, receive delay measurement frame data sent by the external node through the physical layer receiver, and generate response information according to the delay measurement frame data.

In an embodiment of the present invention, after receiving the second pseudorandom sequence, the analog front end 101 performs digital-to-analog conversion on the second pseudorandom sequence to obtain a corresponding modulation signal, and the topology identification receiving module 103 includes: a first input end of the demodulator is connected with the analog front end 101, a second input end of the demodulator is used for inputting coherent carrier waves, and the demodulator is used for demodulating the modulation signals through the coherent carrier waves to obtain demodulation signals; and the input end of the low-pass filter is connected with the output end of the demodulator, and the low-pass filter is used for performing low-pass filtering on the demodulation signal. The first input end of the correlation peak searching submodule is connected with the output end of the low-pass filter, the second input end of the correlation peak searching submodule is used for inputting a local correlation sequence, and the correlation peak searching submodule is used for performing correlation operation on the demodulation signal and the local correlation sequence to search a peak value position; and the input end of the capturing submodule is connected with the output end of the related peak searching submodule, and the capturing submodule is used for generating interruption when capturing the peak position.

In an embodiment of the present invention, the topology identification receiving module 103 further includes: and the low-pass filter is connected between the output end of the demodulator and the first input end of the relevant peak searching submodule and is used for performing low-pass filtering on the demodulation signal.

In one embodiment of the present invention, the first pseudo random sequence and the second pseudo random sequence are orthogonal sequences with good autocorrelation performance.

In one embodiment of the present invention, the high speed power line carrier chip 100 is used for the central coordinator CCO, the proxy coordinator PCO, and the station STA in the low voltage distribution substation.

It should be noted that, for other specific implementations of the high-speed power line carrier chip according to the embodiment of the present invention, reference may be made to the above-mentioned method for identifying the physical topology of the low-voltage distribution substation area.

According to the high-speed power line carrier chip disclosed by the embodiment of the invention, the simulation front end, the topology identification sending module, the topology identification receiving module, the timer and the power carrier layer are arranged in the HPLC chip, so that the low-voltage distribution area physical topology identification method is integrated in the chip, and the physical topology is obtained at a lower cost. And a physical sending layer and a physical receiving layer are also arranged in the HPLC chip, so that the low-voltage distribution station area physical topology identification method is further integrated in the chip. Moreover, the CCO can broadcast the phase information of all nodes, and then firstly perform point-to-neighbor time delay measurement according to the phase information to obtain the distance parameters from the CCO to the child nodes thereof in each phase, and then perform point-to-neighbor time delay measurement according to the PCO with the child nodes to obtain the distance parameters from the PCO with the child nodes to the child nodes thereof in each phase, and the CCO can obtain a physical topology according to the logical topology and the measured distance parameters, thereby realizing simple and efficient acquisition of the physical topology. In addition, the invention combines the power line carrier communication and spread spectrum communication time delay measurement technology to carry out physical topology identification on the distribution network of the low-voltage distribution area. The method can be completed through an HPLC chip, namely, the updating of the real-time topological structure can be completed only through a user electricity consumption information acquisition chip, and meanwhile, the time delay measurement technology based on spread spectrum communication can also complete accurate topological identification and measurement even under a complex electromagnetic environment. In addition, the invention does not need to install a special topology recognition device, has high integration level, adopts power line carrier communication, has low cost and high measurement precision, and can solve the problems of noise interference, insufficient analysis precision, incapability of being flexibly suitable for various power distribution transformer areas and the like under strong electromagnetic environment. Moreover, the invention has low complexity and high accuracy. The data training set and the test set which are actually measured do not need to be prepared in advance, and the receiver spread spectrum communication time delay measuring method based on the software radio scheme has the advantages of high flexibility, high measuring precision and high anti-interference strength. Different configurations may be implemented in different zones. The invention provides an integration scheme based on a PLC carrier communication chip, can be seamlessly integrated in chips of an intelligent electric meter and other PLC communication modules, can carry out frequency division and time division transmission with normal HPLC communication, does not influence the normal HPLC communication, does not need to repeatedly install equipment, has low cost, does not need to newly add installation hardware, and has low construction cost and excellent performance.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein may be considered as a sequential list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description herein, the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like refer to orientations and positional relationships based on the orientation shown in the drawings, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the description of the present specification, unless otherwise specified, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the second feature or the first and second features may be indirectly contacting each other through intervening media. Also, a first feature "on," "above," and "over" a second feature may be directly on or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A low-voltage power distribution station physical topology identification method is characterized in that the low-voltage power distribution station comprises a Central Coordinator (CCO), a Proxy Coordinator (PCO) and a Station (STA), and the method comprises the following steps:

the CCO broadcasts phase information of all nodes, and performs point-to-neighbor time delay measurement according to the phase information to obtain distance parameters from the CCO to child nodes of the CCO under each phase;

all PCOs with child nodes carry out point-to-neighbor delay measurement according to the phase information and the delay measurement instruction to obtain distance parameters from all PCOs with child nodes to child nodes thereof under each phase, and the distance parameters are reported to the CCO step by step, wherein the delay measurement instruction is issued by a father node PCO or CCO of the PCO with child nodes;

and the CCO obtains the physical topology of the low-voltage power distribution area according to the logic topology among the nodes and the distance parameters among the nodes in each phase.

2. The method according to claim 1, wherein said CCO performs a point-to-neighbor time delay measurement based on said phase information, and comprises:

and the CCO performs delay measurement from the CCO to a neighbor PCO one by one according to the phase information and a preset phase sequence, and performs delay measurement from the CCO to a neighbor STA one by one according to the phase information after the delay measurement from the CCO to the neighbor PCO is finished, wherein the neighbor PCO and the neighbor STA of the CCO are child nodes of the CCO.

3. The method according to claim 1, wherein the CCO is referred to as node a, any child node of the CCO is referred to as node B, or the PCO having child nodes is referred to as node a, any child node of the PCO having child nodes is referred to as node B, the node a and the node B are communicatively connected through a power line channel, and the process of measuring the delay from node a to node B includes:

the node A sends a first pseudo-random sequence to the node B and records a sending time t _ tx;

the node B carries out demodulation operation after the first pseudo-random sequence, carries out correlation operation on a demodulation result and a local first correlation sequence to find a peak position, and sends a second pseudo-random sequence to the node A when the peak position is found;

the node A carries out demodulation operation after the second pseudo-random sequence, carries out correlation operation on a demodulation result and a local second correlation sequence to find a peak position, and records a peak time t _ rx when the peak position is found;

and the node A obtains the distance parameter between the node A and the node B according to the t _ rx and the t _ tx.

4. The low voltage distribution substation physical topology identification method according to claim 3, wherein said node A obtains said distance parameter by the following formula:

d-ttransmit v,

where d is the distance parameter, t _ transmission ═ t _ rx-t _ tx)/2-t _ operation, t _ operation is an operation time of the demodulation operation and the correlation operation, and v is a speed at which an electromagnetic wave is transmitted in the power line channel.

5. The method according to claim 3, wherein before the node A sends the first pseudo-random sequence to the node B, the method further comprises:

the node A initiates time delay measurement frame data to the node B;

the node B returns response information according to the time delay measurement frame data;

the node A receives the response information, wherein the response information is used for triggering the node A to send the first pseudo-random sequence to the node B.

6. The method of identifying a physical topology of a low voltage distribution substation according to claim 5,

when the node A is the CCO, the time delay measurement frame data comprises an information source address and a carrier frequency, and the response information comprises the number of child nodes of the node B;

when the node a is the PCO, the delay measurement frame data includes a Flag of the node a, and the response information includes the number of child nodes of the node B, where the Flag of the node a is used to identify the level of the node a.

7. The method of identifying the physical topology of a low voltage distribution substation of claim 1, wherein before the CCO broadcasts phase information for all nodes, the method further comprises:

the CCO broadcasts global measurement parameters, wherein the global measurement parameters comprise at least one of communication timeout time, maximum retransmission times of delay measurement communication, node information effective time, average times of delay measurement, a delay measurement signal-to-noise ratio threshold and a delay measurement communication success rate threshold.

8. The method according to claim 1, wherein the CCO broadcasts the Phase information of all nodes by broadcasting Phase information frame data Net _ Phase _ List _ Borad, wherein the Phase information frame data Net _ Phase _ List _ Borad comprises a report frame identifier, a number of report nodes, an identifier of each node and its Phase.

9. A high-speed power line carrier chip, the chip comprising:

the system comprises an analog front end, a first pseudo-random sequence and a second pseudo-random sequence, wherein the analog front end is connected to an external node through a power line channel and is used for sending the first pseudo-random sequence to the external node and receiving the second pseudo-random sequence sent by the external node;

the topology identification sending module is connected with the analog front end and used for sending the first pseudorandom sequence to the analog front end;

a topology identification receiving module, connected to the analog front end, for performing demodulation operation on the second pseudo random sequence, performing correlation operation on a demodulation result and a local correlation sequence to find a peak value, and generating an interrupt when the peak value is found;

a timer and a power carrier layer, wherein the timer is connected with the topology identification receiving module, the power carrier layer is connected with the topology identification sending module and the timer,

when the node where the chip is located is a father node of the external node, the timer performs timing under the triggering of the interruption, the power carrier layer is used for starting the topology identification sending module, controlling the timer to perform timing simultaneously, and obtaining a distance parameter between the node where the chip is located and the external node according to two timing moments of the timer;

and when the node where the chip is located is a child node of the external node, the power carrier layer is used for starting the topology identification sending module under the triggering of the interruption.

10. The high-speed power line carrier chip according to claim 9, wherein the power carrier layer is specifically configured to obtain the distance parameter according to the following formula:

d-ttransmit v,

where d is the distance parameter, t _ transmission ═ t _ rx-t _ tx)/2-t _ operation, t _ rx is a preceding timing instant, t _ tx is a following second timing instant, t _ operation is an operation time of the demodulation operation and the correlation operation, and v is a speed at which the electromagnetic wave is transmitted in the power line channel.

11. The high-speed power line carrier chip of claim 9, wherein the chip further comprises:

the physical layer transmitter and the physical layer receiver are connected with the power carrier layer and the analog front end;

when the node where the chip is located is a father node of the external node, the power carrier layer is further configured to send delay measurement frame data to the external node through the physical layer transmitter, receive response information returned by the external node through the physical layer receiver, and start the topology identification sending module under the triggering of the response information;

when the node where the chip is located is a child node of the external node, the power carrier layer is further configured to send response information to the external node through the physical layer transmitter, receive delay measurement frame data sent by the external node through the physical layer receiver, and generate the response information according to the delay measurement frame data.

12. The high-speed power line carrier chip of claim 9, wherein the analog front end performs digital-to-analog conversion on the second pseudo-random sequence to obtain a corresponding modulation signal after receiving the second pseudo-random sequence, and the topology identification receiving module comprises:

a demodulator, a first input end of which is connected to the analog front end, a second input end of which is used to input a coherent carrier, and the demodulator is used to demodulate the modulated signal by the coherent carrier to obtain a demodulated signal;

the input end of the low-pass filter is connected with the output end of the demodulator, and the low-pass filter is used for performing low-pass filtering on the demodulation signal;

a correlation peak finding sub-module, a first input of the correlation peak finding sub-module is connected to an output of the low pass filter, a second input of the correlation peak finding sub-module is used for inputting the local correlation sequence, and the correlation peak finding sub-module is used for correlating the demodulated signal with the local correlation sequence to find a peak position;

a capture submodule, an input of the capture submodule connected to an output of the correlation peak finding submodule, the capture submodule configured to generate the interrupt when a peak position is captured.

13. The high-speed power line carrier chip according to claim 9, wherein the first pseudo-random sequence and the second pseudo-random sequence are orthogonal sequences with good autocorrelation performance.

14. The high speed powerline carrier chip of any one of claims 9-13, in which the chip is used for a central coordinator CCO, a proxy coordinator PCO and a station STA in the low voltage distribution substation.