CN114785396A - Method, system and terminal for configuring, searching mapping and managing flow of logical port - Google Patents
Method, system and terminal for configuring, searching mapping and managing flow of logical port Download PDFInfo
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Abstract
The invention belongs to the technical field of data exchange, and discloses a method, a system and a terminal for configuring, searching and mapping a logical port and managing flow. The invention adopts a Hash mapping mode to compress the station address and then configure a logical port mapping table, carries out logical port number search on the data frame, carries out logical port distinguishing by the output port side after the operation of replacing the frame header, and stores the logical port distinguishing into different logical port queues formed by a plurality of Block RAMs.
Description
Technical Field
The invention belongs to the technical field of data exchange, and particularly relates to a method, a system and a terminal for configuring, searching and mapping a logical port and managing flow.
Background
At present, aiming at the field of satellite-borne switching, a relay satellite serving as an access network often needs to establish a multiplexing channel with different ground stations, different beam channels are established according to ground station clusters in different areas, and priority-based quality of service guarantees need to be provided for the different beam channels for satellite-borne switching equipment, so that different logic channels need to be planned for the different ground station clusters, service data streams needed by the satellite-borne switching equipment for forwarding the beams in different time slots are facilitated, and the time slots going to the different ground station clusters in loads corresponding to the same physical port are reflected as different logic ports when the satellite-borne switching equipment forwards the service data streams in the different time slots. With the increasing development and wide application of communication technology, satellite communication is also developed, and the requirement of people on the development of satellite data exchange is more urgent, and an on-satellite switching system usually not only needs to realize a packet switching function, but also needs to realize time division multiplexing and simultaneously support the network access service of a plurality of ground stations within the satellite beam coverage range. The technology of dividing multiple corresponding logical ports according to the time slots of different ground stations and performing traffic management in packet switching is still little studied. How to efficiently and quickly establish a logical port table and perform quick lookup mapping, and to ensure Quality of service (Qos) in logical port flow control is also a problem that needs to be solved at present.
The division of the logical port numbers of different ground station clusters needs to be divided into groups according to the station addresses, and if a direct mapping mode is adopted, even if the BlockRam is used, the depth of using the BlockRam is too large, and too many on-chip storage resources are occupied, if the TCAM mode is adopted, extra cost and hardware resource overhead cannot be realized only by using the FPGA, the address is configured as a logic segment table after the address of the ground station is compressed by a hash function, the resource occupancy rate of the BlcokRam can be greatly reduced by the address searching mode without additionally introducing TCAM hardware, meanwhile, only two clock cycles are needed during configuration, only one clock cycle is needed during query, so that the short configuration query time is achieved while the hardware resource is less occupied, and the service quality of the high-priority service can be ensured by controlling the flow according to the service data priority in the logic port.
Through the above analysis, the problems and defects of the prior art are as follows: how to solve the problem of the establishment of a logic port table, the consideration of the speed of searching and relational mapping on the realization of hardware and the occupancy rate of hardware resources, and simultaneously, the service quality in the flow control of the logic port is ensured.
Disclosure of Invention
The present invention provides a method, a system and a terminal for logical port configuration, lookup mapping and traffic management, and in particular, relates to a method, a system and a terminal for logical port configuration, lookup mapping and traffic management based on hash compression.
The invention is realized in this way, a method for configuring, searching and mapping logical ports and managing flow, the method searches logical ports according to station addresses before entering a grouping processing and flow classifying module by data frames gathered and polled by each input interface, enters a queue management module by replacing the searched logical port number and a frame header fixed field, enters the logical port flow management module after being forwarded to a corresponding physical port through a crossbar network, controls whether to store the data frames in a corresponding logical port FIFO queue according to a post-stage start-stop signal by taking the frame header logical port number field as a basis, and finally converges each logical port FIFO queue to a corresponding physical port for output.
Further, the method for configuring, searching and mapping the logical port and managing the flow rate adopts a hash mapping mode to compress the station address and then configure a logical port mapping table, searches the logical port number of the data frame, performs logical port distinguishing on the output port side after replacing the frame header, and stores the logical port distinguishing into different logical port queues formed by a plurality of Block RAMs.
Further, the logical port configuration, lookup mapping and traffic management method completes mapping of the logical port number and the destination station address by using a CRC function to perform hash hashing on the logical port table, ensures configuration by means of mapping the compressed destination station to a lookup table formed by Blcock Ram, and searches low time delay and low hardware resource occupancy rate realized on hardware; for the flow control function of the logic port, the peripheral control logic is added to be implemented in a mode of a plurality of FIFO queues.
Further, the logical port configuration, lookup mapping and traffic management method includes the following steps:
step one, parallelization of configuration frames: in a logic port configuration frame analysis module, performing serial-parallel conversion on an arriving logic port configuration data frame to obtain a parallel configuration frame field;
step two, extracting configuration fields: in a logic port configuration frame analysis module, aiming at the offset fields of a parallelized configuration frame, sequentially matching with a protocol, judging frame headers, frame lengths and equipment type equipment numbers, and extracting configuration fields, namely a destination station address field and an operation field, after the frame type fields are all legal fields;
step three, compressing by the destination station: in a destination station hash compression configuration module, carrying out hash hashing on the extracted 24-bit destination station address field through a CRC (cyclic redundancy check) function to obtain a compressed destination station address compressed into 10 bits;
step four, configuring a logic port: in the logic port configuration module, the compressed destination address is used as an address to address the logic port table, and a 4-path group-associated binary group consisting of the destination address and the logic port number is obtained; judging the extracted 8-bit operation field, if the value is 0xde, deleting the matched offset field, and writing all 0; if the extracted 8-bit operation field value is not 0xde, it indicates that the logical port table needs to be configured, and writes the Tag and content values into the idle offset position in the addressed logical port table;
step five, logical port query: in a logic port table query module, performing hash hashing on a 24-bit destination station address field input by polling by using the same CRC function during configuration to obtain a compressed destination station address compressed into 10 bits, using the compressed destination station address as an address addressing logic port table, searching for a 4-path group-associated binary group consisting of the destination station address before compression and a logic port number, selecting the same content with the same Tag value, namely selecting the logic port number matched with the address of the destination station before compression, and replacing the logic port number field with a data frame header;
step six, writing in the logical port FIFO: in the logical port flow control module, identifying logical port numbers in the data frame headers and matching the logical port numbers, and determining whether to store the data frames according to whether the priority of the current data frames meets the priority threshold set by the corresponding logical port FIFO;
step seven, parallelizing the flow control frame: in a logic port flow control module, performing serial-parallel conversion on an arriving logic port flow control data frame to obtain a corresponding physical port and a starting and stopping state of each logic port;
step eight, start-stop signal extraction: in a logical port flow control module, aiming at the sequential matching of offset fields of a parallelized flow control frame and a protocol, extracting configuration fields after judging that a frame header, a frame length, a device type equipment number and a frame type field are all legal fields, wherein the configuration fields are a physical port number and start-stop signals of 16 logical ports under the physical port;
step nine, reading out the logical port FIFO: in a logic port flow control module, judging whether a data frame to be sent exists in the current FIFO according to the position of the FIFO threshold of the current logic port, and determining whether to read the data frame in the current logic port FIFO or not according to the convergence back pressure signal of the rear-stage port and the flow control start-stop signal;
step ten, the logic port is gathered: in the logical port output aggregation module, fair polling is carried out on non-empty logical port FIFOs according to the FIFO states of all logical ports under the current physical port, and when a high-speed interface connected with a rear-stage physical port allows data to be sent, data is read from the logical port FIFOs which acquire fair polling authority, so that aggregation of all the logical ports is completed.
In the invention, the first step, the seventh step and the eighth step, the parallelization serial configuration frame is convenient for configuration field extraction.
In the step two of the invention, the judgment, the filtration and the illegal data adjustment are carried out on each field type to avoid error identification, and aiming at the step three, the method has the positive effects that the storage resource overhead (Block Ram overhead) for inquiring the logic port number is greatly reduced, the destination station address is compressed after passing through a hash function to obtain the entry address of a logic port hash bucket (namely a logic port table), and compared with the mode of directly taking the destination station address as the entry address of the logic port table, the required depth of the Block Ram is 2^24, and the depth of the compressed logic port table only needs 2^10 to greatly reduce the occupancy rate of hardware storage resources.
In the fourth step of the present invention, the active role is to solve the conflict problem that after the station address is compressed in the third step, different 24-bit destination station addresses are mapped to the same 10-bit compressed address, and the bit width of the logical port table is set to 128-bit key value pairs capable of storing 4 groups (original destination station address, logical port number) to ensure 4 conflicts.
Step five of the invention has the positive effects that the compressed address can be directly used for accessing the logic port table by inquiring the compressed address, the inquiring time only needs one clock cycle, and the arrangement of the Tag value can avoid the matching to the logic port corresponding to the destination address which has the same compressed address with the destination address
Step six of the invention has the positive effect of providing different service quality guarantees for the data streams with different priorities arriving under each logical port, namely, the flow control is carried out based on the specific priority to ensure that the high-priority data stream can be guaranteed to reduce frame loss as much as possible when the whole composite service stream bandwidth exceeds the link bandwidth.
The ninth step of the invention has the positive effect of responding to the start-stop control signal of the rear-stage terminal in time, and the back pressure effect of avoiding data loss caused by the caching step of the internal interface module.
The positive effect of the step-ten fair polling in the present invention is to guarantee the fairness of scheduling among the logical ports.
Further, the method for configuring the logic port table in step four includes:
(1) the Tag value to be configured is that the bit width of the destination station address is 24 bits, and the value range of each bit is binary number from all '0' to all '1'; the content value to be configured is a logical port number, the bit width of the operation field is 8 bits, the value range is from all binary numbers '0' to all binary numbers '1', the bit width of the destination station address after hash compression to be configured is 10 bits, and the value range is from all binary numbers '0' to all binary numbers '1';
(2) judging whether the content value, namely the logical port number field, is the value of the operation field, is 0xde after the value is converted into the hexadecimal number, if so, executing the step (3); otherwise, executing step (6);
(3) addressing the logic port table according to the station address after Hash compression, finding the position of a corresponding Blcok Ram row and reading out the content, wherein 4-way group-connected key value pairs are stored in a coexistence manner, the key value pairs are binary groups consisting of original destination station addresses and logic port numbers, matching the obtained destination station address before compression with the original destination station address in the 4 groups of key value pairs, judging whether the same value exists or not, and if so, executing the step (4); otherwise, executing the step (5);
(4) setting all the Tag parts in 4 groups of key value pairs which are matched with the original destination station address field part to be 0, setting the bit width to be 32, and executing the step (8);
(5) setting the configuration error signal err to be 1, and executing the step (9);
(6) addressing the logic port table according to the station address after Hash compression, finding the position of a corresponding Blcok Ram row and reading out the content, wherein 4-way group-connected key value pairs are stored in a coexistence manner, the key value pairs are binary groups consisting of original destination station addresses and logic port numbers, matching the obtained destination station address before compression with the original destination station address in the 4 groups of key value pairs, judging whether the same value exists or whether the Tag value is all '0', if so, executing the step (7); otherwise, executing the step (5);
(7) writing a configuration value into a first group of key value pairs of which the Tag parts are matched with the original destination station address field part or the Tag parts are all '0' in 4 groups of key value pairs, wherein the configuration value is a duplet consisting of the original destination station address and a logic port number, and executing the step (8);
(8) setting a configuration success signal finish to be 1, and executing the step (9);
(9) and outputting the configuration state.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of: the method comprises the steps that a data frame after being gathered and polled through each input interface is searched for a logical port according to a station address before entering a grouping processing and flow classifying module, the searched logical port number and a frame header fixed field are replaced and then enter a queue management module, the data frame is forwarded to a corresponding physical port through a crossbar network and then enters a logical port flow management module, the logical port is distinguished according to the frame header logical port number field, whether the data frame is stored in a corresponding logical port FIFO queue or not is controlled according to a post-stage start-stop signal, and finally each logical port FIFO queue is gathered to the corresponding physical port to be output.
Another object of the present invention is to provide a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program causes the processor to execute the logical port configuration, lookup mapping, and traffic management method.
Another objective of the present invention is to provide an information data processing terminal, which is used for implementing the logical port configuration, lookup mapping and traffic management method.
Another objective of the present invention is to provide a logical port configuration, lookup mapping and traffic management system for implementing the logical port configuration, lookup mapping and traffic management method, where the logical port configuration, lookup mapping and traffic management system includes a destination hash compression module, a logical port table configuration module, a destination hash compression module, a logical port table query module, a logical port flow control frame parsing module, a logical port flow control module and a logical port output aggregation module;
the system comprises a logic port configuration frame analysis module, a control information analysis module and a control information analysis module, wherein the logic port configuration frame analysis module is used for analyzing and controlling a logic port configuration null control frame generated by a computer, identifying a frame header field and extracting a corresponding control information field after confirming a check field after performing serial-parallel conversion on a configuration data frame, and analyzing logic port control information;
the configuration destination station hash compression module is used for performing hash compression on a 24-bit destination station address to 10 bits, so that the logic port configuration module can address the logic port table by using the address after 10 bits of compression;
the logical port configuration module is used for writing a Tag value and a content value into an address of the true dual-port BlcokRAM corresponding to the post-compression station address, and the Tag value and the content value are a binary group consisting of the station address and the logical port number before compression;
the query destination station hash compression module is used for extracting and hash compressing a destination station field carried in an arrival data frame to obtain an address required for querying a logic port table and confirming a Tag value;
the logical port table query module is used for addressing a logical port table consisting of the true dual-port BlcokRAM, searching 4-path group-associated binary groups consisting of destination station addresses and logical port numbers, matching the corresponding binary groups according to the station addresses before compression to obtain correct logical port fields, and replacing the correct logical port fields with the redundant fields of the data frame headers;
the logic port flow control frame analysis module is used for analyzing the back pressure data frame of the switch post-stage equipment and obtaining a flow control start-stop signal;
the logical port flow control module is used for judging which logical port FIFO the data frame should be distributed to according to the logical port number replaced at the head of the current data frame and the threshold value of the logical port FIFO corresponding to the priority of the data frame, and determining the reading of the data frame according to the start-stop signal of the logical port;
and the logical port output aggregation module is used for performing fair polling on the logical port FIFO with the current flow control start-stop signal set as 'start', and then aggregating the data frames to a physical port to be transmitted to the post-stage equipment of the switch.
Further, the logical port configuration frame parsing module parses the logical port control information into two types:
the configuration information field is composed of a binary group consisting of a destination station address and a logical port number;
and the second group is represented by a binary group consisting of a destination station address and a special character, wherein the special character represents deleting the logic port configuration under the destination station address.
In combination with the above technical solutions and the technical problems to be solved, please analyze the advantages and positive effects of the technical solutions to be protected in the present invention from the following aspects:
first, aiming at the technical problems existing in the prior art and the difficulty in solving the problems, the technical problems to be solved by the technical scheme of the present invention are closely combined with the technical scheme to be protected and the results and data in the research and development process, and some creative technical effects brought after the problems are solved are analyzed in detail and deeply. The specific description is as follows:
the invention searches the logic port according to the station address before the data frame aggregated and polled by each input interface enters the grouping processing and flow classifying module, replaces the inquired logic port number and the frame header fixed field, then enters the queue management module, forwards the data frame to the corresponding physical port through a crossbar network, then enters the logic port flow management module, distinguishes the logic port according to the frame header logic port number field, controls whether the data frame is stored in the corresponding logic port FIFO queue according to the post-stage start-stop signal, and finally aggregates each logic port FIFO queue to the corresponding physical port for outputting.
The invention adopts a Hash mapping mode to compress the station address and then configures a logical port mapping table, searches the logical port number of the data frame, performs logical port distinguishing on the output port side after replacing the frame header, stores the logical port distinguishing into different logical port queues formed by a plurality of Block RAMs, has the advantages of simple data structure, rapid configuration, searching and mapping and easy hardware realization, and is suitable for high-speed establishment searching and flow management of the network node logical port in a communication network.
The invention completes the mapping of the logical port number and the destination station address by using the CRC function to carry out hash on the logical port table, ensures the configuration by mapping the compressed destination station to the lookup table formed by the Blcock Ram, and finds the low time delay and the low hardware resource occupancy rate realized on hardware. For the flow control function of the logic port, a peripheral control logic is added to realize a form of a plurality of FIFO queues, so that the queue management of the logic port becomes simple, the additional linked list management overhead is not needed, the utilization rate of the whole storage resource is improved, and the service quality of data flow is ensured by setting a corresponding enqueue threshold for each priority data frame in each logic port FIFO.
Secondly, considering the technical scheme as a whole or from the perspective of products, the technical effect and advantages of the technical scheme to be protected by the invention are specifically described as follows:
the invention gives consideration to the lower hardware resource occupancy rate required by the establishment and the lookup of the logical port table and the efficient and accurate establishment of the lookup speed, and provides the logical port flow control system supporting the Qos guarantee.
Third, as inventive supplementary proof of the claims of the present invention, there are several important aspects as follows:
the technical scheme of the invention fills the technical blank in the industry at home and abroad:
aiming at the field of satellite-borne switching, a relay satellite serving as an access network often needs to establish a multiplexing channel with different ground stations, different beam channels are established according to ground station clusters in different areas, and priority-based service quality guarantee needs to be provided for the different beam channels for satellite-borne switching equipment, so that different logic channels need to be planned for the different ground station clusters, the satellite-borne switching equipment can conveniently forward service data streams required by the beams at different time slots, and the time slots which are forwarded to the different ground station clusters in loads corresponding to the same physical port by the satellite-borne switching equipment are embodied as different logic ports. The invention provides a combination of packet switching and channel multiplexing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for configuring, mapping, and managing traffic of a logical port according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a method for configuring, mapping, and managing traffic of a logical port according to an embodiment of the present invention.
Fig. 3 is a block diagram of a logical port configuration, lookup mapping, and traffic management system according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of logical port configuration and lookup mapping according to an embodiment of the present invention.
Fig. 5 is a simulation test chart provided by the embodiment of the invention.
Fig. 6 is a screenshot of a network tester provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In view of the problems in the prior art, the present invention provides a method, a system and a terminal for logical port configuration, mapping and traffic management, and the present invention is described in detail below with reference to the accompanying drawings.
First, an embodiment is explained. This section is an illustrative example developed to explain the claims in order to enable those skilled in the art to fully understand how to implement the present invention.
As shown in fig. 1, a logical port configuration, lookup mapping, and traffic management system provided in an embodiment of the present invention includes: the method comprises eight modules in total, namely destination station hash compression configuration, logical port table configuration, destination station hash compression query, logical port table query, logical port flow control frame analysis, logical port flow control and logical port output convergence.
As shown in fig. 2, the modules of the present invention are connected by a bus, wherein the logic port is connected with the logic port flow control management module by a queue management and crossbar network module after the logic port lookup mapping.
As shown in fig. 3, the functions of the modules of the present invention are as follows:
a logic port configuration frame analysis module for analyzing and controlling a logic port configuration null control frame generated by a computer, after serial-parallel conversion is carried out on an arrival configuration data frame, a frame header field is identified and a check field is confirmed, a corresponding control information field is extracted, logic port control information is analyzed into two types, wherein one type is that a configuration information field is formed by a binary group (destination station address and logic port number), and the other type is represented by a binary group (destination station address and special characters), wherein the special characters represent that logic port configuration under the destination station address is deleted;
a destination station hash compression module is configured, and is used for carrying out hash compression on a 24-bit destination station address to 10 bits, so that the logic port configuration module can address the logic port table by the 10-bit compressed address;
a logical port configuration module, configured to write a Tag value and a content value, that is, a binary group composed of a station address before compression and a logical port number, to an address of the true dual-port blcok ram corresponding to the post-compression station address;
the query destination station hash compression module is used for extracting and hash compressing a field carrying a destination station in an arrival data frame to obtain an address required for querying a logic port table and confirming a Tag value;
a logic port table query module, which is used for addressing a logic port table composed of a true dual-port BlcokRAM, searching 4-path group-associated (destination station address, logic port number) binary groups, obtaining correct logic port fields according to the binary groups corresponding to the station address before compression and replacing the correct logic port fields with data frame header redundant fields;
the logic port flow control frame analysis module is used for analyzing the back-pressure data frame of the switch post-stage equipment and obtaining a flow control start-stop signal;
the logical port flow control module is used for judging which logical port FIFO the data frame should be distributed to according to the logical port number replaced at the frame head of the current data frame and the threshold value of the logical port FIFO corresponding to the priority of the data frame, and determining the reading of the data frame according to the start-stop signal of the logical port;
and the logical port output aggregation module is used for carrying out fair polling on the logical port FIFO with the current flow control start-stop signal set as 'start', and then aggregating the data frames to a physical port to be sent to the post-stage equipment of the switch.
The logical port configuration, lookup mapping and flow management method based on hash compression of the present invention will be further described.
In the logical port configuration frame, the frame structure mainly comprises a 32-bit frame head field, a 16-bit frame length field, a 16-bit equipment number field, an 8-bit frame type field and N groups of load parts of 32 bits (original destination station addresses and operation fields), and the serial data frame is put into a 32-bit shift register under the drive of a channel associated clock for parallelization to obtain a parallelization field.
And 2, extracting the configuration field.
In the logic port configuration frame analysis module, a field extraction counter is started by taking the same time of a 32-bit parallel shift register value and a configuration frame header as an initial start, corresponding bit positions in the shift register are extracted successively according to offset fields of the configuration frame, the frame length and the equipment type equipment number are judged in sequence, and configuration fields, namely a destination station address field and an operation field, are extracted after frame type fields are legal fields.
And 3, compressing the destination station.
The destination station address is 24 bits, and in order to obtain the addressing address used in the logical port table, the address needs to be compressed, and in the hash compression module of the configured destination station, the extracted 24-bit destination station address field is hashed by a CRC function to obtain the addressing address compressed into 10 bits.
And 4, configuring the logic port.
In the logic port configuration module, firstly, a compressed destination station address is used as an address to address a logic port table to obtain a 4-path group-associated (destination station address, logic port number) binary group, then, the extracted 8-bit operation field is judged, and if the value of the extracted 8-bit operation field is 0xde, the matched offset field is deleted, namely, all 0 is written; if the extracted 8-bit operation field value is not 0xde, it indicates that the logical port table needs to be configured, and then the Tag and content values, i.e. (destination address, logical port number) are written into the free offset location in the addressed logical port table.
Fig. 4 is a schematic diagram of logical port table configuration and query mapping according to an embodiment of the present invention, and further illustrates the logical port configuration in step 4.
In the embodiment of the invention, the depth of the logic port table is 1024, the bit width is 128, the logic port table is composed of true double-port Blcok Ram, the A port query and the B port configuration can be realized, and 4-path group association can be supported for a storage space containing 128 bits of content at each address, namely 4 groups of key value pairs with the same compressed address, namely (Tag, content) binary groups, namely (original destination station address, logic port number) binary groups are stored, so that the conflict tolerance range of the logic port table after the destination station address compression is ensured to be 4. For 4 groups of key value pairs, each group of key value pair is composed of an original destination address with 24 bits and a logical port number with 8 bits, if the 32-bit content is binary value "0", it indicates that the space is free, and mapping configuration between the new logical port number and the destination address can be performed, and the 4 groups of key value pairs are respectively marked as offset1, offset2, offset3, and offset4 corresponding to offset amounts of 1, 2, 3, and 4 according to the distribution in 128 bits.
After comparing the extracted 8-bit operation field with the special identifier 0xde, it is determined whether the operation field indicates a delete operation or a logical port number field:
if the field is represented as a logical port number field, a 128-bit memory value at a compressed address is read, the original destination station address is compared with Tag values in 4 groups of key value pairs one by one, if the 4 groups all have non-0 Tag values, configuration exceeding a conflict tolerance range of a logical port table is indicated, an error marking signal err needs to be returned to set the signal to be '1', if the Tag values in the 4 groups of key value pairs are all 0, the idle degree at the address is represented as 4, and so on, if the Tag value in the 1 group of key value pairs is 0, the idle degree at the address is represented as 1, and the key value with the lowest offset is selected to perform writing operation on a space.
If the field indicates deletion operation, a 128-bit memory value at the compressed address is read, the original destination station address is compared with Tag values in 4 groups of key value pairs one by one, if no non-0 Tag value exists in 4 groups, the idle degree at the address is 4, deletion operation cannot be performed, an error mark err is returned to set the signal to be 1, if the Tag value in the key value pair and the destination station address in the deletion operation exist, the key value pair space needs to be deleted, and all 0 s are written into the key value pair space.
And 5, querying the logical port.
In the logic port table query module, the 24-bit destination station address field input by polling is hashed by the same CRC function during configuration to obtain a compressed destination station address compressed into 10 bits, the compressed destination station address is used as an address addressing logic port table to find out the 4-path group-associated (destination station address before compression, logic port number) binary group, and the same content with the same Tag value, namely the destination station address before compression, is selected to select the logic port number matched with the content. According to the transmission format of the data frame on the bus, namely the locallink format with the data part bit width of 64, the 8-bit logical port number field needs to be replaced to the 15 th bit to the 8 th bit of the header of the data frame.
And 6, writing in the logical port FIFO.
In the logical port flow control module, 16 sets of logical port FIFOs are set to meet the requirement of providing storage areas for 16 time division multiplexing channel identifications, wherein the cache depth of each logical port FIFO is 16384, the bit width of each logical port FIFO is 64 bits, 72 longest frames with the length of 1800 bytes or 2048 shortest frames with the length of 64 bytes can be met, 4 longest frame thresholds are set for priority levels 4 to 7 respectively, 14 longest frame thresholds are set for priority levels 0 to 3 respectively, namely, the priority level 7 threshold is 4 longest frames, the priority level 6 is 8 longest frames, and so on, the priority level 0 is 72 longest frames, thereby providing different service quality guarantees for 8 types of priority levels. And selecting a matched logical port FIFO according to the logical port number in the data frame header, and determining whether the data frame is stored according to whether the priority of the current data frame meets the priority threshold set by the corresponding logical port FIFO.
And 7, flow control frame parallelization.
In the logical port flow control module, the frame structure mainly comprises a 32-bit frame head field, a 16-bit frame length field, a 16-bit equipment number field and a load part of a 16-bit logical port start-stop signal, and a serial data frame is put into a 32-bit shift register under the drive of a channel associated clock to be parallelized, so that a parallelized field is obtained. And obtaining the start-stop states of the corresponding physical ports and the logic ports.
And 8, extracting start-stop signals.
And starting a field extraction counter by taking the same time of the 32-bit parallel shift register value and the frame head of the configuration frame as an initial start, successively extracting corresponding bit positions in the shift register according to the offset of each offset field of the configuration frame, and sequentially judging the frame length, the equipment type equipment number and the start-stop signal of each logic port with 16 bits after the frame type fields are legal fields.
And 9, reading out the logical port FIFO.
In the logic port flow control module, whether a data frame to be sent exists in the current FIFO is judged according to the position of the current logic port FIFO threshold, and whether the data frame in the current logic port FIFO is read is determined according to the back-stage port convergence back-pressure signal and the flow control start-stop signal.
Step 10, the logical ports are converged.
In the logical port output aggregation module, fair polling is carried out on non-empty logical port FIFOs according to the FIFO states of all logical ports under the current physical port, and when a high-speed interface connected with a rear-stage physical port allows data to be sent, data is read from the logical port FIFOs which acquire fair polling authority, so that aggregation of all the logical ports is completed.
And II, application embodiment. In order to prove the creativity and the technical value of the technical scheme of the invention, the part is the application example of the technical scheme of the claims on specific products or related technologies.
The invention is used in the satellite-ground switching equipment of the access network relay satellite, for the access network relay satellite, the channel of the access network relay satellite and the ground station cluster channel need to be switched in real time based on the time division multiplexing mode, and different ground station clusters are planned to be different logic port numbers, so the logic port queue provided by the invention provides temporary storage for the data stream service of different ground station clusters in the on-satellite switching equipment in the time slot not established by the communication link, and the flow control based on priority is carried out in the time slot corresponding to each logic port, thereby ensuring the service quality of the high-priority service in the time slot corresponding to each logic port.
It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus and its modules of the present invention may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of hardware circuits and software, e.g., firmware.
And thirdly, evidence of relevant effects of the embodiment. The embodiment of the invention has some positive effects in the process of research and development or use, and indeed has great advantages compared with the prior art, and the following contents are described by combining data, charts and the like in the test process.
Fig. 5 is a simulation test chart, which is implemented by performing protocol conversion on a two-layer ethernet data stream generated by a network tester through a ground detection device, configuring flow control information and logic port information by an exchange terminal of a ground detection device simulation and exchange unit, and observing the flow control condition through the network tester receiving condition.
Priority flow control test procedure
and 2, establishing 8 100Mbps bandwidth data streams entering exchange from 8 exchange ports, wherein the priority of each 100Mbps bandwidth data stream is 0-7, observing information such as receiving and sending data rate, frame loss rate and the like from an interface of a network tester, and recording test results and data.
As shown in fig. 6, the network tester captures:
the total uplink bandwidth is 800Mbps, the downlink bandwidth is 600Mbps, no frame loss is guaranteed for the data stream Qos with the priority level of 0 and the priority level of 1, no reception is guaranteed for the data stream Qos with the priority level of 6 and the data stream Qos with the priority level of 7, namely, the data frames are completely lost, and the frame loss number is sequentially increased for the data frames with the other priority levels according to the priority importance degree.
The invention is applied to the satellite-borne switching equipment, has good effect and can provide different service quality guarantees according to the priority of the logic port.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for configuring, mapping and managing logic port includes carrying out logic port lookup on data frame after being gathered and polled by each input interface according to station address before data frame is entered into grouping processing and flow classifying module, entering queue management module after queried logic port number and frame header fixed field are replaced, entering logic port flow management module after data frame is forwarded to corresponding physical port through crossbar network, using frame header logic port number field as basis to distinguish logic port to control whether data frame is stored in corresponding logic port FIFO queue according to post-stage start-stop signal, finally gathering each logic port FIFO queue to corresponding physical port for outputting.
2. The method for logical port configuration, lookup mapping and traffic management according to claim 1, wherein the method for logical port configuration, lookup mapping and traffic management employs a hash mapping method to compress a station address and configure a logical port mapping table, performs logical port number lookup on a data frame, performs logical port differentiation on an output port side after a frame header is replaced, and stores the logical port differentiation into different logical port queues composed of a plurality of blockrams.
3. The method for logical port configuration, lookup mapping and traffic management according to claim 1, wherein the logical port configuration, lookup mapping and traffic management method performs mapping of a logical port number and a destination station address by using a CRC function to perform hash on a logical port table, and ensures configuration by mapping the compressed destination station to a lookup table formed by Blcock rams, thereby searching for low latency and low hardware resource occupancy rate realized on hardware; for the flow control function of the logic port, the peripheral control logic is added to be implemented in a plurality of FIFO queues.
4. The method for logical port configuration, lookup mapping and traffic management as claimed in claim 1, wherein the method for logical port configuration, lookup mapping and traffic management comprises the steps of:
step one, parallelizing configuration frames: in a logic port configuration frame analysis module, performing serial-parallel conversion on an arriving logic port configuration data frame to obtain a parallel configuration frame field;
step two, extracting configuration fields: in a logic port configuration frame analysis module, aiming at each offset field of a parallelized configuration frame, sequentially matching with a protocol, judging a frame header, a frame length and a device type equipment number, and extracting configuration fields, namely a destination station address field and an operation field, after the frame type fields are all legal fields;
step ten, the logic port is gathered: in the logical port output aggregation module, fair polling is carried out on non-empty logical port FIFOs according to the state of each logical port FIFO under the current physical port, and when a high-speed interface connected with a rear-stage physical port allows data to be sent, data is read from the logical port FIFO with the fair polling authority, and aggregation of each logical port is completed.
5. The method for logical port configuration, lookup mapping and traffic management as claimed in claim 4, wherein the method for configuring the logical port table in step four includes:
(1) the Tag value to be configured is that the bit width of the destination station address is 24 bits, and the value range of each bit is binary number from all '0' to all '1'; the content value to be configured is a logical port number, the bit width of the operation field is 8 bits, the value range is from all binary numbers '0' to all binary numbers '1', the bit width of the destination station address after hash compression to be configured is 10 bits, and the value range is from all binary numbers '0' to all binary numbers '1';
(2) judging whether the content value, namely the logical port number field, and the operation field value are 0xde after being converted into hexadecimal numbers, if so, executing the step (3); otherwise, executing the step (6);
(3) addressing the logic port table according to the station address after hash compression, finding the position of the corresponding Blcok Ram row and reading out the content, wherein 4-way group-associated key value pairs coexist and stored, the key value pair is a binary group consisting of an original destination station address and a logic port number, matching the obtained destination station address before compression with the original destination station address in the 4 groups of key value pairs, judging whether the same value exists, and if so, executing the step (4); otherwise, executing the step (5);
(4) setting all the Tag parts in 4 groups of key value pairs which are matched with the original destination station address field part to be 0, setting the bit width to be 32, and executing the step (8);
(5) setting the configuration error signal err to be 1, and executing the step (9);
(6) addressing the logic port table according to the station address after hash compression, finding the position of the corresponding Blcok Ram row and reading out the content, wherein 4-way group-associated key value pairs coexist and stored, the key value pair is a binary group consisting of an original destination station address and a logic port number, matching the obtained destination station address before compression with the original destination station address in the 4 groups of key value pairs, judging whether the same value exists or whether the Tag value is all '0', and if so, executing the step (7); otherwise, executing the step (5);
(7) writing a configuration value into a Tag part in 4 groups of key value pairs, wherein the Tag part is a key value pair matched with an original destination station address field part, or writing a first group of key value pairs with Tag part being all '0', and the configuration value is a binary group consisting of an original destination station address and a logical port number, and executing the step (8);
(8) setting a configuration success signal finish to be 1, and executing the step (9);
(9) and outputting the configuration state.
6. A computer arrangement comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of: the data frames after being aggregated and polled by each input interface are searched for a logical port according to a station address before entering a grouping processing and flow classifying module, the searched logical port number and a frame header fixed field are replaced and then enter a queue management module, the data frames are forwarded to a corresponding physical port through a crossbar network and then enter a logical port flow management module, the logical port is distinguished according to the frame header logical port number field, whether the data frames are stored in a corresponding logical port FIFO queue or not is controlled according to a post-stage start-stop signal, and finally, each logical port FIFO queue is aggregated to the corresponding physical port for output.
7. A computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the logical port configuration, lookup mapping and traffic management method according to any one of claims 1 to 5.
8. An information data processing terminal, characterized in that the information data processing terminal is used for implementing the logical port configuration, lookup mapping and traffic management method as claimed in any one of claims 1 to 5.
9. The logical port configuration, lookup mapping and flow management system for implementing the logical port configuration, lookup mapping and flow management method according to any one of claims 1 to 5, wherein the logical port configuration, lookup mapping and flow management system comprises a destination station hash compression module, a logical port table configuration module, a destination station hash compression module, a logical port table query module, a logical port flow control frame parsing module, a logical port flow control module and a logical port output convergence module;
the system comprises a logic port configuration frame analysis module, a control information extraction module and a control information extraction module, wherein the logic port configuration frame analysis module is used for analyzing a logic port configuration null control frame generated by a control computer, identifying a frame header field and extracting a corresponding control information field after confirming a check field after performing serial-parallel conversion on a configuration data frame, and analyzing logic port control information;
the configuration destination station hash compression module is used for performing hash compression on the 24-bit destination station address to 10 bits, so that the logic port configuration module can address the logic port table by using the address after 10-bit compression;
the logical port configuration module is used for writing a Tag value and a content value into an address of the true dual-port BlcokRAM corresponding to the post-compression station address, and the Tag value and the content value are a binary group consisting of the station address and the logical port number before compression;
the query destination station hash compression module is used for extracting and hash compressing a destination station field carried in an arrival data frame to obtain an address required for querying a logic port table and confirming a Tag value;
the logical port table query module is used for addressing a logical port table consisting of the true dual-port BlcokRAM, searching a 4-path group-associated binary group consisting of a destination station address and a logical port number, matching the corresponding binary group according to the station address before compression to obtain a correct logical port field and replacing the correct logical port field with a data frame header redundancy field;
the logic port flow control frame analysis module is used for analyzing the back-pressure data frame of the switch post-stage equipment and obtaining a flow control start-stop signal;
the logical port flow control module is used for judging which logical port FIFO the data frame should be distributed to according to the logical port number replaced at the head of the current data frame and the threshold value of the logical port FIFO corresponding to the priority of the data frame, and determining the reading of the data frame according to the start-stop signal of the logical port;
and the logical port output aggregation module is used for performing fair polling on the logical port FIFO with the current flow control start-stop signal set as 'start', and then aggregating the data frames to a physical port to be sent to the post-stage equipment of the switch.
10. The logical port configuration, lookup mapping and traffic management system according to claim 9 wherein the logical port configuration frame parsing module parses logical port control information into two types:
the configuration information field is composed of a binary group consisting of a destination station address and a logical port number;
and the second group is represented by a binary group consisting of a destination station address and a special character, wherein the special character represents deleting the logic port configuration under the destination station address.
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