CN114785330A - High voltage integrated circuit, counting method and semiconductor circuit - Google Patents
High voltage integrated circuit, counting method and semiconductor circuit Download PDFInfo
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- CN114785330A CN114785330A CN202210598150.1A CN202210598150A CN114785330A CN 114785330 A CN114785330 A CN 114785330A CN 202210598150 A CN202210598150 A CN 202210598150A CN 114785330 A CN114785330 A CN 114785330A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08116—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in composite switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
Abstract
The invention provides a high-voltage integrated circuit, a counting method and a semiconductor circuit, wherein the high-voltage integrated circuit comprises an overcurrent protection circuit and a drive circuit; the input end of the over-current protection circuit is used for receiving an external current signal, the output end of the over-current protection circuit is connected with the driving circuit, and the over-current protection circuit is used for judging the current signal according to a preset judgment rule to generate an over-current signal; the preset judgment rule is that whether the number of current values of the current signals larger than a preset current threshold value in a preset time period exceeds a preset count value or not, if yes, the output of the overcurrent protection circuit is closed, and if not, overcurrent signals are generated; the overcurrent protection circuit comprises a timer and a counter, wherein the timer is used for setting a preset time period, and the counter is used for setting a preset count value and counting the number of current values of the current signals which are larger than a preset current threshold value; the driving circuit drives an external switching tube according to the overcurrent signal. The technical scheme of the invention can filter interference signals and has high reliability.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a high-voltage integrated circuit, a counting method and a semiconductor circuit.
Background
A high Voltage Integrated circuit (hvic) is an Integrated circuit product for converting an MCU signal into a driving signal for driving a switching tube such as an IGBT. Generally, a high-voltage integrated circuit integrates various basic devices such as a switch tube, a diode, a voltage regulator tube, a resistor, a capacitor and the like to form a driving circuit, a pulse generating circuit, a delay circuit, a filter circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage protection circuit, a bootstrap circuit and the like. When the high-voltage integrated circuit works, on one hand, the high-voltage integrated circuit receives a control signal of the external processor and drives the subsequent switch tube to work, and on the other hand, the high-voltage integrated circuit also sends a related working state detection signal back to the external processor so as to realize the control of the working condition of the circuit.
In the related art, the overcurrent protection circuit is integrated in the high-voltage integrated circuit, and when various overcurrent conditions occur, the overcurrent protection circuit has a single circuit function and cannot flexibly exert the overcurrent protection function. When the overcurrent signal reaches the threshold value, the overcurrent protection circuit enters the overcurrent protection function, and the overcurrent signal cannot be intelligently judged to be a real overcurrent or an interference signal, so that the high-voltage integrated circuit can generate misoperation to influence the normal work of the high-voltage integrated circuit.
Disclosure of Invention
The invention aims to provide a high-voltage integrated circuit which can effectively filter interference signals and has high reliability aiming at the defects in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a high voltage integrated circuit, which includes an overcurrent protection circuit and a driving circuit; the input end of the over-current protection circuit is used for receiving an external current signal, the output end of the over-current protection circuit is connected with the driving circuit, and the over-current protection circuit is used for judging the current signal according to a preset judgment rule to generate an over-current signal; the preset judgment rule is that whether the number of current values of the current signals which are larger than a preset current threshold value exceeds a preset count value or not within a preset time period, if so, the output of the over-current protection circuit is closed, and if not, an over-current signal is generated; the overcurrent protection circuit comprises a timer and a counter, the timer is used for setting the preset time period, and the counter is used for setting the preset count value and counting the number of the current values of the current signals which are larger than the preset current threshold value; and the driving circuit drives an external switching tube according to the overcurrent signal.
Furthermore, the driving circuit comprises a high-voltage side driving circuit, an interlocking circuit and a low-voltage side driving circuit, wherein the high-voltage side driving circuit is connected with the low-voltage side driving circuit through the interlocking circuit.
Furthermore, the high-side driving circuit is provided with 3 channels, the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit, the high-side undervoltage protection circuit is used for realizing a high-side driving undervoltage protection function, and the bootstrap circuit is used for realizing a bootstrap power supply function; the low-voltage side driving circuit is provided with 3 channels.
Furthermore, the high-voltage integrated circuit also comprises an overvoltage protection circuit, an enabling circuit, an over-temperature protection circuit and an error reporting circuit;
the output end of the overcurrent protection circuit is connected to the first input end of the error reporting circuit;
the output end of the overvoltage protection circuit is connected to the second input end of the error reporting circuit;
the output end of the enabling circuit is connected to the third input end of the error reporting circuit;
the output end of the over-temperature protection circuit is connected to the fourth input end of the error reporting circuit;
the first output end of the error reporting circuit is connected to the input end of the driving circuit;
and the first output end of the error reporting circuit is used for being connected with an external processor.
Furthermore, the high-voltage integrated circuit further comprises a power supply circuit, and an output end of the power supply circuit is connected to an input end of the overvoltage protection circuit.
Furthermore, the over-current protection circuit further comprises a first comparator, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, an NMOS transistor, an OR gate and a logic circuit,
a positive input end of the first comparator is used as an input end of the over-current protection circuit;
a negative input end of the first comparator is connected to a second end of the first voltage-dividing resistor and a first end of the second voltage-dividing resistor respectively;
the first end of the first voltage-dividing resistor is used for being connected to a reference voltage, the second end of the second voltage-dividing resistor is respectively connected to the first end of the third voltage-dividing resistor and the drain of the NMOS transistor, and the second end of the third voltage-dividing resistor is connected to the ground;
the grid electrode of the NMOS transistor is connected to the signal control end of the logic circuit, and the source electrode of the NMOS transistor is connected to the ground;
the output end of the first comparator is respectively connected to the first input end of the counter and the first input end of the OR gate;
the output end of the timer is connected to the second input end of the counter, and the output end of the counter is connected to the second input end of the OR gate;
the output end of the OR gate is connected to the input end of the logic circuit;
and the output end of the logic circuit is used as the output end of the overcurrent protection circuit.
Further, the timer comprises a pulse circuit, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a diode, a second comparator, a third comparator, a first NAND gate, a second NAND gate, a third NAND gate, an inverter and a bipolar junction transistor,
the output end of the pulse circuit is connected to the first end of the second capacitor;
a second end of the second capacitor is connected to a positive terminal of the diode, a second end of the sixth resistor and a positive terminal of the third comparator respectively, and a negative terminal of the diode and a first end of the sixth resistor are both connected to a power supply voltage;
a negative end of the third comparator is respectively connected to a second end of the second resistor and a first end of the third resistor, and a second end of the third resistor is connected to the ground;
the output end of the third comparator is connected to the first input end of the second NAND gate;
the positive end of the second comparator is respectively connected to the second end of the first resistor, the first end of the second resistor and the first end of the first capacitor, the first end of the first resistor is connected to a power supply voltage, and the second end of the first capacitor is connected to the ground;
the negative end of the second comparator is respectively connected to the second end of the fifth resistor, the first end of the third capacitor and the collector of the bipolar junction transistor, the fifth resistor is connected to a power supply voltage, and the second end of the third capacitor and the emitter of the bipolar junction transistor are both connected to the ground;
the base of the bipolar junction transistor is connected to the second end of the fourth resistor;
the output end of the second comparator is connected to the first input end of the first NAND gate;
the second input end of the first NAND gate is connected to a power supply voltage, and the third input end of the first NAND gate is respectively connected to the output end of the second NAND gate and the first input end of the third NAND gate;
a second input end of the third NAND gate is connected to a power supply voltage;
the output end of the first NAND gate is connected to the second input end of the second NAND gate;
and the output end of the third NAND gate is respectively connected to the first end of the fourth resistor and the input end of the phase inverter, and the output end of the phase inverter is used as the output end of the timer.
Furthermore, the counter comprises a time input circuit, a counting control circuit, a zero clearing circuit, a counting circuit and a carry circuit,
the input end of the time input circuit is used as the time input end of the counter, the first output end of the time input circuit is connected to the input end of the counting control circuit, and the second output end of the time input circuit is connected to the input end of the zero clearing circuit;
the output end of the counting control circuit is connected to the first input end of the counting circuit, the output end of the zero clearing circuit is connected to the second input end of the counting circuit, and the third input end of the counting circuit is used as the counted signal input end of the counter;
the output end of the counting circuit is connected to the input end of the carry circuit;
and the output end of the carry circuit is used as the output end of the counter.
In a second aspect, the present invention also provides a counting method, which is applied to the high voltage integrated circuit provided by the present invention, and the method comprises the following steps:
step S1, setting a timing time in the time input circuit;
step S2, starting the counting control circuit and sending a counting starting instruction;
step S3, receiving a counted signal to the counting circuit, and the counting circuit counts;
step S4, determining whether the counting circuit reaches a counting carry, if yes, sending a carry signal and entering step S5, if no, returning to step S3;
step S5, the count circuit is cleared and the process returns to step S3.
In a third aspect, the present invention further provides a semiconductor circuit, which includes a switching tube and the above-mentioned high voltage integrated circuit provided by the present invention; the high-voltage integrated circuit is connected to the switch tube and used for driving the switch tube.
The invention has the beneficial effects that: in the invention, a timer and a counter are arranged through an overcurrent protection circuit of the high-voltage integrated circuit, the timer is used for setting the preset time period, the counter is used for setting the preset counting value and counting the number of current values of the current signals which are larger than a preset current threshold value, and the overcurrent protection circuit judges the current signals according to a preset judgment rule to generate overcurrent signals. The circuit arrangement enables the high-voltage integrated circuit to determine whether the current signal is a real overcurrent or an interference signal. Thereby preventing the drive circuit from being triggered due to interference signals, and improving the reliability.
Drawings
Fig. 1 is a block diagram of a high voltage integrated circuit according to an embodiment of the present invention;
FIG. 2 is a circuit schematic of one implementation of a high voltage integrated circuit provided by an embodiment of the present invention;
fig. 3 is a circuit schematic diagram of an embodiment of an over-current protection circuit according to the present invention;
FIG. 4 is a schematic circuit diagram of a timer of a high voltage integrated circuit according to an embodiment of the present invention;
FIG. 5 is a graph of voltage versus time for the operation of the timer of FIG. 4;
FIG. 6 is a block diagram of a counter of a high voltage integrated circuit according to an embodiment of the present invention;
FIG. 7 is a block flow diagram of a counting method of the present invention;
fig. 8 is a schematic structural diagram of a semiconductor circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples.
A high voltage integrated circuit 100 of the present invention. Referring to fig. 1-2, fig. 1 is a block diagram of a high voltage integrated circuit 100 according to an embodiment of the present invention; fig. 2 is a circuit schematic diagram of an implementation of the high voltage integrated circuit 100 according to an embodiment of the present invention.
The high-voltage integrated circuit 100 includes an overcurrent protection circuit 10, a driving circuit 20, an overvoltage protection circuit 30, an enable circuit 40, an over-temperature protection circuit 50, an error reporting circuit 60, and a power supply circuit 70.
The circuit connection relationship of the high-voltage integrated circuit 100 is as follows:
the output end of the over-current protection circuit 10 is connected to the driving circuit 20. The output terminal of the over-current protection circuit 10 is connected to the first input terminal of the error reporting circuit 60. An output of the over-voltage protection circuit 30 is connected to a second input of the error reporting circuit 60. An output of the enabling circuit 40 is connected to a third input of the error reporting circuit 60. The output terminal of the over-temperature protection circuit 50 is connected to the fourth input terminal of the error reporting circuit 60. A first output terminal of the error reporting circuit 60 is connected to an input terminal of the driving circuit 20. A first output of the error reporting circuit 60 is used for connecting to an external processor. The output of the power circuit 70 is connected to the input of the overvoltage protection circuit 30. Wherein, the first and the second end of the pipe are connected with each other,
the power circuit 70 includes a 5V LDO circuit and a 1.2V BANDGAP circuit, supplies external 5V power and 15V voltage to all circuits and circuits inside the HVIC, and provides a stable 1.2V voltage reference for the HVIC and external circuits.
The input end of the over-current protection circuit 10 is configured to receive an external current signal ITRIP, and the over-current protection circuit 10 is configured to determine the current signal ITRIP according to a preset determination rule to generate an over-current signal. The preset judgment rule is that whether the number of the current values of the current signals ITRIP which are larger than a preset current threshold value exceeds a preset count value within a preset time period, if so, the output of the overcurrent protection circuit 10 is turned off, and if not, overcurrent signals are generated.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a specific implementation of the overcurrent protection circuit 10 according to an embodiment of the present invention. Specifically, the over-current protection circuit 10 includes a timer 101, a counter 102, a first comparator CMP, a first voltage dividing resistor RV1, a second voltage dividing resistor RV2, a third voltage dividing resistor RV3, an NMOS transistor Q1, an OR gate OR, and a logic circuit 103.
The circuit connection relationship of the over-current protection circuit 10 is as follows:
the positive input terminal of the first comparator CMP is used as the input terminal of the over-current protection circuit 10.
The negative input terminal of the first comparator CMP is connected to the second terminal of the first voltage-dividing resistor RV1 and the first terminal of the second voltage-dividing resistor RV2, respectively.
A first end of the first voltage-dividing resistor RV1 is used for connecting 620 to a reference voltage, a second end of the second voltage-dividing resistor RV2 is connected to a first end of the third voltage-dividing resistor RV3 and a drain of the NMOS transistor Q1, respectively, and a second end of the third voltage-dividing resistor RV3 is connected to a ground GND.
The gate of the NMOS transistor Q1 is connected to the signal control terminal of the logic circuit 103, and the source of the NMOS transistor Q1 is connected to the ground GND.
The outputs of the first comparator CMP are connected to a first input of the counter 102 and a first input of the OR gate OR, respectively.
An output terminal of the timer 101 is connected to a second input terminal of the counter 102, and an output terminal of the counter 102 is connected to a second input terminal of the OR gate OR.
The output of the OR gate OR is connected to the input of the logic circuit 103.
The output end of the logic circuit 103 is used as the output end of the over-current protection circuit 10.
The operating principle of the over-current protection circuit 10 is as follows: the timer 101 sets an M time, and during the M time, when the current signal ITRIP outputs the voltage signal which exceeds the voltage division point 0504N times, that is, when the counter 102 counts N times of the voltage signal when the current signal ITRIP exceeds the voltage division point (the connection point between the second voltage division resistor RV2 and the third voltage division resistor RV 3) within the M time, the carry output port of the counter 102 is at a high potential, the output port compared at this time is at a low potential, OR the output port of the gate OR outputs a high potential, the current signal itrp is masked, the logic circuit 103 may consider that the application circuit of the high voltage integrated circuit 100 does not have the overcurrent phenomenon (OR the current signal itrp is an interference signal, and no overcurrent protection is needed), and the high voltage integrated circuit 100 continues to operate normally. Meanwhile, the counter 102 is started to be cleared, so that the counted and recorded signals of N times are cleared, the timer 101 also restarts to count new time, and the work is repeated.
In the period M, when the current signal ITRIP exceeds the voltage signal at the voltage division point for N times, that is, when the counter 102 counts the voltage signal at the voltage division point for N times, the counter 102 outputs a low voltage from the carry output port, and when the current signal ITRIP exceeds the threshold, the comparator CMP outputs a low voltage, OR the output port of the gate OR outputs a low voltage, so as to enter the over-current protection; when the current signal ITRIP does not exceed the threshold, the comparator CMP outputs a high voltage, the output port of the OR gate OR outputs a high voltage, and the high voltage integrated circuit 100 operates normally.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of the timer 101 of the high voltage integrated circuit 100 according to the embodiment of the present invention.
The timer 101 is configured to set the preset time period.
Specifically, the timer 101 includes a pulse circuit 101a, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a diode D1, a second comparator a1, a third comparator a2, a first nand gate G1, a second nand gate G2, a third nand gate G3, an inverter G4, and a bipolar junction transistor Q2.
The circuit connection relationship of the timer 101 is as follows:
the output terminal of the pulse circuit 101a is connected to the first terminal of the second capacitor C2.
A second end of the second capacitor C2 is connected to the positive terminal of the diode D1, the second end of the sixth resistor R6, and the positive terminal of the third comparator a2, respectively, and a negative terminal of the diode D1 and a first end of the sixth resistor R6 are both connected to a power supply voltage.
The negative terminal of the third comparator a2 is connected to the second terminal of the second resistor R2 and the first terminal of the third resistor R3, respectively, and the second terminal of the third resistor R3 is connected to the ground GND.
The output of the third comparator A2 is connected to the first input of the second NAND gate G2.
The positive terminal of the second comparator a1 is connected to the second terminal of the first resistor R1, the first terminal of the second resistor R2, and the first terminal of the first capacitor C1, respectively, the first terminal of the first resistor R1 is connected to a power supply voltage, and the second terminal of the first capacitor C1 is connected to the ground GND.
The negative terminal of the second comparator a1 is connected to the second terminal of the fifth resistor R5, the first terminal of the third capacitor C3, and the collector of the bjt Q2, respectively, the fifth resistor R5 is connected to the power supply voltage, and the second terminal of the third capacitor C3 and the emitter of the bjt Q2 are both connected to the ground GND.
The base of the bjt Q2 is connected to the second terminal of the fourth resistor R4.
The output of the second comparator A1 is connected to the first input of the first NAND-gate G1.
The second input of the first nand gate G1 is connected to a power supply voltage, and the third input of the first nand gate G1 is connected to the output of the second nand gate G2 and the first input of the third nand gate G3, respectively.
A second input of the third nand gate G3 is connected to a supply voltage.
The output of the first NAND gate G1 is connected to a second input of the second NAND gate G2.
The output end of the third nand gate G3 is connected to the first end of the fourth resistor R4 and the input end of the inverter G4, and the output end of the inverter G4 is used as the output end of the timer 101.
The working principle of the timer 101 is as follows:
the diode D1 is a clamping diode, the input end of the circuit is at the power level in the steady state, the internal discharge is performed, the bipolar junction transistor Q2 is a switching MOS transistor, the bipolar junction transistor Q2 is turned on, the output end Vo outputs the low level, and when the pulse circuit 101a outputs the pulse signal. And the potential of V1 is instantaneously lower than 1/3Vcc, the low-level comparator acts, the monostable circuit starts a steady-state process, the second capacitor C2 starts charging, and Vc increases according to an exponential law. When Vc is charged to 2/3Vcc, the high level comparator is activated, the second comparator a1 is turned over, the output Vo returns from high level to low level, the bjt Q2 is turned on again, the charge on the second capacitor C2 is quickly discharged through the bjt Q2, the transient state is over, and the capacitor is recovered to be stable, so that the next trigger pulse is ready to arrive.
Referring to fig. 5, fig. 5 is a voltage-time relationship diagram of the timer 101 in fig. 4 during operation. The duration Tw of the transient state of the timer 101 (i.e., the delay time) is determined by the magnitude of the resistor R and the capacitor C in the external device. Tw =1.1RC, and the delay time can be varied between several microseconds and several tens of minutes by changing the sizes of the resistor R and the capacitor C.
The counter 102 is configured to set the preset count value and count the number of the current values of the current signal ITRIP that are greater than the preset current threshold.
Referring to fig. 6, fig. 6 is a block diagram of a counter 102 of the high voltage integrated circuit 100 according to an embodiment of the present invention.
Specifically, the counter 102 includes a time input circuit 1021, a count control circuit 1022, a clear circuit 1023, a count circuit 1024, and a carry circuit 1025.
An input end of the time input circuit 1021 is used as a time input end TIN of the counter 102, a first output end of the time input circuit 1021 is connected to an input end of the count control circuit 1022, and a second output end of the time input circuit 1021 is connected to an input end of the zero clearing circuit 1023.
An output terminal of the count control circuit 1022 is connected to a first input terminal of the counting circuit 1024, an output terminal of the zero clearing circuit 1023 is connected to a second input terminal of the counting circuit 1024, and a third input terminal of the counting circuit 1024 is used as a counted signal input terminal IN of the counter 102.
An output of the counting circuit 1024 is connected to an input of the carry circuit 1025.
The output terminal of the carry circuit 1025 serves as the output terminal OUT1 of the counter 102.
The working process of the counter 102 is as follows:
the time input circuit 1021 receives the timing time signal from the TIN, and the time input circuit 1021 informs that the count control circuit 1022 starts counting to reach the required carry output. After the one-cycle counting is completed, the clear circuit 1023 clears the count circuit 1024 and the carry circuit 1025 to prepare for the next counting.
The driving circuit 20 drives an external switching tube according to the overcurrent signal.
The driving circuit 20 includes a high-voltage side driving circuit 201, an interlock circuit 202, and a low-voltage side driving circuit 203, and the high-voltage side driving circuit 201 is connected to the low-voltage side driving circuit 203 through the interlock circuit 202.
In this embodiment, the high-side driving circuit 201 has 3 channels, and the high-side driving circuit 201 includes a high-side under-voltage protection circuit 201a and a bootstrap circuit 201 b. The high-side undervoltage protection circuit 201a is used for realizing a high-side driving undervoltage protection function. The bootstrap circuit 201b is used to implement a bootstrap power supply function. The low-voltage side driving circuit 203 is provided with 3 channels.
The invention also provides a counting method, which is applied to the high-voltage integrated circuit 100, in particular to the counter 102.
Referring to fig. 7, fig. 7 is a flow chart diagram of the counting method of the present invention.
Specifically, the counting method comprises the following steps:
step S1, a timing time is set in the time input circuit 1021.
In step S2, the count control circuit 1022 is activated to issue a start count command.
Step S3, receiving the counted signal to the counting circuit 1024, and the counting circuit 1024 counts.
Step S4, determining whether the counting circuit 1024 reaches the counting carry, if yes, sending a carry signal and entering step S5, otherwise, returning to step S3.
Step S5, the counter circuit 1024 is cleared, and the process returns to step S3.
The invention also provides a semiconductor circuit 300.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a semiconductor circuit according to an embodiment of the invention.
The semiconductor circuit 300 comprises a switching tube 200 and the high voltage integrated circuit 100. The high voltage integrated circuit 100 is connected to the switching tube 200, and the high voltage integrated circuit 100 is used for driving the switching tube 200.
It is understood that the contents of the above-mentioned embodiments of the high voltage integrated circuit are all applicable to the embodiment of the semiconductor circuit 300, the functions implemented by the embodiment of the semiconductor circuit 300 are the same as those of the above-mentioned embodiment of the high voltage integrated circuit 100, and the advantageous effects achieved by the embodiment of the high voltage integrated circuit 100 are also the same as those achieved by the above-mentioned embodiment of the high voltage integrated circuit 100.
In the invention, a timer 101 and a counter 102 are arranged through an overcurrent protection circuit 10 of the high-voltage integrated circuit 100, the timer 101 is used for setting the preset time period, the counter 102 is used for setting the preset count value and counting the number of current values of the current signals which are larger than a preset current threshold value, and the overcurrent protection circuit 10 judges the current signals according to a preset judgment rule to generate overcurrent signals. This circuit arrangement allows the high voltage integrated circuit 100 to determine whether a current signal is truly over-current or a problem with an interfering signal. Thereby preventing the driving circuit 20 from being triggered by the interference signal and thus improving reliability.
The above description is only a preferred embodiment of the present invention, and for those skilled in the art, the present invention should not be limited by the description of the present invention, which should be interpreted as a limitation.
Claims (10)
1. The high-voltage integrated circuit is characterized by comprising an overcurrent protection circuit and a drive circuit;
the input end of the over-current protection circuit is used for receiving an external current signal, the output end of the over-current protection circuit is connected with the driving circuit, and the over-current protection circuit is used for judging the current signal according to a preset judgment rule to generate an over-current signal; the preset judgment rule is that whether the number of current values of the current signals which are larger than a preset current threshold value exceeds a preset count value or not within a preset time period, if so, the output of the over-current protection circuit is closed, and if not, an over-current signal is generated;
the overcurrent protection circuit comprises a timer and a counter, the timer is used for setting the preset time period, and the counter is used for setting the preset count value and counting the number of the current values of the current signals which are larger than the preset current threshold value;
and the driving circuit drives an external switching tube according to the overcurrent signal.
2. The high voltage integrated circuit of claim 1, wherein the driver circuit comprises a high voltage side driver circuit, an interlock circuit, and a low voltage side driver circuit, the high voltage side driver circuit and the low voltage side driver circuit being connected through the interlock circuit.
3. The high-voltage integrated circuit according to claim 2, wherein the high-voltage side driving circuit is provided with 3 channels, the high-voltage side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit, the high-side undervoltage protection circuit is used for realizing a high-side driving undervoltage protection function, and the bootstrap circuit is used for realizing a bootstrap power supply function; the low-voltage side driving circuit is provided with 3 channels.
4. The high voltage integrated circuit of claim 1, further comprising an over-voltage protection circuit, an enable circuit, an over-temperature protection circuit, and an error reporting circuit;
the output end of the overcurrent protection circuit is connected to the first input end of the error reporting circuit;
the output end of the overvoltage protection circuit is connected to the second input end of the error reporting circuit;
the output end of the enabling circuit is connected to the third input end of the error reporting circuit;
the output end of the over-temperature protection circuit is connected to the fourth input end of the error reporting circuit;
the first output end of the error reporting circuit is connected to the input end of the driving circuit;
and the first output end of the error reporting circuit is used for connecting an external processor.
5. The high voltage integrated circuit of claim 4, further comprising a power supply circuit, an output of the power supply circuit being connected to an input of the over-voltage protection circuit.
6. The high voltage integrated circuit of claim 1, wherein the over-current protection circuit further comprises a first comparator, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, an NMOS transistor, an OR gate, and a logic circuit,
a positive input end of the first comparator is used as an input end of the overcurrent protection circuit;
the negative input end of the first comparator is respectively connected to the second end of the first divider resistor and the first end of the second divider resistor;
a first end of the first voltage-dividing resistor is used for being connected to a reference voltage, a second end of the second voltage-dividing resistor is respectively connected to a first end of the third voltage-dividing resistor and a drain of the NMOS transistor, and a second end of the third voltage-dividing resistor is connected to the ground;
the grid electrode of the NMOS transistor is connected to the signal control end of the logic circuit, and the source electrode of the NMOS transistor is connected to the ground;
the output end of the first comparator is respectively connected to the first input end of the counter and the first input end of the OR gate;
the output end of the timer is connected to the second input end of the counter, and the output end of the counter is connected to the second input end of the OR gate;
the output end of the OR gate is connected to the input end of the logic circuit;
and the output end of the logic circuit is used as the output end of the overcurrent protection circuit.
7. The HVIC of claim 1, wherein the timer comprises a pulse circuit, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a diode, a second comparator, a third comparator, a first NAND gate, a second NAND gate, a third NAND gate, an inverter, and a bipolar junction transistor,
the output end of the pulse circuit is connected to the first end of the second capacitor;
a second end of the second capacitor is connected to a positive terminal of the diode, a second end of the sixth resistor and a positive terminal of the third comparator respectively, and a negative terminal of the diode and a first end of the sixth resistor are both connected to a power supply voltage;
the negative end of the third comparator is respectively connected to the second end of the second resistor and the first end of the third resistor, and the second end of the third resistor is connected to the ground;
the output end of the third comparator is connected to the first input end of the second NAND gate;
the positive end of the second comparator is respectively connected to the second end of the first resistor, the first end of the second resistor and the first end of the first capacitor, the first end of the first resistor is connected to a power supply voltage, and the second end of the first capacitor is connected to the ground;
the negative end of the second comparator is respectively connected to the second end of the fifth resistor, the first end of the third capacitor and the collector of the bipolar junction transistor, the fifth resistor is connected to a power supply voltage, and the second end of the third capacitor and the emitter of the bipolar junction transistor are both connected to the ground;
the base of the bipolar junction transistor is connected to the second end of the fourth resistor;
the output end of the second comparator is connected to the first input end of the first NAND gate;
a second input end of the first NAND gate is connected to a power supply voltage, and a third input end of the first NAND gate is respectively connected to an output end of the second NAND gate and a first input end of the third NAND gate;
a second input end of the third NAND gate is connected to a power supply voltage;
the output end of the first NAND gate is connected to the second input end of the second NAND gate;
and the output end of the third NAND gate is respectively connected to the first end of the fourth resistor and the input end of the phase inverter, and the output end of the phase inverter is used as the output end of the timer.
8. The high voltage integrated circuit of claim 1, wherein the counter comprises a time input circuit, a count control circuit, a clear circuit, a count circuit, and a carry circuit,
the input end of the time input circuit is used as the time input end of the counter, the first output end of the time input circuit is connected to the input end of the counting control circuit, and the second output end of the time input circuit is connected to the input end of the zero clearing circuit;
the output end of the counting control circuit is connected to the first input end of the counting circuit, the output end of the zero clearing circuit is connected to the second input end of the counting circuit, and the third input end of the counting circuit is used as the counted signal input end of the counter;
the output end of the counting circuit is connected to the input end of the carry circuit;
and the output end of the carry circuit is used as the output end of the counter.
9. A counting method applied to the high voltage integrated circuit according to claim 8, comprising the steps of:
step S1, setting a timing time in the time input circuit;
step S2, starting the counting control circuit and sending a counting starting instruction;
step S3, receiving a counted signal to the counting circuit, and the counting circuit counts;
step S4, judging whether the counting circuit reaches the counting carry, if yes, sending a carry signal and entering step S5, if not, returning to the step S3;
step S5, the count circuit is cleared and the process returns to step S3.
10. A semiconductor circuit, characterized in that the semiconductor circuit comprises a switching tube and a high voltage integrated circuit according to any one of claims 1 to 8; the high-voltage integrated circuit is connected to the switch tube and used for driving the switch tube.
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| CN115333342A (en) * | 2022-10-11 | 2022-11-11 | 广东汇芯半导体有限公司 | High voltage integrated circuit and semiconductor circuit |
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| CN115333342A (en) * | 2022-10-11 | 2022-11-11 | 广东汇芯半导体有限公司 | High voltage integrated circuit and semiconductor circuit |
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