CN114784156A

CN114784156A - Light emitting diode and light emitting device

Info

Publication number: CN114784156A
Application number: CN202210485205.8A
Authority: CN
Inventors: 陈劲华; 王彦钦; 郭桓邵; 彭钰仁
Original assignee: Tianjin Sanan Optoelectronics Co Ltd
Current assignee: Tianjin Sanan Optoelectronics Co Ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2022-07-22

Abstract

The invention discloses a light-emitting diode and a light-emitting device, wherein the light-emitting diode comprises a semiconductor epitaxial lamination layer, a first current expansion layer, a first covering layer, an active layer, a second covering layer and a second current expansion layer, wherein the semiconductor epitaxial lamination layer is provided with a first surface and a second surface which are opposite; the method is characterized in that: the first cover layer comprises a superlattice structure formed by alternately stacking a first sub-layer and a second sub-layer; the first sublayer is made of combined Al_x1Ga_1‑x1InP material composition; the second sublayer is made of Al_x2Ga_1‑x2InP material, wherein x1 is more than 0 and x2 is less than or equal to 1. The first covering layer and/or the second covering layer adopt a superlattice structure, so that the crystal quality of the semiconductor epitaxial lamination and the current spreading uniformity of the light-emitting diode can be improved, and the light-emitting efficiency and the light-emitting brightness of the light-emitting diode are improved.

Description

Light emitting diode and light emitting device

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a light-emitting diode and a light-emitting device.

Background

A Light Emitting Diode (LED) has the advantages of high Light Emitting intensity, high efficiency, small volume, and long service life, and is considered as one of the most potential Light sources. In recent years, LEDs have been widely used in daily life, for example, in the fields of illumination, signal display, backlight, vehicle lights, and large screen display, and these applications also put higher demands on the brightness and light emitting efficiency of LEDs.

Disclosure of Invention

In order to improve the brightness of the light emitting diode, the invention provides a light emitting diode and a light emitting device, wherein the light emitting diode comprises: the semiconductor epitaxial lamination layer is provided with a first surface and a second surface which are opposite, and comprises a first current expansion layer, a first covering layer, an active layer, a second covering layer and a second current expansion layer which are sequentially stacked from the first surface to the second surface; the method is characterized in that: the first covering layer comprises a superlattice layer formed by alternately stacking a first sublayer and a second sublayer; the first sublayer is made of combined Al_x1Ga_1-x1InP material composition; the second sublayer is made of Al_x2Ga_1-x2InP material, wherein x1 is more than 0 and x2 is less than or equal to 1.

In some alternative embodiments, x2-x1 ≧ 0.2.

In some alternative embodiments, the content x1 of the Al component of the first sublayer ranges from 0.4 ≦ x1 < 1; the content x2 of the Al component of the second sublayer is in the range of 0.6-1 to x 1-1.

In some optional embodiments, the first sub-layer has a thickness in a range of 0.5 to 15 nm; the thickness range of the second sub-layer is 2-15 nm.

In some alternative embodiments, the superlattice structure has more than 10 pairs of periods.

In some optional embodiments, the first capping layer has a thickness of 300 to 1500nm and a doping concentration of 3E17 to 9E 17.

In some optional embodiments, the first cladding layer includes at least a first portion and a second portion, the first portion is composed of AlInP material, and the second portion is a superlattice layer formed by alternately stacking the first sub-layer and the second sub-layer.

In some optional embodiments, the first portion of the first cladding layer has a thickness in a range of 300 to 1500nm, and the second portion has a thickness in a range of 35 to 250 nm.

In some alternative embodiments, the second cover layer comprises a third sublayer and a fourth sublayer alternating with each otherA superlattice layer formed by stacking, the first sublayer consisting of combinational Al_z1Ga_1-z1InP material composition; the second sublayer is made of Al_z2Ga_1-z2InP material, wherein x1 is more than 0 and x2 is less than or equal to 1.

In some optional embodiments, the second capping layer includes at least a first portion and a second portion, the first portion is a superlattice layer formed by alternately stacking a third sublayer and a fourth sublayer; the second portion is composed of an AlInP material.

In some optional embodiments, the light emitting diode further comprises a first spacer layer and a second spacer layer, the first spacer layer being located between the first cladding layer and the active layer, the second spacer layer being located between the active layer and the second cladding layer.

In some optional embodiments, the thickness of the first spacer layer is less than 300nm, and the doping concentration is less than 1E17/cm³。

In some optional embodiments, the thickness of the second spacer layer is less than 300nm, and the doping concentration is less than 1E17/cm³。

The present invention also provides a light emitting diode, including: the semiconductor epitaxial lamination layer is provided with a first surface and a second surface which are opposite, and comprises a first current expansion layer, a first covering layer, an active layer, a second covering layer and a second current expansion layer which are sequentially stacked from the first surface to the second surface; the method is characterized in that: the second covering layer comprises a superlattice layer formed by alternately stacking a third sublayer and a fourth sublayer; the third sublayer is composed of combined Al_z1Ga_1-z1InP material composition; the fourth sublayer consisting of Al_z2Ga_1-z2InP material, wherein z1 is more than 0 and more than z2 is less than or equal to 1.

In some alternative embodiments, z2-z1 ≧ 0.2.

In some alternative embodiments, the third sublayer has an Al component z1 content ranging from 0.4 ≦ z1 < 1; the content z2 of the Al component of the fourth sublayer ranges from 0.6 to 1 and z2 to 1.

In some optional embodiments, the active layer radiates light having a wavelength of 550 to 950 nm.

The invention also provides a light-emitting device which comprises the light-emitting diode.

The invention provides a light emitting diode, which has the following beneficial effects:

(1) the first covering layer adopts a superlattice structure, can be better matched with lattices of the first spacing layer, the barrier layer in the active layer and the well layer, and effectively releases stress, so that the epitaxial growth quality of the near-active region is improved, the crystal defects of the semiconductor epitaxial lamination are reduced, and the effective recombination of carriers is improved;

(2) designing the N-type covering layer as Al_x1Ga_1-x1InP/Al_x2Ga_1-x2The InP superlattice structure improves the luminous efficiency of the light-emitting diode by improving the uniformity of current expansion;

(3) designing the P-type cladding layer as Al_z1Ga_1-z1InP/Al_z2Ga_1-z2Structure of InP superlattice of Al_zGa_1- _zThe valence band edge of the P-type cladding layer can be optimized by InP, so that the hole concentration of the P-type cladding layer is increased, and the external quantum efficiency is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

While the invention will be described in connection with certain exemplary implementations and methods of use, it will be understood by those skilled in the art that it is not intended to limit the invention to these embodiments. On the contrary, the intent is to cover all alternatives, modifications and equivalents as included within the spirit and scope of the invention as defined by the appended claims.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. Furthermore, the drawing figures are a descriptive summary and are not drawn to scale.

Fig. 1 is a schematic view of an epitaxial structure according to embodiment 1 of the present invention.

Fig. 2 is a schematic structural diagram of a light emitting diode according to embodiment 1 of the present invention.

Fig. 3 to 5 are schematic structural diagrams of the light emitting diode in the manufacturing process of embodiment 2 of the invention.

Fig. 6 is a schematic structural diagram of a light emitting diode according to embodiment 3 of the present invention.

Fig. 7 to 8 are schematic structural diagrams of a light emitting diode in the manufacturing process of embodiment 4 of the invention.

Fig. 9 is a schematic structural diagram of a light emitting diode according to embodiment 5 of the present invention.

Fig. 10 is a schematic structural diagram of a light emitting diode according to embodiment 6 of the present invention.

Fig. 11 is a schematic structural diagram of a light emitting diode according to embodiment 7 of the present invention.

Fig. 12 is a schematic structural diagram of a light emitting diode according to embodiment 8 of the present invention.

Fig. 13 is a schematic structural diagram of a light-emitting device according to embodiment 9 of the present invention.

Reference numerals: growing a substrate: 100, respectively; buffer layer: 101; etching a stop layer: 102; first ohmic contact layer: 103; first current spreading layer: 104; a first cover layer: 105; the first spacing layer: 106; an active layer: 107; a second spacer layer: 108; a second cover layer: 109; second current spreading layer: 110; second ohmic contact layer: 111; substrate: 200 of a carrier; bonding layer: 201; mirror layer: 202; ohmic contact metal layer: 202 a; a dielectric material layer: 202 b; a first electrode: 203; a second electrode: 204; bonding glue: 205; temporary substrate: 206.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

In the description of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

Moreover, the terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "couple" or "couples," and the like, do not denote physical or mechanical connections, but rather may include electrical connections, optical connections, and the like, whether direct or indirect.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Example 1

The embodiment provides a light emitting diode, wherein a first covering layer and a second covering layer of the light emitting diode adopt a superlattice structure, so that the crystal quality of a semiconductor epitaxial lamination layer and the uniformity of current spreading of the light emitting diode can be improved, and the light emitting efficiency and the light emitting brightness of the light emitting diode are improved.

Fig. 1 is a schematic diagram of an led epitaxial structure according to a preferred embodiment, the led epitaxial structure includes: a growth substrate 100; the semiconductor epitaxial lamination layer comprises a first current expansion layer 104, a first covering layer 105, a first spacing layer 106, an active layer 107, a second spacing layer 108, a second covering layer 109, a second current expansion layer 110 and a second ohmic contact layer 111 which are sequentially laminated on the growth substrate 100.

Specifically, referring to fig. 1, the material of the growth substrate 100 includes, but is not limited to, GaAs, and other materials such as GaP, InP, etc. may be used. In the present embodiment, GaAs growth substrate 100 is taken as an example. Optionally, a buffer layer 101, an etch stop layer 102 and a first ohmic contact layer 103 are further sequentially disposed between the growth substrate 100 and the first current spreading layer 104; because the lattice quality of the buffer layer 101 is good relative to the lattice quality of the growth substrate 100, the growth of the buffer layer 101 on the growth substrate 100 is beneficial to eliminating the influence of the lattice defect of the growth substrate 100 on the semiconductor epitaxial lamination; etch stop layer 102 is used as a stop layer for the post-step chemical etch, and in some alternative embodiments, etch stop layer 102 is an n-type etch stop layer of n-GaInP. To facilitate subsequent removal of the growth substrate 100, the thickness thereof is controlled to within 500nm, more preferably within 200 nm. In some optional embodiments, the ohmic contact layer 103 is made of GaAs material, has a thickness ranging from 10 to 100nm and a doping concentration of 1 to 10E +18/cm³Preferably 2E18/cm³To achieve better ohmic contact results.

The semiconductor epitaxial stack may be formed on the Growth substrate 100 by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), epitaxial Growth (epitaxial Growth Technology), Atomic beam Deposition (ALD), and the like. The semiconductor epitaxial lamination layer is a semiconductor material capable of providing conventional radiation such as ultraviolet, blue, green, yellow, red, infrared light and the like, specifically can be a material of 200-950 nm, such as common nitride, specifically can be a gallium nitride-based semiconductor epitaxial lamination layer, and the gallium nitride-based epitaxial lamination layer is commonly doped with elements such as aluminum, indium and the like and mainly provides radiation of 200-550 nm wave band; or common epitaxial lamination of AlGaInP-based or AlGaAs-based semiconductors, which mainly provides radiation in the wavelength range of 550-950 nm.

The semiconductor epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer from a direction away from the growth substrate 100. The first type semiconductor layer and the second type semiconductor layer may be doped n-type or p-type, respectively, to enable at least the provision of electrons or holes, respectively. The n-type semiconductor layer may be doped with an n-type dopant such as Si, Ge, or Sn, and the p-type semiconductor layer may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. When the first type semiconductor layer is an n-type semiconductor, the second type semiconductor layer is a p-type semiconductor layer; when the first type semiconductor layer is a p-type semiconductor layer, the second type semiconductor layer is an n-type semiconductor layer. The first type semiconductor layer, the active layer and the second conductive type semiconductor layer can be made of AlGaInN, GaN, AlGaN, AlGaInP or GaAs or AlGaAs. In some optional embodiments, the first type semiconductor layer is an n-type semiconductor layer, and the second type semiconductor layer is a p-type semiconductor layer; in some optional embodiments, the first type semiconductor layer is a p-type semiconductor layer, and the second type semiconductor layer is an n-type semiconductor layer.

The first and second type semiconductor layers include a first and second capping layers 105 and 107, respectively, which provide electrons or holes to the active layer 106. In order to improve the uniformity of the current spreading, the first type semiconductor layer and the second type semiconductor layer further comprise a first current spreading layer 104 and a second current spreading layer 108. In order to prevent the dopants of the first and second cladding layers 104 and 108 from diffusing into the active layer 106, affecting the crystal quality of the active layer 106, a first spacer layer 105 is preferably present between the first cladding layer 104 and the active layer 106; a second spacer layer 107 is present between the second cladding layer 108 and the active layer 106.

The first current spreading layer 104 plays a role of current spreading, the spreading capability of which is related to the thickness, and in this embodiment, the preferred material is Al_y1Ga_1-y1InP with the thickness of 2500-4000 nm and the n-type doping concentration of 4E 17-8E 17/cm³. The n-type doping is usually Si doping, without excluding other element equivalent substitution dopings.

The first spacer layer 106 is located between the first cladding layer 105 and the active layer 107, and is preferably made of Al_a1Ga_1- _a1InP, the thickness of the first spacing layer 106 is preferably less than 300nm, and the content of Al component a1 ranges from 0.3 to 1; the doping concentration is lower than 1E17/cm³。

The first cladding layer 105 is composed of a superlattice structure formed by alternately stacking a first sub-layer 105a and a second sub-layer 105b, and the first sub-layer 105a is composed of combined Al_x1Ga_1-x1InP material composition; the second sub-layer 105b is made of Al_x2Ga_1-x2InP material, wherein x1 is more than 0 and x2 is less than or equal to 1. In some alternative embodiments, it is preferred that x2-x1 ≧ 0.2, more preferably x2-x1 ≧ 0.4. The thickness of the first sub-layer 105a is 0.5-15 nm, more preferably 0.5-10 nm, and the thickness of the second sub-layer 105b is 2-15 nm, more preferably 2-10 nm. The number of cycles of the superlattice layer is 10 pairs or more, and more preferably 15 pairs or more.

In some alternative embodiments, the content x1 of the Al component of the first sub-layer 105a ranges from 0.4 ≦ x1 < 1; the content x2 of the Al component of the second sub-layer 105b is in the range of 0.6-1 to x 1-1. In this embodiment, the first sub-layer 105a is preferably Al_x1Ga_1-x1InP, wherein x1 is more than or equal to 0.4 and less than 1; the second sublayer is AlInP.

The first cladding layer 105 is designed as Al_x1Ga_1-x1InP/Al_x2Ga_1-x2InP superlattice structure, new cladding layer structure, and first spacer layer 106, well layer and barrier layer in active layer 107The lattice matching of the layer is better, the stress can be effectively released, the crystal quality of the active region is improved, the crystal defects are reduced, the effective combination of current carriers is improved, and the luminous efficiency of the light-emitting diode is improved. The first cladding layer 105 is designed to be Al_x1Ga_1-x1InP/Al_x2Ga_1-x2The InP superlattice structure can improve the uniformity of current spreading, thereby improving the external quantum efficiency of the light-emitting diode.

The active layer 107 provides a light radiation region for the recombination of electrons and holes, and different materials may be selected according to the emission wavelength, and the active layer 107 may be a periodic structure of a single quantum well or a multiple quantum well. The active layer 107 in this embodiment is an n-cycle quantum well structure, each of which comprises a well layer and a barrier layer deposited in this order, wherein the barrier layer has a larger band gap than the well layer. By adjusting the composition ratio of the semiconductor material in the active layer 107, light of a target wavelength is desirably radiated. The active layer 107 is a layer of material that provides electroluminescent radiation, such as AlGaInP or AlGaAs, and more preferably AlGaInP, which is a single or multiple quantum well. In this embodiment, the semiconductor epitaxial stacked layer is preferably made of an AlGaInP-based or GaAs-based material, and the active layer radiates light having a wavelength of 550 to 950 nm.

In the embodiment, the periodicity n of the quantum well structure is 5-100. The well layer is made of Al_x3Ga_1-x3InP material composition; the barrier layer is made of Al_yGa_1-yAnd the InP material consists of x3 which is more than or equal to 0 and less than or equal to 1. The thickness of the well layer is 5-25 nm; the thickness of the barrier layer is 5-25 nm; the barrier layer has an Al component content y within a range of 0.3-0.85.

The second spacer layer 108 is located on the active layer 107, and the material of the second spacer layer 108 is preferably Al_b2Ga_1-b2InP, the thickness of the second spacer layer 108 is preferably 300nm or less, and the Al component content b1 of the second spacer layer 107 is 0.3-1; the doping concentration is lower than 1E17/cm³。

The second type semiconductor layer includes a second capping layer 109, a second current spreading layer 110, and a second ohmic contact layer 111; wherein the secondThe covering layer 109 serves to provide holes for the active layer 107, in this embodiment, it is preferable that the second covering layer 109 is formed by a superlattice structure formed by alternately stacking third sub-layers 109a and fourth sub-layers 109b, and the third sub-layers 109a are formed by combined Al_z1Ga_1-z1InP material composition; the fourth sublayer 109b is made of Al_z2Ga_1-z2InP material, wherein z is more than 0 and more than 1 and more than or equal to z2 and less than or equal to 1. In some alternative embodiments, z2-z1 is preferably 0.2 or more, and more preferably z2-z1 is 0.4 or more. The thickness of the third sub-layer 108a is 0.5-15 nm, the preferable thickness is 0.5-10 nm, and the thickness of the fourth sub-layer 108b is 2-15 nm, the preferable thickness is 2-10 nm. The number of cycles of the superlattice layer is 10 pairs or more, and more preferably 15 pairs or more.

In some alternative embodiments, the third sublayer 109a has an Al component content z1 in the range of 0.4 ≦ z1 < 1; the content z2 of the Al component of the fourth sublayer 109b is in the range of 0.6. ltoreq. z 1. ltoreq.1. In this embodiment, the third sub-layer 109a is preferably Al_z1Ga_1-z1InP, wherein z1 is more than or equal to 0.4 and less than 1; the fourth sublayer is AlInP. The p-type doping is typically Mg doping, without excluding equivalent substitution of other elements. The second cladding layer 109 is designed as Al_z1Ga_1-z1InP/Al_z2Ga_1-z2The structure of the InP superlattice, wherein AlGaInP can optimize the valence band edge of the P-type covering layer, thereby increasing the hole concentration of the P-type covering layer and improving the external quantum efficiency.

The second current spreading layer 110 functions as a current spreading, and the spreading capability thereof is related to the thickness, so that the thickness thereof can be selected according to the specific device size in the present embodiment, and the preferred thickness is controlled to be more than 300nm and less than 12000 nm. In this embodiment, the thickness of the second current spreading layer 110 is preferably 500 to 10000 nm. In this embodiment, the preferred material is GaP, and the p-type doping concentration is 6E 17-2E 18/cm³The p-type doping is usually magnesium doping, without excluding equivalent substitution of other elements.

The second ohmic contact layer 110 is preferably made of GaP with a doping concentration of 1E19/cm³More preferably 5E19/cm³To achieve better ohmicAnd (4) contacting. The thickness of the second ohmic contact layer 109 is preferably 40nm or more and 150nm or less. In this embodiment, the thickness of the second ohmic contact layer 110 is preferably 60 nm.

Fig. 2 shows a schematic diagram of a light emitting diode employing the epitaxial structure shown in fig. 1, the light emitting diode comprising a substrate 200, the semiconductor epitaxial stack bonded to the substrate 200 through a bonding layer 201, the semiconductor epitaxial stack comprising a first ohmic contact layer 103, a first current spreading layer 104, a first capping layer 105, a first spacer layer 106, an active layer 107, a second spacer layer 108, a second capping layer 109, a second current spreading layer 110 and a second ohmic contact layer 111 sequentially stacked on the substrate 200.

The substrate 200 is a conductive substrate, and the conductive substrate may be silicon, silicon carbide, or a metal substrate, and the metal substrate is preferably a copper, tungsten, or molybdenum substrate. The thickness of the substrate 200 is preferably 50 μm or more in order to be able to support the semiconductor epitaxial stack with sufficient mechanical strength. In addition, in order to facilitate the machining of the substrate 200 after the bonding to the semiconductor epitaxial stack, the thickness of the substrate 200 is preferably not more than 300 μm. In this embodiment, the substrate 200 is preferably a copper substrate.

A second electrode 204 is disposed on the second ohmic contact layer 111, and an ohmic contact is formed between the second electrode 204 and the second ohmic contact layer 111 to realize current flowing. The second ohmic contact layer 111 remains only a portion vertically below the second electrode 204. The second current spreading layer 110 includes two portions in the horizontal direction, i.e., includes a portion P1 located below the second electrode 204, and a portion P2 not located below the second electrode 204 is exposed to be defined as a light emitting surface. The light emitting surface of the second current spreading layer 110 may be formed around the second electrode 24. The light-emitting surface is further formed into a pattern surface or a roughened surface through an etching process, wherein the pattern surface can be an etched pattern. The roughened surface can have a regular surface structure or any irregular surface micro-nano structure, and light which is substantially a light-emitting layer on the roughened surface or the pattern surface can escape more easily, so that the light-emitting efficiency is improved. Preferably, the light-emitting surface is a roughened surface, and the height difference (or height difference) of the roughened surface structure is less than 1 micrometer, preferably 10-300 nm.

The second current spreading layer 110 includes a second surface of the portion P1 located only under the second electrode 204, and is not roughened since it is protected by the second electrode 204. The level of the roughened surface of the second current spreading layer 110 is substantially lower relative to the level of the second surface (interface) located under the second electrode 204 due to the roughening process.

Specifically, as shown in fig. 2, in the present embodiment, the second current spreading layer 110 includes a portion P1 located under the second electrode 204 and a portion P2 not located under the second electrode 204, the second current spreading layer 110 has a first thickness t1 at the portion P1 covered by the electrode, and the second current spreading layer 108 not covered by the second electrode has a second thickness t 2. Preferably, the first thickness t1 is 1.5-2.5 μm, and the second thickness t2 is 0.5-1.5 μm. The thickness t1 of the portion P1 is greater than the thickness t2 of the portion P2. Preferably, the second thickness t2 is at least 0.3 μm greater than the first thickness t 1.

A mirror layer 202 may be disposed between the semiconductor epitaxial stack and the substrate 200, wherein the mirror layer 202 includes an ohmic contact metal layer 202a and a dielectric material layer 202b, which cooperate to form an ohmic contact with the first ohmic contact layer 103 on one hand and reflect the light beam emitted from the active layer 106 to the light-emitting surface of the second current spreading layer 110 or the sidewall of the semiconductor epitaxial stack for light-emitting.

The light emitting diode further comprises a first electrode 203. In some embodiments, the first electrode 203 is located on the back side of the substrate 200. Alternatively, the first electrode 203 is provided on the same side of the substrate 200 as the semiconductor epitaxial stack.

The first electrode 203 and the second electrode 204 include a transparent conductive material and/or a metal material. The transparent conductive material includes a transparent conductive layer such as ITO or IZO, and the metal material includes at least one of GeAuNi, AuGe, AuZn, Au, Al, Pt, and Ti.

In order to improve the reliability of the light emitting diode, an insulating protective layer (not shown) is provided on the surface and the side wall of the light emitting diode, the insulating protective layer is of a single-layer or multi-layer structure and is made of SiO₂，SiN_x，Al₂O₃，Ti₃O₅Is formed of at least one material of (a).

In this embodiment, the first capping layer 105 is made of Al_x1Ga_1-x1InP/Al_x2Ga_1-x2The InP superlattice structure can be better matched with lattices of the first spacing layer, the well layer and the barrier layer in the active layer, stress can be effectively released, crystal quality of the active region is improved, crystal defects are reduced, effective combination of current carriers is improved, and accordingly light emitting efficiency of the light emitting diode is improved; the first cladding layer 105 is designed as Al_x1Ga_1-x1InP/Al_x2Ga_1-x2The InP superlattice structure can improve the uniformity of current spreading, thereby improving the external quantum efficiency of the light-emitting diode. The second cover layer 109 is designed as Al_z1Ga_1-z1InP/Al_z2Ga_1- _z2The structure of the InP superlattice, wherein the AlGaInP can optimize the valence band edge of the P-type covering layer, thereby increasing the hole concentration of the P-type covering layer and improving the external quantum efficiency.

Example 2

Fig. 3 to 5 are schematic views showing a manufacturing process of the light emitting diode according to embodiment 1, and a method for manufacturing the light emitting diode according to this embodiment is described in detail below with reference to the schematic views.

First, referring to fig. 1, an epitaxial structure is provided, which specifically includes the following steps: a growth substrate 100 is provided, a semiconductor epitaxial stack including a buffer layer 101 and an etch stop layer 102 sequentially stacked on a surface of the growth substrate 100 is epitaxially grown through an epitaxial process such as MOCVD, for removing the epitaxial growth substrate 100, and then a semiconductor epitaxial stack including a first ohmic contact layer 103, a first current spreading layer 104, a first capping layer 105, a first spacer layer 106, an active layer 107, a second spacer layer 108, a second capping layer 109, a second current spreading layer 110, and a second ohmic contact layer 111 is grown.

In the present embodiment, a commonly used GaAs substrate is used as the growth substrate 100, and the material of the buffer layer 101 is disposed according to the growth substrate 100, it should be noted that the growth substrate 100 is not limited to GaAs, and other materials, such as GaP, InP, etc., may also be used, and the corresponding disposition and material of the buffer layer 101 thereon may be selected according to the specific growth substrate 100. An etch stop layer 102, such as GaInP, is disposed on the buffer layer 101, and in order to facilitate the subsequent removal of the subsequent growth substrate 100, a thinner etch stop layer 102 is preferably disposed, and the thickness thereof is controlled within 500nm, and more preferably within 200 nm.

Then, referring to fig. 3, a second electrode 204 is formed on the second ohmic contact layer 111, and the semiconductor epitaxial stack is bonded to a temporary substrate 206 through a bonding paste 205, wherein the bonding paste 205 is preferably BCB paste, and the temporary substrate 206 is preferably a glass substrate.

Then, removing the growth substrate 100, the buffer layer 101 and the etch stop layer 102 by using a wet etching method to expose the first ohmic contact layer 103, and forming a mirror layer 202 on the first ohmic contact layer 103, wherein the mirror layer 202 comprises an ohmic contact metal layer 202a and a dielectric material layer 202b, and the ohmic contact metal layer 202a and the dielectric material layer are matched to form ohmic contact with the first ohmic contact layer 103 on one hand and to reflect light emitted from the active layer to the lower side on the other hand; a substrate 200 is provided, a metal bonding layer 201 is provided on the substrate 200, and the substrate 201 and the mirror layer 202 are bonded to obtain the structure shown in fig. 4.

Then, the temporary substrate 206 is removed by wet etching, a mask is formed to cover the second electrode 204, and the second ohmic contact layer 111 around the second electrode 204 is exposed; an etching process is performed to remove the second ohmic contact layer 111 around the second electrode 204 by etching, so that the second ohmic contact layer 111 not located under the second electrode 204 is completely removed while exposing the second current spreading layer 110, and then the second current spreading layer 110 is etched to form a patterned or roughened surface, thereby forming the structure shown in fig. 5. The process of removing the second ohmic contact layer 111 and the roughening treatment of the second current spreading layer 110 may be a wet etching process in one or more steps, and the solution of the wet etching process may be an acidic solution, such as hydrochloric acid, sulfuric acid, or hydrofluoric acid, or citric acid, or any other preferable chemical reagent.

Finally, a first electrode 203 is formed on the back surface of the substrate 200, and a unitized led is obtained by etching, splitting, and other processes according to the size requirement, as shown in fig. 2.

Example 3

Fig. 6 shows a schematic diagram of a light emitting diode employing the epitaxial structure shown in fig. 1 in another embodiment, the light emitting diode includes a substrate 200, the semiconductor epitaxial stack is bonded to the substrate 200 through a bonding layer 201, and the semiconductor epitaxial stack includes a second ohmic contact layer 111, a second current spreading layer 110, a second capping layer 109, a second spacer layer 108, an active layer 107, a first spacer layer 106, a first capping layer 105, a first current spreading layer 104 and a first ohmic contact layer 103, which are sequentially stacked on the substrate 200.

The substrate 200 is a conductive substrate, and the conductive substrate may be silicon, silicon carbide, or a metal substrate, and the metal substrate is preferably a copper, tungsten, or molybdenum substrate. The thickness of the substrate 200 is preferably 50 μm or more in order to be able to support the semiconductor epitaxial stack with sufficient mechanical strength. In addition, in order to facilitate the machining of the substrate 200 after the bonding to the semiconductor epitaxial stack, the thickness of the substrate 200 is preferably not more than 300 μm. In this embodiment, the substrate 200 is preferably a silicon substrate.

A first electrode 203 is disposed on the first ohmic contact layer 103, and an ohmic contact is formed between the first electrode 203 and the first ohmic contact layer 103 to allow current to flow. The first ohmic contact layer 103 remains only a portion vertically below the first electrode 203. The first current spreading layer 104 includes two portions in the horizontal direction, that is, includes a portion P3 located below the first electrode 203, and a portion P4 not located below the first electrode 203 is exposed to be defined as a light exit surface. The light emitting surface of the first current spreading layer 104 may be formed around the first electrode 203. The light-emitting surface is further formed into a pattern surface or a roughened surface through an etching process, wherein the pattern surface can be an etched pattern. The roughened surface can have a regular surface structure or any irregular surface micro-nano structure, and light which is substantially a light-emitting layer on the roughened surface or the pattern surface can escape more easily, so that the light-emitting efficiency is improved. Preferably, the light-emitting surface is a roughened surface, and the height difference (or height difference) of the roughened surface structure is less than 1 micrometer, preferably 10-300 nm.

The first current spreading layer 104 includes a second surface of the portion P1 located only under the first electrode 203, and is not roughened since it is protected by the first electrode 203. The level of the roughened surface of the first current spreading layer 104 is substantially lower with respect to the level of the second surface (interface) located under the first electrode 203 due to the roughening process.

Specifically, as shown in fig. 6, in the present embodiment, the first current spreading layer 104 includes a portion P3 located under the first electrode 203 and a portion P4 not located under the first electrode 203, the first current spreading layer 104 has a first thickness t3 at the portion P3 covered by the electrode, and the first current spreading layer 104 not covered by the first electrode has a second thickness t 4. Preferably, the first thickness t3 is 1.5 to 2.5 micrometers, and the second thickness t4 is 0.5 to 1.5 micrometers. The thickness t3 of the portion P3 is greater than the thickness t4 of the portion P4. Preferably, the second thickness t4 is at least 0.3 μm greater than the first thickness t 3.

A mirror layer 202 may be disposed between the semiconductor epitaxial stack and the substrate 200, and the mirror layer 202 includes a P-type ohmic contact metal layer 202a and a dielectric material layer 202b, which cooperate to form an ohmic contact with the second ohmic contact layer 110 on one hand and reflect the light beam emitted from the active layer 106 to the light-emitting surface of the first current spreading layer 104 or the sidewall of the semiconductor epitaxial stack for light emission on the other hand.

The light emitting diode further comprises a second electrode 204. In some embodiments, the second electrode 204 is located on the back side of the substrate 200. Alternatively, the second electrode 204 is disposed on the same side of the substrate 200 as the semiconductor epitaxial stack.

The first electrode 203 and the second electrode 204 include a transparent conductive material and/or a metal material. The transparent conductive material includes a transparent conductive layer, such as ITO or IZO, and the metal material includes at least one of GeAuNi, AuGe, AuZn, Au, Al, Pt, Ti.

Example 4

Fig. 7 to 8 are schematic views showing a manufacturing process of the light emitting diode according to the embodiment 3, and a method for manufacturing the light emitting diode according to the embodiment is described in detail with reference to the schematic views.

First, referring to fig. 1, an epitaxial structure is provided, which specifically includes the following steps: a growth substrate 100 is provided, a semiconductor epitaxial stack including a buffer layer 101 and an etch stop layer 102 sequentially stacked on a surface of the growth substrate 100 is epitaxially grown through an epitaxial process such as MOCVD, for removing the epitaxial growth substrate 100, and then a semiconductor epitaxial stack including a first ohmic contact layer 103, a first current spreading layer 104, a first capping layer 105, a first spacer layer 106, an active layer 107, a second spacer layer 108, a second capping layer 109, a second current spreading layer 110, and a second ohmic contact layer 110 is grown.

Next, the semiconductor epitaxial stack is transferred onto the base plate 200, and the growth substrate 100 is removed, so as to obtain the structure shown in fig. 7, which specifically includes the following steps: a mirror layer 202 is formed on the second ohmic contact layer 111 and includes an ohmic contact metal layer 202a and a dielectric material layer 202b, which are matched to form ohmic contact with the second ohmic contact layer 111 on the one hand and reflect the light emitted from the active layer to the lower part on the other hand; providing a substrate 200, disposing a metal bonding layer 201 on the substrate 200, bonding the substrate 201 and the mirror layer 202, and removing the growth substrate 100, wherein in the case that the growth substrate 100 is gallium arsenide, the wet etching process may be used to remove until the first ohmic contact layer 103 is exposed.

Next, as shown in fig. 8, a first electrode 203 is formed on the first ohmic contact layer 103, the first electrode 203 is in good ohmic contact with the first ohmic contact layer 103, and a second electrode 204 is formed on the back surface side of the substrate 200, whereby a conduction current can be passed between the first electrode 203 and the second electrode 204 and the semiconductor epitaxial stack. The substrate 200 has a thickness capable of supporting all layers thereon.

Then, a mask is formed to cover the first electrode 203, and the first ohmic contact layer 103 around the first electrode 203 is exposed; an etching process is performed to remove the first ohmic contact layer 103 around the first electrode 203 by etching, so that the ohmic contact layer 103 not under the first electrode 109 is completely removed while exposing the first current spreading layer 104, and then the first current spreading layer 104 is etched to form a patterned or roughened surface, thereby forming the structure shown in fig. 6. The process of removing the ohmic contact layer and the roughening treatment of the first current spreading layer 104 may be a wet etching process in one or more steps, and the solution for wet etching may be an acidic solution, such as hydrochloric acid, sulfuric acid, or hydrofluoric acid, or citric acid, or any other preferred chemical reagent.

And finally, obtaining the unitized invisible light emitting diode by processes of etching, splitting and the like according to size requirements.

Example 5

Compared with the light emitting diode shown in fig. 2 in embodiment 1, as shown in fig. 9, the first cladding layer 105 in this embodiment includes a first portion 105-1 and a second portion 105-2, the first portion 105-1 is a superlattice structure formed by alternately stacking a first sub-layer 105a and a second sub-layer 105b, and the second portion is composed of AlInP material; the first portion 105-1 is closer to the active layer than the second portion 104-2; the thickness of the first part of the first covering layer is 35-250 nm, and the thickness of the second part of the first covering layer is 300-1500 nm.

The second cladding layer 109 includes a first portion 109-1 and a second portion 109-2, the first portion 109-1 of the second cladding layer is a superlattice structure formed by alternately stacking a first sub-layer 109a and a second sub-layer 109b, and the second portion is composed of an AlInP material; the first portion 109-1 is closer to the active layer than the second portion 109-2; the thickness of the first part 109-1 of the second covering layer is 35-250 nm, and the thickness of the second part 109-2 is 300-1500 nm.

The first cladding layer and the second cladding layer in the embodiment include a first portion and a second portion, the first portion is composed of a superlattice structure, the second portion is composed of an AlInP material, the lattice matching performance of the first portion and the second portion with a well layer and a barrier layer in a spacer layer and an active layer is better, stress can be effectively released, the crystal quality of the active region is improved, crystal defects are reduced, effective recombination of carriers is improved, and therefore the light emitting efficiency of the light emitting diode is improved. The P-type cap layer 109 is designed to be Al_z1Ga_1-z1InP/Al_z2Ga_1-z2Structure of InP superlattice of Al_zGa_1-zInP can optimize the valence band edge of the P-type covering layer, thereby increasing the hole concentration of the P-type covering layer and improvingExternal quantum efficiency. The first cladding layer 105 is designed to be Al_x1Ga_1-x1InP/Al_x2Ga_1-x2The InP superlattice structure can improve the uniformity of current expansion, particularly improve the mobility of electrons under the condition of low current, and thus improve the external quantum efficiency of the light-emitting diode under the condition of low current.

In this embodiment, the first capping layer and the second capping layer adopt a partial superlattice structure, but the present invention is not limited to this embodiment. In some optional embodiments, the first cladding layer is a partial superlattice structure, and the second cladding layer adopts a full superlattice structure or is an AlInP material; in some alternative embodiments, the first cladding layer is of a full superlattice structure or of an AlInP material, and the second cladding layer is of a partial superlattice structure. The first covering layer and/or the second covering layer adopt a superlattice structure, so that the luminous efficiency of the light-emitting diode can be improved.

Example 6

Compared with the led shown in fig. 2 in embodiment 1, as shown in fig. 10, the first cladding layer 105 in this embodiment includes a first portion 105-1, a second portion 105-2 and a third portion 105-3, the first portion 105-1 and the third portion are composed of AlInP material, the second portion is composed of a superlattice structure formed by alternately stacking a first sub-layer 105a and a second sub-layer 105b, the number of periods of the superlattice structure is 10 pairs or more, the first portion has a thickness in a range of 150 to 750nm, the second portion has a thickness in a range of 35 to 250nm, and the third portion has a thickness in a range of 150 to 750 nm.

The second cladding layer 109 in the present embodiment includes a first portion 109-1, a second portion 109-2 and a third portion 109-3, the first portion 109-1 and the third portion 109-3 are composed of an AlInP material, the second portion is a superlattice structure formed by alternately stacking a first sublayer 109a and a second sublayer 109b, the number of periods of the superlattice structure is 10 pairs or more, the first portion has a thickness of 150 to 750nm, the second portion has a thickness of 35 to 250nm, and the third portion has a thickness of 150 to 750 nm.

Example 7

Compared with the light emitting diode shown in fig. 1 in embodiment 1, as shown in fig. 11, the first cladding layer 105 in this embodiment is a superlattice structure formed by alternately stacking the first sub-layer 105a and the second sub-layer 105b, and the second cladding layer is an AlInP material, in this embodiment, the first cladding layer adopts a superlattice structure, which has better lattice matching with the well layer and the barrier layer in the first spacer layer 106 and the active layer 107, and can effectively release stress, improve the crystal quality of the active region, reduce crystal defects, and promote effective recombination of carriers, thereby improving the light emitting efficiency of the light emitting diode. The first capping layer 105 in this embodiment adopts a superlattice structure, which can improve the uniformity of current spreading and improve the external quantum efficiency of the light emitting diode.

Example 8

Compared with the light emitting diode shown in fig. 1 in embodiment 1, as shown in fig. 12, the second cladding layer 109 in this embodiment is a superlattice structure formed by alternately stacking the first sub-layer 109a and the second sub-layer 109b, and the first cladding layer is an AlInP material. The second cladding layer 109 is designed as Al_z1Ga_1-z1InP/Al_z2Ga_1-z2Structure of InP superlattice, wherein Al_zGa_1-zThe valence band edge of the P-type covering layer can be optimized by InP, so that the hole concentration of the P-type covering layer is increased, and the external quantum efficiency is improved.

Example 9

Referring to fig. 13, the light emitting device 300 includes a plurality of light emitting diodes arranged in an array according to any of the foregoing embodiments, and fig. 11 shows a portion of the light emitting diodes 1 in an enlarged schematic view.

In this embodiment, the light emitting device 300 may be a military aircraft dashboard, a stage light, a projector, or a display screen.

The light emitting device 300 has the advantages of the light emitting diodes of the embodiments.

It should be noted that the above-mentioned embodiments are only for illustrating the present invention, and not for limiting the present invention, and those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention, so that all equivalent technical solutions also belong to the scope of the present invention, and the scope of the present invention should be defined by the claims.

Claims

1. A light emitting diode, comprising:

the semiconductor epitaxial lamination layer is provided with a first surface and a second surface which are opposite, and comprises a first current expansion layer, a first covering layer, an active layer, a second covering layer and a second current expansion layer which are sequentially stacked from the first surface to the second surface;

the method is characterized in that: the first cover layer comprises a superlattice layer formed by alternately stacking a first sublayer and a second sublayer; the first sublayer is made of combined Al_x1Ga_1-x1InP material composition; the second sublayer is made of Al_x2Ga_1-x2InP material, wherein x1 is more than 0 and x2 is less than or equal to 1.

2. The led of claim 1, wherein: x2-x1 is more than or equal to 0.2.

3. The led of claim 2, wherein: the content x1 of the Al component of the first sublayer is in the range of 0.4-1 x 1-1; the content x2 of the Al component of the second sublayer is in the range of 0.6-1 to x 1-1.

4. The led of claim 1, wherein: the thickness range of the first sub-layer is 0.5-15 nm; the thickness of the second sub-layer is 2-15 nm.

5. The led of claim 1, wherein: the number of cycles of the superlattice structure is 10 pairs or more.

6. The led of claim 1, wherein: the thickness of the first covering layer is 300-1500 nm, and the doping concentration is 3E 17-9E 17.

7. The led of claim 1, wherein: the first covering layer at least comprises a first part and a second part, wherein the first part is composed of AlInP materials, and the second part is a superlattice layer formed by alternately stacking the first sub-layer and the second sub-layer.

8. The led of claim 7, wherein: the thickness of the first part of the first covering layer ranges from 300nm to 1500nm, and the thickness of the second part of the first covering layer ranges from 35 nm to 250 nm.

9. The led of claim 1, wherein: the second covering layer comprises a superlattice layer formed by alternately stacking third sublayers and fourth sublayers, wherein the third sublayers are formed by combined Al_z1Ga_1-z1InP material composition; the fourth sublayer consisting of Al_z2Ga_1-z2InP material, wherein z1 is more than 0 and more than z2 is less than or equal to 1.

10. The led of claim 9, wherein: the second covering layer at least comprises a first part and a second part, wherein the first part is composed of AlInP materials, and the second part is a superlattice layer formed by alternately stacking the first sub-layer and the second sub-layer.

11. The led of claim 1, wherein: the semiconductor device further comprises a first spacer layer and a second spacer layer, wherein the first spacer layer is positioned between the first covering layer and the active layer, and the second spacer layer is positioned between the active layer and the second covering layer.

12. The led of claim 11, wherein: the thickness of the first spacing layer is less than 300nm, and the doping concentration is lower than 1E17/cm³。

13. The led of claim 11, wherein said second spacer layer has a thickness of less than 300nm and said doping concentration is less than 1E17/cm³。

14. A light emitting diode, comprising:

the method is characterized in that: the second covering layer comprises a superlattice layer formed by alternately stacking a third sublayer and a fourth sublayer; the third sublayer is composed of combined Al_z1Ga_1-z1InP material composition; the fourth sublayer consisting of Al_z2Ga_1-z2InP material, wherein z is more than 0 and more than 1 and more than or equal to z2 and less than or equal to 1.

15. The led of claim 14, wherein: z2-z1 is more than or equal to 0.2.

16. The led of claim 14, wherein: the content z1 of the Al component of the third sublayer ranges from 0.4 to z1 and is less than 1; the content z2 of the Al component of the fourth sublayer ranges from 0.6 to 1 in z 2.

17. The light-emitting diode according to claim 1 or claim 14, wherein: the active layer radiates light with a wavelength of 550-950 nm.

18. A light emitting device, characterized by: a light emitting diode comprising any one of claims 1 to 17.