CN114783952A - Method for manufacturing semiconductor device - Google Patents
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- CN114783952A CN114783952A CN202210451008.4A CN202210451008A CN114783952A CN 114783952 A CN114783952 A CN 114783952A CN 202210451008 A CN202210451008 A CN 202210451008A CN 114783952 A CN114783952 A CN 114783952A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
An embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a dummy gate electrode layer on the gate dielectric layer; forming a patterned mask layer over the dummy gate electrode layer; patterning the dummy gate electrode layer into a plurality of patterned dummy gate electrodes with the patterned mask layer as a mask, the patterned dummy gate electrodes being spaced apart from each other such that each patterned dummy gate electrode has a profile with a wide top and a narrow bottom in a cross-sectional view, wherein the patterning includes etching the dummy gate electrode layer with increasingly stronger lateral etching characteristics; forming gate spacers on sidewalls of the patterned dummy gate electrodes; and replacing the patterned dummy gate electrode with a metal-containing gate electrode.
Description
Divisional application
The present application is a divisional application entitled "reducing metal gate overhang by forming a dummy gate electrode wide at the top and narrow at the bottom", filed on 10.08.2017, and having a patent application number of 201710680527.7.
Technical Field
Embodiments of the present invention relate generally to the field of semiconductors, and more particularly, to methods of fabricating semiconductor devices.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in a generation of ICs, each of which has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. In the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be produced using a fabrication process) has decreased.
To facilitate the semiconductor device scaling process, metal gate electrodes may be used instead of conventional polysilicon electrodes. The formation of the metal gate electrode may include a gate replacement process in which the dummy gate electrode is removed to form an opening at its location, and the opening is subsequently filled with a metal material to form the metal gate electrode. However, conventional gate replacement processes may leave overhanging portions in the openings, which may prevent the metal material from filling the openings. Accordingly, voids may be formed in the metal gate, which reduces the performance of the semiconductor device.
Thus, while existing gate replacement processes have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.
Disclosure of Invention
According to some embodiments of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a polysilicon layer over a substrate; etching the polysilicon layer to form a dummy gate electrode, the dummy gate electrode including a top portion having a first lateral dimension and a bottom portion having a second lateral dimension, the first lateral dimension being greater than or equal to the second lateral dimension; and replacing the dummy gate electrode with a metal gate electrode.
According to further embodiments of the present invention, there is also provided a method of manufacturing a semiconductor device, the method including: forming a gate dielectric layer over the substrate; forming a dummy gate electrode layer over the gate dielectric layer; etching the dummy gate electrode layer with an etchant including fluorine and chlorine to form a dummy gate electrode, wherein the etching includes increasing a fluorine content of the etchant as the etching enters deeper into the dummy gate electrode layer; forming spacers on sidewalls of the dummy gate electrodes; forming source/drain regions on opposite sides of the dummy gate electrode and in the substrate; and replacing the dummy gate electrode with a metal gate electrode.
According to still further embodiments of the present invention, there is also provided a semiconductor device including: a high-k gate dielectric layer disposed over the substrate; and a metal gate electrode disposed over the high-k gate dielectric layer; wherein: the metal gate electrode has a top portion and a bottom portion, the bottom portion being closer to the high-k gate dielectric layer than the top portion; the top portion has a first lateral dimension; the bottom portion has a second transverse dimension; and the first lateral dimension is not less than the second lateral dimension.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a schematic cross-sectional side view of a semiconductor device at a stage of fabrication according to various embodiments of the present invention.
Fig. 2 is a schematic cross-sectional side view of a semiconductor device at a stage of fabrication in accordance with various embodiments of the invention.
Fig. 2A is a schematic cross-sectional side view of a semiconductor device at a stage of fabrication according to various embodiments of the present invention.
Fig. 3 is a schematic cross-sectional side view of a semiconductor device at a stage of manufacture according to various embodiments of the invention.
Fig. 4 is a schematic cross-sectional side view of a semiconductor device at a stage of fabrication according to various embodiments of the present invention.
Fig. 5 is a schematic cross-sectional side view of a semiconductor device at a stage of fabrication according to various embodiments of the present invention.
Fig. 6 is a schematic cross-sectional side view of a semiconductor device at a stage of manufacture according to various embodiments of the invention.
Figure 7 illustrates several suitable cross-sectional profiles of a dummy gate electrode fabricated in accordance with various embodiments of the present invention.
Fig. 8 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …", "below …", "lower", "above …", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
With advances in semiconductor manufacturing technology, metal gate transistors have been used in recent years to enhance the performance of ICs. Metal gate transistors use metal gate electrodes instead of conventional polysilicon gate electrodes. The manufacturing process of the metal gate transistor may include a gate replacement process in which the polysilicon dummy gate electrode is replaced by a metal gate electrode after the source/drain regions are formed. However, as semiconductor devices are scaled down, the critical dimension (e.g., the width of the gate) becomes smaller and smaller, while the aspect ratio (e.g., the ratio between the height of the gate and the width of the gate) may increase. The small CD and high aspect ratio of the gate may lead to problems or difficulties in replacing the polysilicon dummy gate electrode with a metal gate electrode. For example, small CDs and high aspect ratios may result in a "floating" condition in which the opening is partially blocked (formed by removing the dummy polysilicon gate electrode). This may result in voids in the metal gate electrode subsequently formed in the opening. Voids in the metal gate electrode degrade the performance (e.g., excessive resistivity) of the transistor device, which is undesirable.
In order to overcome the above problems, the present invention uses a new etching process in the formation of the dummy gate electrode. The new etch process changes the profile/shape of the dummy gate electrode such that the top portion of the dummy gate electrode is wider (or at least not narrower) than the bottom portion of the dummy gate electrode. This is in sharp contrast to conventionally fabricated dummy gate electrodes, where the top of the dummy gate electrode is narrower than the bottom of the dummy gate electrode. As will become more apparent based on the following discussion, the unique profile of the dummy gate electrodes will result in openings (formed by their removal) that are more easily filled with metal material in subsequent processes, which results in a substantially void-free metal gate electrode. Details of the present invention are discussed below with reference to fig. 1-8.
Fig. 1-6 are simplified schematic partial cross-sectional side views of semiconductor device 35 during various stages of fabrication. The semiconductor device 35 may be part of an Integrated Circuit (IC) chip, a system on chip (SoC), or a portion thereof. It may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, laterally diffused MOS (ldmos) transistors, high power MOS transistors, or other types of transistors. It should be appreciated that fig. 1-6 have been simplified in order to provide a better understanding of the inventive concepts of the present invention. It should therefore be noted that additional processes may be provided before, during, and after the processes shown in fig. 1-6 to complete the fabrication of semiconductor device 35, and that some other processes may only be briefly described herein.
Referring to fig. 1, a semiconductor device 35 has a substrate 40. The substrate 40 is a silicon substrate doped with a P-type dopant such as boron (e.g., a P-type substrate). Alternatively, substrate 40 may be other suitable semiconductor materials. For example, the substrate 40 may be a silicon substrate (N-type substrate) doped with an N-type dopant such as phosphorus or arsenic. Substrate 40 may alternatively be made of some other suitable elemental semiconductor such as diamond or germanium; a suitable compound semiconductor such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. Further, the substrate 40 may include an epitaxial layer (epi layer), may be strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure.
Still referring to fig. 1, Shallow Trench Isolation (STI) features 45 are formed in the substrate 40. The STI features 45 are formed by etching a recess (or trench) in the substrate 45 and filling the recess with a dielectric material. In the present embodiment, the dielectric material of the shallow trench isolation feature 45 includes silicon oxide. In alternative embodiments, the dielectric material of the STI features 45 may include silicon nitride, silicon oxynitride, fluorine doped silicate (FSG), and/or low-k dielectric materials known in the art. In other embodiments, Deep Trench Isolation (DTI) features may be formed instead of or in combination with STI features 45.
An interfacial layer may optionally be formed over substrate 40. The interfacial layer may be formed by an Atomic Layer Deposition (ALD) process and include silicon oxide (SiO)2)。
A gate dielectric layer 60 is formed over the upper surface of the substrate 40 (or over the interfacial layer if formed). In some embodiments, the gate dielectric layer 60 may be formed by an ALD process. In some embodiments, gate dielectric layer 60 comprises a high-k dielectric material. The high-k dielectric material is of greater than SiO2A dielectric constant of (4) or (4). In an embodiment, the gate dielectric layer 60 comprises hafnium oxide (HfO)2) Having a dielectric constant in the range of from about 18 to about 40. In an alternative embodiment, gate dielectric layer 60 may comprise ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5One of HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO and SrTiO.
A capping layer 70 is formed over the gate dielectric layer 60. Formation of capping layer 70 includes one or more deposition and patterning processes. In some embodiments, capping layer 70 comprises a lanthanum oxide material (LaO)xWhere x is an integer), it should be understood that the capping layer may comprise other suitable materials (e.g., such as LaO)x、GdOx、DyOxOr ErOxRare earth oxide of (ii). In some embodiments, the material of the capping layer may be selected such that it may help to adjust the workfunction of a transistor gate (formed later) such that it may beA desired threshold voltage for the transistor is achieved. It will be appreciated that at this stage of fabrication, a gate dielectric layer 60 and a capping layer 70 are formed over both the NMOS transistor region and the PMOS transistor region. In some embodiments, the capping layer has a thickness in a range from about 5 angstroms to about 20 angstroms.
A polysilicon layer 80 is formed over the capping layer 70. The polysilicon layer 80 will be patterned later to form dummy gate electrodes. A patterned hard mask layer 90 is formed over the polysilicon layer 80. In some embodiments, the patterned hard mask layer 90 includes multiple layers having different material compositions. For example, the patterned hard mask layer 90 may include a silicon nitride layer formed over the polysilicon layer 80, and it may also include a silicon oxide layer formed over the silicon nitride layer. The patterned hard mask layer 90 may be patterned into a plurality of segments, such as segments 90A and 90B, by a photolithographic process.
Referring now to fig. 2, the sections 90A and 90B of the patterned hard mask layer 90 may be used as masks to define the gate structures of the transistors. In more detail, the etching process 100 is performed to etch the polysilicon layer 80. The segments 90A and 90B of the patterned hard mask layer 90 are used as an etch mask in the etch process 100 to protect portions of the underlying layers, including the polysilicon layer 80, the capping layer 70, and the gate dielectric layer 60, from being etched.
The etching process 100 forms gate structures 120A and 120B separated by opening 130, wherein gate structure 120A includes segment 90A, remaining portion 80A of the polysilicon layer, remaining portion 70A of the capping layer, and remaining portion 60A of the gate dielectric layer, and gate structure 120B includes segment 90B, remaining portion 80B of the polysilicon layer, remaining portion 70B of the capping layer, and remaining portion 60B of the gate dielectric layer. It should be understood that the remaining portions 80A and 80B of the polysilicon layer are used here as dummy gate electrodes and will be removed in a later dummy gate replacement process.
In accordance with an embodiment of the present invention, the etch process 100 is configured to form dummy gate electrodes 80A-80B having inwardly sloped sidewall profiles. For example, dummy gate electrode 80A (or 80B) has a lateral dimension 140 near its upper surface and a lateral dimension 141 near its bottom surface. Lateral dimension 140 is greater than or equal to (or not less than) lateral dimension 141. In some embodiments, lateral dimension 140 is at least 5%, such as about 5% -20%, greater than lateral dimension 141, and thus, dummy gate electrodes 80A and 80B shown in fig. 2 each have a cross-sectional profile/shape that loosely (loosely) resembles an inverted or inverted trapezoid, but it is understood that in real-world fabrication, the sidewall surfaces of dummy gate electrodes 80A-80B may not be as straight or smooth as shown in fig. 2, as fig. 2 merely provides a simplified illustration.
This inverted trapezoidal shape of the dummy gate electrodes 80A-80B is obtained by configuring the lateral etch characteristics of the etch process 100. For example, the etch process 100 may be configured to have increasingly stronger lateral etch characteristics as the etch proceeds deeper (i.e., closer to the substrate 40). In some embodiments, the etch process 100 includes multiple etch steps, where each etch step has an associated lateral etch rate, and each subsequent etch step has a greater lateral etch rate than the previous etch step.
The etching process (or the various etching steps included therein) may include the simultaneous application of a high electronegativity etchant and a chlorine etchant within an etching chamber in which the wafer having undergone etching process 100 is placed. In some embodiments, the chlorine etchant may include Cl having a flow rate in a range between about 30 standard cubic centimeters per minute (sccm) and about 36sccm2A gas or plasma, and the high electronegativity etchant may comprise a fluorine-containing gas or plasma having a flow rate in a range between about 80sccm to about 120 sccm. As a non-limiting example, the fluorine-containing gas or plasma may include a gas such as CxFy(where x and y are positive integers, e.g. CF4Or C2F6)、CHF3HBr or NF3Of (a) a fluorine-rich material. The etching mechanism is as follows:
the fluorine-containing etchant reacts with the surface oxides (e.g., formed on the sidewalls of the dummy gate electrodes 80A-80B as they are etched) to produce silicon-containing and oxygen-containing gases, which can be removed from the etch chamber by a purging mechanism. For example, using CF4As an etchant, the surface oxide may be according to the following formula with CF4Reaction: SiO 22+CF4＝>SiF4+CO2In which SiF4+CO2Is a gas that can be removed from the etch chamber.
The chlorine-containing etchant reacts with the polysilicon material of the dummy gate electrodes 80A-80B to form another gas (e.g., SiCl) that can be removed from the etch chamber by a purging mechanismxWhere x is a positive integer).
The flow rate of the fluorine-containing etchant may be related to the lateral etch characteristics of the etch process 100. For example, increasing the flow rate of the fluorine-containing etchant enhances the lateral etch rate of the etch process 100. Thus, to achieve the desired wide top and narrow bottom profile of the dummy gate electrodes 80A-80B, the etch process 100 may be configured such that the fluorine content is increased (e.g., by increasing the flow rate of the fluorine-containing etchant) as deeper and deeper portions of the polysilicon layer 80 are etched. For example, in the first etching step of performing etching on the top of the dummy gate electrodes 80A/80B, the flow rate of the fluorine-containing etchant may be configured to X sccm. In the second etching step of performing etching on the middle portion of the dummy gate electrodes 80A/80B, the flow rate of the fluorine-containing etchant may be configured to Y sccm. In the third etching step of performing etching on the bottom of the dummy gate electrodes 80A/80B, the flow rate of the fluorine-containing etchant may be configured to be Z sccm. Z is greater than Y, and Y is greater than X, and X is not less than 80 sccm. Of course, three etching steps are merely examples, and the etching process 100 may be configured to have two etching steps or four or more etching steps in other embodiments, as long as the fluorine content in the etchant increases with each etching step.
Because the etchants used herein are rich in fluorine content, fluorine particles 150 may remain on the surface of the substrate 40, STI features 45, or even on the sides of the gate structures 120A-120B after the completion of the etching process 100. Due to the high fluorine content in the etch process 100, these fluorine particles may still remain after the various cleaning processes are performed. In other words, the removal of the fluorine particles 150 may not be complete, and some traces thereof may be found in the actually manufactured semiconductor device. The presence of fluorine particles 150 may be detected by a particular semiconductor manufacturing inspection tool. The fluorine residue may be evidence of an etching process similar to the etching process 100 for manufacturing a semiconductor device according to the present invention.
In some embodiments, a passivation gas may also be applied with the etchant to facilitate formation of dummy gate electrodes 80A-80B having a wide top and narrow bottom profile. As the etching process 100 occurs, the passivation gas forms a passivation material on the exposed surfaces of the polysilicon layer 80. The passivation material helps prevent further etching of the polysilicon material. A simplified example of this is shown in fig. 2A. Referring to fig. 2A, as the top of polysilicon layer 80 is etched, the passivation gas forms passivation material 170A-170B on the sidewalls of dummy gate electrodes 80A-80B near the top. This will allow the etch process 100 to proceed down and continue to laterally etch the lower portion of the polysilicon layer 80 without further laterally etching the dummy gate electrodes 80A-80B at the top because they are protected by the passivation material 170A-170B.
It should also be noted that since dummy gate electrodes 80A-80B have a profile that is wide at the top and narrow at the bottom, openings 130 separating dummy gate electrodes 80A-80B have a profile that is narrow at the top and wide at the bottom.
Referring now to FIG. 3, gate spacers 190A-190B are formed on the sidewalls of the gate structures 120A-120B. Gate spacers 190A-190A comprise a dielectric material. In some embodiments, gate spacers 190A-190B comprise silicon nitride. In alternative embodiments, the gate spacers 190A-190B may comprise silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof.
Thereafter, heavily doped source and drain regions 200A and 200B (also referred to as S/D regions) are formed in the NMOS and PMOS portions of the substrate 40, respectively. The S/D regions 200A-200B may be formed by an ion implantation process or by a diffusion process. An N-type dopant, such as phosphorus or arsenic, may be used to form the NMOS S/D region 200B, and a P-type dopant, such as boron, may be used to form the PMOS S/D region 200A. As shown in FIG. 3, S/D regions 200A-200B are aligned with the outer boundaries of gate spacers 190A-190B, respectively. The S/D regions 200A-200B may be said to be formed in a "self-aligned" manner, as no photolithography process is required to define the area or boundaries of the S/D regions 200A-200B. One or more annealing processes are performed on the semiconductor device 35 to activate the S/D regions 200A-200B. It should also be understood that in some embodiments, lightly doped source/drain (LDD) regions may be formed in the NMOS and PMOS regions of the substrate 40 prior to forming the gate spacers 190A-190B. The LDD regions are not specifically shown herein for simplicity.
Referring now to fig. 4, an interlayer (or interlevel) dielectric (ILD) layer 220 is formed over the substrate 40 and the gate structure 220. ILD layer 220 may be formed by Chemical Vapor Deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable methods. For example, ILD layer 220 fills openings 130. In an embodiment, ILD layer 220 comprises silicon oxide. In other embodiments, ILD layer 220 may comprise silicon oxynitride, silicon nitride, or a low-k material. A polishing process, such as a Chemical Mechanical Polishing (CMP) process, may be performed on the ILD layer 220 to planarize the ILD layer 220. Polishing is performed until the top surfaces of the dummy gate electrodes 80A of the gate structures 120A-120B are exposed. The hard masks 90A-90B are also removed by a polishing process.
Still referring to fig. 4, after the ILD layer 200 is formed and subsequent planarization, an etch process 260 is performed to remove the dummy gate electrodes 80A-80B. In some embodiments, the etching process 260 may include a dry etching process. In the illustrated embodiment, the gate dielectric layers 60A-60B and the capping layers 70A-70B are not removed by the etch process 260. As a result of the etch process 260, trenches or openings 270A-270B are formed. Since dummy gate electrodes 80A-80B are formed to have a profile that is wider at the top and narrower at the bottom (e.g., dimension 140> -dimension 141), trenches 270A-270B also inherit this profile, meaning that the trenches can also have a lateral dimension 140 that is wider at the top and narrower at the bottom, dimension 141. The shape/profile of this particular configuration of trenches 270A-270B makes them easier to fill, even though trenches 270A-270 have a small CD and a high aspect ratio.
Referring now to fig. 5, a plurality of metal deposition processes 280 are performed to deposit metal layer 290 and metal layer 291. A metal layer 290 is formed over the exposed surfaces of ILD layer 220, spacers 190A-190B, and capping layers 70A-70B and partially fills trenches 270A-270B. Metal layer 291 is formed over metal layer 290. In some embodiments, metal layer 290 includes a workfunction metal that helps to adjust the workfunction of the MOS transistor so that a desired threshold voltage for the MOS transistor may be achieved. In some embodiments, the workfunction metal may comprise a P-type workfunction metal, which may comprise tungsten (W), tungsten nitride (WN), or tungsten aluminum (WAl), as examples. In some embodiments, the work function metal may include an N-type work function metal, which may include titanium nitride (TiN), as an example.
In some embodiments, metal layer 291 comprises a fill metal that serves as the primary conductive portion of the gate electrode. In some embodiments, the fill metal layer comprises tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), or combinations thereof. In other embodiments, a barrier layer may be formed between the fill metal layer and the workfunction metal in order to reduce diffusion between the workfunction metal and the fill metal. The barrier layer may comprise TiN or TaN. In addition, a wetting layer (e.g., containing Ti) may optionally be formed between the barrier layer and the fill metal layer to enhance formation of the fill metal layer.
Referring now to fig. 6, a planarization process 300 is performed to polish metal layers 291 and 290 until the upper surfaces of metal layers 291 and 290 are substantially coplanar with the upper surface of ILD layer 220. In some embodiments, the planarization process 300 includes a CMP process. After performing the planarization process 300, the remaining portions 290A and 291A of the metal layer filling the trench 270A collectively constitute a metal gate electrode for PMOS, and the remaining portions 290B and 291B of the metal layer filling the trench 270B collectively constitute a metal gate electrode for NMOS.
The profile of trenches 270A-270B allows metal layer 290-291 to easily fill trenches 270A-270B without gaps or voids for the reasons described above. In contrast, in the conventional gate replacement process, overhangs (overhangs) existing near the upper portion of the opening (i.e., the opening formed by removing the dummy gate electrode) may hinder the formation of the metal gate. The overhang is formed as a result of conventional fabrication because the etched dummy gate electrode has a tapered shape with a narrower top than bottom. Thus, the resulting trench is narrow at the top and wide at the bottom, creating a suspension. The overhang may cause difficulties in the metal layer filling the trench, resulting in voids/gaps within the metal electrode. This problem is overcome by the present invention because the etch process 100 discussed above with reference to fig. 2 is specifically configured to form dummy gate electrodes 80A-80B that are wider at the top and narrower at the bottom (e.g., by increasing the lateral etch rate as the etch deepens), thereby allowing the trenches 270A-270B to be easily filled without a large number of voids or gaps in the formed metal electrodes. Therefore, semiconductor performance is improved.
It should be understood that although fig. 2-6 illustrate an approximately inverted trapezoidal profile (i.e., loosely resembling an inverted trapezoid) for etched dummy gate electrodes 80A-80B (and thus having the same profile as the metal gate electrode used to replace the dummy gate electrode), this particular profile/shape is not required and may vary in different embodiments. For example, fig. 7 illustrates several other suitable cross-sectional profiles/shapes 400-405 for the dummy gate electrodes 80A-80B (and thus the metal gate electrodes). The profile 400 is shaped like a rectangle, with the lateral dimension at its top and the lateral dimension at its bottom being similar to each other. The profile 401 is shaped to have side surfaces, each side surface comprising a concave section and a convex section. The profile 402 is shaped to have a more curved or rounded sidewall surface. The shape of the outline 403 resembles two combined rectangles, where the upper rectangle is wider than the bottom rectangle. The shape of the outline 404 resembles three combined rectangles, where the upper rectangle is wider than the middle rectangle, which is wider than the bottom rectangle. The profile 405 resembles two combined inverted trapezoids, with the top trapezoid being wider than the bottom trapezoid.
For all profiles 400 and 405, they have a common factor, i.e. the lateral dimension at the top is larger than or equal to the lateral dimension at the bottom. Further, this configuration allows easy filling to form a void-free metal gate electrode. These profiles or shapes 400-405 as illustrated in fig. 7 may be achieved by adjusting the process recipe or process parameters of the etching process 100 described above. Indeed, other suitable profiles/shapes (not shown here) may also be obtained for the dummy gate electrode (and thus the metal gate electrode) according to aspects of the present invention.
The gate replacement process discussed above involves a "gate last" process in which a high-k gate dielectric is formed and a dummy gate electrode is formed and then replaced by a metal gate electrode. However, it should be understood that aspects of the present invention may also be applied to a "high-k last" gate replacement process. In a "post high-k" gate replacement process, instead of forming a high-k gate dielectric, a dummy gate dielectric (e.g., silicon oxide) is first formed and a dummy gate electrode (e.g., polysilicon) is formed over the dummy gate dielectric. After forming the source/drain regions, the dummy gate dielectric is replaced with a high-k gate dielectric and the dummy gate electrode is replaced with a metal gate electrode. Regardless, the above-described etching process is still suitable for forming the dummy gate electrode and the dummy gate dielectric to have a profile that is wider at the top than at the bottom in order to facilitate filling the opening with the high-k dielectric and the metal gate electrode. Further, it should be understood that aspects of the present invention may be applied to "2-dimensional" planar devices or "3-dimensional" FinFET devices.
It should also be understood that additional processes may be performed to complete the fabrication of semiconductor device 35. For example, these additional processes may include forming contact holes for gate structures, forming interconnect structures (e.g., lines and vias, metal layers, and interlayer dielectrics that provide electrical interconnections to devices including formed metal gates), depositing passivation layers, packaging, testing, and the like. For simplicity, these additional processes are not described herein. It should also be understood that some of the manufacturing processes used in the various embodiments described above may be combined, depending on design needs and manufacturing requirements.
Fig. 8 is a flow chart of a method 600 for fabricating a semiconductor device in accordance with various aspects of the present invention. The method 600 includes a step 610 of forming a high-k gate dielectric layer over a substrate.
The method 600 includes a step 620 of forming a polysilicon layer over the high-k gate dielectric layer.
The method 600 includes a step 630 of etching the polysilicon layer to form a dummy gate electrode having a top portion of a first lateral dimension and a bottom portion of a second lateral dimension. The second lateral dimension is greater than or equal to the first lateral dimension.
In some embodiments, a top portion of the dummy gate electrode is formed when the etching is performed at a first lateral etching rate, and a bottom portion of the dummy gate electrode is formed when the etching is performed at a second lateral etching rate that is greater than the first lateral etching rate.
In some embodiments, the etching comprises using a fluorine-containing etchant, and wherein the etching is performed by increasing the fluorine content of the etchant as the etching deeper into the polysilicon layer. In some embodiments, increasing the fluorine content comprises increasing the flow rate of the fluorine-containing etchant. In some embodiments, the flow rate is not less than 80 standard cubic centimeters per minute (sccm) throughout the etching process. In some embodiments, the flow rate ranges from about 80sccm to about 120 sccm. In some embodiments, etching includes applying a chlorine-containing etchant simultaneously with the fluorine-containing etchant.
In some embodiments, the etching includes applying a passivation gas while etching the top of the dummy gate electrode.
In some embodiments, the etching is performed such that the dummy gate electrode has a cross-sectional profile similar to an inverted trapezoid.
In some embodiments, the first lateral dimension is at least 20% greater than the second lateral dimension.
It should be understood that additional process steps may be performed before, during, or after steps 610-640 discussed above to complete the fabrication of the semiconductor device. For example, prior to replacing the dummy gate electrode, method 600 may include the steps of forming spacers on sidewalls of the dummy gate electrode, forming source/drain regions on opposite sides of the dummy gate electrode and in the substrate, and forming an interlayer dielectric (ILD) over the substrate. For simplicity, other process steps are not discussed herein.
Based on the foregoing discussion, it can be seen that the present invention provides advantages over conventional systems and methods of forming rail structures. However, it is to be understood that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the overhang problems that plague existing gate replacement processes are reduced or eliminated. By carefully configuring the etching process, the resulting dummy gate electrode is formed to have a profile that is wider at the top and narrower at the bottom. Once the dummy gate electrode is removed, the trench formed at the removed dummy gate electrode also inherits this top wide and bottom narrow profile. This profile allows the trench to be easily filled with a metal material that is used to form the metal gate electrode. Thus, the formed metal gate electrode is substantially void-free or gapless and therefore has better performance than conventionally formed metal gates.
One aspect of the present invention includes a method of manufacturing a semiconductor device. A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion of a first lateral dimension and a bottom portion of a second lateral dimension. The first lateral dimension is greater than or equal to the second lateral dimension. The gate electrode is replaced with a metal gate electrode.
Another aspect of the invention relates to a method of manufacturing a semiconductor device. A gate dielectric layer is formed over the substrate. A dummy gate electrode layer is formed over the gate dielectric layer. The dummy gate electrode layer is etched with an etchant containing fluorine and chlorine to form a dummy gate electrode. The etching includes increasing a fluorine content of the etchant as the etching proceeds deeper into the dummy gate electrode layer. Spacers are formed on sidewalls of the dummy gate electrodes. Source/drain regions may be formed on opposite sides of the dummy gate electrode and in the substrate. The gate electrode is replaced with a metal gate electrode.
Another aspect of the invention relates to a semiconductor device. The semiconductor device includes a high-k gate dielectric layer disposed over a substrate. The semiconductor device includes a metal gate electrode disposed over a high-k gate dielectric layer. The metal gate electrode has a top portion and a bottom portion. The bottom portion is closer to the high-k gate dielectric layer than the top portion. The top portion has a first lateral dimension. The bottom portion has a second transverse dimension. The first lateral dimension is not less than the second lateral dimension.
According to some embodiments of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a polysilicon layer over a substrate; etching the polysilicon layer to form a dummy gate electrode, the dummy gate electrode including a top portion having a first lateral dimension and a bottom portion having a second lateral dimension, the first lateral dimension being greater than or equal to the second lateral dimension; and replacing the dummy gate electrode with a metal gate electrode.
In the above method, further comprising: forming a high-k gate dielectric layer over the substrate prior to forming the polysilicon layer, wherein the polysilicon layer is formed over the high-k gate dielectric layer.
In the above method, before replacing the dummy gate electrode, the method further includes: forming spacers on sidewalls of the dummy gate electrodes; forming source/drain regions on opposite sides of the dummy gate electrode and in the substrate; and forming an interlayer dielectric (ILD) over the substrate.
In the above method, when the etching is performed at a first lateral etching rate, the top portion of the dummy gate electrode is formed; and forming the bottom portion of the dummy gate electrode when the etching is performed at a second lateral etch rate, wherein the second lateral etch rate is greater than the first lateral etch rate.
In the above method, the etching comprises using a fluorine-containing etchant, and wherein the etching is carried out by increasing the fluorine content of the etchant as the etching progresses deeper into the polysilicon layer.
In the above method, increasing the fluorine content comprises increasing a flow rate of the fluorine-containing etchant.
In the above method, the flow rate is in a range between 80sccm and 120 sccm.
In the above method, the etching comprises applying a chlorine-containing etchant simultaneously with the fluorine-containing etchant.
In the above method, the etching includes applying a passivation gas when etching the top portion of the dummy gate electrode.
In the above method, the etching is performed so that the dummy gate electrode has a cross-sectional profile similar to an inverted trapezoid.
In the above method, the first lateral dimension is at least 20% greater than the second lateral dimension.
According to further embodiments of the present invention, there is also provided a method of manufacturing a semiconductor device, the method including: forming a gate dielectric layer over the substrate; forming a dummy gate electrode layer over the gate dielectric layer; etching the dummy gate electrode layer with an etchant including fluorine and chlorine to form a dummy gate electrode, wherein the etching includes increasing a fluorine content of the etchant as the etching enters deeper into the dummy gate electrode layer; forming spacers on sidewalls of the dummy gate electrodes; forming source/drain regions on opposite sides of the dummy gate electrode and in the substrate; and replacing the dummy gate electrode with a metal gate electrode.
In the above method, increasing the fluorine content is performed such that a top portion of the dummy gate electrode is wider than a bottom portion of the dummy gate electrode.
In the above method, the etching is performed so that the dummy gate electrode has a cross-sectional profile similar to an inverted trapezoid.
In the above method, the etchant includes a fluorine-containing etchant and a chlorine-containing etchant; and increasing the fluorine content comprises increasing a flow rate of the fluorine-containing etchant.
In the above method, the etching further includes applying a passivation gas when forming the top portion of the dummy gate electrode.
According to still further embodiments of the present invention, there is also provided a semiconductor device including: a high-k gate dielectric layer disposed over the substrate; and a metal gate electrode disposed over the high-k gate dielectric layer; wherein: the metal gate electrode has a top portion and a bottom portion, the bottom portion being closer to the high-k gate dielectric layer than the top portion; the top portion has a first lateral dimension; the bottom portion has a second transverse dimension; and the first lateral dimension is not less than the second lateral dimension.
In the above semiconductor device, further comprising fluorine particles disposed on the upper surface of the substrate.
In the above semiconductor device, the metal electrode has a cross-sectional profile similar to an inverted trapezoid.
In the above semiconductor device, the first lateral dimension is at least 20% greater than the second lateral dimension.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
forming a dummy gate electrode layer on the gate dielectric layer;
forming a patterned mask layer over the dummy gate electrode layer;
patterning the dummy gate electrode layer into a plurality of patterned dummy gate electrodes using the patterned mask layer as a mask, the patterned dummy gate electrodes being spaced apart from each other such that each patterned dummy gate electrode has a profile in a cross-sectional view that is wide at the top and narrow at the bottom, wherein the patterning includes etching the dummy gate electrode layer with increasingly stronger lateral etching characteristics;
forming gate spacers on sidewalls of the patterned dummy gate electrodes; and
the patterned dummy gate electrode is replaced with a metal-containing gate electrode.
2. The method of claim 1, wherein etching the dummy gate electrode layer comprises performing a plurality of etching steps, wherein each subsequent etching step etches the dummy gate electrode layer at a faster etch rate than a previous etching step.
3. The method of claim 1, wherein etching the dummy gate electrode layer comprises etching the dummy gate electrode layer in an etch chamber while applying an electronegative etchant.
4. The method of claim 3, wherein the electronegative etchant comprises a fluorine-containing gas or plasma.
5. The method of claim 4, wherein the fluorine-containing gas or plasma is applied at a flow rate in a range of 80 standard cubic centimeters per minute to 120 standard cubic centimeters per minute.
6. The method according to claim 4, wherein etching the dummy gate electrode layer with the stronger and stronger lateral etching characteristics includes increasing a flow rate of the fluorine-containing gas or plasma as a deeper portion of the dummy gate electrode layer is reached.
7. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a substrate;
forming a dummy gate electrode layer over the gate dielectric layer;
patterning the dummy gate electrode layer into a plurality of patterned dummy gate electrodes by a multiple etching process, wherein the multiple etching process has increasingly stronger lateral etching characteristics, so that each patterned dummy gate electrode has a tapered cross-sectional profile, and an upper portion of the patterned dummy gate electrode is wider than a lower portion of the patterned dummy gate electrode;
forming gate spacers on sidewalls of the patterned dummy gate electrodes;
removing the patterned dummy gate electrode, thereby forming a plurality of openings at least partially defined by the gate spacers; and
the plurality of openings are filled with a metal-containing gate electrode layer.
8. The method of claim 7, wherein the plurality of etching processes are performed in an etching chamber while applying an electronegative etchant and a chlorine-containing etchant.
9. The method of claim 8, wherein,
the electronegative etchant comprises a fluorine-containing gas or plasma; and
as the dummy gate electrode layer is etched deeper, a plurality of etching processes are performed at least in part by increasing the flow rate of the fluorine-containing gas or plasma.
10. A method of manufacturing a semiconductor device, comprising:
forming an unpatterned dummy gate structure over a substrate;
performing a first etching process on the unpatterned dummy gate structure, wherein the first etching process has a first lateral etching characteristic;
performing a second etching process on the unpatterned dummy gate structure after the first etching process, wherein the second etching process has a second lateral etching characteristic that is greater than the first lateral etching characteristic;
performing a third etching process on the unpatterned dummy gate structure after the second etching process, wherein the third etching process has a third lateral etching characteristic that is greater than the second lateral etching characteristic, and after the third etching process is completed, the unpatterned dummy gate structure is etched into a plurality of patterned dummy gate structures that are separated from one another;
forming gate spacers on sidewalls of the patterned dummy gate structures; and
the patterned dummy gate structure is replaced with a metal-containing gate structure.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662405301P | 2016-10-07 | 2016-10-07 | |
| US62/405,301 | 2016-10-07 | ||
| US15/420,580 | 2017-01-31 | ||
| US15/420,580 US10446662B2 (en) | 2016-10-07 | 2017-01-31 | Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode |
| CN201710680527.7A CN107919328A (en) | 2016-10-07 | 2017-08-10 | By being formed, top is wide and the pseudo- gate electrode of narrow base suspends to reduce metal gates |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710680527.7A Division CN107919328A (en) | 2016-10-07 | 2017-08-10 | By being formed, top is wide and the pseudo- gate electrode of narrow base suspends to reduce metal gates |
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| CN114783952A true CN114783952A (en) | 2022-07-22 |
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| CN113314536A (en) * | 2020-02-27 | 2021-08-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
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