CN114781630A - Weight data storage method and device, chip, electronic equipment and readable medium - Google Patents
Weight data storage method and device, chip, electronic equipment and readable medium Download PDFInfo
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Abstract
The present disclosure provides a weight data storage method applied to a neuromorphic chip, the neuromorphic chip including an on-chip storage structure and a plurality of processing cores, each processing core including a plurality of neurons, the method including: storing the weight data corresponding to each neuron to an off-chip storage structure, wherein the off-chip storage structure is positioned outside the neuromorphic chip; storing the weight index information corresponding to each neuron to the corresponding on-chip storage structure; wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure. The present disclosure also provides a weight data storage device, a neuromorphic chip, an electronic device, and a computer-readable medium.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a weight data storage method and apparatus, a neuromorphic chip, an electronic device, and a computer-readable medium.
Background
High-performance brain-like computing technology and brain simulation technology become important means for researching brain science, and the development of computational neuroscience has important influence on the technologies such as the intelligent science field, the cognitive science field, information processing and artificial intelligence. Millions of neurons are required to co-operate to perform the basic functions of the human brain, and a larger-scale brain simulation system is required to simulate the brain functions more accurately.
In the related art, in a neuromorphic chip, each core (also referred to as a core or a processing core) generally needs to store a weight matrix required by a spiking neural network in advance, the weight matrix contains a large number of connection weights between neurons, and the storage precision of the connection weights is generally high, such as fp16, which results in excessive occupation of the on-chip storage space of the neuromorphic chip.
Disclosure of Invention
The disclosure provides a weight data storage method and device, a neuromorphic chip, electronic equipment and a computer-readable medium.
According to a first aspect of the present disclosure, an embodiment of the present disclosure provides a weight data storage method applied to a neuromorphic chip, where the neuromorphic chip includes an on-chip storage structure and a plurality of processing cores, each of which includes a plurality of neurons, the weight data storage method including: storing the weight data corresponding to each neuron to an off-chip storage structure, wherein the off-chip storage structure is positioned outside the neuromorphic chip; storing the weight index information corresponding to each neuron to the corresponding on-chip storage structure; wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.
In some embodiments, a plurality of the processing cores are correspondingly provided with one of the on-chip storage structures, or each of the processing cores is correspondingly provided with one of the on-chip storage structures.
In some embodiments, the weight index information includes a starting storage address and length information of weight data corresponding to the neuron in the off-chip storage structure.
In some embodiments, the off-chip memory structure includes a plurality of memory areas, each memory area corresponding to one of the neurons, each memory area including at least one weight data configuration area, each weight data configuration area corresponding to one target processing core connected to the neuron; the storing the weight data corresponding to each neuron to an off-chip storage structure comprises: for each neuron, storing corresponding weight data between the neuron and the corresponding target processing core into a corresponding storage area; in the storage area corresponding to the neuron, the corresponding weight data between the neuron and each corresponding target processing core are sequentially stored in the corresponding weight data configuration area; and generating the weight index information corresponding to the neuron.
In some embodiments, said storing weight data corresponding to each of said neurons into an off-chip storage structure comprises: generating a weight data packet corresponding to each neuron according to the weight data corresponding to each neuron; and storing the weight data packet corresponding to each neuron in the off-chip storage structure, and generating the corresponding weight index information.
In some embodiments, the weight data includes connection identification information and weight information; the connection identification information comprises a plurality of connection identifications, each connection identification corresponds to one target neuron in a target processing core connected with the neuron, and the plurality of connection identifications comprise at least one first connection identification and at least one second connection identification, wherein the first connection identification represents that the neuron has connection weight with the target neuron in the target processing core, and the second connection identification represents that the neuron does not have connection weight with the target neuron in the target processing core; the weight information includes a connection weight corresponding to the first connection identifier.
In some embodiments, in the case where the weight data corresponding to each of the neurons is stored in a memory area form, the weight data configuration area includes a connection identification portion and a weight portion; the connection identification part is used for configuring connection identification information corresponding to a target processing core connected with the neuron and corresponding to the weight data configuration area, and the weight part is used for configuring connection weight corresponding to the first connection identification in the connection identification information.
In some embodiments, where the weight data corresponding to each of the neurons is stored in the form of a weight data packet, the weight data packet includes: the weight data configuration part corresponding to each target processing core connected with the neuron comprises a connection identification part and a weight part; the packet head part is used for configuring the number of target processing cores connected with the neuron, the core identifier of each target processing core connected with the neuron and the length information of the corresponding weight data configuration part; in the weight data configuration part corresponding to each target processing core, the connection identification part is used for configuring connection identification information corresponding to the target processing core connected with the neuron, and the weight part is used for configuring connection weight corresponding to the first connection identification in the connection identification information.
In some embodiments, the neuromorphic chip is for operating a spiking neural network; for each neuron, the target processing core connected with the neuron is a successor processing core of the current processing core where the neuron is located, or the target processing core connected with the neuron is a successor processing core of the current processing core where the neuron is located; the former processing core is the processing core in the previous network structure layer of the network structure layer where the current processing core is located; and the subsequent processing core is the next network structure layer of the network structure layer where the current processing core is located.
According to a second aspect of the present disclosure, an embodiment of the present disclosure provides a weight data storage device, which is applied to a neuromorphic chip, where the neuromorphic chip includes an on-chip storage structure and a plurality of processing cores, and each processing core includes a plurality of neurons; the weight data storage device includes:
a first storage execution module configured to store weight data corresponding to each of the neurons to an off-chip storage structure, the off-chip storage structure being located outside the neuromorphic chip; and
a second storage execution module configured to store weight index information corresponding to each of the neurons into the corresponding on-chip storage structure;
wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.
According to a third aspect of the present disclosure, embodiments of the present disclosure provide a neuromorphic chip comprising a plurality of processing cores each comprising a plurality of neurons, and a weight data storage comprising the weight data storage described above.
According to a fourth aspect of the present disclosure, an embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executable by the at least one processor to enable the at least one processor to perform the above-mentioned weight data storage method.
According to a fifth aspect of the present disclosure, embodiments of the present disclosure provide a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-mentioned weight data storage method.
It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
FIG. 1 is a schematic structural diagram of a neuromorphic chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a processing core of FIG. 1;
fig. 3 is a flowchart of a method for storing weight data according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of one specific implementation of step S1 in FIG. 3;
FIG. 5 is a schematic diagram of a weight data allocation region in a memory region of an off-chip memory structure;
FIG. 6 is a diagram illustrating a connection relationship between a current processing core and a connected target processing core;
FIG. 7 is a flowchart of another specific implementation of step S1 in FIG. 3;
FIG. 8 is a diagram illustrating a weight packet format;
FIG. 9 is a diagram illustrating a connection relationship between a current processing core and a plurality of connected target processing cores;
FIG. 10 is a diagram illustrating a transmission process of weight data of neurons;
fig. 11 is a schematic structural diagram of a weight data storage device according to an embodiment of the present disclosure;
fig. 12 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising … …, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Brain-like computing constructs an electronic brain similar to a biological brain by mimicking the operating mechanisms of the biological brain for data processing with high accuracy and processing efficiency. Architectures based on von neumann architectures have limited support for brain-like computing, limiting the range of applications for neural networks and are less energy efficient, so neuromorphic chips (e.g., brain-like computing chips) have come into force in order to obtain new architectures that more closely match neural computing, which are typically crowdsourced structures.
Fig. 1 is a schematic structural diagram of a neuromorphic chip according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of a processing core in fig. 1, where the neuromorphic chip includes a plurality of processing cores, each of which generally includes a group (a plurality) of neurons, a group of axons, a group of dendrites, and a synapse array, and may simulate a behavior of a biological neuron cluster, and each of the processing cores in the neuromorphic chip may complete a dendrite integral calculation process and a soma calculation process of a corresponding group of neurons. The dendrite is a structure for receiving external stimulation and generating input current, the axon is a structure for transmitting a pulse to synapses of a subsequent neuron, the synapses are structures for connecting the neurons, and the synapse array is an array consisting of synapses and connects a group of axons and a group of dendrites.
For each neuron within the processing core, a dendrite integration computation process, also referred to in the disclosed embodiments as a membrane potential integration operation, is used to describe the process of integrating the pulse data of all input axons connected to the dendrites of that neuron. The cell body operation process is responsible for updating the membrane potential of the neuron and judging the issuance of the pulse, the cell body operation process is also called issuance operation in the embodiment of the disclosure, if the membrane potential of any neuron meets the issuance condition, the axon of the neuron issues the pulse represented by 1 to a subsequent neuron connected with the neuron; otherwise, the axon of the neuron may fire a pulse denoted by 0 to a subsequent neuron connected to the neuron. The neuromorphic chip can be used as a super-large-scale integrated system of an electronic analog circuit to accurately simulate the neurobiological structure in a nervous system.
In the related art, a synapse array is generally used to simulate a connection relationship between a group of neurons of one processing core and a group of neurons of another processing core, as an array storage structure for storing a connection topology and connection weights (also referred to as synapse weights) between the group of neurons of one processing core and the group of neurons of another processing core. However, the weight matrix stored in correspondence to the synapse array usually includes a large amount of connection weights between neurons, and the storage precision of the connection weights is usually high, for example, fp16, which results in excessive occupation of the on-chip storage space of the neuromorphic chip, and therefore, how to effectively save the storage resources of the connection weights on the neuromorphic chip, save the on-chip storage space of the neuromorphic chip, and improve the utilization rate of the on-chip storage space becomes a technical problem to be solved at present.
In order to effectively solve the technical problems in the related art, the embodiments of the present disclosure provide a weight data storage method and apparatus, a neuromorphic chip, an electronic device, and a computer-readable medium, according to the technical solution provided by the embodiments of the present disclosure, each processing core does not need to store a weight matrix required for the operation of a neuron, weight data corresponding to each neuron of each processing core is stored in an off-chip storage structure of the neuromorphic chip, and an on-chip storage structure of the neuromorphic chip stores weight index information of the weight data, so that the occupation of the weight data of the neuron on-chip storage space of the neuromorphic chip is effectively reduced, the on-chip storage space of the neuromorphic chip is saved, and the on-chip storage space utilization rate of the neuromorphic chip is improved. In some application scenarios, when one processing core issues a pulse to another processing core, it is not necessary to transmit the relevant weight parameter, and the other processing core may obtain the corresponding weight data from the off-chip storage structure according to the operation requirement, thereby effectively reducing the occupation of hardware processing resources, and improving the hardware processing performance of the processing core to a certain extent, i.e. improving the performance of the neuromorphic chip.
The technical solutions of the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Fig. 3 is a flowchart of a weight data storage method provided by an embodiment of the present disclosure, and referring to fig. 3, the embodiment of the present disclosure provides a weight data storage method, the method is applied to a neuromorphic chip, the method may be executed by a weight data storage device, the device may be implemented in a software and/or hardware manner, the device may be integrated in a processing core of the neuromorphic chip, or may be independently disposed outside the neuromorphic chip, the weight data storage method of the embodiment of the present disclosure is implemented by interacting with the neuromorphic chip, and the weight data storage method includes:
and step S1, storing the weight data corresponding to each neuron to an off-chip storage structure, wherein the off-chip storage structure is positioned outside the neuromorphic chip.
And step S2, storing the weight index information corresponding to each neuron into a corresponding on-chip storage structure.
Wherein, the weight index information corresponding to the neuron is used for indexing the weight data corresponding to the neuron in an off-chip storage structure.
In the embodiment of the present disclosure, the off-chip Memory structure may be any type of Memory such as a Double Data Rate SDRAM (DDR), a Non-Volatile Memory (NVM), and a Flash Memory (Flash).
In the embodiment of the present disclosure, in the neuromorphic chip, a plurality of processing cores are correspondingly provided with one piece of the in-memory structure, or each processing core is correspondingly provided with one piece of the in-memory structure.
For each processing core, the on-chip storage structure may store configuration information for each neuron of the processing core, configuration information common to a plurality of neurons of the processing core, and weight index information corresponding to each neuron.
Wherein the configuration information of each neuron may include: the neuron's historical membrane potential, membrane potential threshold, and corresponding refractory period. If the current time is in the corresponding refractory period of the neuron, according to the bionic characteristics of the pulse neural network, when the neuron sends the output information at the current time, the output information of the neuron is not responded, namely, the sending operation of the neuron is not processed in the corresponding refractory period of the neuron. Alternatively, the configuration information of each neuron may include: a type Identification (ID) corresponding to configuration information common to the plurality of neurons.
Configuration information common to multiple neurons may include: a function table, and a correspondence of type ID to historical membrane potential, membrane potential threshold, and refractory period of each neuron. Wherein the function table may comprise activation functions of the neural network, may be non-linear activation functions or linear activation functions. The historical membrane potential, the membrane potential threshold and the corresponding refractory period of each neuron can be determined by the corresponding relationship between the type ID and the historical membrane potential, the membrane potential threshold and the refractory period of each neuron.
In an embodiment of the present disclosure, the weight index information corresponding to each neuron may include a starting storage address and length information of the weight data corresponding to the neuron in an off-chip storage structure.
In some embodiments, the off-chip storage structure may include a plurality of storage areas, each storage area corresponding to a neuron, each storage area including at least one weight data configuration area, each weight data configuration area corresponding to a target processing core connected to a neuron, by storing the weight data corresponding to each neuron in a partitioned storage area form. Fig. 4 is a flowchart of a specific implementation manner of step S1 in fig. 3, and as shown in fig. 4, in some embodiments, step S1 may further include: step S101 to step S102.
And step S101, storing corresponding weight data between each neuron and the corresponding target processing core into a corresponding storage area.
In the storage area corresponding to the neuron, corresponding weight data between the neuron and each corresponding target processing core are sequentially stored in a corresponding weight data configuration area. In the off-chip storage structure, each storage area may correspond to an identifier of a neuron corresponding to the configuration, and each weight data configuration area may correspond to a core identifier of a target processing core corresponding to the configuration, so as to perform data retrieval and reading.
And step S102, generating weight index information corresponding to the neuron.
Specifically, according to the storage condition (such as the storage address and length of the storage area and the weight data configuration area) of the weight data between the neuron and each target processing core in the off-chip storage structure, the weight index information of the corresponding weight data between the neuron and each target processing core in the off-chip storage structure is generated so as to read the corresponding weight data from the corresponding storage area and the corresponding weight data configuration area in the off-chip storage structure.
In some embodiments, the weight data corresponding to each neuron is stored in a compressed manner, so that storage resources of an off-chip storage structure occupied by the weight data can be effectively reduced. The weight data may include connection identification information and weight information, the connection identification information includes a plurality of connection identifications, each connection identification corresponds to a target neuron in a target processing core connected with the neuron, the plurality of connection identifications include at least one first connection identification and at least one second connection identification, the first connection identification indicates that the neuron has a connection weight with the target neuron in the target processing core, and the second connection identification indicates that the neuron does not have a connection weight with the target neuron in the target processing core; the weight information includes a connection weight corresponding to the first connection identification. Wherein, the first connection identifier may be represented by a numeral 1, and the second connection identifier may be represented by a numeral 0.
The connection weight is used for performing membrane potential integration operation of the corresponding neuron in the target processing core or performing membrane potential integration operation of the neuron in the current processing core.
In some embodiments, the neuromorphic chip is configured to run a spiking neural network, and for each neuron, the target processing core connected to the neuron is a preceding processing core of a current processing core in which the neuron is located, or the target processing core connected to the neuron is a succeeding processing core of the current processing core in which the neuron is located. The former processing core is connected with the current processing core and is positioned in the previous network structure layer of the network structure layer where the current processing core is positioned, and the latter processing core is connected with the current processing core and is positioned in the next network structure layer of the network structure layer where the current processing core is positioned.
And under the condition that the target processing core is a successor processing core of the current processing core, connecting the weights for performing the membrane potential integration operation of the neurons in the current processing core, and under the condition that the target processing core is a successor processing core of the current processing core, connecting the weights for performing the membrane potential integration operation of the corresponding neurons in the target processing core.
Fig. 5 is a schematic structural diagram of a weight data configuration area in a storage area of an off-chip storage structure, and accordingly, as shown in fig. 5, in the case of storing weight data corresponding to each of the neurons in the storage area, the weight data configuration area includes a connection identification portion and a weight portion, the connection identification portion is used for configuring connection identification information corresponding to a target processing core connected to the neuron and corresponding to the weight data configuration area, and the weight portion is used for configuring a connection weight corresponding to a first connection identification in the connection identification information.
Fig. 6 is a schematic diagram of a connection relationship between a current processing core and one connected target processing core, for example, in a case where the target processing cores connected to a neuron are all successor processing cores of the current processing core in which the neuron is located, as shown in fig. 6, it is exemplified that the neuron B1 is a current neuron of the current processing core B, and the target neuron in the target processing core a includes 4 target neurons (target neuron a1 to target neuron a4), and the neuron B1 of the current processing core B and the neuron a1 to the target neuron a4 all have a connection relationship, where the neuron B1 and the target neuron a1 have a connection weight and are denoted as 1, the neuron B1 and the target neuron a4 have a connection weight and are denoted as 2, and the neuron B1 and the target neuron a2 have no connection weight, the neuron B1 and the target neuron A3 have no connection weight, therefore, the connection identification information of the weight data corresponding to the neuron B1 includes "1001", and in connection with fig. 5, in the off-chip storage structure, in the storage area corresponding to the neuron B1 of the current processing core B, in the weight data arrangement area corresponding to the target processing core a connected to the neuron B1, the connection identification portion corresponds to the storage area "1001", and the weight portion corresponds to the storage areas of the weight value 1 and the weight value 2.
For example, in the case where the target processing cores connected to the neuron are all successors of the current processing core in which the neuron is located, as shown in fig. 6, taking neuron a1 as the current neuron of the current processing core a and the target neuron in target processing core B includes 3 target neurons (target neuron B1 to target neuron B3) as an example for explanation, neuron a1 of the current processing core a and target neuron B1 to target neuron B3 all have connection relationships, where neuron a1 and target neuron B1 have connection weights and are denoted as weight values 3, and no connection weight exists between neuron a1 and target neurons B2 and B3, so that connection identification information of weight data corresponding to neuron a1 includes "100", and with reference to fig. 5, in the off-chip storage structure, in the storage area corresponding to neuron a1 of the current processing core a, the data configuration area corresponding to the target processing core B1 connected to the neuron a is located in the off-chip storage structure, the connection identification portion corresponds to storing "100" and the weight portion corresponds to storing a weight value of 3.
In some embodiments, the weight data corresponding to each neuron is stored in the form of a weight data packet, fig. 7 is a flowchart of another specific implementation manner of step S1 in fig. 3, as shown in fig. 7, and step S1 may further include: step S111 and step S112.
And step S111, generating a weight data packet corresponding to each neuron according to the weight data corresponding to each neuron.
Fig. 8 is a schematic diagram of a format of a weighting data packet, as shown in fig. 8, the weighting data packet includes: the weight data configuration part corresponding to each target processing core (such as the target processing core 1 and the target processing core 2) connected with the neuron comprises a connection identification part and a weight part.
The header part is used for configuring the number of target processing cores connected with the neurons, the core identification of each target processing core connected with the neurons and the length information of the corresponding weight data configuration part. In the header portion, the number of target processing cores connected to the neuron and the core identifier of each target processing core connected to the neuron may be represented by binary numbers, for example, if the number is 1, the corresponding binary number is 0001, and if the core identifier is "2", the corresponding binary number is 0010.
In the weight data configuration part corresponding to each target processing core, the connection identification part is used for configuring connection identification information corresponding to the target processing core connected with the neuron, and the weight part is used for configuring connection weight corresponding to a first connection identification in the connection identification information.
For example, referring to fig. 6, taking the neuron B1 of the current processing core B as an example, the number of target processing cores connected to the neuron B1 is 1, that is, the target processing core a, the core identifier of the target processing core a is "2", the connection identifier information corresponding to the neuron B1 is "1001", and the corresponding connection weights are respectively a weight value 1 and a weight value 2, and then the weight data packet corresponding to the neuron B1 is as shown in table 1.
TABLE 1
| 0001. 0010, Length 1 | 1001 | Weight value 1, weight value 2 |
Wherein 0001 represents the number of target processing cores to which neuron B1 is connected, i.e., 1; 0010 denotes the core identification of the target processing core a to which the neuron B1 is connected, i.e., "2"; length 1 indicates length information of the weight data configuration section in the weight data packet shown in table 1, 1001 indicates connection identification information corresponding to neuron B1, specifically, indicates that there is a connection weight between neuron B1 and target neurons a1 and a4 of target processing core a, there is no connection weight between neuron B1 and target neurons a2 and A3 of target processing core a, in the weight section, a weight value of 1 indicates a connection weight corresponding to neuron B1 and target neuron a1 of target processing core a, and a weight value of 2 indicates a connection weight corresponding to neuron B1 and target neuron a4 of target processing core a.
Fig. 6 illustrates only a case where one neuron of a current processing core is connected to one target processing core, and the embodiments of the present disclosure include but are not limited thereto. In some embodiments, one neuron of a current processing core may also have an interconnect relationship with multiple target processing cores. Fig. 9 is a schematic diagram illustrating a connection relationship between a current processing core and a plurality of target processing cores connected to the current processing core, and as shown in fig. 9, a neuron a1 has an interconnection relationship with neurons B1 to B4 and neurons C1 to C3, where the neuron a1 is located in the current processing core a, the neurons C1 to C3 are located in the target processing core C, and the neurons B1 to B4 are located in the target processing core B.
Taking the neuron a1 of the current processing core a in fig. 9 as an example, the number of target processing cores connected to the neuron a1 is 2, that is, the target processing cores B and C, the core identifier of the target processing core C is "2", the core identifier of the target processing core B is "3", the connection identifier information corresponding to the neuron a1 and the target processing core C is "100", the corresponding connection weight is a weight value of 4, the connection identifier information corresponding to the neuron a1 and the target processing core B is "0010", the corresponding connection weight is a weight value of 5, and then the weight data packet corresponding to the neuron a1 is as shown in table 2.
TABLE 2
Wherein, from left to right, the first "0010" represents the number of target processing cores to which neuron a1 is connected, i.e., 2; the second "0010" represents the core identification of the target processing core C to which the neuron a1 is connected, i.e., "2"; "0011" represents the core identification of the target processing core B to which the neuron a1 is connected, i.e., "3"; length 1 represents length information of a weight data arrangement portion corresponding to a target processing core C connected to the neuron a1, 100 represents connection identification information corresponding to the neuron a1, specifically represents that a connection weight is provided between the neuron a1 and a target neuron C1 of the target processing core C, a connection weight is not provided between the neuron a1 and target neurons C2, C3 of the target processing core C, and a weight value of 4 represents a connection weight corresponding to a connection weight between the neuron a1 and a target neuron C1 of the target processing core C in a weight portion, in a connection identification portion of the weight data arrangement portion corresponding to the target processing core C; length 2 represents length information of a weight data configuration section corresponding to the target processing core B connected to the neuron a1, 0010 represents connection identification information corresponding to the neuron a1, specifically, represents that there is a connection weight between the neuron a1 and the target neuron B3 of the target processing core B, there is no connection weight between the neuron a1 and the target neurons B1, B2, and B4 of the target processing core B, and in the weight section, a weight value of 5 represents a connection weight corresponding to the neuron a1 and the target neuron B3 of the target processing core B.
And step S112, storing the weight data packet corresponding to each neuron in an off-chip storage structure, and generating corresponding weight index information.
Specifically, according to the storage condition of the weight data packet corresponding to the neuron in the off-chip storage structure (such as the storage address and the length of the weight data packet corresponding to the neuron), weight index information of the weight data packet corresponding to the neuron in the off-chip storage structure is generated, so as to read the corresponding weight data packet from the off-chip storage structure.
Fig. 10 is a schematic diagram illustrating a transmission process of weight data corresponding to a neuron, in some embodiments, for example, the weight data corresponding to the neuron is stored in an off-chip storage structure in the form of a weight data packet, and the weight data corresponding to the neuron is the weight data corresponding to the neuron between the neuron and a subsequent processing core, as shown in fig. 10, when a current membrane potential of a neuron a1 of a current processing core a reaches a membrane potential threshold and needs to be issued to the subsequent processing core B and the subsequent processing core C, a weight data packet corresponding to the neuron a1 may be read from the off-chip storage structure according to weight index information corresponding to a neuron a1 stored in the on-chip storage structure, the weight data packet may be buffered in the on-chip storage structure, and by analyzing the weight data packet, the weight data needed to be issued to the subsequent processing core B and the weight data needed to be issued to the subsequent processing core C may be determined, for example, the weight data to be issued to the subsequent processing core B includes connection identifier information of "0010" and weight information of 5, and the weight data to be issued to the subsequent processing core C includes connection identifier information of "100" and weight information of 4.
Then, the weight data to be issued to the subsequent processing core B and the issue information (pulse data) of the neuron a1 are packaged and transmitted to the subsequent processing core B through the corresponding routing node, the subsequent processing core B can determine the neuron a1 of the current processing core a to issue according to the received data, the neuron a1 and the neuron B3 of the current processing core B have a connection weight, and the connection weight is a weight value of 5, so that the membrane potential integration operation of the neuron B3 is performed on the neuron B3 in the subsequent process.
Similarly, the weight data to be issued to the subsequent processing core C and the issue information (pulse data) of the neuron a1 are packaged and transmitted to the subsequent processing core C through the corresponding routing node, the subsequent processing core C can determine, according to the received data, that the neuron a1 of the current processing core a issues, the neuron a1 and the neuron C1 of the current processing core C have a connection weight, and the connection weight is a weight value of 4, so that the membrane potential integration operation of the neuron C1 is performed on the neuron C1 in the subsequent process.
Wherein, the membrane potential integration operation process may include: and weighting and summing the pulse data connected to the neurons according to the corresponding connection weights to obtain the integrated potential of the neurons. After the membrane potential integration operation process is carried out, the method further comprises the following steps: issuing a calculation procedure. The issuance calculation process may include: and adding the integrated potential of the neuron with the corresponding historical membrane potential to update the membrane potential of the neuron, and determining that the neuron emits pulse data when the updated membrane potential exceeds a preset membrane potential threshold, otherwise determining that the neuron does not emit the pulse data.
The pulse data issued by the neuron can be encoded according to three-valued data, for example, 0, 1 and-1, which can be used to describe that the neuron is in a state of no action, activation and inhibition respectively, in the embodiment of the present disclosure, the issuing of the neuron means that the value of the pulse data is 1 or-1, and 0 indicates that the pulse data is not issued.
In the case where the weight data corresponding to the neuron is the weight data corresponding between the neuron and the preceding processing core, the data packet issued by the preceding processing core to the neuron of the current processing core may include but is not limited to the issue information (pulse data) and the core identification of the current processing core, the identification of the neuron of the current processing core, after the current processing core receives and analyzes the data packet issued by the previous processing core, the identification of the neuron in the current core corresponding to the issuance can be determined, namely, the identification of the neuron needing membrane potential updating subsequently, so as to read the weight index information corresponding to the neuron from the on-chip storage structure, reading corresponding weight data packet from the off-chip storage structure according to the weight index information, and analyzing the weight data packet, so as to obtain the corresponding weight data between the neuron and the preceding processing core, and then the above-mentioned membrane potential integration operation process can be carried out on the neuron based on the weight data corresponding to the neuron.
Fig. 11 is a schematic structural diagram of a weight data storage device according to an embodiment of the present disclosure, and as shown in fig. 11, an embodiment of the present disclosure provides a weight data storage device 200 applied to a neuromorphic chip, where the neuromorphic chip includes an on-chip storage structure and a plurality of processing cores, each processing core includes a plurality of neurons, and the weight data storage device 200 includes: a first storage execution module 201 and a second storage execution module 202.
The first storage execution module 201 is configured to store the weight data corresponding to each neuron to an off-chip storage structure, where the off-chip storage structure is located outside the neuromorphic chip; and a second storage execution module 202 configured to store weight index information corresponding to each neuron to a corresponding on-chip storage structure. Wherein, the weight index information corresponding to the neuron is used for indexing the weight data corresponding to the neuron in an off-chip storage structure.
In addition, each module of the weight data storage device 200 provided in the embodiment of the present disclosure is specifically configured to implement the weight data storage method provided in the above embodiment, and for specific description of each module of the weight data storage device 200, reference may be made to the description of the weight data storage method in the above embodiment, which is not described herein again.
The embodiment of the present disclosure further provides a neuromorphic chip, which includes a plurality of processing cores and a weight data storage device, where each processing core includes a plurality of neurons, and the weight data storage device includes the above weight data storage device.
Fig. 12 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Referring to fig. 12, an embodiment of the present disclosure provides an electronic device 300, including: at least one processor 301; and a memory 302 communicatively coupled to the at least one processor 301; the memory 302 stores one or more computer programs executable by the at least one processor 301, and the one or more computer programs are executable by the at least one processor 301 to enable the at least one processor 301 to perform the above-described weight data storage method.
Furthermore, a computer-readable medium is provided in the embodiments of the present disclosure, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the above-mentioned weight data storage method.
Embodiments of the present disclosure also provide a computer program product comprising a computer program, which when executed by a processor implements the above-mentioned weight data storage method.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as is well known to those skilled in the art.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. It will, therefore, be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (13)
1. A weight data storage method is applied to a neuromorphic chip, the neuromorphic chip comprises an on-chip storage structure and a plurality of processing cores, each processing core comprises a plurality of neurons, and the weight data storage method comprises the following steps:
storing the weight data corresponding to each neuron to an off-chip storage structure, wherein the off-chip storage structure is positioned outside the neuromorphic chip; and
storing the weight index information corresponding to each neuron to the corresponding on-chip storage structure;
wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.
2. The method for storing weight data according to claim 1, wherein a plurality of the processing cores are provided with one of the on-chip storage structures, or each of the processing cores is provided with one of the on-chip storage structures.
3. The weight data storage method of claim 1, wherein the weight index information comprises starting storage address and length information of weight data corresponding to the neuron in the off-chip storage structure.
4. The weight data storage method of claim 1, wherein the off-chip storage structure comprises a plurality of storage areas, each storage area corresponding to one of the neurons, each storage area comprising at least one weight data configuration area, each weight data configuration area corresponding to one target processing core connected to the neuron;
the storing the weight data corresponding to each neuron to an off-chip storage structure comprises:
for each neuron, storing corresponding weight data between the neuron and the corresponding target processing core into a corresponding storage area; in the storage area corresponding to the neuron, the corresponding weight data between the neuron and each corresponding target processing core are sequentially stored in the corresponding weight data configuration area;
and generating the weight index information corresponding to the neuron.
5. The method of claim 1, wherein said storing weight data corresponding to each of said neurons into an off-chip storage structure comprises:
generating a weight data packet corresponding to each neuron according to the weight data corresponding to each neuron;
storing the weight data packet corresponding to each neuron in the off-chip storage structure, and generating the corresponding weight index information.
6. The weight data storage method according to claim 4 or 5, wherein the weight data includes connection identification information and weight information;
the connection identification information comprises a plurality of connection identifications, each connection identification corresponds to one target neuron in a target processing core connected with the neuron, and the plurality of connection identifications comprise at least one first connection identification and at least one second connection identification, wherein the first connection identification represents that the neuron has connection weight with the target neuron in the target processing core, and the second connection identification represents that the neuron does not have connection weight with the target neuron in the target processing core;
the weight information includes a connection weight corresponding to the first connection identifier.
7. The weight data storage method according to claim 6, wherein in the case of storing the weight data corresponding to each of the neurons by a memory area form, the weight data configuration area includes a connection identification portion and a weight portion;
the connection identification part is used for configuring connection identification information corresponding to a target processing core connected with the neuron and corresponding to the weight data configuration area, and the weight part is used for configuring connection weight corresponding to the first connection identification in the connection identification information.
8. The weight data storage method according to claim 6, wherein in the case where the weight data corresponding to each of the neurons is stored by a weight data packet form,
the weight packet includes: the weight data configuration part corresponding to each target processing core connected with the neuron comprises a connection identification part and a weight part;
the packet head part is used for configuring the number of target processing cores connected with the neuron, the core identifier of each target processing core connected with the neuron and the length information of the corresponding weight data configuration part;
in the weight data configuration part corresponding to each target processing core, the connection identification part is used for configuring connection identification information corresponding to the target processing core connected with the neuron, and the weight part is used for configuring connection weight corresponding to the first connection identification in the connection identification information.
9. The weight data storage method of claim 6, wherein the neuromorphic chip is configured for operating a spiking neural network;
for each neuron, the target processing core connected with the neuron is a successor processing core of the current processing core where the neuron is located, or the target processing core connected with the neuron is a successor processing core of the current processing core where the neuron is located;
the previous processing core is connected with the current processing core and positioned in a previous network structure layer of the network structure layer where the current processing core is positioned; the subsequent processing core is connected with the current processing core and is positioned in the next network structure layer of the network structure layer where the current processing core is positioned.
10. A weight data storage device is applied to a neuromorphic chip, wherein the neuromorphic chip comprises an on-chip storage structure and a plurality of processing cores, and each processing core comprises a plurality of neurons; the weight data storage means includes:
a first storage execution module configured to store weight data corresponding to each of the neurons to an off-chip storage structure, the off-chip storage structure being located outside the neuromorphic chip; and
a second storage execution module configured to store weight index information corresponding to each of the neurons into the corresponding on-chip storage structure;
wherein the weight index information corresponding to the neuron is used to index the weight data corresponding to the neuron in the off-chip storage structure.
11. A neuromorphic chip comprising a plurality of processing cores and a weight data store, each processing core comprising a plurality of neurons, the weight data store comprising the weight data store of claim 10.
12. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executable by the at least one processor to enable the at least one processor to perform the weight data storage method of any of claims 1-9.
13. A computer-readable medium, on which a computer program is stored, wherein the computer program, when being executed by a processor, carries out the weight data storage method according to any one of claims 1 to 9.
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