CN114779877A - Compact direct digital frequency synthesizer and sinusoidal data compression method - Google Patents
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Abstract
The present disclosure provides a compact direct digital frequency synthesizer comprising: the phase generation module is used for performing cyclic summation accumulation on the selected frequency control words to obtain phase data of a complete period; the sine wave generation module is connected with the phase generation module and is used for converting phase data into digital sine wave data of a complete cycle; and the digital-to-analog conversion module is connected with the sine wave generation module and is used for converting the digital sine wave data into an analog signal and outputting the analog signal. Meanwhile, the present disclosure also provides a sinusoidal data compression method based on the compact direct digital frequency synthesizer, which includes: accumulating the frequency control words by using a phase generation module to obtain phase data of a complete period, wherein the phase data comprises address bits required by mapping data; and compressing the phase data of the whole period to a quarter period by using a sine symmetric algorithm, and taking out the highest two significant bits to complete the reconstruction of the data from the quarter period to the whole period.
Description
Technical Field
The present disclosure relates to the field of electronic devices, and more particularly, to a compact direct digital frequency synthesizer capable of compressing the size of a ROM in a large area and a method for compressing sinusoidal data.
Background
With the rapid development of the modern communication industry and the field of mixed signals, DDS (Direct Digital Synthesizer) is applied more widely, and people are continuously raising various standards for signal sources, and are demanding higher stability, frequency switching speed, frequency resolution and smaller size of the signal sources. Frequency synthesizers play a dominant role in broadband frequency generation applications such as flexible clock synthesis, cellular base station frequency hopping synthesizers, and radar systems.
The purity of the conventional DDS output signal depends on the resolution of the values stored in a Read Only Memory (ROM), and it is feasible to increase the resolution of the data in the ROM, but sometimes higher resolution means larger ROM size, however, as the ROM size increases, the access speed and the maximum output frequency decrease, and larger ROM size means higher power consumption, lower reliability and greater cost, so it is important to compress the size of the ROM while satisfying the high resolution.
Disclosure of Invention
Technical problem to be solved
Based on the above problems, the present disclosure provides a compact direct digital frequency synthesizer and a sinusoidal data compression method, so as to alleviate technical problems in the prior art, such as higher power consumption, lower reliability, higher cost, and the like, when a DDS meets the requirement of a ROM with high resolution.
(II) technical scheme
In one aspect of the present disclosure, there is provided a compact direct digital frequency synthesizer comprising: the phase generation module is used for circularly summing and accumulating the selected frequency control words to obtain phase data of a complete period; the sine wave generation module is connected with the phase generation module and is used for converting phase data into digital sine wave data of a complete cycle; the digital-to-analog conversion module is connected with the sine wave generation module and used for converting the digital sine wave data into an analog signal and outputting the analog signal; wherein the phase data comprises address bits required for mapping data and controlling the frequency of the sine wave; the sine wave generation module comprises: the system comprises a first compensator, a second compensator, a third compensator, a first multiplexer, a second comprehensive multiplexer and a ROM lookup table; wherein the first compensator is used to spread the sinusoidal data for a quarter cycle to half cycle portion, the second compensator is used to spread the spread of 1/8 cycles to 1/4 cycles of data in a four-wire approximation algorithm, and the third compensator is used to spread 1/2 cycles to the full cycle; the first multiplexer is used for adjusting the value of the MSB and the second MSB to complete data from 1/8 cycles to 1/4 cycles after the QLA algorithm, and the second multiplexer is used for completing the selection of the ROM list address bits to complete the mapping of phase to amplitude; the ROM lookup table is used for storing sine wave data based on a sine symmetry algorithm, an improved Sandland algorithm, a sine phase difference algorithm, a four-line approximation algorithm and a quantization and error ROM algorithm.
According to an embodiment of the present disclosure, the phase generation module includes:
a 32-bit register for storing a 32-bit frequency control word;
a multiplexer for selecting a 32-bit frequency control word;
an adder for adding the frequency control word and the sum bit;
the frequency of the sinusoid is:
where Δ p is a frequency control word, fclkN is the bit width of the phase generation block for the clock frequency.
According to an embodiment of the present disclosure, the ROM lookup table is used to store sine wave data based on a sine symmetry algorithm, an improved sandland algorithm, a sine phase difference algorithm, a four-line approximation algorithm, and a quantization and error ROM algorithm.
According to an embodiment of the present disclosure, the sine wave generation module further includes: a sine symmetric algorithm unit, an improved Sandland algorithm unit, a sine phase difference algorithm unit, a four-line approximate algorithm unit, a quantization and error ROM algorithm unit, a coarse ROM and a fine ROM; wherein the content of the first and second substances,
the sinusoidal symmetry algorithm unit is used for compressing the data in the whole period to a quarter period;
a modified sandland algorithm unit for dividing quarter sine information into coarseROM and fine ROM,
according to the following steps: sin (α + β + γ) ═ sin (α + β) cos (γ) + cos (α + β) sin (γ)
≈sin(α+β)+cos(α)sin(γ)；
The quarter sine address bit is equivalent to alpha + beta + gamma, wherein alpha is the most significant bit, beta is the middle bit, gamma is the least significant bit, sin (alpha + beta) is stored in coarse ROM, and cos (alpha) sin (gamma) is stored in fine ROM;
a sinusoidal phase difference algorithm unit based on:
sin theta is the amplitude value of the sine wave, theta is the address bit of the coarse ROM, and d (theta) is the difference obtained after calculation;
the four-wire approximation algorithm unit is used to further reduce the amplitude values stored in the ROM table,
according to the following steps:
q1(theta) is 0 to four-line approximation algorithm
Magnitude value of the range, q2(theta) in the four-line approximation algorithm
To
Magnitude of range, q3(theta) in the four-line approximation algorithm
To
Magnitude value of the range, q4(theta) in the four-line approximation algorithm
To
The magnitude of the range of values,
according to the following steps:
after the amplitude value of sin theta is optimized by a sine phase difference algorithm and a four-line approximation algorithm, the maximum value is only 0.055 times of the original value;
a quantization and error ROM algorithm unit for storing the magnitude value of sin θ optimized by the above algorithm, wherein the magnitude value includes Q-ROM and E-ROM quantized for coarse ROM, and Q-ROM and E-ROM quantized for fine ROM, according to:
T＝2S×Q+2A×E；
and calculating the total size T of the ROM, wherein S is the address bit corresponding to the Q-ROM after amplitude quantization, Q is the output bit of the Q-ROM, E-ROM is the error between the original data and the quantized data, A is the address bit of the E-ROM, and E is the output bit of the E bit.
According to the embodiment of the disclosure, the sinusoidal symmetry unit completes reconstruction of sinusoidal data in the whole period by changing the values of the most significant bit and the second most significant bit of the address under the condition of saving the quarter sinusoidal information by using quarter symmetry of the sinusoidal function, thereby realizing first compression of the data.
According to the embodiment of the disclosure, one fourth of the sine information is respectively stored in coarse ROM and fine ROM by improving the Sandland algorithm to realize the second compression of the data;
data in the Coarse ROM is sequentially differenced with approximate sine values represented by a sine phase difference algorithm and a four-line approximation algorithm, and the obtained error value is further stored into a Q-ROM and an E-ROM through a quantization error ROM algorithm to realize the final compression of the Coarse ROM;
and the data in the fine ROM is stored into the Q-ROM and the E-ROM through a quantization error ROM algorithm to realize compression of the fine ROM.
According to an embodiment of the present disclosure, the phase generation module generates a phase value for one period in a process of cyclically summing the frequency control words.
According to an embodiment of the present disclosure, the size of the E-ROM in the quantization and error ROM algorithm unit is smaller than the Q-ROM.
In another aspect of the present disclosure, there is provided a sinusoidal data compression method based on the compact direct digital frequency synthesizer of any one of the above embodiments, including: accumulating the frequency control words by using a phase generation module to obtain phase data of a complete period, wherein the phase data comprises address bits required by mapping data; and compressing the phase data of the whole period to a quarter period by using a sine symmetric algorithm, and taking out the highest two significant bits to complete the reconstruction of the data from the quarter period to the whole period.
According to an embodiment of the present disclosure, the data compression method includes: phase accumulation stage, phase segmentation stage, data compression stage and data reconstruction stage; wherein:
in the phase accumulation stage, a 32-bit register is accessed into a multiplexer, the multiplexer is connected with an adder with a built-in register, and the high 16-bit data effective bit of the circularly accumulated data is intercepted and accessed into an improved Morland algorithm unit;
in the phase segmentation stage, 16-bit address bits are equivalent to alpha + beta + gamma, the alpha is accessed into a carese ROM and a line encoder of a fine ROM, and the beta and the gamma are accessed into a second comprehensive multiplexer;
in the data compression stage, the output of the sine phase difference algorithm unit and the data of the four-wire approximation algorithm unit are subjected to difference and stored in a coarse ROM, and the coarse ROM and the fine ROM are respectively connected to a quantization error algorithm element;
in the data reconstruction stage, the output of the improved Sandland algorithm unit is connected to a first compensator, wherein a high effective bit alpha is connected to a line encoder, and a coarse ROM and a Q-ROM in a fine ROM share the same line encoder; beta is accessed into the second integrated multiplexer of the cosase ROM, and gamma is accessed into the second integrated multiplexer of the fine ROM; the alpha + beta is connected into a second compensator, and the second compensator is connected into a first multiplexer; the alpha + beta, the first multiplexer, the cosase ROM and the fine ROM are connected into a comprehensive adder, and the comprehensive adder is connected into a third compensator.
(III) advantageous effects
It can be seen from the above technical solutions that the compact direct digital frequency synthesizer and the sinusoidal data compression method of the present disclosure have at least one or some of the following beneficial effects:
(1) the resolution condition of the value stored in a Read Only Memory (ROM) can be satisfied;
(2) the size of a static memory for storing sine data is compressed, and the reconstruction of a full-period sine wave is completed, so that the size compression reaches 95%, and the output bandwidth is high;
(3) the cost is low.
Drawings
Fig. 1 schematically illustrates a block diagram of components of a compact direct digital frequency synthesizer provided in accordance with an embodiment of the present disclosure;
fig. 2 schematically illustrates an operational schematic diagram of a compact direct digital frequency synthesizer provided according to an embodiment of the present disclosure.
Fig. 3 schematically illustrates an operation principle and a composition diagram of a sine wave generation module provided according to an embodiment of the present disclosure.
Detailed Description
The present disclosure provides a compact direct digital frequency synthesizer and a sinusoidal data compression method, which can satisfy the condition of the resolution of a value stored in a Read Only Memory (ROM), have lower power consumption and cost, and have higher reliability.
To make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be described in further detail below with reference to specific embodiments and the accompanying drawings.
In an embodiment of the present disclosure, there is provided a compact direct digital frequency synthesizer, as shown in fig. 1 and 3, including:
the phase generation module is used for circularly summing and accumulating the selected frequency control words to obtain phase data of a complete period;
the sine wave generation module is connected with the phase generation module and is used for converting phase data into a digital sine wave with a complete cycle;
the digital-to-analog conversion module is used for converting the digital sine wave into an analog signal and outputting the analog signal;
wherein the phase data comprises address bits required for mapping data and the frequency of the control sine wave.
Wherein the phase generation module comprises:
a 32-bit register for storing a 32-bit frequency control word;
a multiplexer for selecting a 32-bit frequency control word;
an adder for adding the frequency control word and the sum bit;
the frequency of the sinusoid is:
where Δ p is a frequency control word, fclkAnd N is the bit width of the phase generation module.
The 32-bit frequency control word is accumulated and summed by a phase accumulator (adder), the most significant bit of 16 bits is taken for phase truncation, and then the most significant bit and the second most significant bit of the 16 bits of data are respectively taken out for controlling the monotonicity of the increment or the decrement of the sinusoidal data and the positive and negative of the data in the first, the second, the third and the four quadrants. The output shape of the phase accumulator is one hypotenuse of a right triangle, the output shape is changed into 4 sawtooth-shaped small triangles after the Most Significant Bit is taken out, then 14-Bit data and a second MSB (Most Significant Bit) are input into the first compensator, the hypotenuses of the two isosceles triangles are output, the shapes of arcs with two positive half cycles are output after passing through a ROM (read only memory) table, then the output of the MSB and the ROM is connected with the second compensator to output a digital sine wave with a complete cycle, the reconstruction of sine data with the complete cycle is finished, and the second compensator is connected with a digital-to-analog converter to convert digital signals into analog signals.
The sine wave generation module comprises: the system comprises a first compensator, a second compensator, a third compensator, a first multiplexer, a second comprehensive multiplexer and a ROM lookup table;
wherein the first compensator is configured to extend sinusoidal data for a quarter cycle to half cycle portion, the second compensator is configured to extend the extension of data 1/8 cycles to 1/4 cycles in a four-wire approximation algorithm, and the third compensator is configured to extend the extension of 1/2 cycles to the entire cycle; the first multiplexer is used for adjusting the value of the most significant bit and the second most significant bit to complete 1/8-1/4-period data after the QLA algorithm, and the second comprehensive multiplexer is used for completing the selection of the ROM list address bits to complete the mapping of phase to amplitude; the ROM lookup table is used for storing sine wave data based on a sine symmetry algorithm, an improved Sandland algorithm, a sine phase difference algorithm, a four-line approximation algorithm and a quantization and error ROM algorithm.
As shown in fig. 3, the sine wave generating module includes a sine symmetric algorithm unit, a modified sandland algorithm unit, a sine phase difference algorithm unit, a four-line approximation algorithm unit, and a quantization error ROM algorithm unit. The sinusoidal symmetry arithmetic unit is used for completing the expansion from quarter-cycle data to full-cycle data. The improved sandland algorithm unit is used for dividing the ROM storing quarter-cycle data into coarse ROM and fine ROM for storage respectively. The sine phase difference algorithm unit and the four-line approximation algorithm unit are used for further compressing the data in the coarse ROM, and the coarse ROM stores the error value after the subtraction. The quantization and error ROM algorithm unit is used to quantize the data in the coarse ROM and the fine ROM at this time to reduce the address bits and data bits again.
The specific process can be as follows:
the improved sandland algorithm is implemented by dividing address bits into α, β, γ: according to the following steps:
sin(α+β+γ)＝sin(α+β)cos(γ)+cos(α+β)sin(γ)
≈sin(α+β)+cos(α)sin(γ)；
the quarter sine address bit is equivalent to alpha + beta + gamma, wherein alpha is the most significant bit, beta is the middle bit, gamma is the least significant bit, sin (alpha + beta) is stored in coarse ROM, and cos (alpha) sin (gamma) is stored in fine ROM; the address bits corresponding to the coarse ROM are alpha and beta, and the address bits corresponding to the fine ROM are alpha and gamma, so most data books in the original ROM are stored in the coarse ROM.
The data in the coarse ROM is compressed continuously through a sine phase difference algorithm and a four-line approximation algorithm. Wherein: a sinusoidal phase difference algorithm unit based on:
d (theta) a function represented by a sinusoidal phase difference, where theta is an address bit corresponding to alpha + beta, sin theta is an amplitude value of a sine wave (sin function) in the range of 0 to pi/2,
according to the following steps:
wherein q is1(θ)，q2(θ)，q3(θ)，q4(θ) is an approximation of a sine function in the range of 0 to π/2, respectively, θ being an α + β address bit, according to:
after subtracting the sinusoidal phase difference and the amplitude of the four-wire approximation algorithm, the maximum amplitude is only 0.055 times of the original amplitude. Q of four-line approximation algorithm1The (theta) part of the data is passed through
Is shifted down in phase by one bit, q2Of part (theta)Data is generated by shifting the phase by two bits and changing the most significant and the next most significant bits to 10, q3(theta) and q4The value of (θ) is generated by a compensator. At this time, the coarse ROM stores the error value after the above two steps of algorithms. The quantization and error ROM algorithms quantize both coarse ROM and fine ROM into Q-ROM, respectively, while the E-ROM holds the quantized error values
According to the following steps:
T＝2S×Q+2A×E
where S is the address bit of the Q-ROM and Q is the output. A is the address bit of E-ROM, E is the output;
in another aspect of the present disclosure, a method for compressing sinusoidal data based on a compact direct digital frequency synthesizer is further provided, including: accumulating the frequency control words by using a phase generation module to obtain address bits for addressing a ROM (read only memory) table; compressing the data of the whole period to a quarter period by using a sine symmetric algorithm, and removing the highest two effective bits to complete the reconstruction of the data from the quarter period to the whole period; dividing the ROM for storing the sine information of the quarter cycle into two ROM tables, coarse ROM and fine ROM for storage respectively by using an improved Sandland algorithm; further compressing the size of the coarse ROM by using a sine phase difference and a four-line approximation algorithm, and storing a error value after difference in the coarse ROM; quantizing the coarse ROM and the fine ROM respectively by using a quantization error ROM algorithm, storing quantized data in a Q-ROM, and storing errors generated by quantization in an E-ROM;
according to an embodiment of the present disclosure, the data compression method includes: phase accumulation stage, phase segmentation stage, data compression stage and data reconstruction stage; wherein:
in the phase accumulation stage, a 32-bit register is accessed into a multiplexer, the multiplexer is connected with an adder with a built-in register, and the data subjected to cyclic accumulation is intercepted to obtain high 16-bit data effective bits and is accessed into an improved Morland algorithm unit;
in the phase segmentation stage, 16-bit address bits are equivalent to alpha + beta + gamma, and the alpha is accessed into a carese ROM and a line encoder of a fine ROM, the beta is accessed into a coarse ROM, and the gamma is accessed into a column encoder of the fine ROM;
in the data compression stage, the output of the sine phase difference algorithm unit and the data of the four-wire approximation algorithm unit are subjected to difference and stored in a coarse ROM, and the coarse ROM and the fine ROM are respectively connected to a quantization error algorithm element;
in the data reconstruction stage, the output of the improved Sandland algorithm unit is connected to a first compensator, wherein a high effective bit alpha is connected to a line encoder, and a coarse ROM and a Q-ROM in a fine ROM share the same line encoder; beta is accessed into the second integrated multiplexer of the cosase ROM, and gamma is accessed into the second integrated multiplexer of the fine ROM; the alpha + beta is accessed into a second compensator, and the second compensator is accessed into the first multiplexer; the alpha + beta, the first multiplexer, the cosase ROM and the fine ROM are connected into a comprehensive adder, and the comprehensive adder is connected into a third compensator.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. In addition, the above definitions of the various elements and methods are not limited to the specific structures, shapes or modes of operation set forth in the examples, which may be readily modified or substituted by those of ordinary skill in the art.
From the above description, those skilled in the art should clearly recognize that the compact direct digital frequency synthesizer and the sinusoidal data compression method of the present disclosure are suitable.
In summary, the present disclosure provides a compact direct digital frequency synthesizer, comprising: the phase generating module is used for accumulating the frequency control words and taking the accumulated data as a phase sampling address of the waveform memory; the sine wave generating module is used for finding out sine wave sampling values stored in a static memory (ROM) through a lookup table and comprises a ROM lookup table, a first compensator, a second compensator, a third compensator, a first multiplexer and a second comprehensive multiplexer; wherein the first compensator is used for expanding 1/4 sine wave data of cycle part to 1/2 cycle, the second compensator is used for expanding 1/8 cycle to 1/4 cycle of sine data in QLA, the third compensator is used for expanding 1/2 cycle to the whole cycle; the first multiplexer is used for adjusting the value of the highest and the second most significant bits to complete 1/8-1/4 cycles of data in the QLA; the second multiplexer selects column address bits in the large ROM; the ROM is used for storing the amplitude value of the sampled sine wave; the invention compresses the size of the static memory for storing sine data and completes the reconstruction of the sine wave in the whole period, the size compression reaches 95 percent, and the invention has higher output bandwidth.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
Further, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A compact direct digital frequency synthesizer comprising:
the phase generation module is used for circularly summing and accumulating the selected frequency control words to obtain phase data of a complete period;
the sine wave generation module is connected with the phase generation module and is used for converting phase data into digital sine wave data of a complete cycle;
the digital-to-analog conversion module is connected with the sine wave generation module and is used for converting the digital sine wave data into an analog signal and outputting the analog signal;
wherein the phase data comprises address bits required for mapping data and controlling the frequency of the sine wave; the sine wave generation module comprises: the system comprises a first compensator, a second compensator, a third compensator, a first multiplexer, a second comprehensive multiplexer and a ROM lookup table; wherein the first compensator is used to spread the sinusoidal data for a quarter cycle to half cycle portion, the second compensator is used to spread the spread of 1/8 cycles to 1/4 cycles of data in a four-wire approximation algorithm, and the third compensator is used to spread 1/2 cycles to the full cycle; the first multiplexer is used for adjusting the value of the MSB and the second MSB to complete data from 1/8 cycles to 1/4 cycles after the QLA algorithm, and the second multiplexer is used for completing the selection of the ROM list address bits to complete the mapping of phase to amplitude; the ROM lookup table is used for storing sine wave data based on a sine symmetry algorithm, an improved Sandland algorithm, a sine phase difference algorithm, a four-line approximation algorithm and a quantization and error ROM algorithm.
2. The compact direct digital frequency synthesizer according to claim 1, wherein said phase generation module comprises:
a 32-bit register for storing a 32-bit frequency control word;
a multiplexer for selecting a 32-bit frequency control word;
an adder for adding the frequency control word and the sum bit;
the frequency of the sinusoid is then:
where Δ p is a frequency control word, fclkAnd N is the bit width of the phase generation module.
3. The compact direct digital frequency synthesizer of claim 1, the ROM lookup table for holding sine wave data based on a sine symmetry algorithm, a modified sandland algorithm, a sine phase difference algorithm, a four-line approximation algorithm, and a quantization and error ROM algorithm.
4. The compact direct digital frequency synthesizer according to claim 3, wherein said sine wave generation module further comprises: the system comprises a sine symmetrical algorithm unit, an improved Sandland algorithm unit, a sine phase difference algorithm unit, a four-line approximation algorithm unit, a quantization and error ROM algorithm unit, a coarse ROM and a fine ROM; wherein the content of the first and second substances,
the sinusoidal symmetry algorithm unit is used for compressing the data in the whole period to a quarter period;
a modified sandland algorithm unit for dividing quarter sine information into coarseROM and fine ROM,
according to the following steps: sin (α + β + γ) ═ sin (α + β) cos (γ) + cos (α + β) sin (γ)
≈sin(α+β)+cos(α)sin(γ)；
The quarter sine address bit is equivalent to alpha + beta + gamma, wherein alpha is the most significant bit, beta is the middle bit, gamma is the least significant bit, sin (alpha + beta) is stored in coarse ROM, and cos (alpha) sin (gamma) is stored in fine ROM;
a sinusoidal phase difference algorithm unit based on:
sin theta is an amplitude value of the sine wave, theta is an address bit of the coarse ROM, and d (theta) is a difference value obtained after calculation;
the four-wire approximation algorithm unit is used to further reduce the amplitude values stored in the ROM table,
according to the following steps:
q1(theta) is 0 to four-line approximation algorithm
Magnitude of range, q2(theta) in the four-line approximation algorithm
To
Magnitude of range, q3(theta) in the four-line approximation algorithm
To
Magnitude value of the range, q4(theta) in the four-line approximation algorithm
To
The magnitude of the range is such that,
according to the following steps:
after the amplitude value of sin theta is optimized through a sine phase difference algorithm and a four-wire approximation algorithm, the maximum value is only 0.055 times of the original value;
a quantization and error ROM algorithm unit for storing the magnitude value of sin θ optimized by the above algorithm, wherein the magnitude value includes Q-ROM and E-ROM quantized for coarse ROM, and Q-ROM and E-ROM quantized for fine ROM, according to:
T＝2s×Q+2A×E；
and calculating the total size T of the ROM, wherein S is the address bit corresponding to the Q-ROM after amplitude quantization, Q is the output bit of the Q-ROM, E-ROM is the error between the original data and the quantized data, A is the address bit of the E-ROM, and E is the output bit of the E bit.
5. The compact direct digital frequency synthesizer according to claim 4, wherein said sinusoidal symmetry unit uses quarter symmetry of the sinusoidal function to accomplish the first compression of the data by changing the values of the most significant bit and the second most significant bit of the address to accomplish the reconstruction of the sinusoidal data for the entire cycle while preserving quarter sinusoidal information.
6. The compact direct digital frequency synthesizer according to claim 5, wherein the quarter of the sine information is stored in coarse ROM and fine ROM respectively by improving the Mordelan algorithm to realize the second compression of data;
data in the Coarse ROM is sequentially differenced with approximate sine values represented by a sine phase difference algorithm and a four-line approximation algorithm, and the obtained error value is further stored into a Q-ROM and an E-ROM through a quantization error ROM algorithm to realize the final compression of the Coarse ROM;
data in the fine ROM is compressed by storing the data into a Q-ROM and an E-ROM through a quantization error ROM algorithm.
7. The compact direct digital frequency synthesizer according to claim 4 in which the phase generation module generates a one period phase value during the cyclic summation of the frequency control words.
8. The compact direct digital frequency synthesizer according to claim 7, wherein the E-ROM in the quantization and error ROM algorithm unit is smaller in size than the Q-ROM.
9. A sinusoidal data compression method based on a compact direct digital frequency synthesizer according to any one of claims 1 to 7, comprising:
accumulating the frequency control words by using a phase generation module to obtain phase data of a complete period, wherein the phase data comprises address bits required by mapping data;
and compressing the phase data of the whole period to a quarter period by using a sine symmetry algorithm, and taking out the highest two effective bits to complete the reconstruction of the data from the quarter period to the whole period.
10. A method of data compression as claimed in claim 1 comprising: phase accumulation stage, phase segmentation stage, data compression stage and data reconstruction stage; wherein:
in the phase accumulation stage, a 32-bit register is accessed into a multiplexer, the multiplexer is connected with an adder with a built-in register, and the high 16-bit data effective bit of the circularly accumulated data is intercepted and accessed into an improved Morland algorithm unit;
in the phase segmentation stage, 16-bit address bits are equivalent to alpha + beta + gamma, the alpha is accessed into a carese ROM and a line encoder of a fine ROM, and the beta and the gamma are accessed into a second comprehensive multiplexer;
in the data compression stage, the output of the sine phase difference algorithm unit and the data of the four-wire approximation algorithm unit are subjected to difference and then stored in a coarse ROM, and the coarse ROM and the fine ROM are respectively connected into a quantization error algorithm element;
in the data reconstruction stage, the output of the improved Sandland algorithm unit is connected with a first compensator, wherein the high effective bit alpha is connected with a line encoder, and the same line encoder is shared by a coarse ROM and a Q-ROM in a fine ROM; beta is accessed into the second integrated multiplexer of the cosase ROM, and gamma is accessed into the second integrated multiplexer of the fine ROM; the alpha + beta is accessed into a second compensator, and the second compensator is accessed into the first multiplexer; the alpha + beta, the first multiplexer, the cosase ROM and the fine ROM are connected into a comprehensive adder, and the comprehensive adder is connected into a third compensator.
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