CN114765472A - Test system, test method and test control device - Google Patents
Test system, test method and test control device Download PDFInfo
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- CN114765472A CN114765472A CN202110029272.4A CN202110029272A CN114765472A CN 114765472 A CN114765472 A CN 114765472A CN 202110029272 A CN202110029272 A CN 202110029272A CN 114765472 A CN114765472 A CN 114765472A
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- H04B17/00—Monitoring; Testing
- H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
- H04B17/0085—Monitoring; Testing using service channels; using auxiliary channels using test signal generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
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Abstract
The invention provides a test system, a test method and a test control device, which belong to the technical field of communication, wherein the test system comprises: simulating a terminal and a terminal consistency analyzer; the analog terminal is connected with the equipment to be tested and used for sending a test signal; the terminal consistency analyzer is connected with the equipment to be tested and used for receiving the test signals forwarded by the equipment to be tested and decoding and analyzing the test signals. The invention can simulate the signaling transmission process truly, improve the reliability of the test environment of the equipment to be tested and test the best capability of the equipment to be tested.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a test system, a test method, and a test control apparatus.
Background
Referring to fig. 1, in a conventional analog system device, such as an analog repeater, an uplink sensitivity test is mainly performed by generating a signal by a signal generator (or called as a signal source), inputting the signal into a device to be tested, outputting the signal to a spectrum analyzer through the device to be tested, and detecting an Error Vector Magnitude (EVM) of a received signal to obtain a receiving sensitivity of the device to be tested.
However, the signal generator and the spectrum analyzer cannot truly simulate the signaling transmission process, in addition, the spectrum analyzer needs to calculate the EVM to meet a certain power requirement for the signal, i.e., a signal with higher power is needed, the uplink sensitivity to be tested is a signal with extremely low power, and the spectrum analyzer cannot calculate the corresponding EVM and cannot test the best capability of the device to be tested.
Disclosure of Invention
In view of the above, the present invention provides a test system, a test method and a test control device, which are used to solve the problem that the current test method for simulating the receiving sensitivity of a receiver cannot truly simulate the signaling transmission process and cannot test the best capability of the device.
In order to solve the above technical problem, in a first aspect, the present invention provides a test system, including: simulating a terminal and a terminal consistency analyzer;
the analog terminal is connected with the equipment to be tested and used for sending a test signal;
the terminal consistency analyzer is connected with the equipment to be tested and is used for receiving the test signals forwarded by the equipment to be tested and decoding and analyzing the test signals.
Optionally, the test system further includes: a combiner and a signal generator;
the combiner is arranged between the analog terminal and the equipment to be tested;
the signal generator is connected with the combiner and is used for sending interference signals to the combiner;
the combiner is configured to combine the test signal sent by the analog terminal and the interference signal sent by the signal generator into a single signal, and forward the single signal to the terminal consistency analyzer through the device to be tested.
In a second aspect, the present invention further provides a testing method applied to any one of the testing systems described in the first aspect, where the method includes:
controlling the analog terminal to send a test signal according to the first power;
judging whether a first block error rate and/or a first cyclic redundancy check code check error rate obtained by decoding and analyzing the test signal forwarded by the equipment to be tested by the terminal consistency analyzer meet preset conditions or not;
if the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset condition, determining the sensitivity of the equipment to be tested;
if the first block error rate and/or the check error rate of the first cyclic redundancy check code do not meet the preset condition, adjusting the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset condition.
Optionally, if the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the preset condition, determining the sensitivity of the device to be tested includes:
comparing the first power with a standard value, wherein the standard value is a sensitivity standard value of the equipment to be tested which is specified in advance;
and if the difference value of the first power and the standard value is smaller than or equal to a first preset value, determining the first power as the sensitivity of the equipment to be tested.
Optionally, before the controlling the analog terminal to send the test signal according to the first power, the method further includes:
starting the simulation terminal and the terminal consistency analyzer, and respectively configuring cell parameters;
and determining that the simulated terminal has searched the cell and completing cell synchronization.
Optionally, the cell parameter includes at least one of a bandwidth, a transmission power, an SSB subcarrier spacing, an uplink and a downlink frequency point, an SSB offset, a physical layer parameter, and each protocol layer parameter.
Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the analog terminal and the equipment to be tested; the signal generator is connected with the combiner and is used for sending interference signals to the combiner; the combiner is used for combining the test signal sent by the analog terminal and the interference signal sent by the signal generator into a signal and then forwarding the signal to the terminal consistency analyzer through the equipment to be tested; the method further comprises the following steps:
controlling the analog terminal to send the test signal according to a second power, wherein the second power is a preset power or the sum of a preset sensitivity standard value and a preset backspacing value of the device to be tested;
controlling the signal generator to output a first interference signal;
judging whether a second block error rate obtained by decoding and analyzing the first synthesized signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a second preset value and/or whether a check error rate of a second cyclic redundancy check code is smaller than or equal to a third preset value; the first synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and the first interference signal sent by the signal generator by the combiner;
if the second block error rate is less than or equal to the second preset value and/or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determining that the blocking test is passed;
otherwise, determining that the blocking test fails.
Optionally, the testing method further includes:
controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal;
judging whether a third block error rate obtained by decoding and analyzing the second synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a fourth preset value and/or whether a check error rate of a third cyclic redundancy check code is smaller than or equal to a fifth preset value; the second synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and a second interference signal sent by the signal generator by the combiner;
if the third block error rate is less than or equal to the fourth preset value and/or the check error rate of the third cyclic redundancy check code is less than or equal to a fifth preset value, determining that the blocking test is passed;
otherwise, determining that the blocking test fails.
In a third aspect, the present invention further provides a test control apparatus applied to any one of the test systems described in the first aspect, the test control apparatus including:
the first analog terminal control module is used for controlling the analog terminal to send a test signal according to the first power;
the first judgment module is used for judging whether a first block error rate and/or a check error rate of a first cyclic redundancy check code obtained by decoding and analyzing the test signal forwarded by the equipment to be tested by the terminal consistency analyzer meets a preset condition or not;
the sensitivity determining module is used for determining the sensitivity of the equipment to be tested under the condition that the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset conditions;
the first analog terminal control module is further configured to adjust the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the preset condition, under the condition that the first block error rate and/or the check error rate of the first cyclic redundancy check code do not satisfy the preset condition.
Optionally, the sensitivity determining module includes:
the comparison unit is used for comparing the first power with a standard value, wherein the standard value is a sensitivity standard value of the equipment to be tested which is specified in advance;
and the sensitivity determining unit is used for determining the first power as the sensitivity of the equipment to be tested if the difference value of the first power and the standard value is less than or equal to a first preset value.
Optionally, the test control apparatus further includes:
the second analog terminal control module is used for starting the analog terminal and configuring cell parameters;
the first terminal consistency analyzer control module is used for starting the terminal consistency analyzer and configuring cell parameters;
and the cell synchronization determining module is used for determining that the analog terminal searches the cell and completing cell synchronization.
Optionally, the cell parameter includes at least one of a bandwidth, a transmission power, an SSB subcarrier spacing, an uplink and a downlink frequency point, an SSB offset, a physical layer parameter, and each protocol layer parameter.
Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the analog terminal and the equipment to be tested; the signal generator is connected with the combiner and is used for sending interference signals to the combiner; the combiner is used for combining the test signal sent by the analog terminal and the interference signal sent by the signal generator into a signal and then forwarding the signal to the terminal consistency analyzer through the equipment to be tested; the test control apparatus further includes:
the third analog terminal control module is used for controlling the analog terminal to send the test signal according to a second power, wherein the second power is a preset power or the sum of a preset sensitivity standard value and a preset backspacing value of the device to be tested;
the signal generator control module is used for controlling the signal generator to output a first interference signal;
the second judgment module is used for judging whether a second block error rate obtained by decoding and analyzing the first synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is less than or equal to a second preset value and/or whether a check error rate of a second cyclic redundancy check code is less than or equal to a third preset value; the first synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and the first interference signal sent by the signal generator by the combiner;
the block determining module is used for determining that the block test is passed under the condition that the second block error rate is less than or equal to the second preset value and/or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value; otherwise, determining that the blocking test fails.
Optionally, the signal generator control module is further configured to control the signal generator to output a second interference signal, where the second interference signal is different from the first interference signal;
the second judging module is further configured to judge whether a third block error rate obtained by decoding and analyzing the second synthesized signal forwarded by the device to be tested by the terminal consistency analyzer is less than or equal to a fourth preset value and/or whether a check error rate of a third cyclic redundancy check code is less than or equal to a fifth preset value; the second synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and a second interference signal sent by the signal generator by the combiner;
the block determining module is further configured to determine that the block test passes when the third block error rate is less than or equal to the fourth preset value and/or the check error rate of the third cyclic redundancy check code is less than or equal to a fifth preset value; otherwise, determining that the blocking test does not pass.
In a fourth aspect, the present invention further provides a test control apparatus, including a memory, a processor, and a program stored in the memory and executable on the processor; the processor, when executing the program, implements the steps of any of the test methods provided by the second aspect above.
In a fifth aspect, the present invention further provides a readable storage medium, on which a program is stored, which when executed by a processor implements the steps in any of the test methods provided in the second aspect.
The technical scheme of the invention has the following beneficial effects:
in the embodiment of the invention, the simulation terminal is used for replacing the signal generator to send the test signal, the simulation terminal is connected with the equipment to be tested, the test signal is forwarded to the terminal consistency analyzer through the equipment to be tested, and then the terminal consistency analyzer directly measures the sensitivity of the received signal, so that the signaling transmission process can be truly simulated, the reliability of the test environment of the equipment to be tested is improved, and the best capability of the equipment to be tested can be tested.
Drawings
FIG. 1 is a diagram illustrating a conventional method for testing the receiving sensitivity of a device under test;
FIG. 2 is a schematic structural diagram of a test system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another testing system according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a testing method according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a test control apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another test control apparatus in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It should be apparent that the described embodiments are only some of the embodiments of the present invention, and not all of them. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a test system according to an embodiment of the present invention, the test system including: an analog terminal 21 and a terminal consistency analyzer 22;
the analog terminal 21 is connected with the device to be tested 23, and the analog terminal 21 is used for sending a test signal;
the device to be tested 23 is configured to receive the test signal sent by the analog terminal 21 and forward the test signal to the terminal consistency analyzer 22;
the terminal consistency analyzer 22 is connected to the device to be tested 23, and the terminal consistency analyzer 22 is configured to receive the test signal forwarded by the device to be tested 23 and decode and analyze the test signal.
It should be noted that, at the beginning of the test, the analog terminal 21 needs to complete a synchronization process through interaction of signaling information with the terminal consistency analyzer 22, that is, complete a process of accessing the analog terminal 21 to the terminal consistency analyzer 22, which is similar to a process of accessing a base station by a terminal and will not be described in detail here.
In this embodiment of the present invention, the device under test 23 may be an analog system device, such as an analog repeater or other analog receivers. The test system may be used to test the receiving sensitivity, or uplink sensitivity, of the device under test 23.
In the embodiment of the invention, the simulation terminal 21 is used for replacing the signal generator 25 to send the test signal, the simulation terminal 21 is connected with the device to be tested 23, the test signal is forwarded to the terminal consistency analyzer 22 through the device to be tested 23, and then the terminal consistency analyzer 22 directly measures the sensitivity of the received signal, so that the signaling transmission process can be truly simulated, the reliability of the test environment of the device to be tested 23 is improved, and the best capability of the device to be tested 23 can be tested.
Optionally, as shown in fig. 3, the test system further includes: a combiner 24 and a signal generator 25;
the combiner 24 is arranged between the analog terminal 21 and the device under test 23;
the signal generator 25 is connected to the combiner 24, and the signal generator 25 is configured to send an interference signal to the combiner 24;
the combiner 24 is configured to combine the test signal sent by the analog terminal 21 and the interference signal sent by the signal generator 25 into a single signal, and forward the single signal to the terminal consistency analyzer 22 through the device to be tested 23.
Specifically, the connection process of the test system is that the input port of the device under test 23 is connected to the combiner 24, one end of the combiner 24 is connected to the transmitting port of the analog terminal 21, and the other end is connected to the signal generator 25. The output port of the device under test 23 is connected to the receiving port of the terminal consistency analyzer 22.
The signal generator 25 may not operate, that is, the signal generator 25 may not output an interference signal, and at this time, the combiner 24 only sends the test signal output by the analog terminal 21 to the device under test 23. The signal generator 25 may not be operated, for example, when performing a sensitivity test of the device under test 23.
The signal generator 25 may also be referred to as a signal source. The combiner 24 may be a broadband combiner.
Further optionally, the test system may further include a test control device, configured to control operations of the analog terminal 21 and/or the signal generator 25, and control a test process. The test control device may be, for example, a processor, a controller, or the like.
Referring to fig. 4, fig. 4 is a schematic flow chart of a testing method according to a second embodiment of the present invention, which is applied to the testing system according to the first embodiment of the present invention, and includes the following steps:
step 41: controlling the analog terminal to send a test signal according to the first power;
step 42: judging whether a check Error Rate of a first Block Error Rate (BLER) and/or a first Cyclic Redundancy Check (CRC) code obtained by decoding and analyzing the test signal forwarded by the device to be tested by the terminal consistency analyzer meets a preset condition or not;
that is to say, in the embodiment of the present application, only the block error rate of the test signal may be obtained, and whether the block error rate satisfies the preset condition is determined, or only the check error rate of the CRC of the test signal may be obtained, and whether the check error rate of the CRC satisfies the preset condition is determined, or both the block error rate of the test signal and the check error rate of the CRC of the test signal may be obtained, and whether the block error rate satisfies the preset condition and whether the check error rate of the CRC satisfies the preset condition are determined at the same time. Moreover, it should be understood by those skilled in the art that the specific preset conditions may be different in different scenarios, and the preset conditions that the block error rate needs to satisfy and the preset conditions that the check error rate of the CRC needs to satisfy may also be different.
For example, the preset condition that the block error rate needs to be satisfied may be equal to a preset block error rate, and for example, if the block error rate obtained by decoding and analyzing the received test signal by the terminal consistency analyzer is 5%, it is determined that the preset condition is satisfied.
In addition, the parameters to be determined may be other parameters besides the block error rate and the check error rate of the CRC, which are not described in detail herein.
Specifically, the analog terminal forwards a test signal sent by the first power to the terminal consistency analyzer via the device to be tested, and the terminal consistency analyzer performs decoding analysis on the received test signal to obtain the block error rate.
Step 43: if the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset conditions, determining the sensitivity of the equipment to be tested;
for example, the power of the test signal sent by the analog terminal when the terminal consistency analyzer determines that the block error rate satisfies the preset condition may be used as the sensitivity of the device under test.
Step 44: if the first block error rate and/or the check error rate of the first cyclic redundancy check code do not meet the preset condition, adjusting the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset condition.
For example, if the block error rate is lower than a preset block error rate, for example, the block error rate is 2%, the output power of the analog terminal for sending the test signal is reduced; and if the block error rate is higher than the preset block error rate, increasing the output power of the test signal sent by the analog terminal.
In the embodiment of the invention, the simulation terminal is used for replacing the signal generator to send the test signal, the simulation terminal is connected with the equipment to be tested, the test signal is forwarded to the terminal consistency analyzer through the equipment to be tested, and then the terminal consistency analyzer directly measures the sensitivity of the received signal, so that the signaling transmission process can be truly simulated, the reliability of the test environment of the equipment to be tested is improved, and the best capability of the equipment to be tested can be tested.
The above test method is exemplified below.
Optionally, if the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the preset condition, determining the sensitivity of the device to be tested includes:
comparing the first power with a standard value, wherein the standard value is a sensitivity standard value of the equipment to be tested which is specified in advance; for example, corresponding sensitivity standard values may be predefined for different types of devices, e.g. in a test standard.
And if the difference value of the first power and the standard value is smaller than or equal to a first preset value, determining the first power as the sensitivity of the equipment to be tested.
That is, the sensitivity of the device under test can be determined only if the measured sensitivity is not much different from the standard sensitivity value of the device of the type specified in the test standard.
Optionally, before the controlling the analog terminal to send the test signal according to the first power, the method further includes:
starting the simulation terminal and the terminal consistency analyzer, and respectively configuring cell parameters;
and determining that the simulated terminal has searched the cell and completing cell synchronization.
Specifically, the analog terminal 21 may complete a synchronization process with the terminal consistency analyzer 22 through interaction of signaling information, that is, complete a process of accessing the analog terminal 21 to the terminal consistency analyzer 22, where the specific process is similar to a process of accessing a terminal to a base station, and is not described in detail here.
Further optionally, the cell parameter includes at least one of a bandwidth, a transmission power, an SSB subcarrier spacing, an uplink and downlink frequency point, an SSB offset, a physical layer parameter, and each protocol layer parameter.
Specifically, when a test is started, the analog terminal needs to be opened, and cell parameters, such as bandwidth, transmission power, Synchronization Signal/physical broadcast channel Signal Block (Synchronization Signal and PBCH Block, SSB or SS/PBCH Block) subcarrier spacing, uplink and downlink frequency points, SSB offset, and the like, need to be configured; and the terminal consistency analyzer is required to be opened, and cell parameters, such as bandwidth, transmitting power, SSB subcarrier spacing, uplink and downlink frequency points, SSB offset, physical layer parameters, parameters of each protocol layer and the like, are configured. When the cell is searched by the analog terminal and the state is Synchronization (SYNC), and after the cell synchronization is completed, the terminal consistency analyzer is used to demodulate the test signal of the analog terminal, and the block error rate at this time may be 1%, for example.
That is, when a test is started, the analog terminal and the terminal consistency analyzer need to be turned on, and relevant parameters (frequency point, power, relevant access configuration) are configured, so that the terminal consistency analyzer can demodulate an uplink signal (i.e., a test signal) of the analog terminal.
In addition, initial parameter configuration is required to be performed when the test is started, the device to be tested is powered on, and the device to be tested is set to be in a receiving mode.
Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the analog terminal and the equipment to be tested; the signal generator is connected with the combiner and is used for sending interference signals to the combiner; the combiner is used for combining the test signal sent by the analog terminal and the interference signal sent by the signal generator into a signal and then forwarding the signal to the terminal consistency analyzer through the equipment to be tested; the method further comprises the following steps:
controlling the analog terminal to send the test signal according to a second power, wherein the second power is a preset power or the sum of a preset sensitivity standard value and a preset backspacing value of the device to be tested;
for example, the second power of the analog terminal for sending the test signal may be set according to the specification of the test standard, or the signal transmission power of the analog terminal may be adjusted to be the sensitivity standard value + a preset back-off value, where the back-off value is determined according to the test standard, for example, the back-off value is 6dB, and the back-off value may also be referred to as a margin.
Controlling the signal generator to output a first interference signal;
specifically, the signal generator is turned on and outputs an interference signal, the waveform, frequency and/or power of which are set according to the test specification.
Judging whether a second block error rate obtained by decoding and analyzing the first synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a second preset value and/or whether a check error rate of a second cyclic redundancy check code is smaller than or equal to a third preset value; the first synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and the first interference signal sent by the signal generator by the combiner;
the second predetermined value may be equal to the predetermined block error rate in the sensitivity test, for example, equal to 5%. The third preset value may be equal to or different from the second preset value.
If the second block error rate is less than or equal to the second preset value and/or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determining that the blocking test is passed;
specifically, the blocking test based on the first interference signal passes;
otherwise, determining that the blocking test does not pass. In particular, the blocking test based on the first interfering signal fails.
The embodiment of the invention can also carry out the blocking test on the equipment to be tested.
Of course, when the test is started, the connection process of the test system needs to be completed, specifically, the input port of the device to be tested is connected to the combiner, and the analog terminal and the signal generator are connected at the same time, and the signal generator is used for injecting the interference signal.
The embodiment of the invention utilizes the simulation terminal and the terminal consistency analyzer to carry out the uplink index test, and the uplink index comprises uplink sensitivity and blockage.
Optionally, the method further includes:
controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal; specifically, the first interference signal and the second interference signal may have different frequencies, different powers, and/or different signal systems;
the waveform, frequency and/or power of the second interference signal is set according to a test specification.
Judging whether a third block error rate obtained by decoding and analyzing the second synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a fourth preset value and/or whether a check error rate of a third cyclic redundancy check code is smaller than or equal to a fifth preset value; the second synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and a second interference signal sent by the signal generator by the combiner; wherein the fifth preset value is equal to or different from the fourth preset value.
Specifically, the terminal consistency analyzer receives the second synthesized signal forwarded by the device to be tested and decodes and analyzes the second synthesized signal to obtain the block error rate.
If the third block error rate is less than or equal to the fourth preset value and/or the check error rate of the third cyclic redundancy check code is less than or equal to a fifth preset value, determining that the blocking test is passed; specifically, the blocking test based on the second interference signal passes;
otherwise, determining that the blocking test fails. In particular, the blocking test based on the second interference signal fails.
That is, when performing a congestion test, the test may be performed multiple times using different interference signals.
According to the embodiment of the invention, the uplink receiving sensitivity and other blocking tests of the equipment to be tested can be directly measured by the terminal consistency analyzer, so that the test accuracy is improved.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a test control apparatus according to a third embodiment of the present invention, where the test control apparatus 50 can be applied to any one of the test systems described in the first embodiment of the present invention, and includes:
a first analog terminal control module 51, configured to control an analog terminal to send a test signal according to a first power;
the first judging module 52 is configured to judge whether a first block error rate and/or a check error rate of a first cyclic redundancy check code, which are obtained by decoding and analyzing the test signal forwarded by the device to be tested by the terminal consistency analyzer, satisfy a preset condition;
a sensitivity determining module 53, configured to determine the sensitivity of the device to be tested when the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset condition;
the first analog terminal control module 51 is further configured to adjust the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the preset condition, when the first block error rate and/or the check error rate of the first cyclic redundancy check code do not satisfy the preset condition.
In the embodiment of the invention, the simulation terminal is used for replacing the signal generator to send the test signal, the simulation terminal is connected with the equipment to be tested, the test signal is forwarded to the terminal consistency analyzer through the equipment to be tested, and then the terminal consistency analyzer directly measures the sensitivity of the received signal, so that the signaling transmission process can be truly simulated, the reliability of the test environment of the equipment to be tested is improved, and the best capability of the equipment to be tested can be tested.
Optionally, the sensitivity determining module 53 includes:
the comparison unit is used for comparing the first power with a standard value, wherein the standard value is a sensitivity standard value of the equipment to be tested which is specified in advance;
and the sensitivity determining unit is used for determining the first power as the sensitivity of the equipment to be tested if the difference value of the first power and the standard value is less than or equal to a first preset value.
Optionally, the test control apparatus 50 further includes:
the second analog terminal control module is used for starting the analog terminal and configuring cell parameters;
the first terminal consistency analyzer control module is used for starting the terminal consistency analyzer and configuring cell parameters;
and the cell synchronization determining module is used for determining that the analog terminal searches the cell and completing cell synchronization.
Optionally, the cell parameter includes at least one of bandwidth, transmission power, SSB subcarrier spacing, uplink and downlink frequency point, SSB offset, physical layer parameter, and protocol layer parameter.
Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the analog terminal and the equipment to be tested; the signal generator is connected with the combiner and is used for sending interference signals to the combiner; the combiner is used for combining the test signal sent by the analog terminal and the interference signal sent by the signal generator into a signal and then forwarding the signal to the terminal consistency analyzer through the equipment to be tested; the test control device 50 further includes:
the third analog terminal control module is used for controlling the analog terminal to send the test signal according to a second power, wherein the second power is a preset power or the sum of a preset sensitivity standard value and a preset backspacing value of the device to be tested;
the signal generator control module is used for controlling the signal generator to output a first interference signal;
the second judgment module is used for judging whether a second block error rate obtained by decoding and analyzing the first synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is less than or equal to a second preset value and/or whether a check error rate of a second cyclic redundancy check code is less than or equal to a third preset value; the first synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and the first interference signal sent by the signal generator by the combiner;
the block determining module is used for determining that the block test is passed under the condition that the second block error rate is less than or equal to the second preset value and/or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value; otherwise, determining that the blocking test fails.
Optionally, the signal generator control module is further configured to control the signal generator to output a second interference signal, where the second interference signal is different from the first interference signal;
the second judging module is further configured to judge whether a third block error rate obtained by decoding and analyzing the second synthesized signal forwarded by the device to be tested by the terminal consistency analyzer is less than or equal to a fourth preset value and/or whether a check error rate of a third cyclic redundancy check code is less than or equal to a fifth preset value; the second synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and a second interference signal sent by the signal generator by the combiner;
the block determining module is further configured to determine that the block test passes when the third block error rate is less than or equal to the fourth preset value and/or the check error rate of the third cyclic redundancy check code is less than or equal to a fifth preset value; otherwise, determining that the blocking test fails.
The embodiment of the present invention is a product embodiment corresponding to the above method embodiment, and therefore, detailed description is omitted here, and please refer to the second embodiment.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a test control device 60 according to a fourth embodiment of the present invention, where the test control device 60 can be applied to any one of the test systems described in the first embodiment, and the test control device 60 includes a processor 61, a memory 62, and a program stored in the memory 62 and capable of being executed on the processor 61; the processor 61 implements the following steps when executing the program:
controlling the analog terminal to send a test signal according to the first power;
judging whether a first block error rate and/or a first cyclic redundancy check code check error rate obtained by decoding and analyzing the test signal forwarded by the equipment to be tested by the terminal consistency analyzer meet preset conditions or not;
if the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset conditions, determining the sensitivity of the equipment to be tested;
if the first block error rate and/or the check error rate of the first cyclic redundancy check code do not meet the preset condition, adjusting the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset condition.
In the embodiment of the invention, the simulation terminal is used for replacing the signal generator to send the test signal, the simulation terminal is connected with the equipment to be tested, the test signal is forwarded to the terminal consistency analyzer through the equipment to be tested, and then the terminal consistency analyzer directly measures the sensitivity of the received signal, so that the signaling transmission process can be truly simulated, the reliability of the test environment of the equipment to be tested is improved, and the best capability of the equipment to be tested can be tested.
Optionally, when the processor 61 executes the program, the following steps may be further implemented:
if the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the preset condition, determining the sensitivity of the device to be tested, including:
comparing the first power with a standard value, wherein the standard value is a sensitivity standard value of the equipment to be tested which is specified in advance;
and if the difference value of the first power and the standard value is smaller than or equal to a first preset value, determining the first power as the sensitivity of the equipment to be tested.
Optionally, when the processor 61 executes the program, the following steps may be further implemented:
before the controlling the analog terminal to send the test signal according to the first power, the method further comprises:
starting the simulation terminal and the terminal consistency analyzer, and respectively configuring cell parameters;
and determining that the simulated terminal has searched the cell and completing cell synchronization.
Optionally, the cell parameter includes at least one of a bandwidth, a transmission power, an SSB subcarrier spacing, an uplink and a downlink frequency point, an SSB offset, a physical layer parameter, and each protocol layer parameter.
Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the analog terminal and the equipment to be tested; the signal generator is connected with the combiner and is used for sending interference signals to the combiner; the combiner is used for combining the test signal sent by the analog terminal and the interference signal sent by the signal generator into a signal and then forwarding the signal to the terminal consistency analyzer through the equipment to be tested;
the processor 61 may also implement the following steps when executing the program:
controlling the analog terminal to send the test signal according to a second power, wherein the second power is a preset power or the sum of a preset sensitivity standard value and a preset backspacing value of the device to be tested;
controlling the signal generator to output a first interference signal;
judging whether a second block error rate obtained by decoding and analyzing the first synthesized signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a second preset value and/or whether a check error rate of a second cyclic redundancy check code is smaller than or equal to a third preset value; the first synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and the first interference signal sent by the signal generator by the combiner;
if the second block error rate is less than or equal to the second preset value and/or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determining that the blocking test is passed;
otherwise, determining that the blocking test does not pass.
Optionally, when the processor 61 executes the program, the following steps may be further implemented:
controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal;
judging whether a third block error rate obtained by decoding and analyzing the second synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a fourth preset value and/or whether a check error rate of a third cyclic redundancy check code is smaller than or equal to a fifth preset value; the second synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and a second interference signal sent by the signal generator by the combiner;
if the third block error rate is less than or equal to the fourth preset value and/or the check error rate of the third cyclic redundancy check code is less than or equal to a fifth preset value, determining that the blocking test is passed;
otherwise, determining that the blocking test fails.
The specific working process of the embodiment of the present invention is the same as that of the second embodiment of the method, and therefore, the detailed description thereof is omitted, and refer to the description of the method steps in the second embodiment.
Fifth, an embodiment of the present invention provides a readable storage medium, on which a program is stored, where the program, when executed by a processor, implements the steps in any of the test methods in the second embodiment. Please refer to the above description of the method steps in the corresponding embodiments.
The readable storage medium includes a computer readable storage medium. Computer-readable storage media, including both permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
While the foregoing is directed to the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the invention as set forth in the appended claims.
Claims (11)
1. A test system, comprising: simulating a terminal and a terminal consistency analyzer;
the analog terminal is connected with the equipment to be tested and used for sending a test signal;
the terminal consistency analyzer is connected with the equipment to be tested and used for receiving the test signals forwarded by the equipment to be tested and decoding and analyzing the test signals.
2. The test system of claim 1, further comprising: a combiner and a signal generator;
the combiner is arranged between the analog terminal and the equipment to be tested;
the signal generator is connected with the combiner and is used for sending interference signals to the combiner;
the combiner is configured to combine the test signal sent by the analog terminal and the interference signal sent by the signal generator into a single signal, and forward the single signal to the terminal consistency analyzer through the device to be tested.
3. A test method applied to the test system according to claim 1 or 2, comprising:
controlling the analog terminal to send a test signal according to the first power;
judging whether a first block error rate and/or a first cyclic redundancy check code check error rate obtained by decoding and analyzing the test signal forwarded by the equipment to be tested by the terminal consistency analyzer meet preset conditions or not;
if the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset conditions, determining the sensitivity of the equipment to be tested;
if the first block error rate and/or the check error rate of the first cyclic redundancy check code do not meet the preset condition, adjusting the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset condition.
4. The method according to claim 3, wherein the determining the sensitivity of the device under test if the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the predetermined condition comprises:
comparing the first power with a standard value, wherein the standard value is a sensitivity standard value of the equipment to be tested which is specified in advance;
and if the difference value of the first power and the standard value is smaller than or equal to a first preset value, determining that the first power is the sensitivity of the equipment to be tested.
5. The method of claim 3, wherein before controlling the analog terminal to transmit the test signal at the first power, further comprising:
starting the simulation terminal and the terminal consistency analyzer, and respectively configuring cell parameters;
and determining that the simulated terminal has searched the cell and completing cell synchronization.
6. The method of claim 5, wherein the cell parameter comprises at least one of bandwidth, transmission power, SSB subcarrier spacing, uplink and downlink frequency points, SSB offset, physical layer parameter, and protocol layer parameter.
7. The method of any of claims 3-6, wherein the test system further comprises: a combiner and a signal generator; the combiner is arranged between the analog terminal and the equipment to be tested; the signal generator is connected with the combiner and is used for sending interference signals to the combiner; the combiner is used for combining the test signal sent by the analog terminal and the interference signal sent by the signal generator into a signal and then forwarding the signal to the terminal consistency analyzer through the equipment to be tested; the method further comprises the following steps:
controlling the analog terminal to send the test signal according to a second power, wherein the second power is a preset power or the sum of a preset sensitivity standard value and a preset backspacing value of the device to be tested;
controlling the signal generator to output a first interference signal;
judging whether a second block error rate obtained by decoding and analyzing the first synthesized signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a second preset value and/or whether a check error rate of a second cyclic redundancy check code is smaller than or equal to a third preset value; the first synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and the first interference signal sent by the signal generator by the combiner;
if the second block error rate is less than or equal to the second preset value and/or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determining that the blocking test is passed;
otherwise, determining that the blocking test fails.
8. The method of claim 7, further comprising:
controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal;
judging whether a third block error rate obtained by decoding and analyzing the second synthetic signal forwarded by the equipment to be tested by the terminal consistency analyzer is smaller than or equal to a fourth preset value and/or whether a check error rate of a third cyclic redundancy check code is smaller than or equal to a fifth preset value; the second synthesized signal is obtained by synthesizing the test signal sent by the analog terminal and a second interference signal sent by the signal generator by the combiner;
if the third block error rate is less than or equal to the fourth preset value and/or the check error rate of the third cyclic redundancy check code is less than or equal to a fifth preset value, determining that the blocking test is passed;
otherwise, determining that the blocking test fails.
9. A test control apparatus applied to the test system according to claim 1 or 2, comprising:
the first analog terminal control module is used for controlling the analog terminal to send a test signal according to the first power;
the first judgment module is used for judging whether a first block error rate and/or a check error rate of a first cyclic redundancy check code obtained by decoding and analyzing the test signal forwarded by the equipment to be tested by the terminal consistency analyzer meet preset conditions or not;
the sensitivity determining module is used for determining the sensitivity of the equipment to be tested under the condition that the first block error rate and/or the check error rate of the first cyclic redundancy check code meet the preset conditions;
the first analog terminal control module is further configured to adjust the first power of the analog terminal until the first block error rate and/or the check error rate of the first cyclic redundancy check code satisfy the preset condition, when the first block error rate and/or the check error rate of the first cyclic redundancy check code do not satisfy the preset condition.
10. A test control apparatus comprising a memory, a processor and a program stored on the memory and executable on the processor; characterized in that the processor implements the steps in the test method according to any one of claims 3 to 8 when executing the program.
11. A readable storage medium, on which a program is stored, which program, when being executed by a processor, carries out the steps of a testing method according to any one of claims 3 to 8.
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