CN114760122A - UDP (user Datagram protocol) one-way transmission method based on hardware return-free channel - Google Patents
UDP (user Datagram protocol) one-way transmission method based on hardware return-free channel Download PDFInfo
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- 238000012545 processing Methods 0.000 claims description 4
- 239000000725 suspension Substances 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 11
- 238000004891 communication Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
- H04L63/0227—Filtering policies
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
- H04L63/0227—Filtering policies
- H04L63/0236—Filtering by address, protocol, port number or service, e.g. IP-address or URL
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
- H04L63/1441—Countermeasures against malicious traffic
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/164—Adaptation or special uses of UDP protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
The invention discloses a UDP protocol one-way transmission method based on hardware without a return channel, which is characterized in that UDP protocol data can physically realize one-way transmission by combining specific hardware design according to the connection-oriented transmission characteristics of the UDP protocol. The method comprises the following steps: the outer network is a common network interface, the FPGA responds to a necessary ARP data packet, the FGPA filters the data packet, the data of a non-UDP protocol and a non-target IP address are discarded, and the data packet meeting the requirement can be written into the FIFO of the inner network side and sent to the equipment of the inner network side; because the MAC side of RGMII on the internal network side suspends all the information pins related to receiving, the path of sending data from the internal network to the external network is completely blocked physically; the method can effectively prevent the intranet from being attacked by the extranet and can also effectively prevent the intranet information from leaking into the extranet.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a UDP (user Datagram protocol) one-way transmission method based on a hardware return-channel-free UDP (user Datagram protocol).
Background
In recent years, with the rapid development of communication networks and computer information technologies, the problem of information security is more prominent. Because measures for guaranteeing information security are incomplete, production environment is damaged and enterprise information is leaked due to network attacks, how to adopt technical means can effectively resist various network attacks under the condition that data can be normally transmitted, and the requirement for guaranteeing the network security of enterprises is increasingly urgent.
The traditional unidirectional transmission of UDP protocol data generally adopts a firewall to realize the unidirectional transmission of a data link. The control of the data transmission belongs to logic control, and the function of the UDP protocol data one-way transmission control is easy to fail due to the reasons that the firewall rule configuration is unreasonable, the equipment hardware fault, the network attack causes the function of the firewall to fail and the like, so that the safety of the system is threatened.
Disclosure of Invention
The present invention aims to provide a hardware-based UDP protocol unidirectional transmission method without a return channel, so as to solve the problems proposed in the above background art.
In order to solve the technical problems, the invention provides the following technical scheme: the UDP protocol one-way transmission method based on the hardware return-free channel comprises the following steps:
s1, the external network sends UDP data to the one-way transmission module;
s2, the one-way transmission module filters the UDP data message;
and S3, the intranet transmits the data message to the target host in a one-way mode.
Further, in step S1, the external network sends UDP data to the unidirectional transport module: the external network sends the UDP data packet to the one-way transmission module in a traditional mode, and the module writes the data packet into an FIFO chip at the external network side after receiving the data packet;
In step S2, the unidirectional transport module filters the UDP data packet: FGPA reads the data message from FIFO of the external network side, reply necessary ARP message; simultaneously filtering non-UDP messages and non-target IP address messages;
in step S3, the intranet unidirectionally sends the data message to the target host: the intranet side unidirectionally sends the data of the FIFO chip to the intranet equipment; and simultaneously, a physical channel for data transmission from an internal network to an external network is not provided.
Further, in step S1, the external network sends the UDP data to the unidirectional transport module, and the external network device directly sends the data packet of the UDP protocol to the network interface on the external network side without modifying the task.
Further, in step S2, the unidirectional transmission module filters UDP data packets, and the FGPA may respond to the necessary ARP packet and simultaneously filter the protocol; and directly discarding and processing the message data of the non-target.
Further, in step S3, the intranet unidirectionally sends the data packet to the target host, and on the RGMII interface of the intranet, the MAC side suspends all the signal pins related to reception, so that the MAC of the FPGA cannot receive the data sent by the intranet, thereby achieving the purpose of unidirectional transmission of UDP protocol data.
Further, the UDP refers to: a transport layer protocol; the source end and the terminal do not establish connection before data transmission, and the connection state including the receiving and sending states does not need to be maintained because the connection is not established before the data transmission.
Further, the suspension means: in digital logic circuits, the input pins of the logic devices are connected neither high nor low, i.e., they do not physically accept any signal input.
Further, the FPGA means: a field programmable gate array is a circuit that can be modified by user programming after manufacture.
Further, the RGMII refers to: an interface mode of an Ethernet PHY-MAC interface; the PHY means: an Ethernet chip is used for realizing the physical layer of the OSI model, and the main function is to send and receive data frames of the Ethernet.
Further, the FIFO refers to: a first-in first-out memory chip.
Compared with the prior art, the invention has the following beneficial effects:
1. the UDP is a connectionless protocol, a source end and a terminal do not establish connection before data transmission, and the connection state including a receiving and sending state and the like does not need to be maintained as the connection is not established when the data is transmitted; in the hardware design, on an RGMII interface of an internal network and an MAC side, all receiving related signal pins are suspended, so that data sent by the internal network cannot be received in the MAC of the FPGA, and the purpose of unidirectional transmission of UDP protocol data is achieved; because the physical channel from the internal network to the external network is manually disconnected, various network attacks can be effectively resisted, the information of the equipment of the internal network is ensured not to be leaked, and meanwhile, UDP data sent from the external network side can be normally received; through a specific hardware design method and the combination of the characteristics of UDP protocol transmission, the UDP protocol can realize unidirectional transmission from an external network to an internal network; the outer network can normally transmit data to the inner network, and the information of the inner network is prevented from leaking to the outer network through the network path; the one-way transmission can be realized from the internal network to the external network relatively, so that the internal network can normally transmit data to the external network, and meanwhile, the internal network is protected from network attack;
2. The invention suspends the signal receiving and receiving pin of the inner network to realize the one-way transmission of data from the outer network to the inner network, and the realization mode is simple and effective; due to the integration of hardware, the data transmission delay is extremely low, and the link bandwidth is high; because the hardware design is simple, the whole full load operation power consumption is low, the fanless design can be adopted, and the safe and stable operation can be carried out for a long time.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic representation of a pre-application environment of the present invention;
FIG. 2 is a schematic representation of a post-application environment of the present invention;
fig. 3 is a schematic diagram of a flow chart of the implementation of the method.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The hardware return channel-free UDP protocol unidirectional transmission method as shown in fig. 1-3 includes the following steps:
s1, the external network sends UDP data to the one-way transmission module: the outer network sends the UDP data packet to a one-way transmission module in a traditional mode, and the module writes the data packet into an FIFO chip on the outer network side after receiving the data packet; the external network equipment directly sends the data message of the UDP protocol to a network interface at the external network side without modifying the task;
s2, the unidirectional transmission module filters the UDP data message: FGPA reads the data message from FIFO of the external network side, reply to necessary ARP message; simultaneously filtering non-UDP messages and messages of non-target IP addresses; FGPA can respond to necessary ARP message and can filter the protocol at the same time; directly discarding and processing non-target message data;
s3, the intranet unidirectionally sends the data message to the target host: the intranet side unidirectionally sends the data of the FIFO chip to the intranet equipment; meanwhile, a physical channel for data transmission from an internal network to an external network is not provided; on an RGMII interface of the internal network, all signal pins related to receiving are suspended at the MAC side, so that data sent by the internal network cannot be received in the MAC of the FPGA, and the purpose of unidirectional transmission of UDP protocol data is achieved.
As shown in fig. 1, data transmission before the application of the present invention is bidirectional, an internal network and an external network are in the same internal network, an internal network device is completely exposed in the environment of the external network, the internal network device is very vulnerable to network attack, the information system of the internal network is threatened, and information leakage is easily caused;
as shown in fig. 2, after the present invention is applied, the UDP data of the extranet can be transmitted only by the intranet. Because the MAC side of the internal network RGMII interface artificially suspends all signal pins related to receiving, the path of sending data from the internal network to the external network is completely blocked physically;
as shown in fig. 3, the method of the present invention implements a process: the outer network sends UDP data to a one-way transmission module (I) in a traditional mode, the one-way transmission module reads the data from FIFO (first in first out) on the outer network side, responds to a necessary ARP (Address resolution protocol) packet (II), filters data packets of a UDP protocol, discards data packets of a non-UDP protocol and a non-target IP (Internet protocol) address, writes the data into FIFO (fourth) on the inner network side and sends the data to a target host of the inner network; since the MAC side of the intra-network RGMII interface artificially suspends all the receive-related signal pins, the path of sending data from the intra-network to the extra-network is physically blocked completely.
(1) The implementation principle on hardware is as follows: the RX signal of RGMII is disconnected from the PHY chip of the intranet side, so that the MAC of the FPGA cannot receive the data returned by the intranet side;
"there is very low data transmission delay, there is higher link bandwidth": under the FPGA platform, the data transmission delay is less than 1 ms; under the RFC2544 test case, 64-1518 random bytes do not lose packets under the bandwidth of 1000 million 100%.
"the whole full load operation power consumption is low": under an RFC2544 test case, 64-1518 random bytes are fully loaded and run by 100%, and the running power is less than 3W;
on one side needing single transmission, a channel for returning data is removed in the aspect of hardware design; the concrete implementation is as follows: and the MAC side of the internal network RGMII interface artificially suspends the RX signal pin.
(2) According to the MAC RGMII signal, kilomega is 125MHz clock, and each clock is used for transmitting 8bit data bits; the minimum distance between one frame of Ethernet is 96 bits of data bits, namely 12 bytes, so to reach the full speed of giga, one frame of Ethernet will come from the second frame data packet after finishing transmitting 12 clocks, in order to reach the full speed of giga and not to lose the packet, adopt the dilatation of the data bit while receiving, after receiving a byte each time, arrange and make up 4 bytes, namely 32 bits, so can reach within 12 clock cycles and finish analyzing the data, then the system clock has adopted 200MHz to analyze the data, judge whether this frame data packet is UDP, and IP address matches;
If the data packet is configured in four ways, the FIFO received by the data packet from the inner network is transmitted to the FIFO of the outer network for transmission;
according to the parallel processing capability of the FPGA, after receiving the data, the intranet copies the data into two paths of data, wherein one path of data is used for judging a UDP protocol and an IP address, and the other path of data is used for judging an ARP response mechanism and a configuration register; therefore, the judgment and filtering of the IP address protocol of the UDP data can be responded, and the response of the ARP mechanism and the response of the register can be responded at the same time.
(3) According to the PHY chip, the RGMII TX of the PHY chip is an output signal which is output and can be suspended without problems;
however, for the FPGA, the signal at this time is the RGMII RX signal, which is an input signal and is mapped to the pad pins, otherwise, the FPGA compiling is not passed, so these signal pins of the RGMII RX are mapped to other unused pins of the FPGA; the RX clock in the RGMII interface comes from the PHY chip and is 125MHz at 1Gb/s, 25MHz at 100Mb/s and 2.5MHz at 10 Mb/s.
(4) Because the RGMII interface comprises an RX clock signal, the clock corresponds to different clocks of giga, hundred mega and ten mega, and the clock is 125MHZ at 1Gb/s, 25MHz at 100Mb/s and 2.5MHz at 10 Mb/s; according to the clock, in order to realize self-adaptation of giga-hundred mega, the register information of the PHY chip is read by the FPGA through an MDIO interface of the PHY chip at intervals, the state of the handshake between the PHY chip and the opposite side at the moment can be read, for example, whether the PHY chip is connected with the opposite side, the matching speed and full duplex are realized, then the information of the states is adjusted, if the handshake is the tera, the MAC is configured to be the tera, and if the handshake is the tera, the MAC is configured to be the tera; this is equivalent to knowing what the clock of the GMII RX is, although off.
The "outer net" of the present invention means: non-productive networks such as public networks and the like with lower information security requirements.
The "intranet" of the present invention means: networks produced with relatively high information security requirements.
The "FPGA" of the present invention means: a Field Programmable Gate Array (FPGA) is a circuit that can be modified by user programming after manufacture.
The RJ45 refers to: is one type of information jack (i.e., communication outlet) connector in a wiring system.
The "PHY" of the present invention means: an Ethernet chip is used for realizing the physical layer of the OSI model, and the main function is to send and receive data frames of the Ethernet.
The "RGMII" of the present invention means: an interface mode for an Ethernet PHY-MAC interface.
The "FIFO" of the present invention means: a first-in first-out memory chip.
The "UDP" of the present invention means: a transport layer protocol. The source end and the terminal do not establish connection before data transmission, and the connection state, including the receiving and sending state, does not need to be maintained as the connection is not established before the data transmission.
The suspension of the invention means that: in digital logic circuits the input pins of the logic device are connected neither high nor low, i.e. they do not physically accept any signal input.
The invention aims to provide a UDP protocol one-way transmission method based on hardware return-free channel, wherein UDP is a connectionless protocol, a source end and a terminal do not establish connection before data transmission, and the connection state, including receiving and sending states, does not need to be maintained as the connection is not established when the data is transmitted; in the hardware design, all the receiving related signal pins are suspended on an RGMII interface of an internal network and an MAC side, so that data sent by the internal network cannot be received in the MAC of the FPGA, and the aim of unidirectional transmission of UDP protocol data is fulfilled; because the physical channel from the internal network to the external network is manually disconnected, various network attacks can be effectively resisted, the information of the equipment of the internal network is ensured not to be leaked, and simultaneously UDP data sent from the external network side can be normally received; the UDP protocol can realize unidirectional transmission from an external network to an internal network by a specific hardware design method and combining the characteristics of UDP protocol transmission; the outer net can normally transmit data to the inner net, and the information of the inner net is prevented from being leaked to the outer net through the network path; correspondingly, unidirectional transmission can be realized from the intranet to the extranet, the intranet can normally transmit data to the extranet, and meanwhile, the intranet is protected from network attack.
The difference between the present invention and other methods is:
difference a: the difference from the traditional firewall is as follows: traditional firewalls are based on unidirectional transmission of logical communication links of rules. The function of unidirectional transmission control of UDP protocol data is easy to fail due to the reasons that the firewall rule configuration is unreasonable, the equipment hardware is failed, the network attack causes the firewall function to fail and the like, thereby causing the security of the system to be threatened.
Difference b: the difference from the traditional physical isolation: the traditional physical isolation generally adopts a 2+1 structure, both an internal network and an external network can receive and transmit data, and a one-way transmission component is used for physical isolation between the internal network and the external network. The hardware design is complex, the data transmission delay is long, the data transmission bandwidth is not high generally, and the failure of the whole communication link is easily caused by the hardware failure on one side.
The invention has the beneficial effects that:
effect a: the inner network receives and receives the signal pins in the air, so that the one-way transmission of data from the outer network to the inner network is achieved, and the implementation mode is simple and effective.
Effect b: due to the integration of hardware, the method has extremely low data forwarding time delay and higher link bandwidth.
Effect c: because the hardware design is simple, the whole full load operation power consumption is low, the fanless design can be adopted, and the safe and stable operation can be carried out for a long time.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described above, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The UDP protocol one-way transmission method based on the hardware non-return channel is characterized in that: the method comprises the following steps:
s1, the external network sends UDP data to the one-way transmission module;
s2, the unidirectional transmission module filters the UDP data message;
s3, the intranet unidirectionally sends the data message to the target host.
2. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 1, wherein:
in step S1, the external network sends UDP data to the unidirectional transport module: the outer network sends the UDP data packet to a one-way transmission module in a traditional mode, and the module writes the data packet into an FIFO chip on the outer network side after receiving the data packet;
In step S2, the unidirectional transmission module filters the UDP data packet: FGPA reads the data message from FIFO of the external network side, reply to necessary ARP message; simultaneously filtering non-UDP messages and non-target IP address messages;
in step S3, the intranet unidirectionally sends the data message to the target host: the intranet side unidirectionally sends the data of the FIFO chip to the intranet equipment; and simultaneously, a physical channel for data transmission from an internal network to an external network is not provided.
3. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 2, wherein: in step S1, the extranet sends the UDP data to the unidirectional transport module, and the extranet device directly sends the data packet of the UDP protocol to the network interface on the extranet side without modifying the task.
4. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 2, wherein: in step S2, the unidirectional transport module filters UDP data packets, and the FGPA may respond to the necessary ARP packets and simultaneously filter the protocol; and directly discarding and processing the message data of the non-target.
5. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 2, wherein: in step S3, the intranet unidirectionally sends the data packet to the target host, and on the RGMII interface of the intranet, the MAC side suspends all the signal pins related to reception, so that the MAC of the FPGA cannot receive the data sent by the intranet, thereby achieving the purpose of unidirectional transmission of UDP protocol data.
6. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 1, wherein: the UDP refers to: a transport layer protocol; the source end and the terminal do not establish connection before data transmission, and the connection state, including the receiving and sending state, does not need to be maintained as the connection is not established for data transmission.
7. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 5, wherein: the suspension means that: in digital logic circuits the input pins of the logic device are connected neither high nor low, i.e. they do not physically accept any signal input.
8. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 2, wherein: the FPGA refers to: a field programmable gate array is a circuit that can be modified by user programming after manufacture.
9. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 5, wherein: the RGMII refers to: an interface mode of an Ethernet PHY-MAC interface; the PHY means: an Ethernet chip is used for realizing the physical layer of the OSI model, and the main function is to send and receive data frames of the Ethernet.
10. The hardware return-channel-free UDP protocol unidirectional transmission method according to claim 2, wherein: the FIFO refers to: a first-in first-out memory chip.
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| CN205142242U (en) * | 2015-11-24 | 2016-04-06 | 尹璐 | One -way data transmission system |
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| CN201623716U (en) * | 2010-03-26 | 2010-11-03 | 深圳市维信联合科技有限公司 | Unidirectional transmission system with feedback function |
| CN203788294U (en) * | 2014-04-24 | 2014-08-20 | 武汉科源安信科技有限公司 | Unidirectional data transmission machine for optical transmission |
| CN105282172A (en) * | 2015-11-09 | 2016-01-27 | 珠海市鸿瑞软件技术有限公司 | Uniprocessing system based on hardware data transformation technology and network security isolation method thereof |
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