CN114759917A - ISP receiver compatible with PLL and DLL modes - Google Patents
ISP receiver compatible with PLL and DLL modes Download PDFInfo
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- CN114759917A CN114759917A CN202210679197.0A CN202210679197A CN114759917A CN 114759917 A CN114759917 A CN 114759917A CN 202210679197 A CN202210679197 A CN 202210679197A CN 114759917 A CN114759917 A CN 114759917A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
An ISP receiver compatible with processing PLL and DLL modes comprises a bypass frequency division module and a phase-locked loop connected with the bypass frequency division module, wherein the phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator which are connected in sequence; the clock data recovery module is connected with the low-pass filter and the voltage-controlled oscillator; the bypass frequency division module has the functions of: when the input signal is in a DLL mode, the input signal is directly output to the phase-locked loop; when the input signal is in a PLL mode, dividing the frequency of the input signal by four and outputting the divided frequency to a phase-locked loop; the clock data recovery module can select a corresponding working mode according to an input signal. The invention can realize the compatible processing of the DLL and the PLL by setting the working mode of the bypass frequency division module and matching with the corresponding configuration of the clock data recovery module.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, relates to display signal processing, and particularly relates to an ISP receiver compatible with PLL and DLL modes.
Background
ISP (interconnected-serial Protocol) is a clock embedded high-speed serial interface Protocol defined by display driver chip manufacturers and used in a system, and a receiving end needs to recover Clock Data (CDR) in data. The ISP protocol defines two working modes of DLL and PLL, the training modes of the two modes are different, and the specific expression is that the used training clock signals are different, the training clocks of the two modes are shown in FIG. 3, the [1] and [2] in the PLL mode are a signal complete period, and in the DLL mode, the [1] and [2] … [8] are a signal complete period.
The existing ISP receiver is designed to be only applied to a PLL mode or a DLL mode, a transmitting end is required to be matched and adjusted to a corresponding mode to normally work during testing, and a voltage controlled oscillator VCO (voltage controlled oscillator) in the DLL mode is output in a low frequency and multiple phases; the VCO in the PLL mode has high frequency and few phases, so that the PLL mode architecture and the DLL mode architecture are incompatible and cannot simultaneously process two modes.
Disclosure of Invention
In order to overcome the technical defects in the prior art, the invention discloses an ISP receiver compatible with PLL and DLL modes.
The ISP receiver compatible with the PLL and the DLL modes is characterized by comprising a bypass frequency division module and a phase-locked loop connected with the bypass frequency division module, wherein the phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator which are sequentially connected; the clock data recovery module is connected with the low-pass filter and the voltage-controlled oscillator;
the bypass frequency division module has the functions of: when the input signal is in a DLL mode, the input signal is directly output to the phase-locked loop; when the input signal is in a PLL mode, dividing the frequency of the input signal by four and outputting the divided frequency to a phase-locked loop;
the clock data recovery module can select a corresponding working mode according to an input signal.
Preferably, the following components: and the mode discrimination module is in signal connection with the bypass frequency division module and the clock data recovery module.
Preferably, the following components: the bypass frequency division module comprises a four-frequency divider formed by connecting two D triggers in series, Q ends of the two D triggers are connected with a D end through a phase inverter respectively, and the D end of the first D trigger is connected with a clock input end of the second D trigger;
the mode selection end is connected with the input end of the first inverter, the output end of the first inverter is connected with the second inverter, the output end and the reset end of the first inverter are respectively connected with the two input ends of the first AND gate, the output end of the AND gate is connected with the clock ends of the two D triggers,
the clock input end of the bypass frequency division module is connected with the input end of a third inverter, and the output end of the third inverter is connected with the input end of the first D trigger;
the Q end of the first D trigger and the D end of the second D trigger are respectively connected with two input ends of the first NAND gate, the output end of the first NAND gate and the output end of the second inverter are respectively connected with the input ends of the NOR gate, and the output end of the NOR gate and the clock input end are respectively connected with two input ends of the second NAND gate; the output end of the third inverter and the output end of the second inverter are respectively connected with two input ends of a third NAND gate; the output ends of the second NAND gate and the third NAND gate are respectively connected with two input ends of the second AND gate, and the output end of the second AND gate is used as the clock output end of the bypass frequency division module.
Preferably, the following components: the clock data recovery module comprises a data input end, a clock calibration input end, a recovery mode selection end, a current output end, a data output end and a data recovery submodule, and the clock calibration submodule of a DLL (delay locked loop) mode and the clock calibration submodule of a PLL (phase locked loop) mode; the data input end, the current output end, the clock calibration input end and the data output end are connected to the data recovery submodule, data of the data recovery submodule are output to the data output end and are output to the DLL mode clock calibration submodule and the PLL mode clock calibration submodule, and the current output end of the data recovery submodule is connected with the low-pass filter; the recovery mode selection end is connected with the DLL mode clock calibration submodule and the PLL mode clock calibration submodule;
the clock data recovery module further comprises a locking signal output end, the locking signal output end is connected with the DLL mode clock calibration submodule and the PLL mode clock calibration submodule, and the locking signal output end is further connected with a phase frequency detector and a charge pump of a phase-locked loop in a controlled mode.
The invention can realize the compatible processing of the DLL and the PLL by setting the working mode of the bypass frequency division module and matching with the corresponding configuration of the clock data recovery module, and can close the phase locking circuit at proper time so as to reduce the power consumption.
Drawings
FIG. 1 is a schematic diagram of one embodiment of an ISP receiver according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of a bypass divider module according to the present invention;
in fig. 2, INV 1-first inverter, INV 2-second inverter, INV 3-third inverter, INV 4-fourth inverter, INV 5-fifth inverter, NAND 1-first NAND gate, NAND 2-second NAND gate, NAND 3-third NAND gate, AND 1-first AND gate, AND 2-second AND gate, NOR-NOR gate, CLK-clock input, CKOUT-clock output, RESET-RESET terminal, MODE-MODE select terminal;
FIG. 3 is a training clock signal for two operating modes of DLL and PLL, where [0], [1] and [2] … represent consecutive equal time intervals, and 0 and1 represent low and high levels, respectively;
fig. 4 is a schematic diagram of a signal waveform of a bypass frequency division module according to an embodiment of the present invention, where the abscissa in fig. 4 is time and the ordinate is voltage.
FIG. 5 is a diagram of an embodiment of a clock data recovery module according to the present invention, in FIG. 5, a CK-clock calibration input terminal, a Lock-Lock signal output terminal, a DIN-data input terminal, a DOUT-data output terminal, a RMODE-recovery mode selection terminal, and an IOUT-current output terminal.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings and reference numerals.
The ISP receiver compatible with processing PLL and DLL mode of the present invention, as shown in FIG. 1, comprises
The phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator which are connected in sequence, and also comprises a clock data recovery module connected with the low-pass filter and the voltage-controlled oscillator;
the bypass frequency division module has the functions of: when the input signal is in a DLL mode, the input signal is directly output to the phase-locked loop; when the input signal is in a PLL mode, dividing the frequency of the input signal by four and outputting the divided frequency to a phase-locked loop;
the clock data recovery module can select a corresponding working mode according to an input signal.
The mode signal can be directly input to the clock data recovery module and the bypass frequency division module, and the working modes of the bypass frequency division module and the clock data recovery module are selected according to whether the mode signal indicates that the current signal is in a DLL mode or a PLL mode.
In the embodiment shown in fig. 1, the ISP receiver further comprises a mode discrimination module for discriminating the operation mode of the input signal, for example, detecting the frequency of the input signal, and outputting the mode signal to the bypass frequency division module and the clock data recovery module for operation mode selection. The mode discrimination module can be realized by directly detecting the frequency of the input signal by a frequency discriminator.
The invention is used for compatibly processing PLL and DLL mode signals, when the input signal is a low-frequency DLL mode signal, the bypass frequency division module selects to directly output the input signal to the phase-locked loop without processing, and the phase-locked loop carries out phase-locked processing and then outputs a clock signal with the same phase as the input signal to the clock data recovery module for clock extraction and signal identification.
When the input signal is a high-frequency PLL mode signal, the bypass frequency division module outputs the input signal to a phase-locked loop after performing four-frequency division and frequency reduction, and the phase-locked loop outputs a clock signal with the same phase as the input signal to the clock data recovery module for clock extraction and signal identification after performing phase-locked processing.
As shown in fig. 4, a specific waveform schematic diagram of the bypass frequency division module is given, in fig. 4, when the MODE signal is at a low level, the bypass frequency division module operates in the frequency division MODE, performs frequency division on the input signal CLK, and performs frequency division to the input signal CLK, and then outputs the frequency-divided signal.
Fig. 2 shows a specific implementation of the bypass frequency-dividing module, and those skilled in the art can derive other implementations that can implement the same function but have different structures according to the digital circuit principle according to the function of the bypass frequency-dividing module.
As shown in fig. 2, the bypass frequency division module includes a quadruple frequency divider formed by two D flip-flops connected in series, Q ends of the two D flip-flops are connected to a D end through an inverter respectively, and the D end of the first D flip-flop is connected to a clock input end of the second D flip-flop;
the MODE selection end MODE is connected with the input end of a first phase inverter, the output end of the first phase inverter is connected with a second phase inverter, the output end and the RESET end RESET of the first phase inverter are respectively connected with two input ends of a first AND gate, the output end of the AND gate is connected with the clock ends of two D triggers,
the clock input end CLK of the bypass frequency division module is connected with the input end of a third inverter, and the output end of the third inverter is connected with the input end of a first D trigger;
the Q end of the first D trigger and the D end of the second D trigger are respectively connected with two input ends of the first NAND gate, the output end of the first NAND gate and the output end of the second inverter are respectively connected with the input ends of the NOR gate, and the output end of the NOR gate and the clock input end CLK are respectively connected with two input ends of the second NAND gate; the output end of the third inverter and the output end of the second inverter are respectively connected with two input ends of a third NAND gate; the output ends of the second NAND gate and the third NAND gate are respectively connected with two input ends of a second AND gate, and the output end of the second AND gate is used as a clock output end CKOUT of the bypass frequency division module.
When the MODE selection end MODE is in a high level, the MODE is expressed as a DLL MODE, the D trigger does not perform frequency division at the moment, and the bypass frequency division module directly outputs the input clock signal through a second NAND gate and a second AND gate.
The clock data recovery module is used for identifying and processing input data according to a clock signal output by the phase-locked loop, and the clock data recovery module selects different working modes according to different formats of the input data.
In order to reduce power consumption, the present invention improves the original data recovery module, and as shown in fig. 5, a specific embodiment of the clock data recovery module is provided, where the clock data recovery module includes a data input terminal, a clock calibration input terminal, a recovery mode selection terminal, a current output terminal, a data recovery submodule, a DLL mode clock calibration submodule, and a PLL mode clock calibration submodule; the data input end, the current output end, the clock calibration input end and the data output end are connected to the data recovery submodule, data of the data recovery submodule are output to the data output end and are output to the DLL mode clock calibration submodule and the PLL mode clock calibration submodule, and the current output end of the data recovery submodule is connected with the low-pass filter; and the recovery mode selection end is connected with the DLL mode clock calibration submodule and the PLL mode clock calibration submodule.
Data enters from a data input end DIN, the data is recovered by a data recovery submodule, the data recovery submodule is a circuit module for recovering the data according to input data and clock signals, a frequency discrimination phase demodulation module is arranged in the data recovery submodule, and current is output from a current output end to a low-pass filter to be used for controlling the frequency band position of the low-pass filter, and the data recovery submodule is the prior art in the field and is not described any more here.
After data recovery, the data is output from a data output end DOUT and is output to a DLL mode clock calibration submodule and a PLL mode clock calibration submodule, the data are respectively used for carrying out clock calibration under two modes, and a mode control end RMODE input signal controls the working state of the two clock calibration submodules, for example, RMODE is high level and represents a DLL mode, the DLL mode clock calibration submodule normally works to output a locking success signal, and the PLL mode clock calibration submodule does not work and does not output; the DLL mode clock calibration submodule performs clock calibration on input data in the DLL mode, wherein the clock calibration input CK is connected with the output end of the voltage controlled oscillator.
Conversely, if RMODE is low, indicating PLL mode, the PLL mode clock calibration sub-module is operating normally to output a lock success signal while the DLL mode clock calibration sub-module is not operating and has no output.
And after the DLL mode clock calibration submodule or the PLL mode clock calibration submodule finishes clock calibration on data, a locking signal output end Lock outputs a locking success signal, the locking signal output end is connected with the DLL mode clock calibration submodule and the PLL mode clock calibration submodule, and the locking signal output end is also connected with a phase frequency detector and a charge pump of a phase-locked loop.
The locking signal output end is determined by adding signals output by a DLL mode clock calibration submodule and a PLL mode clock calibration submodule, as long as any one clock calibration submodule in two modes realizes clock calibration, the clock data recovery module calibrates the clock, the locking signal output end can output a locking signal, as the frequency and phase discrimination module in the data recovery submodule can realize the frequency and phase discrimination function of input data, at the moment, the frequency and phase discriminator and the charge pump in a phase-locked loop do not need to work, and the locking signal is output to close the frequency and phase discriminator and the charge pump in the phase-locked loop, so that the power consumption is reduced.
The foregoing is a further detailed description of the present invention in connection with specific preferred embodiments thereof, and it is not intended that the specific embodiments of the present invention be limited to these descriptions. For those skilled in the art to which the invention pertains, other embodiments that do not depart from the gist of the invention are intended to be within the scope of the invention.
Claims (4)
1. An ISP receiver compatible with processing PLL and DLL modes is characterized by comprising a bypass frequency division module and a phase-locked loop connected with the bypass frequency division module, wherein the phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator which are connected in sequence; the clock data recovery module is connected with the low-pass filter and the voltage-controlled oscillator; the bypass frequency division module has the functions of: when the input signal is in a DLL mode, the input signal is directly output to the phase-locked loop; when the input signal is in a PLL mode, dividing the input signal by four and outputting the divided input signal to a phase-locked loop; the clock data recovery module can select a corresponding working mode according to an input signal.
2. The ISP receiver compatible for handling PLL and DLL modes as recited in claim 1, wherein: the system also comprises a mode discrimination module which is in signal connection with the bypass frequency division module and the clock data recovery module.
3. The ISP receiver compatible for handling PLL and DLL modes as recited in claim 1, wherein: the bypass frequency division module comprises a four-frequency divider formed by connecting two D triggers in series, Q ends of the two D triggers are connected with a D end through a phase inverter respectively, and the D end of the first D trigger is connected with a clock input end of the second D trigger; the mode selection end is connected with the input end of a first phase inverter, the output end of the first phase inverter is connected with a second phase inverter, the output end and the reset end of the first phase inverter are respectively connected with the two input ends of a first AND gate, the output end of the AND gate is connected with the reset ends of two D triggers, the clock input end of the bypass frequency division module is connected with the input end of a third phase inverter, and the output end of the third phase inverter is connected with the input end of the first D trigger; the Q end of the first D trigger and the D end of the second D trigger are respectively connected with two input ends of the first NAND gate, the output end of the first NAND gate and the output end of the second inverter are respectively connected with the input ends of the NOR gate, and the output end of the NOR gate and the clock input end are respectively connected with two input ends of the second NAND gate; the output end of the third inverter and the output end of the second inverter are respectively connected with two input ends of a third NAND gate; the output ends of the second NAND gate and the third NAND gate are respectively connected with two input ends of the second AND gate, and the output end of the second AND gate is used as the clock output end of the bypass frequency division module.
4. The ISP receiver of claim 1, wherein the ISP receiver compatibly handles PLL and DLL modes: the clock data recovery module comprises a data input end, a clock calibration input end, a recovery mode selection end, a current output end, a data output end and a data recovery submodule, and the clock calibration submodule of a DLL (delay locked loop) mode and the clock calibration submodule of a PLL (phase locked loop) mode; the data input end, the current output end, the clock calibration input end and the data output end are connected to the data recovery submodule, data of the data recovery submodule are output to the data output end and are output to the DLL mode clock calibration submodule and the PLL mode clock calibration submodule, and the current output end of the data recovery submodule is connected with the low-pass filter; the recovery mode selection end is connected with the DLL mode clock calibration submodule and the PLL mode clock calibration submodule; the clock data recovery module further comprises a locking signal output end, the locking signal output end is connected with the DLL mode clock calibration submodule and the PLL mode clock calibration submodule, and the locking signal output end is further connected with a phase frequency detector and a charge pump of the phase-locked loop.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210679197.0A CN114759917B (en) | 2022-06-16 | 2022-06-16 | ISP receiver compatible with PLL and DLL modes |
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| CN202210679197.0A CN114759917B (en) | 2022-06-16 | 2022-06-16 | ISP receiver compatible with PLL and DLL modes |
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| CN114759917B CN114759917B (en) | 2022-09-02 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105656479A (en) * | 2014-11-14 | 2016-06-08 | 成都振芯科技股份有限公司 | Wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit |
| CN107979370A (en) * | 2017-12-11 | 2018-05-01 | 哈尔滨理工大学 | A kind of high-precision phase-locked loop circuit of broadband |
| CN109120257A (en) * | 2018-08-03 | 2019-01-01 | 中国电子科技集团公司第二十四研究所 | A kind of low jitter frequency-dividing clock circuit |
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- 2022-06-16 CN CN202210679197.0A patent/CN114759917B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105656479A (en) * | 2014-11-14 | 2016-06-08 | 成都振芯科技股份有限公司 | Wide-locking range low-voltage controlled oscillator gain phase-locked loop circuit |
| CN107979370A (en) * | 2017-12-11 | 2018-05-01 | 哈尔滨理工大学 | A kind of high-precision phase-locked loop circuit of broadband |
| CN109120257A (en) * | 2018-08-03 | 2019-01-01 | 中国电子科技集团公司第二十四研究所 | A kind of low jitter frequency-dividing clock circuit |
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