CN114759636A - Double-layer active equalization circuit of battery pack - Google Patents
Double-layer active equalization circuit of battery pack Download PDFInfo
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- CN114759636A CN114759636A CN202210454936.6A CN202210454936A CN114759636A CN 114759636 A CN114759636 A CN 114759636A CN 202210454936 A CN202210454936 A CN 202210454936A CN 114759636 A CN114759636 A CN 114759636A
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- battery
- battery pack
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- inductor
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0016—Circuits for equalisation of charge between batteries using shunting, discharge or bypass circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
- H02J7/0048—Detection of remaining charge capacity or state of charge [SOC]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/20—Charging or discharging characterised by the power electronics converter
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention aims to provide a battery pack double-layer active equalization circuit with high equalization speed, when an equalization control circuit detects that the SOC of a certain battery monomer is higher, a corresponding MOS (metal oxide semiconductor) tube is conducted to discharge the battery monomer, and an inductor at one end of the battery monomer is charged; when the MOS tube is switched off, the inductor keeps instantaneous current unchanged, and simultaneously the MOS tube at the other end is conducted to form a loop with the adjacent battery monomer to charge the adjacent battery monomer, so that energy transfer between the adjacent monomers is realized. When the balance control circuit detects that the SOC value of a certain cell stack is higher, the corresponding MOS tube is conducted to discharge the cell stack, and meanwhile, the inductor at one end of the cell stack is charged; when the MOS tube is switched off, the inductor keeps instantaneous current unchanged, and the inductor and other cell stacks form a loop through the diode to charge the other cell stacks, so that energy transfer among the cell stacks is realized.
Description
Technical Field
The invention relates to the technical field of battery pack management, in particular to a battery pack double-layer active equalization circuit.
Background
Lithium batteries are widely used in the field of batteries due to their characteristics of high energy density, long cycle life, low self-discharge, and environmental friendliness. However, the battery cell has small capacity and low load capacity, and cannot meet the actual engineering requirements. In the industry, a plurality of battery cells are generally combined into a module in a certain connection mode so as to improve an SOC platform and store energy of a battery system. However, after the battery pack is used for a period of time, partial SOC loss of the battery occurs, so that the capacities of the batteries are inconsistent, and in order to alleviate the problem of battery inconsistency, the battery with SOC loss in the battery pack needs to be charged to keep the SOC of the battery pack balanced. Common equalization methods are divided into active equalization and passive equalization, wherein the passive equalization method consumes the electric quantity of a high-SOC battery cell to achieve the effect that the SOC of each string of battery cells is consistent, and the equalization process is an electric quantity waste process, so that the service life of a battery pack is shortened, and meanwhile, resources are wasted; the active equalization is to transfer the battery monomer with higher SOC in the battery pack to the battery monomer with lower SOC through the energy transmission device to charge the battery monomer with lower SOC, thereby achieving the effect that the SOC of each battery monomer is consistent. In the prior art, most of the balance among the lithium batteries is realized through a passive balance circuit or a single-layer active balance circuit, and the analysis and research on the balance circuits find that the balance time is long and is a common defect of the balance circuits no matter the balance circuits are passive balance circuits or single-layer active balance circuits, and the balance circuits have complex structures and control logics and higher realization cost.
Disclosure of Invention
The invention aims to provide a battery pack double-layer active equalization circuit with high equalization speed.
In order to achieve the purpose, the invention adopts the technical scheme that: a battery pack double-layer active equalization circuit is provided, wherein the battery pack comprises n battery monomers B1、B2、B3……Bn-1、BnFormed by connecting two groups of two battery monomers in each two adjacent battery monomersThe battery pack is formed by combining, two battery monomers in one battery pack are connected through a bottom layer inductor and an MOS (metal oxide semiconductor) tube to form a bottom layer Buck-Boost equalizing circuit, a plurality of MOS tubes, diodes and a top layer inductor are connected between the battery pack and the battery pack to form a top layer bridge type switch matrix equalizing circuit, the battery monomer with high SOC in the bottom layer Buck-Boost equalizing circuit discharges, and the battery pack with high SOC in the top layer bridge type switch matrix equalizing circuit discharges.
In the scheme, when the balance control circuit detects that the SOC of one battery cell is higher, the corresponding MOS tube is conducted to discharge the battery cell, and the inductor at one end of the battery cell is charged; when the MOS tube is switched off, the inductor keeps instantaneous current unchanged, and simultaneously the MOS tube at the other end is conducted to form a loop with the adjacent battery monomer to charge the adjacent battery monomer, so that energy transfer between the adjacent monomers is realized. When the balance control circuit detects that the SOC value of a certain cell stack is higher, the corresponding MOS tube is conducted to discharge the cell stack, and meanwhile, the inductor at one end of the cell stack is charged; when the MOS tube is switched off, the inductor keeps instantaneous current unchanged, and the inductor and other cell stacks form a loop through the diode to charge the other cell stacks, so that energy transfer among the cell stacks is realized.
Drawings
FIG. 1 is a schematic diagram of a dual-layer active equalization circuit according to the present invention;
FIG. 2 is a schematic diagram of the operation principle of a Buck-Boost equalization circuit at the bottom layer;
FIG. 3 is a schematic diagram of the operation of a top bridge switch matrix circuit;
fig. 4 is a flow chart of a method of operating a dual-layer active equalization circuit.
Detailed Description
As shown in FIG. 1, a battery pack with a double-layer active equalization circuit comprises n (n is even number) battery cells B1、B2、B3……Bn-1、BnThe battery pack is formed by connecting two adjacent battery monomers in series, every two adjacent battery monomers are combined in pairs to form a battery pack, the two battery monomers in one battery pack are connected with one MOS (metal oxide semiconductor) tube through a bottom inductor to form a bottom Buck-Boost equalizing circuit, and a plurality of battery packs are arranged between the battery pack and the battery packThe MOS tube, the diode and a top layer inductor are connected to form a top layer bridge type switch matrix equalizing circuit, a battery monomer with high SOC in the bottom layer Buck-Boost equalizing circuit discharges, and a battery stack with high SOC in the top layer bridge type switch matrix equalizing circuit discharges. When the balance control circuit detects that the SOC of a certain battery monomer is higher, the corresponding MOS tube is conducted to discharge the battery monomer, and meanwhile, the inductor at one end of the battery monomer is charged; when the MOS tube is switched off, the inductor keeps instantaneous current unchanged, and simultaneously the MOS tube at the other end is conducted to form a loop with the adjacent battery monomer to charge the adjacent battery monomer, so that energy transfer between the adjacent monomers is realized. When the balance control circuit detects that the SOC value of a certain cell stack is higher, the corresponding MOS tube is conducted to discharge the cell stack, and meanwhile, the inductor at one end of the cell stack is charged; when the MOS tube is switched off, the inductor keeps instantaneous current unchanged, and the inductor and other cell stacks form a loop through the diode to charge the other cell stacks, so that energy transfer among the cell stacks is realized. When the battery pack is balanced, the double-layer balancing structure can realize the balance of energy between two adjacent single bodies and the balance of energy between any two cell stacks far away from each other, and the two groups of balances can be carried out simultaneously, so that the balancing time is obviously shortened, the balancing efficiency is obviously improved, and the problems of low balancing speed and long balancing time of the traditional balancing circuit are solved.
In the bottom Buck-Boost equalizing circuit, one end of a bottom inductor is connected with the cathode of the previous battery monomer and the anode of the next battery monomer, and the other end of the bottom inductor is connected with the source electrode of the MOS tube corresponding to the previous battery monomer and the drain electrode of the MOS tube corresponding to the next battery monomer. Each MOS tube is connected with a bottom diode in series. The working principle of the bottom Buck-Boost equalizing circuit is shown in FIG. 2: suppose SOCB1＞SOCB2And SOC isB1+SOCB2＞SOCB(n-1)+SOCBnCell B1Has a higher SOC than that of the battery cell B2Then first control Q1On, Q2Is disconnected at this time B1By Q1Bottom layer feeding inductor L1Charging; then Q1Off, Q2Conducting, bottom layer inductance L1Passing the stored energy through Q2Is transmitted to B2。
On the bottom layer, when the SOC difference value between two adjacent battery monomers is detected to be lower than a required balance value, the corresponding two switches are disconnected; at the top level, when the SOC difference between two cell stacks is detected to be lower than the required equalization value, the corresponding two switches are opened. The balance control circuit can accurately calculate the SOC value of each battery monomer and also can accurately calculate the SOC of each battery stack.
In the top layer bridge type switch matrix equalizing circuit, the diode cathode of the upper bridge arm is connected with the anode of the battery stack, the diode anode of the upper bridge arm is connected with the source electrode of the MOS tube, the diode cathode of the lower bridge arm is connected with the cathode of the battery stack, the diode anode of the lower bridge arm is connected with the drain electrode of the MOS tube, and only the front n/2 upper bridge arms and the rear n/2 lower bridge arms are provided with diodes. Each MOS tube is connected with a top layer diode in series. The operation principle of the top bridge type switch matrix equalization circuit is shown in fig. 3, and if the battery pack consists of 6 battery monomers, the battery pack has B in total12、B34、B56Three stacks, assuming SOCB12＞SOCB56Let N stand for1And M2Is turned on when N1And M2Combined top-layer inductor L0Charging, then let N1And M2Opening, N4And M3Closed, the top inductor L0To B56And (6) charging. The balance time of the structure is shortened due to the capacity of simultaneously balancing between non-adjacent cell stacks on the top layer, and the structure is simple due to the fact that only one inductor is needed on the top layer.
When the bottom Buck-Boost equalizing circuit discharges the battery monomer with high SOC and the top bridge type switch matrix equalizing circuit discharges the battery stack with the highest SOC, the control signal is PWM modulation pulse with the duty ratio of 50%.
The equalizing circuit takes the single chip microcomputer as a core, can detect the SOC of each battery stack while detecting the SOC of each battery monomer, and outputs a plurality of paths of PWM control signals.
The magnitude of the balance current is controlled by controlling the conduction time of the MOS tube, and the operation is simple.
The control algorithm of the double-layer active equalization circuit is as follows: if the difference value of the SOC of two adjacent battery monomers in one battery stack exceeds a set target value, the balancing can be directly carried out through an internal Buck-Boost circuit, the Buck-Boost circuit discharges the battery monomers with high SOC in the battery stack, a control signal is PWM (pulse-width modulation) pulse with the duty ratio of 50%, at the moment, an inductor in the Buck-Boost circuit starts to charge, and after the charging is finished, the inductor starts to charge the battery monomers with low SOC and then alternately carries out; the top layer discharges the battery stack with the highest SOC in the battery pack, the control signal is PWM modulation pulse with the duty ratio of 50%, at the moment, the inductor in the bridge type switch matrix starts to charge, after the charging is finished, the inductor starts to charge the battery stack with the low SOC, and the charging is performed alternately. Equalization between the two layers may occur simultaneously.
The circuit does not contain energy consumption elements, and the energy transfer efficiency is high. Compared with a Buck-Boost-based single-layer active equalization circuit, when the circuit is used for equalization, two adjacent monomers in the bottom layer can be directly equalized through the Buck-Boost circuit, the top-layer equalization circuit can equalize two cell stacks, and meanwhile two paths of inductors participate in energy transfer, so that the overall equalization effect is better.
Claims (9)
1. A battery pack double-layer active equalization circuit is characterized in that: the battery pack consists of n battery monomers B1、B2、B3……Bn-1、BnThe battery pack is formed by connecting two adjacent battery monomers in pairs in series to form a battery stack, the two battery monomers in one battery stack are connected through a bottom layer inductor and an MOS (metal oxide semiconductor) tube to form a bottom layer Buck-Boost equalizing circuit, a plurality of MOS tubes, diodes and a top layer inductor are connected between the battery stack and the battery stack to form a top layer bridge type switch matrix equalizing circuit, the battery monomer with high SOC in the bottom layer Buck-Boost equalizing circuit discharges, and the battery stack with high SOC in the top layer bridge type switch matrix equalizing circuit discharges.
2. The battery pack dual-layer active equalization circuit of claim 1, wherein: in the bottom Buck-Boost equalizing circuit, one end of a bottom inductor is connected with the cathode of the previous battery monomer and the anode of the next battery monomer, and the other end of the bottom inductor is connected with the source electrode of the MOS tube corresponding to the previous battery monomer and the drain electrode of the MOS tube corresponding to the next battery monomer.
3. The battery pack dual-layer active equalization circuit of claim 2, wherein: each MOS tube is connected with a bottom diode in series.
4. The battery pack dual-layer active equalization circuit of claim 1, wherein: in the top layer bridge type switch matrix equalizing circuit, the diode cathode of an upper bridge arm is connected with the anode of a battery stack, the diode anode of the upper bridge arm is connected with the source electrode of an MOS (metal oxide semiconductor) tube, the diode cathode of a lower bridge arm is connected with the cathode of the battery stack, and the diode anode of the lower bridge arm is connected with the drain electrode of the MOS tube.
5. The battery pack dual-layer active equalization circuit of claim 4, wherein: only the front n/2 upper bridge arms and the rear n/2 lower bridge arms are provided with diodes.
6. The battery pack dual-layer active equalization circuit of claim 4, wherein: each MOS tube is connected with a top layer diode in series.
7. The battery pack dual-layer active equalization circuit of claim 4, wherein: when the bottom Buck-Boost equalizing circuit discharges the battery monomer with high SOC and the top bridge type switch matrix equalizing circuit discharges the battery stack with the highest SOC, the control signal is PWM modulation pulse with the duty ratio of 50%.
8. The battery pack dual-layer active equalization circuit of claim 1, wherein: the equalizing circuit takes a single chip microcomputer as a core, can detect the SOC of each battery stack while detecting the SOC of each battery cell, and outputs a plurality of paths of PWM control signals.
9. The battery pack dual-layer active equalization circuit of claim 1, wherein: the magnitude of the equalizing current is controlled by controlling the conduction time of the MOS tube.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210454936.6A CN114759636A (en) | 2022-04-27 | 2022-04-27 | Double-layer active equalization circuit of battery pack |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210454936.6A CN114759636A (en) | 2022-04-27 | 2022-04-27 | Double-layer active equalization circuit of battery pack |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116154924A (en) * | 2023-04-14 | 2023-05-23 | 苏州大学 | Active equalization system and method for lithium battery based on double-layer topology |
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- 2022-04-27 CN CN202210454936.6A patent/CN114759636A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116154924A (en) * | 2023-04-14 | 2023-05-23 | 苏州大学 | Active equalization system and method for lithium battery based on double-layer topology |
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