CN114758991A

CN114758991A - Chip packaging structure

Info

Publication number: CN114758991A
Application number: CN202210179596.0A
Authority: CN
Inventors: 马力; 项敏; 季蓉; 郑子企
Original assignee: Tongfu Microelectronics Co Ltd
Current assignee: Tongfu Microelectronics Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2022-07-15

Abstract

The application discloses chip packaging structure includes: a chipset comprising one or more chips; the surface of at least one side of the intermediate board is provided with the chip set; the surface of the intermediate board, on which the chip set is arranged, is provided with a groove body, and the groove body is positioned on the outer side of the chip set; and the plastic packaging layer is positioned on one side of the chip group arranged on the intermediate board, covers the chip group and fills the groove body. The application provides a chip packaging structure can avoid the layering phenomenon to appear in the connection interface of plastic envelope layer and intermediate plate.

Description

Chip packaging structure

Technical Field

The application relates to the technical field of chip packaging, in particular to a chip packaging structure.

Background

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

With the development of the technology, the chip design end disperses the functions, and disperses a multi-functional Integrated system-level chip into single-functional small chips, such as an ASIC (Application Specific Integrated Circuit) chip and an HBM (High Bandwidth Memory) chip, which are connected together through a silicon interposer (Si interposer) to form a functional unit.

And after the chip is separated by a cutting process, the side surface of the plastic packaging layer is aligned with the side surface of the silicon intermediate plate. At the starting point of the side edge of the connecting interface of the plastic packaging layer and the silicon intermediate plate, microcracks formed by cutting exist, and the microcracks easily cause the structure to have a layering phenomenon at the connecting interface due to stress formed by mismatching of thermal expansion coefficients of materials during subsequent reliability tests, so that the packaging structure is damaged.

It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions in the present specification and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present specification.

Disclosure of Invention

The technical problem that this application mainly solved provides a chip packaging structure, can avoid the connection interface of plastic envelope layer and intermediate plate to appear the layering phenomenon.

In order to solve the technical problem, the application adopts a technical scheme that: a chip package structure is provided, which includes:

a chipset comprising one or more chips;

the surface of at least one side of the intermediate board is provided with the chip set; the surface of the intermediate board, on which the chip set is arranged, is provided with a groove body, and the groove body is positioned on the outer side of the chip set;

and the plastic packaging layer is positioned on one side of the chip group arranged on the intermediate board, covers the chip group and fills the groove body.

Furthermore, the number of the groove bodies is multiple, the groove bodies form at least one annular structure, and each annular structure surrounds the periphery of the chip set.

Furthermore, the shape of the groove bodies is punctiform, and a plurality of groove bodies are distributed at intervals to form at least one annular structure.

Furthermore, the shape of the groove bodies is strip-shaped, and the groove bodies are connected end to form at least one closed annular structure.

Further, the depth of the groove body is larger than or equal to 1 micron.

Further, the interposer has opposing first and second surfaces; the interposer is provided with a conductive via for electrically connecting the first surface and the second surface.

Further, the chipset comprises a first chip arranged on the first surface, the first surface is provided with the groove body, the second surface is provided with a first electric connection structure, and the first electric connection structure is electrically connected with the first chip through the conductive through hole.

Further, the chipset comprises a first chip arranged on the first surface and a second chip arranged on the second surface, the first surface and the second surface are both provided with the groove body, and the first chip and the second chip are electrically connected through the conductive through hole.

Furthermore, the second surface is provided with a conductive column, a second electrical connection structure is arranged on one side, away from the interposer, of the plastic package layer on the second surface, and the conductive column electrically connects the interposer and the second electrical connection structure.

Further, the conductive posts are located on the peripheral side of the second chip, and the height of the conductive posts is greater than the distance between one surface of the second chip, which is away from the interposer, and the interposer; the groove body is located on one side, departing from the second chip, of the conductive column.

Different from the prior art, the beneficial effects of the application are that: the chip packaging structure that this application embodiment provided sets up the cell body through the surface that is provided with the chipset at the intermediate plate, and the cell body is filled to the plastic envelope layer, can increase the area of contact of plastic envelope layer and intermediate plate, and the extension of crackle when can prevent the connection interface layering of plastic envelope layer and intermediate plate simultaneously changes crackle propagation direction to the phenomenon of layering appears in the connection interface of avoiding plastic envelope layer and intermediate plate.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

fig. 1 is a schematic structural diagram of a chip package structure provided in this embodiment;

fig. 2 is a schematic structural diagram of another chip package structure provided in this embodiment;

fig. 3 is a schematic top view of an interposer with a chipset mounted thereon according to the present embodiment;

fig. 4 is a schematic top view of another interposer with a chipset mounted thereon according to this embodiment;

FIG. 5 is a structural schematic view of a crack propagation direction.

Description of reference numerals:

1. a chipset; 11. a first chip; 12. a second chip;

2. an intermediate plate; 21. a first surface; 23. a conductive via;

3. a trough body; 31. a punctiform trough body; 32. a strip-shaped groove body;

4. a plastic packaging layer;

5. a conductive post;

61. a first pattern layer; 63. a second pattern layer; 65. a third pattern layer;

71. a first electrical connection structure; 72. a second electrical connection structure;

83. first underfill; 84. second underfill; 85. and a protective layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Please refer to fig. 1 and fig. 2. The embodiment of the application provides a chip packaging structure, which comprises a chip set 1, an intermediate board 2 and a plastic packaging layer 4.

Wherein the chipset 1 comprises one or more chips. At least one side surface of the interposer 2 is provided with a chip set 1. The surface of the intermediate board 2 provided with the chip set 1 is provided with a groove body 3, and the groove body 3 is positioned at the outer side of the chip set 1. The molding layer 4 is located on the side of the interposer 2 where the chip set 1 is located. The plastic package layer 4 covers the chip set 1 and fills the slot 3.

The chip packaging structure provided by the embodiment of the application sets up the groove body 3 through the surface that is provided with the chip group 1 at the intermediate plate 2, and the groove body 3 is filled with the plastic packaging layer 4, can increase the area of contact of the plastic packaging layer 4 and the intermediate plate 2. Meanwhile, the crack can be prevented from expanding when the connecting interface of the plastic packaging layer 4 and the intermediate board 2 is delaminated, and as shown in fig. 5, the crack expanding direction is changed, so that the delamination phenomenon at the connecting interface of the plastic packaging layer 4 and the intermediate board 2 is avoided. In fig. 5, the arrow direction indicates the propagation direction of the crack, and the crack propagates horizontally to the right originally, and due to the provision of the slot 3, the crack propagates downward along the side wall of the slot 3.

In the present embodiment, the number of the grooves 3 is plural, so that the contact area between the molding layer 4 and the intermediate plate 2 can be further increased. The plurality of slots 3 form at least one ring-shaped structure, and each ring-shaped structure surrounds the periphery of the chip set 1. Preferably, the plurality of grooves 3 are uniformly and symmetrically distributed at intervals on the periphery of the chip set 1, so that the interface strength of the plastic package layer 4 and the intermediate plate 2 at each part of the periphery of the chip set 1 can be uniformly enhanced, and delamination is avoided.

As shown in fig. 3, the shape of the trough body 3 may be a point shape, and a plurality of trough bodies 3 are distributed at intervals to form at least one ring-shaped structure. In the present embodiment, the chipset 1 may be substantially rectangular, having four sides. Each side edge is correspondingly provided with a plurality of point-shaped groove bodies 31 which are uniformly arranged at intervals.

As shown in fig. 4, the tank body 3 is shaped like a bar, and a plurality of tank bodies 3 are connected end to form at least one closed ring structure. Four side edges of the roughly rectangular chipset 1 are provided with a strip-shaped slot 32 corresponding to each side edge.

Preferably, the plurality of grooves 3 form a plurality of annular structures. As shown in fig. 3 and 4, the plurality of tanks 3 form two ring structures. The groove 3 is located at the edge of the intermediate plate 2 and can be formed by laser etching. The size, the density and the distribution position of the groove body 3 are not limited uniquely, and the groove body can be designed according to the actual design space and the vacant area of the packaging structure. Specifically, the depth of the groove 3 needs to be greater than or equal to 1 μm.

In the present embodiment, the diameter of the tank body 3 is constant or gradually increased from the tank bottom to the tank opening, thereby facilitating the formation of the tank body 3. In other embodiments, the diameter of the groove body 3 can gradually decrease from the groove bottom to the groove opening, so that the groove body can be better matched with the plastic packaging layer 4, and the interface delamination is prevented.

In the present embodiment, the interposer 2 has a first surface 21 and a second surface (not shown) opposite to each other. The interposer 2 is provided with conductive through holes 23 for electrically connecting the first surface 21 and the second surface. Specifically, the interposer 2 in this embodiment may be a Silicon interposer 2, and the conductive Via 23 may be a Through Silicon Via (TSV). In other embodiments, other materials for interposer 2 and conductive vias 23 may be used.

In one embodiment, as shown in fig. 1, the chip set 1 includes a first chip 11 disposed on a first surface 21, the first surface 21 is provided with a slot 3, a second surface is provided with a first electrical connection structure 71, and the first electrical connection structure 71 and the first chip 11 are electrically connected through a conductive through hole 23. The number of the first chips 11 is not limited, and may be one or more. For example, the first chip 11 may be an asic (application Specific Integrated circuit) chip and an hbm (high Bandwidth memory) chip. The chip packaging structure can be applied to 2.5D packaging in the technical field of advanced packaging.

The first electrical connection structure 71 may be a solder ball or other structure that can be a solder joint. In the 2.5D package structure, one side of the interposer 2 is used for placing the first chip 11, and the other side is used for placing the first electrical connection structure 71, and the first electrical connection structure 71 is used for mounting the chip package structure onto the substrate.

In another embodiment, as shown in fig. 2, the chip set 1 includes a first chip 11 disposed on a first surface 21 and a second chip 12 disposed on a second surface, the first surface 21 and the second surface are both provided with a slot 3, and the first chip 11 and the second chip 12 are electrically connected through a conductive through hole 23. The number of the first chip 11 and the second chip 12 is not limited, and may be one or more. The first chip 11 may be an ASIC chip and an HBM chip, and the second chip 12 may also be an ASIC chip and an HBM chip. The chip packaging structure can be applied to 3D packaging in the technical field of advanced packaging, high-density integration of different chips is realized, the utilization rate of the interposer 2 is improved, the total cost is reduced, and the requirement of electronic products on high performance is met.

In the 3D packaging structure, the two sides of the intermediate board 2 are used for placing the chip set 1, so that the integration level of the device can be further improved, and the requirement of the device on high performance is met; meanwhile, more chips are integrated, so that the utilization rate of the silicon interposer 2 can be improved, and the expensive cost for manufacturing the silicon interposer 2 is reduced.

In the present embodiment, the first chip 11 and the second chip 12 disposed vertically in correspondence may be electrically connected through the conductive via 23. Besides the conductive through hole 23, a wiring layer may be designed in the interposer 2 according to requirements, so that the first chip 11 and the second chip 12 that are not correspondingly arranged up and down can be electrically connected through the conductive through hole 23 and the wiring layer to perform function integration. One first chip 11 may be electrically connected to one or more second chips 12, and one second chip 12 may be electrically connected to one or more first chips 11.

In this embodiment, the second surface is provided with the conductive pillars 5, a second electrical connection structure 72 is disposed on a side of the molding compound layer 4 on the second surface away from the interposer 2, the conductive pillars 5 electrically connect the interposer 2 and the second electrical connection structure 72, and the second electrical connection structure 72 is used for mounting the chip package structure on the substrate, so that the functional surface of the chip set 1 can be electrically connected to the substrate through the conductive pillars 5 and the second electrical connection structure 72. The conductive post 5 may be a copper conductive post 5. The second electrical connection structure 72 may be a solder ball or other structure that may act as a solder joint.

Specifically, the conductive pillars 5 are located on the periphery of the second chip 12, and the height of the conductive pillars 5 is greater than the distance between the interposer 2 and a surface of the second chip 12 away from the interposer 2. The groove body 3 on the second surface is located on one side, away from the second chip 12, of the conductive column 5, so that the groove body 3 forming the annular structure can protect the connection interface between the copper column and the intermediate plate 2 and the connection interface between the plastic package body and the intermediate plate 2 from being layered.

As shown in fig. 2, in this embodiment, the groove bodies 3 of the first surface 21 and the groove bodies 3 of the second surface may be arranged offset in the thickness direction of the intermediate plate 2 (i.e., the vertical direction in fig. 2) so as not to deteriorate the strength of the intermediate plate 2. Of course, in other embodiments, the groove 3 of the first surface 21 and the groove 3 of the second surface may be aligned in the thickness direction of the intermediate plate 2, which is not limited in the present application.

As shown in fig. 1 and 2, the second surface may be provided with a first pattern layer 61, and the first pattern layer 61 may include a plurality of first openings (not shown). The first pattern layer 61 in fig. 1 and 2 is only schematically shown in its structure, and the first pattern layer 61 may be configured as required in practical applications. In the present embodiment, the first pattern layer 61 may be formed of a photoresist, which has an insulating property. The first opening is electrically connected to the conductive via 23.

As shown in fig. 2, a second pattern layer 63 is disposed on a surface of the molding layer 4 away from the interposer 2, where the molding layer 4 is provided with the conductive pillars 5, and the second pattern layer 63 may include a plurality of second openings (not shown). The second pattern layer 63 in fig. 2 is only schematically shown in its structure, and the second pattern layer 63 may be configured as required in practical applications. In the present embodiment, the second pattern layer 63 may be formed of a photoresist, which has an insulating property. The second opening may be electrically connected with the conductive post 5.

As shown in fig. 2, a protective layer 85 may be further disposed on the first surface 21, and the protective layer 85 covers a portion of the first surface 21 except for the conductive through hole 23. The protective layer 85 may be SiN or SiO, and the protective layer 85 may be formed by chemical vapor deposition.

As shown in fig. 2, a third patterned layer 65 may be disposed on a surface of the protection layer 85 facing away from the first surface 21, and the third patterned layer 65 may include a plurality of third openings (not shown), where the third openings expose the conductive vias 23, so that the third openings are electrically connected to the conductive vias 23. A pad may be formed in the third opening, and the pad is electrically connected to the conductive via 23 through the third opening. The third pattern layer 65 may be formed of photoresist, which has an insulating property.

In the present embodiment, as shown in fig. 1 and 2, a first underfill 83 is provided between the first chip 11 and the first surface 21. The first underfill 83 fills the gap between the functional surface of the first chip 11 and the first surface 21, so as to further fix the position of the first chip 11, thereby reducing the probability of the first chip 11 tilting in the subsequent process, and the first underfill 83 can protect the corresponding circuit structure on the functional surface of the first chip 11, thereby reducing the probability of the short circuit of the circuit structure.

As shown in fig. 2, a second underfill 84 is disposed between the second chip 12 and the second surface. The second underfill 84 fills the gap between the functional surface and the second surface of the second chip 12, so as to further fix the position of the second chip 12, thereby reducing the probability of the second chip 12 tilting in the subsequent process, and the second underfill 84 can protect the corresponding circuit structure on the functional surface of the second chip 12, thereby reducing the probability of short circuit of the circuit structure.

It should be noted that, in the description of the present specification, the terms "first", "second", and the like are used for descriptive purposes only and for distinguishing similar objects, and no order is present therebetween, and no indication or suggestion of relative importance is to be made. In addition, in the description of the present specification, the meaning of "a plurality" is two or more unless otherwise specified.

The use of the terms "comprising" or "including" to describe combinations of elements, components, or steps herein also contemplates embodiments that consist essentially of such elements, components, or steps. By using the term "may" herein, it is intended to indicate that any of the described attributes that "may" include are optional.

A plurality of elements, components, parts or steps can be provided by a single integrated element, component, part or step. Alternatively, a single integrated element, component, part or step may be divided into separate plural elements, components, parts or steps. The disclosure of "a" or "an" to describe an element, ingredient, component or step is not intended to foreclose other elements, ingredients, components or steps.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A chip package structure, comprising:

a chipset comprising one or more chips;

2. The chip package structure of claim 1,

the number of the groove bodies is multiple, the groove bodies form at least one annular structure, and each annular structure surrounds the periphery of the chip set.

3. The chip package structure of claim 2,

the shape of the groove bodies is punctiform, and a plurality of groove bodies are distributed at intervals to form at least one annular structure.

4. The chip package structure of claim 2,

the groove bodies are strip-shaped, and the groove bodies are connected end to form at least one closed annular structure.

5. The chip packaging structure according to claim 3 or 4, wherein the depth of the groove is greater than or equal to 1 micron.

6. The chip package structure according to claim 1, wherein the interposer has first and second opposing surfaces; the interposer is provided with a conductive via for electrically connecting the first surface and the second surface.

7. The chip package structure according to claim 6, wherein the chip set includes a first chip disposed on the first surface, the first surface is provided with the slot, the second surface is provided with a first electrical connection structure, and the first electrical connection structure and the first chip are electrically connected through the conductive via.

8. The chip packaging structure according to claim 6, wherein the chip set comprises a first chip disposed on the first surface and a second chip disposed on the second surface, the first surface and the second surface are both provided with the slot, and the first chip and the second chip are electrically connected through the conductive through hole.

9. The chip package structure according to claim 8, wherein the second surface is provided with conductive pillars, and a side of the molding compound on the second surface, which faces away from the interposer, is provided with a second electrical connection structure, and the conductive pillars electrically connect the interposer and the second electrical connection structure.

10. The chip package structure according to claim 9, wherein the conductive pillars are located on a peripheral side of the second chip, and a height of the conductive pillars is greater than a distance between a surface of the second chip facing away from the interposer and the interposer; the groove body is located on one side, deviating from the second chip, of the conductive column.