CN114758717A

CN114758717A - Flash memory test circuit and test method

Info

Publication number: CN114758717A
Application number: CN202210237487.XA
Authority: CN
Inventors: 李欣
Original assignee: Praran Semiconductor Shanghai Co ltd
Current assignee: Praran Semiconductor Shanghai Co ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-07-15

Abstract

The invention discloses a Flash memory test circuit, which can be used for efficiently, easily and accurately measuring frequency signals by a counter or a timer and positioning memory defects by introducing an inverter oscillating ring to change the slight bit line current caused by the change of threshold voltage on a Flash memory unit control gate into the frequency signals which can be directly read by a frequency detection circuit consisting of a trigger and the counter. The invention also discloses a Flash memory testing method.

Description

Flash memory test circuit and test method

Technical Field

The invention relates to the technology of a semiconductor integrated circuit memory, in particular to a Flash memory test circuit and a test method.

Background

The NOR Flash is one of the most popular non-volatile memory products for decades, and the vigorous development of portable equipment under the wind gap opportunity of the Internet of things also brings opportunities for the development of the portable equipment.

In order to ensure the normal operation of the Flash memory, the test operation is indispensable. The test expense and the time required by the test are inevitable expenses in the research and development cost of the memory, and the cost can be effectively reduced by applying a more efficient test method.

Conventional test solutions are common in several ways:

testing Flash memory by using testing machine

The chip testing requirement with the continuously improved complexity can be met by using a high-end testing machine, but the testing cost is also improved.

(II) testing with a Probe card

The FormFactor is the first supplier of the global semiconductor probe card, and various high-performance probe card combinations can be widely applied to various chip tests. The improved probe process is effective in improving test stability, but will bring expensive and unnecessary test cost.

(III) testing with software

The testing program is written into the embedded MCU to test the Flash memory, which has the advantages that the hardware design is not required to be modified and the algorithm can be realized by modifying the software program. The method has the disadvantages that the algorithm is realized by testing the writing and modification of the program, manpower and material resources are consumed, and only partial performance tests of the Flash memory, such as uniform loss and power failure recovery of the NOR Flash memory, can be performed. The test range is limited, and the wide use is difficult.

(IV) set built-in self-test Circuit

Although a certain chip area is sacrificed, the requirement on a probe is not high, and the cost of buying expensive ATE (Automatic Test Equipment) is saved. The test capability of the built-in self-test circuit will increase with the progress of the process, while the test capability of the external test will always advance behind the progress of the process. Finally, the built-in self-test circuit has low development cost, so the built-in self-test circuit is widely applied in the industry.

The built-in self-test circuit can realize the automation of the test, can utilize the system clock to make it enter the 'full speed' test, and will not like the test machine will promote the test cost because of the rise of the working frequency of the test clock, cover more defects, reduce the test time, the built-in self-test circuit can make the initialization to the Flash memory go on the low-cost test equipment in the test too.

The implementation of the built-in self-test circuit is generally based on some algorithms for detecting faults existing in the Flash memory, the coverage rate of the algorithm for the Flash memory determines the requirement for the performance of a probe card in the test, and the cost of the probe card used in the test is effectively reduced, so that the algorithm with high fault coverage rate and high efficiency is necessary to be selected.

Regarding the test algorithm suitable for the built-in self-test circuit of the Flash memory, the following are common in the industry:

parity check pattern detection method;

(II) a checkerboard detection method;

(III) March FT algorithm detection method;

and (IV) a March-like algorithm detection method.

The fault coverage rate of the parity check graph detection method and the checkerboard detection method is low, and all typical memory fault models are difficult to cover; march FT can cover but cannot activate and detect a special fault model of an atypical memory such as Flash; the March-like algorithm considers both typical memory failures and Flash memory specific failures, but does not maximize the activation of cumulative failures. In addition, the March-like algorithm has more steps, and the testing efficiency needs to be improved.

Each of these conventional testing methods based on complex algorithms has advantages and disadvantages, but has disadvantages in that a long testing time is consumed due to its complex testing steps, and a high testing cost of a large-scale Flash memory is caused.

A large number of data latches are needed in a Flash memory with a built-in self-test circuit, and the traditional data latches have a large number of devices, large size and considerable area overhead.

Disclosure of Invention

The invention aims to provide a Flash memory test circuit and a test method, which can measure frequency signals efficiently, easily and accurately by means of a counter or a timer, locate memory defects, simplify, reduce the cost and efficiently test faults of a memory and ensure high sensitivity of the memory.

In order to solve the technical problem, the Flash memory test circuit provided by the invention comprises K sensing circuit modules and an N oscillator ring, wherein K is a positive integer;

the sensing circuit module comprises a pre-charging PMOS tube M1 and a column selection NMOS tube M2;

the source end of the pre-charge PMOS tube M1 is connected with the working voltage, the drain end of the pre-charge PMOS tube M1 is connected with the drain end of the column selection NMOS tube M2 and serves as the control voltage output end Vctr, and the gate end of the pre-charge PMOS tube M1 is used for being connected with a pre-charge control signal Vpre _ charge;

The grid end of the column selection NMOS tube M2 is used for being connected with a selection signal Vselect, and the source end of the column selection NMOS tube M2 is connected with a bit line BL of the Flash memory;

the N oscillator ring comprises a third PMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, 2N inverters and a NAND gate, wherein N is a positive integer;

the source end of the third PMOS tube M3 is connected with the working voltage, and the drain end of the third PMOS tube M3 is connected with the drain end of the fourth NMOS tube M4;

the drain of the fifth NMOS transistor M5 is connected to the source of the fourth NMOS transistor M4, the gate thereof is connected to the control voltage output terminal Vctr, and the source thereof is grounded;

the 2n inverters are connected in series, the input end of the inverter is connected with the drain end of the third PMOS tube M3, and the output end of the inverter is connected with one input end of the NAND gate;

the other input end of the NAND gate is used for receiving a first enable signal EN 1;

the output end of the NAND gate is connected with the gate ends of the third PMOS tube M3 and the fourth NMOS tube M4.

Preferably, the same page of the Flash memory is provided with F columns of bit lines, wherein F is a positive integer smaller than K;

the source ends of column selection NMOS tubes M2 of the F sensing circuit modules are respectively connected with F column bit lines BL of the same page of the Flash memory.

Preferably, an N-ring frequency detection circuit is connected to output terminals of 2N inverters serially connected in the N-oscillator ring, and is configured to detect an oscillation frequency of the N-oscillator ring.

Preferably, the N-ring frequency detection circuit includes a flip-flop and a counter connected in sequence.

Preferably, the Flash memory test circuit further comprises a P oscillator ring;

the P oscillator ring comprises a sixth PMOS tube M6, a seventh PMOS tube M8, an eighth NMOS tube M8, 2n inverters and a NAND gate;

the source end of the sixth PMOS transistor M6 is connected to the working voltage, the drain end of the sixth PMOS transistor M6 is connected to the source end of the seventh PMOS transistor M7, and the gate end of the sixth PMOS transistor M6 is connected to the control voltage output end Vctr;

the drain terminal of the eighth NMOS transistor M8 is connected to the drain terminal of the seventh PMOS transistor M7, and the source terminal of the eighth NMOS transistor M8 is grounded;

the 2n inverters are connected in series, the input end of the inverter is connected with the drain end of the seventh PMOS tube M7, and the output end of the inverter is connected with one input end of the NAND gate;

the other input end of the NAND gate is used for being connected with a second enable signal EN 2;

the output end of the NAND gate is connected with the gate ends of the seventh PMOS tube M7 and the eighth NMOS tube M8.

Preferably, a P-ring frequency detection circuit is connected to output terminals of 2n inverters serially connected in the P-oscillator ring, and is configured to detect an oscillation frequency of the P-oscillator ring.

Preferably, the P-ring frequency detection circuit includes a flip-flop and a counter connected in sequence.

Preferably, the Flash memory test circuit is a built-in self-test circuit and is integrated in a Flash memory chip.

Preferably, the Flash memory is a NOR Flash memory.

In order to solve the technical problem, the invention provides a Flash memory test method adopting the Flash memory test circuit, which comprises the following steps:

s1, resetting a first enable signal EN1 and a second enable signal EN2 to disable an N oscillator ring and a P oscillator ring, and writing the signals into each storage unit of a memory by using a required test mode to complete initialization;

s2, according to a required test mode, selecting and enabling a corresponding N oscillator ring or/and a corresponding P oscillator ring:

s3, pressurizing and selecting the word lines WL line by line, accessing a frequency detection circuit of the corresponding oscillator ring, and reading the oscillation frequency of the corresponding oscillator ring;

s4, if the oscillation frequency of the oscillator ring deviates from the center frequency and exceeds a first set interval, the selected word line WL has a defect, and a word line diagnosis mode is entered.

Preferably, after entering the word line diagnosis mode, the column selection NMOS transistor M2 of one of the sensor circuit modules is selected one by one to turn on the corresponding bit line BL, and at the same time, the column selection NMOS transistors M2 of the other F-1 sensor circuit modules are turned off, the oscillation frequency of the oscillator ring is read, and if the oscillation frequency of the oscillator ring corresponding to a selected sensor circuit module deviates from the center frequency by more than a second setting interval, the bit line BL corresponding to the selected sensor circuit module and the memory cell corresponding to the defective selected word line WL in step S4 fail.

Preferably, in step S1, the test mode is an all 0 test mode, an all 1 test mode or a hybrid test mode;

in the all 0 test mode, 0 is written into each storage unit of the memory;

all 1 test mode, each memory cell of the memory is written with 1;

the mixed mode is that some memory cells of the memory are written with 1 and some memory cells of the memory are written with 0;

in step S2, if the required test mode is the all 0 test mode, the control is enabled by the first enable signal EN1, and only the N-oscillator ring sensitive to the solid 1 fault SA1 is enabled for checking whether the solid 1 fault SA1 exists;

if the required test mode is the all-1 test mode, enabling only the P-oscillator ring sensitive to the solid-0 fault SA0 by enabling control by a second enable signal EN2 for checking whether the solid-0 fault SA0 exists;

if the desired test mode is a hybrid test mode, both the N-oscillator loop and the P-oscillator loop are enabled.

The Flash memory test circuit of the invention optimizes the slight bit line BL current Istress (sensing current) change caused by the change of the threshold voltage Vth on the control gate of the Flash memory unit into the frequency signal which can be directly read by the frequency detection circuit consisting of the trigger and the counter (or the timer) by introducing the inverter oscillating ring.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a circuit diagram of one embodiment of a Flash memory test circuit of the present invention;

FIG. 2 is a schematic diagram of a parallel test architecture of a Flash memory test circuit according to the present invention;

FIG. 3, IBL vs. Vctr vs. Vth;

FIG. 4, Vctr vs. InvP frequency f;

FIG. 5, relationship between Freq and Vth.

Detailed Description

The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

As shown in fig. 1, the Flash memory test circuit includes K Sensing circuit modules (Sensing circuits), and an N oscillator ring, where K is a positive integer;

The Flash memory stores contents through a floating gate, and the change of the charge quantity on the floating gate of the storage unit is the change of the threshold voltage Vth on the control gate of the storage unit. During Erase, there is no tunneling effect on the bit line BL; during programming, there is a current on the bit line BL for hot carrier effect. Due to the change in the thickness of the oxide, the threshold voltage Vth on the Flash memory cell control gate will float: for example vth between-5 v and +5v corresponds to state 1 and state 0, respectively. When the Flash memory has physical defects, the current flowing through the tested memory cell will change due to stress, but this may be a slight fluctuation which is not easy to measure.

In the Flash memory test circuit of the first embodiment, the precharging PMOS transistor M1 and the column selection NMOS transistor M2 form a double transistor together to form a sensing circuit module, which is shared by a column bit line BL; if a connected memory cell selected by the column selection NMOS transistor M2 is in state 1, the current Istress flowing in the bit line BL (bit line) is called a sensing current (about several tens uA); if the selected connected memory cell is in state 0, no current flows.

The N oscillator ring is composed of 2N inverters and an inverter unit controlled by a control voltage output end Vctr signal, and a 2N +1 shockable body is formed. The inverter unit in the N-ring oscillator adopts a classic Voltage Controlled Oscillator (VCO) unit — a current-starved cell (current-starved cell) (the current-starved cell is a basic structure proposed by razavi in JSSCC, and has a relatively simple structure, and the current flowing through the double transistors (the third PMOS transistor M3 and the fourth NMOS transistor M4) of the inverter unit is controlled by a current source, so that the inverter unit is in a current-starved state, and the magnitude of the bias current of the inverter unit is controlled, and the magnitude of the charging and discharging current of the load capacitor can be controlled at the same time.

And a fifth NMOS transistor M5 connected in series at the source terminal of the fourth NMOS transistor M4 and serving as a clamping transistor for clamping the control N oscillator loop.

If selection signal Vselect causes column select NMOS transistor M2 to be selected, i.e., the corresponding bit line BL is selected, column select NMOS transistor M2 will precharge the parasitic capacitor CBL on the bit line BL and stabilize the voltage on the bit line BL. When the precharge control signal Vpre _ charge gradually decreases from high and the column selection NMOS Transistor M2 is selected, if the detection output pad (padso) of the Flash memory chip detects that there is no current on the bit line BL and the control voltage output terminal Vctr is at high voltage (i.e., the voltage at this point is not pulled down), that is, no detection current flows through the STR (Select Transistor), which means that the state is in Erase state, and the read result should correspond to state 1; on the contrary, if the current is detected on the bit line BL, the control voltage output terminal Vctr is pulled down, that is, the bit line BL forms a bleeding path, which proves that the memory cell is in a progam (programmed) state, and the read result should correspond to a state 0. The voltage at the control voltage output terminal Vctr and the current on the selected bit line BL are plotted on the y-axis, and the threshold voltage Vth at the Flash memory cell control gate and the switching of the 01 memory state are plotted on the x-axis, so as to obtain fig. 3.

The period of the ring oscillator is determined by the sum of the delays of the various stages, and it can be theoretically predicted that, taking the N oscillator ring controlled by the fifth NMOS transistor M5 as an example, when the control voltage output terminal Vctr is smaller than a certain critical point, the inverter unit current will decrease due to the incomplete turn-on of the fifth NMOS transistor M5, and as can be seen from the slew rate formula, the delay (delay) will inevitably increase sharply, that is, the oscillation frequency of the N oscillator ring will decrease sharply, as shown in fig. 4. This state is called current-steady state. Since the output of the sensing circuit block is connected to the control input of the starved current phase of the N-oscillator loop, the memory state of the selected memory cell can be read out as the frequency of the N-oscillator loop. For a defective memory cell, the value of the sense current Istress read is different from that of a normal memory cell. From the relationship between the voltage at the control voltage output terminal Vctr and the threshold voltage Vth at the Flash memory cell control gate in fig. 3, and the relationship between the oscillation frequency Freq of the N oscillator loop and the voltage at the control voltage output terminal Vctr in fig. 4, the relationship between the oscillation frequency Freq of the N oscillator loop and the threshold voltage Vth at the Flash memory cell control gate can be obtained, as shown in fig. 5.

The difference between a failure Flash memory unit and a non-failure Flash memory unit is the difference of threshold voltage Vth, if the threshold voltage Vth is used as an independent variable, and the voltage of a control voltage output end Vctr, sensing current Istress and the oscillation frequency Freq of an N oscillator ring are used as dependent variables, the Flash memory test circuit structure can be observed to have higher frequency measurement resolution ratio to be used for diagnosing a failure unit, and the failures of the solid 0 and the solid 1 of the memory unit can be detected.

In the Flash memory test circuit according to the first embodiment, a slight change in the bit line BL current Istress (sense current) due to a change in the threshold voltage Vth of the Flash memory cell control gate is optimized to a frequency signal that can be directly read by the frequency detection circuit including the flip-flop and the counter (or the timer) by introducing the inverter oscillation loop.

Example two

Based on the Flash memory test circuit of the first embodiment, the same page of the Flash memory has F columns of bit lines, wherein F is a positive integer smaller than K;

The source ends of the column selection NMOS tubes M2 of the F sensing circuit modules are respectively connected to the F column bit lines BL of the same page of the Flash memory, as shown in fig. 2.

Preferably, the N-loop frequency detection circuit includes a flip-flop and a counter (or timer) connected in sequence.

In practical applications, if the method of single-column serial test is adopted, it needs to be performed column by column, and the efficiency is too low. A plurality of bits in the same page of the Flash memory need to be tested in parallel, and in order to support the parallel test, the Flash memory test circuit in the second embodiment provides a parallel test architecture scheme, wherein in the scheme, if cells (memory cells) on a word line WL are all in a 0 state, the oscillation frequency Freq of an N oscillator ring is the highest; in contrast, the 1 state of the cell (memory cell) lowers the oscillation frequency Freq of the N-oscillator ring, and any abnormality of the cell (memory cell) causes a frequency shift of the ring oscillator. Thus, detection is only with the N-oscillator loop controlled by the first enable signal EN1, both for solid 1 and soft errors can be tested in parallel.

EXAMPLE III

Based on the second embodiment, the Flash memory test circuit further comprises a P oscillator ring;

the drain end of the eighth NMOS transistor M8 is connected to the drain end of the seventh PMOS transistor M7, and the source end of the eighth NMOS transistor M8 is grounded;

Preferably, the P-ring frequency detection circuit includes a flip-flop and a counter (or timer) connected in sequence.

For the single N-oscillator ring structure controlled by the enable signal EN1 in the first and second embodiments, if the erased memory cell is far more than the programmed memory cell, i.e., "1" is far more than 0, the sensitivity will be greatly reduced due to too large delay (delay), and the oscillation frequency Freq of the N-oscillator ring will be almost constant. So enabling the controlled N-oscillator loop check SA0 (solid 0 fault) accuracy with the first enable signal EN1 awaits improvement.

In the Flash memory test circuit according to the third embodiment, the N-oscillator ring clamped and controlled by the fifth NMOS transistor M5, the P-oscillator ring clamped and controlled by the sixth PMOS transistor M6, and the sensing circuit module together form a Double ring complementary structure (Double ring cell) in the architecture of fig. 1. Wherein the design of the N oscillator loop has a higher sensitivity to SA1 (solid 1 fault); the P-oscillator ring design has a higher sensitivity to SA0 (solid 0 fault).

In the Flash memory test circuit according to the third embodiment, the P oscillator ring enabled and controlled by the second enable signal EN2 is introduced, the relationship between the oscillation frequency Freq of the P oscillator ring clamped and controlled by the sixth PMOS transistor M6 and the control voltage output terminal Vctr is completely reversed with respect to the fifth NMOS transistor M5, and the P oscillator ring clamped and controlled by the sixth PMOS transistor M6 and the fifth NMOS transistor M5 are introduced together to form a double ring, so that a higher resolution can be obtained.

For Flash memories, All-0 (All-0), All-1 (All-1), checkerboard, inverse checkerboard are the most common test patterns. For the Flash memory test circuit with the complementary dual-ring test structure in the third embodiment, the following test method that can be implemented specifically can be designed, which includes the following steps:

S1, resetting a first enable signal EN1 and a second enable signal EN2 to enable an N oscillator ring and a P oscillator ring to be invalid, and writing the N oscillator ring and the P oscillator ring into each storage unit of a memory by using a required test mode to complete initialization;

and S4, if the oscillation frequency of the oscillator ring deviates from the central frequency and exceeds a first set interval, the selected word line WL has defects, and the word line diagnostic mode is entered.

Preferably, in step S1, the test mode is an all-0 test mode, an all-1 test mode or a hybrid test mode;

all 0 test mode, each memory cell of the memory is written with 0;

all 1 test mode, each memory cell of the memory is written with 1;

preferably, in step S2, if the required test mode is the all 0 test mode, the control is enabled by the first enable signal EN1, and only the N-oscillator ring sensitive to the solid 1 fault SA1 is enabled for checking whether the solid 1 fault SA1 exists;

If the required test mode is the all-1 test mode, enabling only the P oscillator loop sensitive to the solid 0 fault SA0 by enabling control through a second enable signal EN2 for checking whether the solid 0 fault SA0 exists;

In step S4, the oscillation frequency of the oscillator loop deviates from the center frequency and exceeds the first set interval, which indicates that there is a memory cell fault on the selected word line WL, and then a single-column test may be performed, the frequency of each column of memory cells is read, and the faulty memory cell that pulls down/raises up the overall frequency is accurately found, thereby realizing accurate detection. The specific method comprises the following steps: after entering a word line diagnosis mode, the column selection NMOS transistor M2 of one of the sensor circuit modules is selected to turn on the corresponding bit line BL one by one and simultaneously the column selection NMOS transistors M2 of the other F-1 sensor circuit modules are turned off, the oscillation frequency of the oscillator loop is read, and if the oscillation frequency of the oscillator loop corresponding to a selected sensor circuit module deviates from the center frequency by more than a second setting interval, the bit line BL corresponding to the selected sensor circuit module and the memory cell corresponding to the defective selected word line WL in step S4 fail.

In step S4, for example, 8M PY2101V1 is used, where a <19> is set to 0, that is, only block0(4M) is detected first, 2048 word lines WL and 256 × 8 bit lines BL are used in parallel, and the frequency of the oscillator loop (phase locked loop) corresponding to all columns is extracted and input to the counter. The word lines WL are selected in a pressurizing mode row by row, the N oscillator ring and the P oscillator ring are started, the frequency is read out from the trigger/counter, the frequency read out when a certain row of word lines WL are tested is too high or too low, the single-column mode is started immediately, the frequency is read out row by row, the specific row (namely, a row is scanned, a problem exists in the scanned row), the fault storage unit causing the frequency of the row to deviate from a correct value is found out, the row is scanned, then the fault point is accurate, and the position of the fault storage unit is determined. And then setting a <19> -1, and detecting block1 in the same step as block 0.

Example four

Based on the Flash memory test circuit of the first embodiment to the third embodiment, the Flash memory test circuit is a built-in self-test circuit and is integrated in a Flash memory chip.

Preferably, the Flash memory is a NOR Flash memory.

The Flash memory test circuit of the fourth embodiment is integrated in a Flash memory chip, and the area of the Flash memory built in the self-test circuit is reduced as much as possible by optimizing the data latch circuit.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A Flash memory test circuit is characterized by comprising K sensing circuit modules and an N oscillator ring, wherein K is a positive integer;

2. The Flash memory test circuit of claim 1,

the same page of the Flash memory is provided with F columns of bit lines, wherein F is a positive integer smaller than K;

3. The Flash memory test circuit of claim 1,

and the N-ring frequency detection circuit is connected with the output ends of the 2N inverters connected in series in the N oscillator ring and is used for detecting the oscillation frequency of the N oscillator ring.

4. The Flash memory test circuit of claim 3,

the N-ring frequency detection circuit comprises a trigger and a counter which are connected in sequence.

5. The Flash memory test circuit of claim 2,

the Flash memory test circuit also comprises a P oscillator ring;

A source terminal of the sixth PMOS transistor M6 is connected to the working voltage, a drain terminal thereof is connected to the source terminal of the seventh PMOS transistor M7, and a gate terminal thereof is connected to the control voltage output terminal Vctr;

6. The Flash memory test circuit of claim 5,

and the P-ring frequency detection circuit is connected with the output ends of the 2n inverters connected in series in the P oscillator ring and is used for detecting the oscillation frequency of the P oscillator ring.

7. The Flash memory test circuit of claim 6,

the P-ring frequency detection circuit comprises a trigger and a counter which are connected in sequence.

8. The Flash memory test circuit according to claim 1 or 2,

the Flash memory test circuit is a built-in self-test circuit and is integrated in a Flash memory chip.

9. The Flash memory test circuit according to claim 1 or 2,

the Flash memory is a NOR Flash memory.

10. A Flash memory test method using the Flash memory test circuit of claim 5, characterized by comprising the steps of:

11. The Flash memory testing method according to claim 10,

after entering a word line diagnosis mode, the column selection NMOS tube M2 of one of the sensing circuit modules is enabled to select and turn on the corresponding bit line BL one by one, and simultaneously the column selection NMOS tubes M2 of other F-1 sensing circuit modules are enabled to be turned off, the oscillation frequency of the oscillator ring is read, if the oscillation frequency of the oscillator ring corresponding to a selected sensing circuit module deviates from the central frequency and exceeds a second set interval, the bit line BL corresponding to the selected sensing circuit module and the memory cell corresponding to the defective selected word line WL in the step S4 are in fault.

12. The Flash memory testing method according to claim 10,

in step S1, the test mode is an all 0 test mode, an all 1 test mode or a hybrid test mode;

all 0 test mode, each memory cell of the memory is written with 0;

all 1 test mode, each memory cell of the memory is written with 1;