CN114758717A - Flash memory test circuit and test method - Google Patents

Abstract

The invention discloses a flash memory test circuit. By introducing an inverter oscillation ring, the subtle bit line current change caused by the change of the threshold voltage on the control gate of the Flash memory unit is optimized to be composed of a flip-flop and a counter. The frequency signal directly read by the frequency detection circuit, the Flash memory test circuit can efficiently, easily and accurately measure the frequency signal with the help of a counter or timer, locate memory defects, and simplify the memory fault test, cost-effective and efficient. At the same time, its high sensitivity is guaranteed. The invention also discloses a flash memory testing method.

Description

Flash memory test circuit and test method

technical field

The invention relates to semiconductor integrated circuit memory technology, in particular to a Flash memory test circuit and a test method.

Background technique

NOR Flash flash memory is one of the most popular non-volatile memory products for decades, and the booming development of portable devices under the opportunity of the Internet of Things also brings opportunities for its development.

In order to ensure the normal operation of the Flash memory, test work is essential. The cost of testing and the time required for testing are unavoidable expenses in memory R&D costs, and the application of more efficient testing methods can effectively reduce costs.

The traditional test solutions are as follows:

(1) Use the test machine to complete the test of the Flash (flash) memory

The use of high-end testing machines can meet the requirements of chip testing with increasing complexity, but this also increases testing costs.

(2) Test with probe card

FormFactor is the world's No. 1 supplier of semiconductor probe cards, and its various high-performance probe card combinations can be widely used in various chip testing. Improving the manufacturing process of the probe can effectively improve the test stability, but it will bring expensive and unnecessary test costs.

(3) Using software testing

The advantage of writing the test program into the embedded MCU to test the Flash memory is that there is no need to modify the hardware design and the algorithm implementation can be realized by modifying the software program. The disadvantage is that it takes manpower and material resources to implement the algorithm by writing and modifying the test program, and it can only test part of the performance of the Flash memory, such as the uniform wear and tear of the NOR Flash flash memory and power-down recovery. The scope of testing is limited and difficult to use widely.

(4) Set the built-in self-test circuit

Although a certain chip area is sacrificed, the requirements for the probe are not high, which saves the cost of buying an expensive ATE (Automatic TestEquipment, integrated circuit automatic test machine). The test capability of the built-in self-test circuit will increase with the progress of the process, while the improvement of the test capability of the external test always lags behind the progress of the process. Finally, the development cost of the built-in self-test circuit is low, so it is widely used in the industry.

The test method of the built-in self-test circuit can automate the test, and can use the system clock to make it enter the "full speed" test, unlike the test machine, which increases the test cost and covers more defects due to the increase of the test clock operating frequency. To reduce the test time, the built-in self-test circuit also enables the initialization of the Flash memory during the test to be performed on low-cost test equipment.

The implementation of the built-in self-test circuit is generally based on some algorithms used to detect the faults of the Flash memory. The coverage of the algorithm to the Flash memory determines the performance requirements of the probe card in the test, effectively reducing the probe card used in the test. Therefore, it is necessary to choose an algorithm with high fault coverage and high efficiency.

Regarding the test algorithms suitable for the built-in self-test circuit of Flash memory, the common ones in the industry are:

(1) Parity pattern detection method;

(2) Checkerboard detection method;

(3) March FT algorithm detection method;

(4) March-like algorithm detection method.

The fault coverage rate of the parity pattern detection method and the checkerboard detection method is low, and it is difficult to cover all typical memory fault models; although March FT can cover it, it cannot activate and detect the unique fault model of atypical memory such as Flash; March The -like algorithm takes into account both typical memory faults and flash memory-specific faults, but does not activate cumulative faults to the greatest extent possible. In addition, the March-like algorithm has many steps, and the test efficiency needs to be improved.

These traditional testing methods based on complex algorithms have their own advantages and disadvantages, but the common disadvantage is that they consume a long testing time due to their complex testing steps and lead to high testing costs for large-scale Flash memories.

In the Flash memory with built-in self-test circuit, a large number of data latches need to be used, while the traditional data latch devices have a large number, large size, and considerable area overhead.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a flash memory test circuit and test method, which can measure frequency signals efficiently, easily and accurately by means of counters or timers, locate memory defects, and simplify the memory fault test at low cost. The high sensitivity is ensured at the same time of high efficiency and high efficiency.

In order to solve the above-mentioned technical problems, the Flash memory test circuit provided by the present invention includes K sensing circuit modules and an N oscillator ring, and K is a positive integer;

The sensing circuit module includes a pre-charged PMOS transistor M1 and a column selection NMOS transistor M2;

The source terminal of the pre-charged PMOS transistor M1 is connected to the working voltage, and the drain terminal of the pre-charged PMOS transistor M1 is connected to the drain terminal of the column selection NMOS transistor M2 as a control voltage output terminal Vctr, and its gate terminal is used to receive the pre-charge control signal Vpre_charge;

Described column selection NMOS tube M2, its gate terminal is used for connecting the selection signal Vselect, and its source terminal is connected to the bit line BL of Flash memory;

The N oscillator ring includes a third PMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, 2n inverters, and a NAND gate, where n is a positive integer;

The source terminal of the third PMOS transistor M3 is connected to the working voltage, and the drain terminal is connected to the drain terminal of the fourth NMOS transistor M4;

The drain terminal of the fifth NMOS transistor M5 is connected to the source terminal of the fourth NMOS transistor M4, the gate terminal is connected to the control voltage output terminal Vctr, and the source terminal is grounded;

The 2n inverters are connected in series, the input terminal is connected to the drain terminal of the third PMOS transistor M3, and the output terminal is connected to an input terminal of the NAND gate;

The other input end of the NAND gate is used to connect the first enable signal EN1;

The output terminal of the NAND gate is connected to the gate terminals of the third PMOS transistor M3 and the fourth NMOS transistor M4.

Preferably, there are F columns of bit lines in the same page of the Flash memory, and F is a positive integer less than K;

The source terminals of the column selection NMOS transistors M2 of the F sensing circuit modules are respectively connected to the F column bit lines BL of the same page of the Flash memory.

Preferably, an N-ring frequency detection circuit is connected to the output ends of 2n inverters connected in series in the N-oscillator ring, and is used for detecting the oscillation frequency of the N-oscillator ring.

Preferably, the N-loop frequency detection circuit includes a flip-flop and a counter connected in sequence.

Preferably, the Flash memory test circuit further includes a P oscillator ring;

The P oscillator ring includes a sixth PMOS transistor M6, a seventh PMOS transistor M8, an eighth NMOS transistor M8, 2n inverters, and a NAND gate;

The source terminal of the sixth PMOS transistor M6 is connected to the working voltage, the drain terminal is connected to the source terminal of the seventh PMOS transistor M7, and the gate terminal is connected to the control voltage output terminal Vctr;

The drain end of the eighth NMOS transistor M8 is connected to the drain end of the seventh PMOS transistor M7, and the source end thereof is grounded;

The 2n inverters are connected in series, the input terminal is connected to the drain terminal of the seventh PMOS transistor M7, and the output terminal is connected to an input terminal of the NAND gate;

The other input end of the NAND gate is used to connect the second enable signal EN2;

The output terminal of the NAND gate is connected to the gate terminals of the seventh PMOS transistor M7 and the eighth NMOS transistor M8.

Preferably, a P-ring frequency detection circuit is connected to the output ends of 2n inverters connected in series in the P-oscillator ring, for detecting the oscillation frequency of the P-oscillator ring.

Preferably, the P-ring frequency detection circuit includes a flip-flop and a counter connected in sequence.

Preferably, the Flash memory test circuit is a built-in self-test circuit integrated in the Flash memory chip.

Preferably, the Flash memory is a NOR Flash memory.

In order to solve the above-mentioned technical problems, the present invention provides a flash memory test method using the Flash memory test circuit, comprising the following steps:

S1. First reset the first enable signal EN1 and the second enable signal EN2 to make the N oscillator ring and the P oscillator ring invalid, and use the required test mode to write into each storage unit of the memory to complete the initialization;

S2. Select to enable the corresponding N oscillator ring or/and P oscillator ring according to the desired test mode:

S3. Press and select the word line WL row by row, connect to the frequency detection circuit of the corresponding oscillator ring, and read the oscillation frequency of the corresponding oscillator ring;

S4. If the oscillation frequency of the oscillator ring deviates from the center frequency and exceeds the first set interval, the selected word line WL is defective, and the word line diagnosis mode is entered.

Preferably, after entering the word line diagnosis mode, one by one, the column selection NMOS transistors M2 of one of the sensing circuit modules are selected to connect to the corresponding bit line BL, and at the same time, the column selection NMOS transistors M2 of the other F-1 sensing circuit modules are selected. Turn off, read the oscillation frequency of the oscillator ring, if the oscillation frequency of the oscillator ring corresponding to a selected sensing circuit module deviates from the center frequency and exceeds the second set interval, the bit line BL and the corresponding bit line BL of the selected sensing circuit module In step S4, the memory cell corresponding to the defective selected word line WL is faulty.

Preferably, in step S1, the test mode is an all-zero test mode, an all-one test mode or a mixed test mode;

All 0 test mode, each storage unit of the memory is written with 0;

All 1 test mode, each storage unit of the memory is written with 1;

Mixed mode, some memory cells are written with 1, and some are written with 0;

In step S2, if the required test mode is the all-zero test mode, the first enable signal EN1 is enabled and controlled, and only the N oscillator ring sensitive to the solid 1 fault SA1 is enabled to check whether there is a solid 1 fault SA1. ;

If the required test mode is the all-one test mode, it is enabled and controlled by the second enable signal EN2, and only the P oscillator ring sensitive to the solid 0 fault SA0 is enabled to check whether there is a solid 0 fault SA0;

If the desired test mode is a mixed test mode, enable both the N oscillator ring and the P oscillator ring.

The flash memory test circuit of the present invention optimizes the subtle bit line BL current Istress (sensing current) change caused by the change of the threshold voltage Vth on the control gate of the Flash memory cell to be able to be triggered by the introduction of an inverter oscillation ring. The frequency signal directly read by the frequency detection circuit composed of a counter and a counter (or timer), the Flash memory test circuit can efficiently, easily and accurately measure the frequency signal with the help of the counter or timer, locate memory defects, and use the counter or timer to measure the frequency signal. The fault test is simplified, cost-effective and efficient, while ensuring its high sensitivity.

Description of drawings

In order to illustrate the technical solutions of the present invention more clearly, the following briefly introduces the accompanying drawings used in the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, which are useful to those skilled in the art. In other words, other drawings can also be obtained from these drawings without any creative effort.

1 is a circuit diagram of an embodiment of a Flash memory test circuit of the present invention;

2 is a schematic diagram of the parallel test architecture of the Flash memory test circuit of the present invention;

Figure 3. The relationship between IBL and Vctr with Vth;

Figure 4. The relationship between Vctr and the frequency f of InvP;

Figure 5. The relationship between Freq and Vth.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

Example 1

As shown in Figure 1, the Flash memory test circuit includes K sensing circuit modules (Sensing circuits) and an N oscillator ring, where K is a positive integer;

The sensing circuit module includes a pre-charged PMOS transistor M1 and a column selection NMOS transistor M2;

The source terminal of the pre-charged PMOS transistor M1 is connected to the working voltage, and the drain terminal of the pre-charged PMOS transistor M1 is connected to the drain terminal of the column selection NMOS transistor M2 as a control voltage output terminal Vctr, and its gate terminal is used to receive the pre-charge control signal Vpre_charge;

Described column selection NMOS tube M2, its gate terminal is used for connecting the selection signal Vselect, and its source terminal is connected to the bit line BL of Flash memory;

The N oscillator ring includes a third PMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, 2n inverters, and a NAND gate, where n is a positive integer;

The source terminal of the third PMOS transistor M3 is connected to the working voltage, and the drain terminal is connected to the drain terminal of the fourth NMOS transistor M4;

The drain terminal of the fifth NMOS transistor M5 is connected to the source terminal of the fourth NMOS transistor M4, the gate terminal is connected to the control voltage output terminal Vctr, and the source terminal is grounded;

The 2n inverters are connected in series, the input terminal is connected to the drain terminal of the third PMOS transistor M3, and the output terminal is connected to an input terminal of the NAND gate;

The other input end of the NAND gate is used to connect the first enable signal EN1;

The output terminal of the NAND gate is connected to the gate terminals of the third PMOS transistor M3 and the fourth NMOS transistor M4.

The Flash memory stores the content through the floating gate, and the change of the charge amount on the floating gate of the memory cell is the change of the threshold voltage Vth on the control gate of the memory cell. During the Erase (erase) period, there is tunneling effect, and there is no current on the bit line BL; during the Program (programming) period, there is a hot carrier effect, and there is current on the bit line BL. Due to the change in the thickness of the oxide, the threshold voltage Vth on the control gate of the Flash memory cell will fluctuate: for example, vth between -5v and +5v corresponds to state 1 and state 0, respectively. When a physical defect occurs in the flash memory, the current flowing through the memory cell under test will change due to the addition of stress, but this may be a small, difficult-to-measure fluctuation.

In the Flash memory test circuit of the first embodiment, the pre-charged PMOS transistor M1 and the column selection NMOS transistor M2 together form a sensing circuit module, which is shared by a column of bit lines BL; When the cell is in state 1, the current Istress flowing to the bit line BL (bit line) is called the sensing current (about tens of uA); if a memory cell selected to be connected is in state 0, there is no current.

The N oscillator ring is composed of 2n inverters and an inverter unit controlled by the control voltage output terminal Vctr signal, forming a "2n+1" shockable. The classic voltage-controlled oscillator (VCO) unit used in the inverter unit in the N oscillation ring----current-starved cell (current-starved cell is the basis proposed by razavi in a JSSCC The structure is relatively simple. The current flowing through the inverter unit double tubes (the third PMOS tube M3 and the fourth NMOS tube M4) is controlled by the current source, so that the inverter unit is in a current starvation state, and the inverter unit is controlled. At the same time as the size of the bias current, the charge and discharge current of the load capacitor can also be controlled).

The fifth NMOS transistor M5 connected in series with the source end of the fourth NMOS transistor M4 acts as a clamping transistor to clamp and control the N oscillator ring.

If the selection signal Vselect causes the column selection NMOS transistor M2 to be selected, that is, the corresponding bit line BL is selected, the column selection NMOS transistor M2 will precharge the parasitic capacitance CBL on the bit line BL, and make the voltage on the bit line BL tend to be Stablize. When the precharge control signal Vpre_charge gradually decreases from high and the column selection NMOS transistor M2 is selected, if the detection output pad (padso) of the Flash memory chip detects that there is no current on the bit line BL, and the control voltage output terminal Vctr is a high voltage (that is, the voltage at this point is not pulled down), that is, there is no detection current flowing through the STR (Select Transistor), which means that it is in the Erase (erase) state, and the read result should correspond to state 1; otherwise, if the bit line is measured There is current on BL, and the control voltage output terminal Vctr is pulled down, that is, the bit line BL constitutes a discharge path, which proves that the memory cell is in the progam (programming) state, and the read result should correspond to state 0. Taking the voltage of the control voltage output terminal Vctr and the current on the selected bit line BL as the y-axis, and the threshold voltage Vth on the control gate of the Flash memory cell and the switching of the 01 storage state as the x-axis, Figure 3 can be obtained.

The cycle of the ring oscillator is determined by the sum of the delays of each stage, which can be predicted theoretically. Taking the N oscillator ring controlled by the fifth NMOS transistor M5 as an example, when the control voltage output Vctr is small to a certain critical point When the 5th NMOS transistor M5 is not fully turned on, the inverter unit current will decrease. It can be seen from the slew rate formula that the delay must increase sharply, that is, the oscillation frequency of the N oscillator ring decreases sharply. ,As shown in Figure 4. This state is called the current-starved stage. Since the output of the sensing circuit block is connected to the control input of the current starvation phase of the N oscillator ring, the memory state of the selected memory cell can be read out as the frequency of the N oscillator ring. For faulty memory cells, the sensed current Istress sensed has a different value than normal memory cells. From the relationship between the control voltage output terminal Vctr voltage in FIG. 3 and the threshold voltage Vth on the control gate of the Flash memory cell, and the relationship between the oscillation frequency Freq of the N oscillator ring and the control voltage output terminal Vctr voltage in FIG. 4, the N oscillation can be obtained. The relationship between the oscillation frequency Freq of the device ring and the threshold voltage Vth on the control gate of the Flash memory cell is shown in FIG. 5 .

The difference between the faulty and non-faulty Flash memory cells lies in the difference in the threshold voltage Vth. If the threshold voltage Vth is used as the independent variable, the control voltage output terminal Vctr voltage, the sensing current Istress, and the oscillation frequency Freq of the N oscillator ring are the dependent variables. It can be observed that the flash memory test circuit structure has a high frequency measurement resolution, which can be used for the diagnosis of the faulty unit, and can detect the faults of the memory cells solid 0 and solid 1.

In the Flash memory test circuit of the first embodiment, by introducing an inverter oscillation ring, the slight change of the bit line BL current Istress (sensing current) caused by the change of the threshold voltage Vth on the control gate of the Flash memory cell is optimized to be able to be determined by The frequency signal directly read by the frequency detection circuit composed of a flip-flop and a counter (or timer), the Flash memory test circuit can efficiently, easily and accurately measure the frequency signal with the help of a counter or a timer, locate memory defects, and use the counter or timer to measure the frequency signal. The fault test is simplified, cost-effective and efficient, while ensuring its high sensitivity.

Embodiment 2

Based on the Flash memory test circuit of the first embodiment, the same page of the Flash memory has F column bit lines, and F is a positive integer less than K;

The source terminals of the column selection NMOS transistors M2 of the F sensing circuit modules are respectively connected to the F column bit lines BL of the same page of the Flash memory, as shown in FIG. 2 .

Preferably, an N-ring frequency detection circuit is connected to the output ends of 2n inverters connected in series in the N-oscillator ring, and is used for detecting the oscillation frequency of the N-oscillator ring.

Preferably, the N-loop frequency detection circuit includes a flip-flop and a counter (or timer) connected in sequence.

In practical applications, if a single-column serial test method is used, it needs to be executed in a column-by-column manner, and the efficiency is too low. Multiple bits in the same page (page) of the Flash memory need to be tested in parallel. In order to support the parallel test, the Flash memory test circuit of the second embodiment proposes a parallel test architecture scheme. In this scheme, if a word line WL is on the The cell (storage unit) is in the 0 state, the oscillation frequency Freq of the N oscillator ring is the highest; on the contrary, the 1 state of the cell (storage unit) will reduce the oscillation frequency of the N oscillator ring Freq, any cell (storage unit) oscillation frequency Freq Anomalies can cause frequency shifts in the ring oscillator. Therefore, the detection is performed only with the N oscillator ring which is enabled and controlled by the first enable signal EN1, and both solid 1 and soft errors can be tested in parallel.

Embodiment 3

Based on the second embodiment, the Flash memory test circuit further includes a P oscillator ring;

The P oscillator ring includes a sixth PMOS transistor M6, a seventh PMOS transistor M8, an eighth NMOS transistor M8, 2n inverters, and a NAND gate;

The source terminal of the sixth PMOS transistor M6 is connected to the working voltage, the drain terminal is connected to the source terminal of the seventh PMOS transistor M7, and the gate terminal is connected to the control voltage output terminal Vctr;

The drain end of the eighth NMOS transistor M8 is connected to the drain end of the seventh PMOS transistor M7, and the source end thereof is grounded;

The 2n inverters are connected in series, the input terminal is connected to the drain terminal of the seventh PMOS transistor M7, and the output terminal is connected to an input terminal of the NAND gate;

The other input end of the NAND gate is used to connect the second enable signal EN2;

The output terminal of the NAND gate is connected to the gate terminals of the seventh PMOS transistor M7 and the eighth NMOS transistor M8.

Preferably, a P-ring frequency detection circuit is connected to the output ends of 2n inverters connected in series in the P-oscillator ring, for detecting the oscillation frequency of the P-oscillator ring.

Preferably, the P-ring frequency detection circuit includes a flip-flop and a counter (or timer) connected in sequence.

For the single-N oscillator ring structure enabled and controlled by the first enable signal EN1 in the first and second embodiments, if the erased memory cells are far more than the programmed memory cells, that is, “1” is far more than 0, because the delay is too large, the sensitivity will be greatly reduced, and the oscillation frequency Freq of the N oscillator ring will remain almost unchanged. Therefore, the accuracy of checking the SA0 (solid 0 fault) with the N oscillator ring enabled and controlled by the first enable signal EN1 needs to be improved.

The Flash memory test circuit of the third embodiment, the N oscillator ring clamped and controlled by the fifth NMOS transistor M5, the P oscillator ring controlled by the sixth PMOS transistor M6, and the sensing circuit module together constitute the architecture of FIG. 1 The double ring cell in . Among them, the design of N oscillator ring has higher sensitivity to SA1 (solid 1 fault); the design of P oscillator ring has higher sensitivity to SA0 (solid 0 fault).

The Flash memory test circuit of the third embodiment introduces a P oscillator ring that is enabled and controlled by the second enable signal EN2, and the oscillation frequency Freq of the P oscillator ring controlled by the sixth PMOS tube M6 is clamped and controlled by the voltage output terminal Vctr. The relationship is completely reversed with that of the fifth NMOS tube M5 clamped to control the N oscillator ring, and the sixth PMOS tube M6 clamped to control the P oscillator ring and the fifth NMOS tube M5 to clamp to control the N oscillator ring to form a double ring (double ring). )), a higher resolution can be obtained.

For Flash memory, All-0 (all 0s), All-1 (all 1s), checkerboard, and inverse checkerboard are the most commonly used test modes. For the Flash memory test circuit of the complementary double-loop test structure of the third embodiment, the following test method that can be implemented can be designed, including the following steps:

S1. First reset the first enable signal EN1 and the second enable signal EN2 to make the N oscillator ring and the P oscillator ring invalid, and use the required test mode to write into each storage unit of the memory to complete the initialization;

S2. Select to enable the corresponding N oscillator ring or/and P oscillator ring according to the desired test mode:

S3. Press and select the word line WL row by row, connect to the frequency detection circuit of the corresponding oscillator ring, and read the oscillation frequency of the corresponding oscillator ring;

S4. If the oscillation frequency of the oscillator ring deviates from the center frequency and exceeds the first set interval, the selected word line WL is defective, and the word line diagnosis mode is entered.

Preferably, in step S1, the test mode is an all-zero test mode, an all-one test mode or a mixed test mode;

All 0 test mode, each storage unit of the memory is written with 0;

All 1 test mode, each storage unit of the memory is written with 1;

Mixed mode, some memory cells are written with 1, and some are written with 0;

Preferably, in step S2, if the required test mode is the all-zero test mode, the first enable signal EN1 is enabled and controlled, and only the N oscillator ring sensitive to the solid-1 fault SA1 is enabled to check whether there is an N oscillator ring. solid 1 fault SA1;

If the required test mode is the all-one test mode, it is enabled and controlled by the second enable signal EN2, and only the P oscillator ring sensitive to the solid 0 fault SA0 is enabled to check whether there is a solid 0 fault SA0;

If the desired test mode is a mixed test mode, enable both the N oscillator ring and the P oscillator ring.

In step S4, the oscillation frequency of the oscillator ring deviates from the center frequency by more than the first set interval, indicating that there is a memory cell failure on the selected word line WL, and then a single-column test can be performed to read the frequency of each column of memory cells, and accurately find the pulley. Low/high overall frequency of faulty memory cells for accurate detection. The specific method is: after entering the word line diagnosis mode, make the column selection NMOS transistor M2 of one of the sensing circuit modules one by one select and connect the corresponding bit line BL, and at the same time make the column selection NMOS transistor M2 of the other F-1 sensing circuit modules. Turn off, read the oscillation frequency of the oscillator ring, if the oscillation frequency of the oscillator ring corresponding to a selected sensing circuit module deviates from the center frequency and exceeds the second set interval, the bit line BL and the corresponding bit line BL of the selected sensing circuit module In step S4, the memory cell corresponding to the defective selected word line WL is faulty.

For step S4, take the 8M PY2101V1 as an example, set a<19>=0, that is, only block0 (4M) is detected first, a total of 2048 word lines WL, 256*8 bit lines BL, using a parallel architecture, the The frequencies of the oscillator loops (phase-locked loops) corresponding to all the columns are drawn and input to the counter. Press and select the word line WL row by row, enable the N oscillator ring and the P oscillator ring, read the frequency from the flip-flop/counter, and find that the frequency read out of a row of word lines WL is too high or too low during the test, Immediately turn on the single-column mode, read the frequency column by column, and find out which column of the faulty memory cell that causes the frequency of the row to deviate from the correct value (that is, scan a row, scan which row has a problem, and then scan the column for this row, and then accurately fault point), and then determine the location of the faulty storage unit. Then set a<19>=1 to detect block1, and the steps are the same as block0.

Embodiment 4

Based on the Flash memory test circuit of the first to third embodiments, the Flash memory test circuit is a built-in self-test circuit integrated in the Flash memory chip.

Preferably, the Flash memory is a NOR Flash memory.

The Flash memory test circuit of the fourth embodiment is integrated in the Flash memory chip, and by optimizing the data latch circuit, the area of the Flash memory with the built-in self-test circuit is reduced as much as possible.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the present invention. within the scope of protection.

Claims (12)

1. a Flash memory test circuit, is characterized in that, it comprises K sensor circuit modules, an N oscillator ring, and K is a positive integer; The sensing circuit module includes a pre-charged PMOS transistor M1 and a column selection NMOS transistor M2; The source terminal of the precharged PMOS transistor M1 is connected to the working voltage, and the drain terminal is connected to the drain terminal of the column selection NMOS transistor M2 as a control voltage output terminal Vctr, and its gate terminal is used to receive the precharge control signal Vpre_charge; Described column selection NMOS tube M2, its gate terminal is used for connecting the selection signal Vselect, and its source terminal is connected to the bit line BL of Flash memory; The N oscillator ring includes a third PMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, 2n inverters, and a NAND gate, where n is a positive integer; The source terminal of the third PMOS transistor M3 is connected to the working voltage, and the drain terminal is connected to the drain terminal of the fourth NMOS transistor M4; The drain terminal of the fifth NMOS transistor M5 is connected to the source terminal of the fourth NMOS transistor M4, the gate terminal is connected to the control voltage output terminal Vctr, and the source terminal is grounded; The 2n inverters are connected in series, the input terminal is connected to the drain terminal of the third PMOS transistor M3, and the output terminal is connected to an input terminal of the NAND gate; The other input end of the NAND gate is used to connect the first enable signal EN1; The output terminal of the NAND gate is connected to the gate terminals of the third PMOS transistor M3 and the fourth NMOS transistor M4. 2. Flash memory test circuit according to claim 1, is characterized in that, There are F column bit lines in the same page of the Flash memory, and F is a positive integer less than K; The source terminals of the column selection NMOS transistors M2 of the F sensing circuit modules are respectively connected to the F column bit lines BL of the same page of the Flash memory. 3. Flash memory test circuit according to claim 1, is characterized in that, An N-ring frequency detection circuit is connected to the output ends of the 2n inverters connected in series in the N-oscillator ring, and is used for detecting the oscillation frequency of the N-oscillator ring. 4. Flash memory test circuit according to claim 3, is characterized in that, The N-loop frequency detection circuit includes a flip-flop and a counter connected in sequence. 5. Flash memory test circuit according to claim 2, is characterized in that, The Flash memory test circuit also includes a P oscillator ring; The P oscillator ring includes a sixth PMOS transistor M6, a seventh PMOS transistor M8, an eighth NMOS transistor M8, 2n inverters, and a NAND gate; The source terminal of the sixth PMOS transistor M6 is connected to the working voltage, the drain terminal is connected to the source terminal of the seventh PMOS transistor M7, and the gate terminal is connected to the control voltage output terminal Vctr; The drain end of the eighth NMOS transistor M8 is connected to the drain end of the seventh PMOS transistor M7, and the source end thereof is grounded; The 2n inverters are connected in series, the input terminal is connected to the drain terminal of the seventh PMOS transistor M7, and the output terminal is connected to an input terminal of the NAND gate; The other input end of the NAND gate is used to connect the second enable signal EN2; The output terminal of the NAND gate is connected to the gate terminals of the seventh PMOS transistor M7 and the eighth NMOS transistor M8. 6. Flash memory test circuit according to claim 5, is characterized in that, A P-ring frequency detection circuit is connected to the output ends of the 2n inverters connected in series in the P-oscillator ring, and is used for detecting the oscillation frequency of the P-oscillator ring. 7. Flash memory test circuit according to claim 6, is characterized in that, The P-ring frequency detection circuit includes a flip-flop and a counter connected in sequence. 8. Flash memory test circuit according to claim 1 or 2, is characterized in that, The Flash memory test circuit is a built-in self-test circuit integrated in the Flash memory chip. 9. Flash memory test circuit according to claim 1 and 2, is characterized in that, The Flash memory is a NOR Flash memory. 10. a method for testing the Flash memory using the described Flash memory test circuit of claim 5, is characterized in that, comprises the following steps: S1. First reset the first enable signal EN1 and the second enable signal EN2 to make the N oscillator ring and the P oscillator ring invalid, and use the required test mode to write into each storage unit of the memory to complete the initialization; S2. Select to enable the corresponding N oscillator ring or/and P oscillator ring according to the desired test mode: S3. Press and select the word line WL row by row, connect to the frequency detection circuit of the corresponding oscillator ring, and read the oscillation frequency of the corresponding oscillator ring; S4. If the oscillation frequency of the oscillator ring deviates from the center frequency and exceeds the first set interval, the selected word line WL is defective, and the word line diagnosis mode is entered. 11. Flash memory testing method according to claim 10, is characterized in that, After entering the word line diagnosis mode, select the column selection NMOS transistor M2 of one of the sensing circuit modules one by one to turn on the corresponding bit line BL, and at the same time turn off the column selection NMOS transistor M2 of the other F-1 sensing circuit modules, read The oscillation frequency of the oscillator ring is obtained. If the oscillation frequency of the oscillator ring corresponding to a selected sensing circuit module deviates from the center frequency and exceeds the second set interval, the bit line BL corresponding to the selected sensing circuit module and step S4 have The memory cell corresponding to the defective selected word line WL is faulty. 12. Flash memory testing method according to claim 10, is characterized in that, In step S1, the test mode is an all-zero test mode, an all-one test mode or a mixed test mode; All 0 test mode, each storage unit of the memory is written with 0; All 1 test mode, each storage unit of the memory is written with 1; Mixed mode, some memory cells are written with 1, and some are written with 0; In step S2, if the required test mode is the all-zero test mode, the first enable signal EN1 is enabled and controlled, and only the N oscillator ring sensitive to the solid 1 fault SA1 is enabled to check whether there is a solid 1 fault SA1. ; If the required test mode is the all-one test mode, it is enabled and controlled by the second enable signal EN2, and only the P oscillator ring sensitive to the solid 0 fault SA0 is enabled to check whether there is a solid 0 fault SA0; If the desired test mode is a mixed test mode, enable both the N oscillator ring and the P oscillator ring.

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