CN114758712A

CN114758712A - Anti-fuse array and programmable nonvolatile memory

Info

Publication number: CN114758712A
Application number: CN202210451536.XA
Authority: CN
Inventors: 陈啸宸
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2022-07-15

Abstract

The disclosure relates to the technical field of integrated circuits, and discloses an antifuse array and a programmable nonvolatile memory. The reading circuit of the anti-fuse array comprises a comparison circuit, a first output control circuit and a latch circuit, wherein the comparison circuit is connected with a second node, a third node and a fourth node and is provided with a first signal end and a second signal end, the first signal end or the second signal end is connected with a data port, and the comparison circuit can respond to a signal of the second node when a clock control signal is in a first level and output a first sensing signal to the third node and a second sensing signal to the fourth node according to a signal comparison result of the first signal end and the second signal end; the first output control circuit is connected with the second node and the grounding terminal and is used for conducting the second node and the grounding terminal when the clock control signal is at the first level; the latch circuit is connected with the third node and the fourth node and can output data stored in the antifuse array according to the first sensing signal and the second sensing signal.

Description

Anti-fuse array and programmable nonvolatile memory

Technical Field

The present disclosure relates to the field of integrated circuits, and more particularly, to an antifuse array and a programmable nonvolatile memory.

Background

One Time Programmable (OTP) memories have a characteristic that a memory state is not affected by power-off, and can be applied to various technical fields. The memory cells of the OTP memory may be divided into fuse-type OTP memory cells (fuse OTP memory cells) and anti-fuse-type OTP memory cells (anti-fuse OTP memory cells). Taking the antifuse-type OTP memory cell as an example, when the antifuse-type OTP memory cell is not programmed (program), it is a high-resistance storage state; conversely, when the antifuse-type OTP memory cell is programmed, it is a low-resistance storage state.

The storage information of the antifuse-type OTP memory cell can be identified and outputted by the antifuse-state read circuit, and in the related art, the read circuit in the antifuse-type OTP memory is liable to cause instability of the power supply voltage.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure provides an antifuse array and a programmable nonvolatile memory.

According to an aspect of the present disclosure, there is provided an antifuse array including a read circuit connected to a data port of the antifuse array, the read circuit including: a comparison circuit connected to a second node, a third node and a fourth node, and having a first signal terminal and a second signal terminal, the first signal terminal or the second signal terminal being connected to the data port, the comparison circuit being configured to output a first sensing signal to the third node and a second sensing signal to the fourth node according to a signal comparison result of the first signal terminal and the second signal terminal in response to a signal of the second node when a clock control signal is at a first level; a first output control circuit connected to a second node and a ground terminal, the first output control circuit being configured to turn on the second node and the ground terminal when the clock control signal is at a first level; a latch circuit connected to the third node and the fourth node, the latch circuit configured to output data stored by the antifuse array according to the first sensing signal and the second sensing signal.

In some embodiments, the comparison circuit comprises: a comparing unit connected to the second node, a fifth node and a sixth node, the comparing unit having the first signal terminal and the second signal terminal, the first signal terminal being connected to the data port, the second signal terminal being configured to receive a preset reference signal, the comparing unit being configured to compare the data signal of the data port with the preset reference signal, and adjust voltage values of the fifth node and the sixth node according to a comparison result in response to a signal of the second node; a signal amplifying unit connected to the fifth node, the sixth node, the third node, the fourth node, and the first node, wherein the signal amplifying unit is configured to amplify a voltage difference between the fifth node and the sixth node, and output the first sensing signal to the third node and the second sensing signal to the fourth node.

In some embodiments, the comparison unit comprises: a first end of the sixth transistor is connected to the fifth node, a second end of the sixth transistor is connected to the second node, and a control end of the sixth transistor receives the preset reference signal; a seventh transistor, wherein a first terminal of the seventh transistor is connected to a sixth node, a second terminal of the seventh transistor is connected to the second node, and a control terminal of the seventh transistor is connected to the data port; the transistor types of the sixth transistor and the seventh transistor are the same.

In some embodiments, the sixth transistor and the seventh transistor are both N-type field effect transistors.

In some embodiments, the signal amplification unit includes: a fourth transistor, a first terminal of which is connected to the third node, a second terminal of which is connected to the fifth node, and a control terminal of which is connected to the fourth node; a fifth transistor, wherein a first terminal of the fifth transistor is connected to the fourth node, a second terminal of the fifth transistor is connected to the sixth node, and a control terminal of the fifth transistor is connected to the third node; a first transistor, a first terminal of which is connected to the first node, a second terminal of which is connected to the third node, and a control terminal of which is connected to the fourth node; a third transistor, wherein a first terminal of the third transistor is connected to the first node, a second terminal of the third transistor is connected to the fourth node, and a control terminal of the third transistor is connected to the third node; the fourth transistor and the fifth transistor are of the same type, and the first transistor and the third transistor are of the same type.

In some embodiments, the fourth transistor and the fifth transistor are N-type field effect transistors; the first transistor and the third transistor are P-type field effect transistors.

In some embodiments, the read circuit further comprises: a second output control circuit connected to a first node, the third node, and the fourth node, the second output control circuit configured to transmit a charging signal of the first node to the third node and the fourth node when the clock control signal is at a second level, wherein the first level of the clock control signal is inverted from the second level.

In some embodiments, the second output control circuit comprises: a tenth transistor, a first terminal of the tenth transistor is connected to the first node, a second terminal of the tenth transistor is connected to the third node, and a control terminal of the tenth transistor receives the clock control signal; a second transistor, a first end of the second transistor is connected to the first node, a second end of the second transistor is connected to the fourth node, and a control end of the second transistor receives the clock control signal; the second transistor and the tenth transistor are of the same type.

In some embodiments, the first output control circuit comprises: a first end of the eighth transistor is connected to the second node, a second end of the eighth transistor is connected to a ground terminal, a control terminal of the eighth transistor receives the clock control signal, and types of the second transistor and the eighth transistor are different.

In some embodiments, the eighth transistor is an N-type fet, and the second and tenth transistors are P-type fets.

In some embodiments, the read circuit further comprises: a level adjustment circuit connecting a fifth node and a sixth node, the level adjustment circuit configured to adjust voltages of the fifth node and the sixth node according to the clock control signal.

In some embodiments, the level adjustment circuit comprises: a ninth transistor, wherein a first end of the ninth transistor is connected to the fifth node, a second end of the ninth transistor is connected to the sixth node, and a control end of the ninth transistor receives the first voltage signal.

In some embodiments, the latch circuit comprises a first nand gate circuit and a second nand gate circuit, wherein a first input terminal of the first nand gate circuit is connected to the third node, and a second input terminal of the first nand gate circuit is connected to an output terminal of the second nand gate circuit; a first input end of the second NAND gate circuit is connected with the fourth node, and a second input end of the second NAND gate circuit is connected with an output end of the first NAND gate circuit; the latch circuit outputs data stored by the antifuse array through an output terminal of the first nand gate circuit or through an output terminal of the second nand gate circuit.

In some embodiments, the clock control signal transitions from the second level to the first level after the data signal is output by the data port.

In some embodiments, further comprising: a precharge circuit provided corresponding to the read circuit, the precharge circuit being connected to a first signal terminal of the comparison circuit, the precharge circuit being configured to precharge the first signal terminal of the comparison circuit before the clock control signal is at the first level.

According to a second aspect of the present disclosure, there is also provided a programmable non-volatile memory comprising the antifuse array according to any of the embodiments of the present disclosure.

In some embodiments, the memory further comprises: a plurality of output circuits, each of the output circuits being connected to the read circuits in a row of the antifuse array and receiving an array select signal, the output circuits being configured to output data read by the read circuits in accordance with the array select signal.

In the antifuse array provided by the disclosure, a comparison circuit in the reading circuit can compare signals of a first signal end and a second signal end, and output a first sensing signal to a third node and a second sensing signal to a fourth node when a clock control signal is at a first level, and a latch can output data stored in the antifuse array according to the first sensing signal and the second sensing signal. The first output control circuit in the reading circuit can conduct the second node and the grounding terminal when the clock control signal is at the first level, because when the clock control signal is at the first level, the second node is conducted with the grounding terminal, and the signals received by the first signal terminal and the second signal terminal of the comparison circuit are different, so that the comparison circuit can output different sensing signals to the third node and the fourth node, and the latch circuit can output the data accessed by the antifuse array according to the sensing signals of the third node and the fourth node. Meanwhile, compared with a conventional reading circuit, when the clock control signal is at the stable first level and the stable second level, the comparison circuit is open to the ground, so that no current is consumed, and only when the clock control signal is at a transition time (namely, a rising edge or a falling edge), the reading circuit provided by the disclosure can reduce the power consumption of the memory.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It should be apparent that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived by those of ordinary skill in the art without inventive effort.

FIG. 1 is a schematic diagram of an antifuse array, according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the read circuit of FIG. 1;

FIG. 3 is a diagram illustrating a read circuit of an antifuse array according to the related art;

FIG. 4 is a schematic diagram of a programmable non-volatile memory according to one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of multiplexing of array select sub-signals according to one embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an output circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of an output circuit according to another embodiment of the present disclosure;

FIG. 8 is a schematic diagram of an output sub-circuit according to one embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a detailed description thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms, such as "upper" and "lower," may be used herein to describe one element of an icon relative to another, such terms are used herein for convenience only, e.g., with reference to the orientation of the example illustrated in the drawings. It will be understood that if the illustrated device is turned upside down, elements described as "upper" will be those that are "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting as to the number of their objects.

Fig. 1 is a schematic structural diagram of an antifuse array according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of a read circuit in fig. 1, as shown in fig. 1 and fig. 2, the antifuse array may include a read circuit 100, the read circuit 100 is connected to a data port of the antifuse array, and the read circuit 100 may include: a comparison circuit 110, a first output control circuit 120, and a latch circuit 130, the comparison circuit 110 being connected to the second node N2, the third node N3, and the fourth node N4, and having a first signal terminal Vminus and a second signal terminal Vplus, the first signal terminal Vminus or the second signal terminal Vplus being connected to the data port, the comparison circuit 110 being configured to output a first sense signal S1 to the third node N3 and a second sense signal S2 to the fourth node N4 in response to a signal of the second node N2 when the clock control signal CLK is at a first level according to a signal comparison result of the first signal terminal Vminus and the second signal terminal Vplus; the first output control circuit 120 is connected to the second node N2 and the ground terminal, and the first output control circuit 120 is configured to turn on the second node N2 and the ground terminal when the clock control signal CLK is at the first level; the latch circuit 130 is connected to the third node N3 and the fourth node N4, and the latch circuit 130 is configured to output Data F _ Data stored by the antifuse array according to the first sensing signal S1 and the second sensing signal S2.

In the antifuse array provided by the present disclosure, the comparison circuit 110 in the read circuit 100 can compare signals of the first signal terminal Vminus and the second signal terminal Vplus, and output the first sensing signal S1 to the third node N3 and the second sensing signal S2 to the fourth node N4 when the clock control signal CLK is at the first level, and the latch can output Data F _ Data stored in the antifuse array according to the first sensing signal S1 and the second sensing signal S2. The first output control circuit 120 in the reading circuit 100 is capable of turning on the second node N2 and the ground terminal when the clock control signal CLK is at the first level, because when the clock control signal CLK is at the first level, the second node N2 is turned on with the ground terminal, and the first signal terminal Vminus and the second signal terminal Vplus of the comparison circuit 110 receive different signals, so that the comparison circuit 110 is capable of outputting different sensing signals to the third node N3 and the fourth node N4, and the latch circuit 130 is capable of outputting the Data F _ Data accessed by the antifuse array according to the sensing signals of the third node N3 and the fourth node N4. Meanwhile, compared with the conventional read circuit, the read circuit 100 provided by the present disclosure opens to ground by the comparison circuit 110 when the clock control signal CLK is at the stable first level and the stable second level, and therefore does not consume current, and only consumes current when the clock control signal CLK is at a transition time (i.e., a rising edge or a falling edge), and therefore, the read circuit 100 provided by the present disclosure can reduce the power consumption of the memory.

As illustrated in fig. 2, in the present exemplary embodiment, the first level may be a high level, that is, the comparison circuit 110 may output the first sensing signal S1 to the third node N3 and output the second sensing signal S2 to the fourth node N4 according to a signal comparison result of the first signal terminal Vminus and the second signal terminal Vplus in response to the signal of the second node N2 when the clock control signal CLK is a high level. The first sensing signal S1 and the second sensing signal S2 may be inverted signals, that is, when the first sensing signal S1 is at a high level, the second sensing signal S2 is at a low level; alternatively, when the first sensing signal S1 is at a low level, the second sensing signal S2 is at a high level.

In the exemplary embodiment, the Data F _ Data stored in the antifuse array is the state Data of the antifuse memory cells in the antifuse array. The state data of the antifuse memory cell includes programmed state data and unprogrammed state data, and the state of the antifuse memory cell can be represented by data "1" when the antifuse memory cell has been programmed, and can be represented by data "0" when the antifuse memory cell is unprogrammed. The read circuit 100 of the antifuse array may read the state Data F _ Data of the antifuse memory cells in the gated antifuse array, and output the read state Data F _ Data of the antifuse memory cells through the output circuit.

In this exemplary embodiment, the comparison circuit 110 has a first signal terminal Vminus and a second signal terminal Vplus, the first signal terminal Vminus can control one branch, the second signal terminal Vplus can control the other branch, and the comparison circuit 110 can control the respective branches to have different states according to a comparison result between a signal of the first signal terminal Vminus and a signal of the second signal terminal Vplus, so as to output corresponding sensing signals to the third node N3 and the fourth node N4. One of two signal terminals of the comparison circuit 110 is connected to the Data port of the antifuse array to receive the Data F _ Data stored in the antifuse array. Illustratively, the first signal terminal Vminus of the comparison circuit 110 may be connected to a data port of the antifuse array, and the second signal terminal Vplus may be used to receive a preset reference signal Vref, so that the comparison circuit 110 may compare the received data signal of the data port with the preset reference signal Vref and output the first sensing signal S1 to the third node N3 and the second sensing signal S2 to the fourth node N4 based on the comparison result. Of course, in other embodiments, the first signal terminal Vminus of the comparing circuit 110 may receive the predetermined reference signal Vref, and the second signal terminal Vminus is connected to the data port of the antifuse array, which is not limited in this disclosure.

In the present exemplary embodiment, the latch circuit 130 in the read circuit 100 is capable of outputting the Data F _ Data stored by the antifuse array according to the first sensing signal S1 and the second sensing signal S2. Illustratively, when the antifuse cell gated in the antifuse array is not programmed, the Data F _ Data stored in the antifuse array is 0, taking as an example that the first signal terminal Vminus of the comparison circuit 110 is connected to the Data port of the antifuse array, the potential of the first signal terminal Vminus is pulled low by the Data F _ Data stored in the antifuse array, so that the potential of the first signal terminal Vminus is lower than the potential of the second signal terminal Vplus, the clock control signal CLK is at a high level, the first output control circuit 120 is turned on to pull the potential of the second node N2 low, the branch controlled by the first signal terminal Vminus of the comparison circuit 110 is connected to the fourth node N4 and the second node N2, the branch controlled by the second signal terminal Vplus is connected to the third node N3 and the second node N2, the potentials of the third node N3 and the fourth node N4 are both pulled low by the second node N2, because the potential of the first signal terminal Vminus is lower than the potential of the second signal terminal Vplus, accordingly, the potential of the fourth node N4 is slower than the potential of the third node N3, that is, the potential of the fourth node N4 is higher than the potential of the third node N3, so that the comparison circuit 110 outputs the first sensing signal S1 at a low level to the third node N3 and outputs the second sensing signal S2 at a high level to the fourth node N4, and the latch circuit 130 outputs a low-level signal through the inverting output terminal according to the two sensing signals and latches the Data F _ Data stored in the antifuse array, thereby enabling the latch circuit 130 to latch the Data F _ Data stored in the antifuse array.

The read circuit 100 of the antifuse array of the present disclosure is further described with reference to the drawings.

As shown in fig. 2, in the present exemplary embodiment, the comparison circuit 110 may include a comparison unit 111 and a signal amplification unit 112, the comparison unit 111 is connected to the second node N2, the fifth node N5 and the sixth node N6, the comparison unit 111 has a first signal terminal Vminus connectable to the data port and a second signal terminal Vplus usable to receive a preset reference signal, the comparison unit 111 may be operable to compare the data signal of the data port with a preset reference signal Vref and adjust voltage values of the fifth node N5 and the sixth node N6 according to a comparison result in response to a signal of the second node N2; the signal amplifying unit 112 is connected to the fifth node N5, the sixth node N6, the third node N3, the fourth node N4 and the first node N1, and the signal amplifying unit 112 is configured to amplify a voltage difference between the fifth node N5 and the sixth node N6, and output a first sensing signal S1 to the third node N3 and a second sensing signal S2 to the fourth node N4. For example, the comparing unit 111 may control two branches, one branch is connected to the fifth node N5 and the second node N2, the other branch is connected to the sixth node N6 and the second node N2, and the comparing unit 111 may compare the received data signal of the data port with the received reference signal Vref, and then correspondingly adjust states of the two branches, so as to adjust voltage values of the fifth node N5 and the sixth node N6. For example, when the second node N2 is at a low level, if the data signal is higher than the predetermined reference signal Vref, the comparison unit 111 can control one branch to rapidly pull down the voltage of the fifth node N5 after comparison, so as to adjust the voltage value of the fifth node N5 to be lower than the voltage value of the sixth node N6. The signal amplifying unit 112 can amplify a voltage difference between the sixth node N6 and the fifth node N5, and control the voltage value of the fourth node N4 to be greater than that of the third node N3 and form positive feedback such that the voltage value of the fourth node N4 is greater than that of the third node N3 more and more, thereby finally outputting the first sensing signal S1 of a low level to the third node N3 and outputting the second sensing signal S2 of a high level to the fourth node N4.

As shown in fig. 2, in the present exemplary embodiment, the comparison unit 111 and the signal amplification unit 112 may be implemented by transistors. For example, the comparing unit 111 may include a sixth transistor M6 and a seventh transistor M7, a first terminal of the sixth transistor M6 may be connected to the fifth node N5, a second terminal of the sixth transistor M6 may be connected to the second node N2, and a control terminal of the sixth transistor M6 may be configured to receive a preset reference signal Vref to receive the data signal. A first terminal of the seventh transistor M7 may be connected to the sixth node N6, a second terminal of the seventh transistor M7 may be connected to the second node N2, and a control terminal of the seventh transistor M7 may be connected to the data port; and the transistor types of the sixth transistor M6 and the seventh transistor M7 are the same. The signal amplifying unit 112 may include a fourth transistor M4, a fifth transistor M5, a first transistor M1, and a third transistor M3, a first terminal of the fourth transistor M4 may be connected to the third node N3, a second terminal of the fourth transistor M4 may be connected to the fifth node N5, and a control terminal of the fourth transistor M4 may be connected to the fourth node N4; a first terminal of the fifth transistor M5 may be connected to the fourth node N4, a second terminal of the fifth transistor M5 may be connected to the sixth node N6, and a control terminal of the fifth transistor M5 may be connected to the third node N3; a first terminal of the first transistor M1 may be connected to the first node N1, a second terminal of the first transistor M1 may be connected to the third node N3, and a control terminal of the first transistor M1 may be connected to the fourth node N4; a first terminal of the third transistor M3 may be connected to the first node N1, a second terminal of the third transistor M3 may be connected to the fourth node N4, and a control terminal of the third transistor M3 may be connected to the third node N3; and the fourth transistor M4 is of the same type as the fifth transistor M5 and the first transistor M1 is of the same type as the third transistor M3.

For example, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may all be N-type field effect transistors, the first transistor M1 and the third transistor M3 may all be P-type field effect transistors, when the second node N2 is at a low level, if a data signal level of the data port is higher than a reference signal level, the opening degree of the sixth transistor M6 is smaller than that of the seventh transistor M7, and because the second node N2 is at a low level, the sixth node N6 is pulled down faster than the fifth node N5 so that a voltage value of the sixth node N6 is smaller than that of the fifth node N5. When the fourth transistor M4 and the fifth transistor M5 are turned on to the same degree, the potential of the first terminal of the fifth transistor M5 is lower than the potential of the first terminal of the fourth transistor M4, that is, the potential of the fourth node N4 is lower than the potential of the third node N3, and since the control terminal of the third transistor M3 is connected to the third node N3, the control terminal of the first transistor M1 is connected to the fourth node N4, and the first transistor M1 and the third transistor M3 are both P-type field effect transistors, the turning on degree of the third transistor M3 is smaller than the turning on degree of the first transistor M1, and since the first terminal of the first transistor M1 and the first terminal of the third transistor M3 are both connected to the first voltage signal of high level, the voltage difference between the third node N3 and the fourth node N4 is larger, that the voltage of the third node N3 is larger than the voltage of the fourth node N4, the fourth transistor M4 is further smaller and smaller, the fifth transistor M5 is turned on more and more until the third transistor M3 and the fourth transistor M4 are completely turned off, the fourth node N4 is pulled down to the low level of the second voltage signal VSS, and the third node N3 is pulled up to the high level of the first voltage signal VDD. Finally, the signal amplification unit 112 performs feedback amplification on the voltage difference between the fifth node N5 and the sixth node N6 and outputs a correct sensing signal through the third node N3 and the fourth node N4. In contrast, when the second node N2 is at a low level, if the data signal level of the data port is lower than the reference signal level, the first transistor M1 and the fifth transistor M5 are finally turned off completely, the third node N3 is pulled down to the low level of the second voltage signal VSS, and the fourth node N4 is pulled up to the high level of the first voltage signal VDD. It should be understood that, in other embodiments, the comparing unit 111 and the signal amplifying unit 112 may also have other circuit structures, and the disclosure is not limited thereto.

As shown in fig. 2, in the present exemplary embodiment, the latch circuit 130 may include a first nand gate 131 and a second nand gate 132, wherein a first input terminal of the first nand gate 131 is connected to the third node N3, and a second input terminal of the first nand gate 131 is connected to an output terminal of the second nand gate 132; a first input terminal of second nand gate circuit 132 is connected to fourth node N4, and a second input terminal of second nand gate circuit 132 is connected to an output terminal of first nand gate circuit 131; the latch circuit 130 may output the Data F _ Data stored by the antifuse array through the output terminal of the first nand gate circuit 131 or through the output terminal of the second nand gate circuit 132. Illustratively, when both the third node N3 and the fourth node N4 are high (the comparison circuit 110 is not enabled), both the first input SB of the first nand gate 131 and the first input RB of the second nand gate 132 of the latch circuit 130 are high signals, and at this time, the output signal of the first nand gate 131 depends on the output signal of the second nand gate 132 at the previous time, and the output signal of the second nand gate depends on the output signal of the first nand gate 131 at the previous time. Taking the example that the reading circuit 100 outputs the Data F _ Data stored in the antifuse array through the output terminal of the second nand gate of the latch circuit 130, at this time, if the first nand gate 131 outputs the low level signal at the previous time, it is obvious that the second nand gate outputs the high level signal at the previous time, one input terminal of the second nand gate 132 acquires the high level signal, the other input terminal acquires the low level signal, and the second nand gate 132 outputs the high level signal at this time, which is the same as the output signal at the previous time, and maintains the state of the output signal at the previous time. If first nand gate 131 outputs a high level signal at the previous time, it is obvious that second nand gate 132 outputs a low level signal at the previous time, both input terminals of second nand gate 132 acquire a high level signal, and second nand gate 132 outputs a low level signal at this time, and the state of the data signal at the previous time is maintained.

And when the comparison circuit 110 is enabled, one of the third node N3 and the fourth node N4 is a high level signal, and the other is a low level signal, taking the third node N3 as a high-level signal, the fourth node N4 as a low-level signal, and the reading circuit 100 outputs the Data F _ Data stored in the antifuse array through the second nand gate 132 of the latch circuit 130, as can be seen from the above analysis, the signal at the first signal terminal Vminus of the comparison circuit 110 is higher than the signal at the second signal terminal Vplus, that is, the antifuse cells gated in the antifuse array are programmed, the Data F _ Data stored in the antifuse array received by the first signal terminal Vminus of the comparison circuit 110 is at a high level, and at this time, the first input RB of the second nand gate 132 of the latch circuit 130 is a low level signal, the second nand gate circuit 132 outputs a high level signal to output the Data F _ Data stored in the antifuse array. Of course, in other embodiments, the latch circuit 130 may have other circuit structures, and the disclosure is not limited thereto.

As shown in fig. 2, in the present exemplary embodiment, the reading circuit 100 may further include a second output control circuit 140, the second output control circuit 140 is connected to the first node N1, the third node N3 and the fourth node N4, and the second output control circuit 140 may be configured to transmit the charging signal of the first node N1 to the third node N3 and the fourth node N4 when the clock control signal CLK is at the second level. The first level of the clock control signal CLK is opposite to the second level, and specifically, the first level may be a high level and the second level may be a low level. The first node N1 may receive the first voltage signal VDD, when the second output control circuit 140 is at the second level, the second output control circuit 140 is turned on, and transmits the high-level first voltage signal VDD of the first node N1 to the third node N3 and the fourth node N4, so that the third node N3 and the fourth node N4 are both at the high level, that is, both input ends of the latch circuit 130 acquire the high-level signal, and the latch circuit 130 holds the Data signal of the antifuse array acquired at the previous time, thereby implementing the function of locking the Data F _ Data.

As shown in fig. 2, in the present exemplary embodiment, both the first output control circuit 120 and the second output control circuit 140 may be implemented by transistors, and the types of transistors in the first output control circuit 120 and the second output control circuit 140 are different. For example, the first output control circuit 120 may include an eighth transistor M8, the second output control circuit 140 may include a second transistor M2 and a tenth transistor M10, a first terminal of the eighth transistor M8 may be connected to the second node N2, a second terminal of the eighth transistor M8 may be connected to a ground terminal, and a control terminal of the eighth transistor M8 may be configured to receive the clock control signal CLK. A first terminal of the tenth transistor M10 may be connected to the first node N1, a second terminal of the tenth transistor M10 may be connected to the third node N3, and a control terminal of the tenth transistor M10 may be configured to receive the clock control signal CLK; a first terminal of the second transistor M2 may be connected to the first node N1, a second terminal of the second transistor M2 may be connected to the fourth node N4, and a control terminal of the second transistor M2 may be configured to receive the clock control signal CLK. Among them, the type of the second transistor M2 is the same as that of the tenth transistor M10, and the type of the eighth transistor M8 is different from that of the second transistor M2 and the tenth transistor M10. For example, the eighth transistor M8 may be an N-type field effect transistor, and the second transistor M2 and the tenth transistor M10 may be P-type field effect transistors. When the clock control signal CLK is at a low level, the eighth transistor M8 is turned off, so that the sensing circuit has no ground path, the second transistor M2 and the tenth transistor M10 are turned on, and the first voltage signal VDD at a high level at the first node N1 is transmitted to the third node N3 and the fourth node N4, so that both input terminals of the latch circuit 130 acquire a high level signal, and the latch circuit 130 maintains the data signal of the antifuse array latched at the previous time. It is understood that, in other embodiments, the first output control circuit 120 and the second output control circuit 140 may have other circuit configurations, and based on other circuit configurations, the second output control circuit 140 may transmit the charging signal of the first node N1 to the third node N3 and the fourth node N4 when the clock control signal CLK is at the second level, and the first output control circuit 120 may turn on the second node N2 and the ground when the clock control signal CLK is at the first level, which is not limited by the disclosure.

As shown in fig. 2, in the present exemplary embodiment, the reading circuit 100 may further include a level adjustment circuit 113, the level adjustment circuit 113 may connect the fifth node N5 and the sixth node N6, and the level adjustment circuit 113 may adjust the voltages of the fifth node N5 and the sixth node N6 according to the clock control signal CLK. The level adjustment circuit 113 may be implemented by a transistor. For example, the level adjustment circuit 113 may include a ninth transistor M9, a first terminal of the ninth transistor M9 may be connected to the fifth node N5, a second terminal of the ninth transistor M9 may be connected to the sixth node N6, and a control terminal of the ninth transistor M9 may be configured to receive the first voltage signal VDD. Wherein the ninth transistor M9 can adjust the voltages of the fifth node N5 and the sixth node N6 when the clock signal CLK goes down from high level to low level, specifically, when the clock signal CLK goes high level, each node of the reading circuit 100 reaches a stable state due to a rising edge, taking the example that the signal level of the first signal terminal Vminus of the comparison circuit 110 is higher than that of the second signal terminal Vplus, in the stable state, the fifth node N5 is at an intermediate level, the sixth node N6 is at low level, when the clock signal CLK goes low level, the second transistor M2 and the tenth transistor M10 are turned on to charge each node of the reading circuit 100, and since the potentials of the first terminal and the second terminal of the ninth transistor M9 are different, the opening degrees of the fourth transistor M4 and the fifth transistor M5 are different, so that the charging speeds of the two terminals of the ninth transistor M9 are different, the ninth transistor M9 can balance the charging speed of both ends, so that when the next clock control signal CLK changes from low level to high level, the levels of both ends of the ninth transistor M9, i.e., the fifth node N5 and the sixth node N6, are substantially the same, and the voltage adjustment of the fifth node N5 and the sixth node N6 is completed. Of course, in other embodiments, the level adjustment circuit 113 may have other circuit structures, and the level adjustment circuit 113 may be capable of adjusting the voltages of the fifth node N5 and the sixth node N6 according to the clock control signal CLK based on other circuit structures.

It should be noted that, the reading circuit 100 of the antifuse array provided in the present disclosure may have lower current power consumption, may save the power consumption of the antifuse array, may greatly reduce the load of the power supply, and ensure that the power supply stably outputs the power supply signal. The current consumption of the read circuit 100 will be described by way of example with reference to the circuit configuration shown in fig. 2.

As shown in fig. 2, in the present exemplary embodiment, the reading circuit 100 consumes current only when the clock control signal CLK makes a transition (i.e., a rising edge or a falling edge), and has only a leakage current when the clock control signal CLK is at a stable low level or a stable high level. Specifically, when the clock control signal CLK is at a low level, since the eighth transistor M8 is turned off, the path from the power supply to the ground of the read circuit 100 is disconnected, and there is only a leakage current of the transistor in the read circuit 100, so that the power consumption of the read circuit 100 can be greatly reduced. When the clock control signal CLK is at a high level, the second transistor M2 and the tenth transistor M10 are turned off, and from the above analysis, when the clock control signal CLK reaches a stable high level, the third transistor M3 and the fourth transistor M4 in the comparison circuit 110 are turned off (or the first transistor M1 and the fifth transistor M5 are turned off, depending on the signal comparison result of the first signal terminal Vminus and the second signal terminal Vplus), so that two paths from the power supply to the ground are disconnected, and thus, when the clock control signal CLK is at a stable high level, the power supply is not passed to the ground, and therefore, the overall power consumption of the reading circuit 100 can be saved as well.

Fig. 3 is a schematic diagram of a read circuit of an antifuse array in the related art, in the antifuse array shown in fig. 3, the read circuit 100 is composed of comparators and latches, and usually, the power consumption of a single comparator is about 50 μ a, and if all comparators in the antifuse array are enabled simultaneously, the current consumed by the antifuse array of 36 columns × 16 rows is about 50uA × 16 × 36 × 2 ═ 58mA, which will impose a great burden on the power supply, and the excessive current may cause instability of the power supply voltage, and even cause the whole circuit to fail to operate normally.

In the reading circuit provided by the exemplary embodiment, when the clock control signal CLK is at a low level, the average current consumed is 20 to 33nA, which is multiplied by the number of the reading circuits 100 in the antifuse array, and the total current consumed is about 23.04 to 38.02 uA; when the clock control signal CLK is high, 185nA of average current is consumed, multiplied by the number of read circuits 100 in the antifuse array, and the total current consumed is about 213.12 uA. It can be seen that the current consumed by the read circuit 100 of the antifuse array provided by the present disclosure is much smaller than the current of 58mA consumed by the conventional read circuit shown in fig. 3, so that the power consumption of the antifuse array can be greatly saved, the load of the power supply can be greatly reduced, and the power supply can be ensured to stably output the power supply signal.

In addition, the area occupied by the read circuit in the circuit board provided by the exemplary embodiment is smaller than the area occupied by the read circuit shown in fig. 3 by about 3%, which is beneficial to optimizing the size of the antifuse array and the memory formed by the antifuse array, and improving the applicability of the antifuse array and the memory formed in particular.

As shown in fig. 1, in the exemplary embodiment, the antifuse array may further include a program control circuit 400, and the program control circuit 400 may program a selected antifuse memory cell in response to a program control signal Zadd. Illustratively, the program control circuit 400 may include a twelfth transistor M12, a control terminal of the twelfth transistor M12 receiving the program control signal Zadd, a first terminal of the twelfth transistor M12 being connected to the data port of the antifuse array (i.e., the first signal terminal Vminus of the comparison circuit 110), and a second terminal receiving the first setting voltage VSS. The twelfth transistor M12 may be an N-type field effect transistor, and the first setting voltage VSS may be a low-level voltage signal. When the programming control signal Zadd is at a high level, the twelfth transistor M12 is turned on, the first set voltage VSS at the second terminal of the twelfth transistor M12 is transmitted to one terminal of the turned-on antifuse memory cell, a high voltage is applied to the gate of the antifuse memory cell by Fsbln, the gate oxide dielectric of the antifuse memory cell is broken down, the antifuse memory cell is programmed, and accordingly, the antifuse memory cell assumes a low resistance state. It should be understood that, in other embodiments, the program control circuit 400 may also have other circuit structures, and the disclosure is not limited thereto.

As shown in fig. 1, in the exemplary embodiment, the antifuse array may further include a precharge circuit 300, the precharge circuit 300 may be disposed corresponding to the read circuit 100, the precharge circuit 300 may be connected to the first signal terminal Vminus of the comparison circuit 110, and the precharge circuit 300 may precharge the first signal terminal Vminus of the comparison circuit 110 before the clock control signal CLK becomes the first level. Specifically, the precharge circuit 300 is disposed in one-to-one correspondence with the antifuse array, the precharge circuit 300 is connected to the first signal terminal Vminus of the comparison circuit 110, and the precharge circuit 300 may precharge the first signal terminal Vminus of the comparison circuit 110 before the comparison circuit 110 is enabled, and charge the first signal terminal Vminus to a high level. Illustratively, the precharge circuit 300 may include an eleventh transistor M11, a control terminal of the eleventh transistor M11 receiving the precharge control signal Pre-charge, a first terminal connected to the precharge signal VDD, and a second terminal connected to the first signal terminal Vminus of the comparison circuit 110. The eleventh transistor M11 may be a P-type field effect transistor, and the precharge signal VDD may be a high level signal. When the precharge control signal Pre-charge is a low level signal, the eleventh transistor M11 is turned on, the precharge signal VDD having a first terminal at a high level is transmitted to the first signal terminal Vminus of the comparison circuit 110, and the first signal terminal Vminus of the comparison circuit 110 is charged to a high level. It is understood that in other embodiments, when the second signal terminal Vplus of the comparison circuit 100 is connected to the data port of the antifuse array, the pre-charge circuit 300 is connected to the second signal terminal Vplus of the comparison circuit 100. In addition, in other embodiments, the precharge circuit 300 may have other circuit structures, which is not limited in this disclosure.

In the exemplary embodiment, the clock control signal CLK may be controlled to change from the second level to the first level (from the low level to the high level) after the Data signal is output from the Data port for a certain period of time, so that when the reading circuit 100 reads Data F _ Data, the Data signal of the Data port is already in a stable state, and the comparison circuit 110 can be ensured to accurately sense the Data stored in the antifuse array, thereby outputting a correct first sensing signal S1 to the third node N3 and outputting a stable second sensing signal S2 to the fourth node N4. In some embodiments of the present disclosure, the clock control signal CLK may be delayed by 10ns to 100ns (e.g., 10ns, 20ns, 30ns, 40ns, 50ns, 60ns, 70ns, 80ns, 90ns, 100ns) from a low level signal to a high level signal after the precharge control signal Pre-charge is ended.

Fig. 4 is a schematic structural diagram of a programmable nonvolatile memory according to an embodiment of the present disclosure, and as shown in fig. 4, the present disclosure further provides a programmable nonvolatile memory which may include an antifuse array according to any of the above embodiments of the present disclosure. It can be understood that fig. 1 is equivalent to the schematic structure of one antifuse array in fig. 5.

In the exemplary embodiment, the adjacent antifuse arrays 100 may multiplex one array selection sub-signal RdSel _ n, that is, one array selection sub-signal RdSel _ n may turn on the plurality of columns of the antifuse arrays 100. Illustratively, fig. 5 is a schematic diagram of multiplexing array selection sub-signals according to an embodiment of the present disclosure, and as shown in fig. 5, the memory may include M columns of antifuse arrays 100, the antifuse array 100 located in the M-th column (Segment _ M) and the antifuse array 100 located in the (M +1) -th column (Segment _ M +1) multiplex the same array selection sub-signal RdSel _ n, and the antifuse array 100 located in the M-th column (Segment _ M) and the antifuse array 100 located in the (M +2) -th column (Segment _ M +2) use two different array selection sub-signals RdSel _ n and RdSel _ n +1, only one row of the array selection sub-signal RdSel _ n is an active signal at the same time, and M is an odd number smaller than M. The array select sub-signal RdSel _ n is an active signal, i.e., the array select sub-signal RdSel _ n can gate a set of antifuse arrays. That is, starting from the first column, two adjacent columns of antifuse arrays 100 are grouped, and the same array selection sub-signal RdSel _ n turns on one group of antifuse arrays 100. For example, if the memory includes 36 columns of antifuse arrays 100, then the 1 st (Segment _1) antifuse array 100 may multiplex the same array select sub-signal rdsegment _1 with the 2 nd (Segment _2) antifuse array 100, the 3 rd (Segment _3) antifuse array 100 and the 4 th (Segment _4) antifuse array 100 may multiplex the same array select sub-signal rdsegment _2, the 5 th (Segment _5) antifuse array 100 may multiplex the same array select sub-signal rdsegment _3 with the 6 th (Segment _6) antifuse array 100, and so on, the 35 th (Segment _35) antifuse array 100 may multiplex the same array select sub-signal rdsegment _18 with the 36 th (Segment _36) antifuse array 100. Of course, in other embodiments, the array selection sub-signal RdSel _ n may also have other multiplexing manners, for example, three antifuse arrays 100 multiplex the same array selection sub-signal RdSel _ n for a group, that is, the antifuse arrays 100 in the 1 st column (Segment _1), the 2 nd column (Segment _2) and the 3 rd column (Segment _3) multiplex the same array selection sub-signal RdSel _1, the 4 th column (Segment _4), the 5 th column (Segment _5) and the 6 th column (Segment _6) and the same array selection sub-signal RdSel _2, and so on, and the disclosure is not limited thereto.

As shown in fig. 1 and 4, in the present exemplary embodiment, the memory may further include a plurality of output circuits 20, each output circuit 20 is connected to the read circuit 100 in one row of the antifuse arrays and receives the array selection signal RdSel _ n, and one output circuit 20 is connected to the read circuit 100 in one row of the antifuse arrays and outputs the Data F _ Data read by one of the antifuse arrays that is gated in the row. In this way, only when the array selection sub-signal RdSel _ n of one antifuse array is at a high level, the antifuse memory cell state Data F _ Data read by the column of the antifuse array is output. Output circuit 20 may include one or more output sub-circuits. Fig. 6 is a schematic structural diagram of an output circuit according to an embodiment of the disclosure, and as shown in fig. 6, the output circuit 20 includes an output sub-circuit 201, in this case, each antifuse array in the same row is connected to the output sub-circuit 201, and the output sub-circuit 201 outputs the Data F _ Data read by the reading circuit 100 according to an array selection signal RdSel _ n.

Fig. 7 is a schematic diagram of an output circuit according to another embodiment of the disclosure, and as shown in fig. 7, the output circuit 20 may include two output sub-circuits, for example, a first output sub-circuit 201 and a second output sub-circuit 202, which is equivalent to the structure that the read circuits 100 of the anti-fuse arrays in odd columns are connected to the first output sub-circuit 201, and the read circuits 100 of the anti-fuse arrays in even columns are connected to the second output sub-circuit 202. If the selected antifuse memory cell is located in the antifuse array in even columns, the Data F _ Data of the antifuse memory cell is output only through the second output sub-circuit 202 without passing through the first output sub-circuit 201, and similarly, the Data F _ Data of the antifuse memory cells located in the antifuse array in odd columns is output only through the first output sub-circuit 201 without passing through the second output sub-circuit 202, so when one column of the antifuse array in even columns and one column of the antifuse array in odd columns are simultaneously selected, the Data F _ Data of the antifuse array in odd columns can be output through the first output sub-circuit 201, and the Data F _ Data of the antifuse array in even columns can be output through the second output sub-circuit 202. Obviously, the output circuit 20 can save the time for transferring the Data F _ Data, improve the speed for transferring the Data F _ Data, and reduce the attenuation of the Data F _ Data during the transfer.

It can be understood that when the output circuit 20 includes only one output sub-circuit 201, only one bit of Data F _ Data can be output by one output circuit 20 at a time, and if the output circuit 20 includes two output sub-circuits 201, two bits of Data F _ Data can be output by the output circuit 20 at a time, and it can be seen that the output efficiency of the Data F _ Data can be improved by providing two output sub-circuits 201.

Of course, in other embodiments, the output circuit 20 may further include 3 or more output sub-circuits, which may be specifically set according to the data transmission speed, the data storage manner, and the data amount. For example, the output circuit 20 may include 3 output sub-circuits 201, wherein the read circuit 100 of the 1 st column (Segment _1) antifuse array, the read circuit 100 of the 4 th column (Segment _4) antifuse array, and the read circuit 100 … … of the 7 th column (Segment _7) antifuse array are connected to the first output sub-circuit 201, the read circuit 100 of the 2 nd column (Segment _2) antifuse array, the read circuit 100 of the 5 th column (Segment _5) antifuse array, and the read circuit 100 … … of the 8 th column antifuse array are connected to the second output sub-circuit 202, the read circuit 100 of the 3 rd column (Segment _3) antifuse array, the read circuit 100 of the 6 th column (Segment _6) antifuse array, and the read circuit 100 … … of the 9 th column antifuse array are connected to the third output sub-circuit 203, and so on. Similarly, the output circuit 20 includes a plurality of output sub-circuits, which can improve the data output efficiency of the antifuse array.

Fig. 8 is a schematic structural diagram of an output sub-circuit according to an embodiment of the disclosure, and as shown in fig. 8, the output sub-circuit may include a transmission circuit 2012 and a plurality of selection circuits 2011, each selection circuit 2011 is connected to one reading circuit 100, and each selection circuit 2011 can output Data F _ Data read by the reading circuit 100 in response to one array selection sub-signal RdSel _ n; the transfer circuit 2012 is connected between the output terminals of the plurality of selection circuits 2011 and the Data port, and the transfer circuit 2012 can transfer the Data F _ Data output by the selection circuits 2011 to the Data port. Illustratively, the selection circuit 2011 may include an and circuit 21, and the transmission circuit 2012 may include a plurality of cascaded or gates 22, where one input terminal of the and circuit 21 is connected to the output terminal of the reading circuit 100, another input terminal thereof receives the array selection sub-signal RdSel _ n, and an output terminal thereof is connected to another input terminal of the or gate 22. A first input terminal of each of the or gate circuits 22 is connected to an output terminal of the corresponding selection circuit 2011, a second input terminal of the first or gate circuit 22 is grounded, an output terminal of the last or gate circuit 22 is connected to the data port, and an output terminal of the previous or gate circuit 22 is connected to a second input terminal of the next or gate circuit 22.

Illustratively, the memory includes a 36 column × 16 row antifuse array, the output circuit 20 has the circuit structure shown in fig. 5, taking one row of the antifuse array as an example, the or gate 22 connected to the read circuit 100 of the 1 st (Segment _1) antifuse array is the first stage of the transfer circuit 2012 in the first output sub-circuit 201, the or gate 22 connected to the read circuit 100 of the 3 rd (Segment _3) antifuse array is the second stage of the transfer circuit 2012, and so on. If the 1 st column (Segment _1) antifuse array is gated and the stored Data F _ Data is at a high level (i.e., the selected antifuse memory cell is programmed), the first selection circuit 2011 in the first output sub-circuit 201 outputs a high level, the other selection circuits 2011 all output a low level, each stage of the transmission circuit 2012 outputs a high level, the first output sub-circuit 201 finally outputs a high level signal, and the programming state of the gated antifuse memory cell in the 1 st column (Segment _1) antifuse array is output. Alternatively, if the 1 st column (Segment _1) antifuse array is gated and the stored Data F _ Data is at a low level (i.e., the selected antifuse memory cell is not programmed), the first-stage selection circuit 2011 in the first output sub-circuit 201 outputs a low level, the other selection circuits 2011 also output a low level, each stage of the transmission circuit 2012 outputs a low level, the first output sub-circuit 201 finally outputs a low level signal, and the unprogrammed state of the gated antifuse memory cell in the 1 st column (Segment _1) antifuse array is output. Alternatively, if the 3 rd column (Segment _3) antifuse array is gated and the stored Data F _ Data is at a high level (that is, the selected antifuse memory cell is programmed), the second-stage selection circuit 2011 in the first output sub-circuit 201 outputs a high level, the other selection circuits 2011 all output a low level, the first stage of the transfer circuit 2012 outputs a low level, the second to last stages of the transfer circuit 2012 all output a high level, the first output sub-circuit 201 finally outputs a high-level signal, and the program state of the gated antifuse memory cell in the 3 rd column (Segment _3) antifuse array is output.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. An antifuse array, comprising a read circuit coupled to a data port of the antifuse array, the read circuit comprising:

a comparison circuit connected to a second node, a third node and a fourth node, and having a first signal terminal and a second signal terminal, the first signal terminal or the second signal terminal being connected to the data port, the comparison circuit being configured to output a first sensing signal to the third node and a second sensing signal to the fourth node according to a signal comparison result of the first signal terminal and the second signal terminal in response to a signal of the second node when a clock control signal is at a first level;

A first output control circuit connected to a second node and a ground terminal, the first output control circuit being configured to turn on the second node and the ground terminal when the clock control signal is at a first level;

a latch circuit connected to the third node and the fourth node, the latch circuit configured to output data stored by the antifuse array according to the first sensing signal and the second sensing signal.

2. The antifuse array of claim 1, wherein the comparison circuit comprises:

a comparing unit, connected to the second node, a fifth node and a sixth node, having the first signal terminal and the second signal terminal, where the first signal terminal is connected to the data port, the second signal terminal is used for receiving a preset reference signal, and the comparing unit is configured to compare the data signal of the data port with the preset reference signal, and adjust voltage values of the fifth node and the sixth node according to a comparison result in response to a signal of the second node;

a signal amplifying unit connected to the fifth node, the sixth node, the third node, the fourth node, and the first node, wherein the signal amplifying unit is configured to amplify a voltage difference between the fifth node and the sixth node, and output the first sensing signal to the third node and the second sensing signal to the fourth node.

3. The antifuse array of claim 2, wherein the comparison unit comprises:

a first end of the sixth transistor is connected to the fifth node, a second end of the sixth transistor is connected to the second node, and a control end of the sixth transistor receives the preset reference signal;

a seventh transistor, wherein a first terminal of the seventh transistor is connected to a sixth node, a second terminal of the seventh transistor is connected to the second node, and a control terminal of the seventh transistor is connected to the data port;

the transistor types of the sixth transistor and the seventh transistor are the same.

4. The antifuse array of claim 3, wherein the sixth transistor and the seventh transistor are both NFETs.

5. The antifuse array of claim 2, wherein the signal amplification unit comprises:

a fourth transistor, a first terminal of which is connected to the third node, a second terminal of which is connected to the fifth node, and a control terminal of which is connected to the fourth node;

a fifth transistor, a first terminal of which is connected to the fourth node, a second terminal of which is connected to the sixth node, and a control terminal of which is connected to the third node;

A first transistor, a first terminal of which is connected to the first node, a second terminal of which is connected to the third node, and a control terminal of which is connected to the fourth node;

a third transistor, a first end of the third transistor being connected to the first node, a second end of the third transistor being connected to the fourth node, and a control end of the third transistor being connected to the third node;

the fourth transistor and the fifth transistor are of the same type, and the first transistor and the third transistor are of the same type.

6. The antifuse array of claim 5, wherein the fourth and fifth transistors are N-type field effect transistors; the first transistor and the third transistor are P-type field effect transistors.

7. The antifuse array of claim 1, wherein the read circuit further comprises:

a second output control circuit connected to a first node, the third node, and the fourth node, the second output control circuit configured to transmit a charging signal of the first node to the third node and the fourth node when the clock control signal is at a second level, wherein the first level of the clock control signal is inverted from the second level.

8. The antifuse array of claim 7, wherein the second output control circuit comprises:

a tenth transistor, a first terminal of the tenth transistor is connected to the first node, a second terminal of the tenth transistor is connected to the third node, and a control terminal of the tenth transistor receives the clock control signal;

a second transistor, a first end of the second transistor is connected to the first node, a second end of the second transistor is connected to the fourth node, and a control end of the second transistor receives the clock control signal;

the second transistor and the tenth transistor are of the same type.

9. The antifuse array of claim 8, wherein the first output control circuit comprises:

and a first end of the eighth transistor is connected to the second node, a second end of the eighth transistor is connected to a ground terminal, a control terminal of the eighth transistor receives the clock control signal, and types of the second transistor and the eighth transistor are different.

10. The antifuse array of claim 9, wherein the eighth transistor is an N-type field effect transistor, and the second and tenth transistors are P-type field effect transistors.

11. The antifuse array of claim 1, wherein the read circuit further comprises:

a level adjustment circuit connected to a fifth node and a sixth node, the level adjustment circuit configured to adjust voltages of the fifth node and the sixth node according to the clock control signal.

12. The antifuse array of claim 11, wherein the level adjustment circuit comprises:

a ninth transistor, a first terminal of the ninth transistor is connected to the fifth node, a second terminal of the ninth transistor is connected to the sixth node, and a control terminal of the ninth transistor receives the first voltage signal.

13. The antifuse array of claim 1, wherein the latch circuit comprises a first NAND gate and a second NAND gate, wherein,

a first input end of the first NAND gate circuit is connected with the third node, and a second input end of the first NAND gate circuit is connected with an output end of the second NAND gate circuit;

a first input end of the second NAND gate circuit is connected with the fourth node, and a second input end of the second NAND gate circuit is connected with an output end of the first NAND gate circuit;

The latch circuit outputs data stored by the antifuse array through an output terminal of the first nand gate circuit or through an output terminal of the second nand gate circuit.

14. The antifuse array of claim 1, wherein the clock control signal transitions from the second level to the first level after the data port outputs the data signal.

15. The antifuse array of claim 2, further comprising:

a precharge circuit provided corresponding to the read circuit, the precharge circuit being connected to a first signal terminal of the comparison circuit, the precharge circuit being configured to precharge the first signal terminal of the comparison circuit before the clock control signal is at the first level.

16. A programmable non-volatile memory comprising the antifuse array of any of claims 1-15.

17. The antifuse array of claim 16, wherein the memory further comprises:

a plurality of output circuits, each of the output circuits being connected to the read circuits in a row of the antifuse array and receiving an array selection signal, the output circuits being configured to output data read by the read circuits in accordance with the array selection signal.