CN114756832A - Watchdog overtime restart field capture system, method, device and storage medium - Google Patents
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Abstract
The invention discloses a watchdog overtime restart field capture system, method, device and storage medium, the system includes: the watchdog counting module is used for counting when the watchdog is started, and generating a first overtime signal when the counting value reaches a preset overtime threshold value; the watchdog timeout processing module is used for responding to the first timeout signal, storing the current field information of the CPU as abnormal field information to the watchdog SRAM storage module, setting the watchdog timeout flag to be 1, and sending a first reset signal to the CPU; and the watchdog information acquisition module is used for reading the watchdog overtime identification when the CPU is reset, acquiring abnormal field information from the watchdog SRAM storage module and sending the abnormal field information to the CPU memory if the watchdog overtime identification is 1, setting the watchdog overtime identification to be 0, and restarting the watchdog through the watchdog starting module. The invention is beneficial to the recovery of the abnormal site of the CPU and the analysis of the abnormal reason, improves the reliability of the system and can be widely applied to the technical field of computers.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a watchdog overtime restart field capturing system, method, device and storage medium.
Background
The hardware watchdog is a timer circuit, and the watchdog counter can be modified by the watchdog feeding program at regular time to prevent the watchdog timer from overtime, and if the watchdog feeding program is abnormal to stop feeding the watchdog, the abnormal processing of the watchdog, such as resetting the system, can be triggered. The abnormal field loss after the system reset restart is usually performed by the analysis of the fault abnormality through the printed record information before the restart.
In the prior art, when the watchdog is restarted due to abnormal operation of the system, the system loses an abnormal site, so that the reason for the abnormal situation and the position of program operation before restarting cannot be located, and debugging personnel cannot perform subsequent fault analysis and debugging.
Disclosure of Invention
The present invention aims to solve at least to some extent one of the technical problems existing in the prior art.
Therefore, an object of the embodiments of the present invention is to provide a watchdog timeout restart field capture system capable of saving an abnormal field.
Another object of the embodiments of the present invention is to provide a watchdog timeout restart field capture method.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention comprises the following steps:
in a first aspect, an embodiment of the present invention provides a watchdog timeout restart field capture system, including:
the watchdog counting module is used for counting when the watchdog is started, and generating a first overtime signal when the counting value reaches a preset overtime threshold value;
the watchdog SRAM storage module is used for storing the abnormal field information of the CPU;
the watchdog timeout processing module is used for responding to the first timeout signal, storing the current field information of the CPU as the abnormal field information to the watchdog SRAM storage module, setting a watchdog timeout identifier to be 1, and sending a first reset signal to the CPU;
the watchdog starting module is used for controlling the starting of the watchdog;
and the watchdog information acquisition module is used for reading the watchdog timeout identification when the CPU is reset, acquiring the abnormal field information from the watchdog SRAM storage module and sending the abnormal field information to the CPU memory if the watchdog timeout identification is 1, setting the watchdog timeout identification to be 0, and restarting the watchdog through the watchdog starting module.
Further, in one embodiment of the present invention, the exception field information includes program counter information, program status register information, and stack register information.
Further, in an embodiment of the present invention, the watchdog information processing module is further configured to: and reading the watchdog timeout identification when the CPU is reset, and starting the watchdog through the watchdog starting module if the watchdog timeout identification is 0.
Further, in an embodiment of the present invention, the watchdog timeout restart field capture system further includes:
and the abnormal field information viewing module is used for receiving an operation instruction of a user, acquiring the abnormal field information from the CPU register according to the operation instruction and returning the abnormal field information to the user.
In a second aspect, an embodiment of the present invention provides a watchdog timeout restart field capture method, including the following steps:
counting when the watchdog is started, and generating a first overtime signal when the count value reaches a preset overtime threshold value;
responding to the first overtime signal, storing the current field information of the CPU as abnormal field information to a watchdog SRAM storage module, setting a watchdog overtime mark to be 1, and sending a first reset signal to the CPU;
and the watchdog timeout identifier is used for reading the watchdog timeout identifier when the CPU is reset, acquiring the abnormal field information from the watchdog SRAM storage module and sending the abnormal field information to a CPU memory if the watchdog timeout identifier is 1, setting the watchdog timeout identifier to be 0, and restarting the watchdog.
Further, in one embodiment of the present invention, the exception field information includes program counter information, program status register information, and stack register information.
Further, in an embodiment of the present invention, the watchdog timeout restart live capture method further includes the following steps:
and reading the watchdog timeout identification when the CPU is reset, and starting the watchdog through the watchdog starting module if the watchdog timeout identification is 0.
Further, in an embodiment of the present invention, the watchdog timeout restart live capture method further includes the following steps:
and receiving an operation instruction of a user, acquiring the abnormal field information from the CPU register according to the operation instruction, and returning the abnormal field information to the user.
In a third aspect, an embodiment of the present invention provides a watchdog timeout restart field capture device, including:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement a watchdog timeout restart live capture method as described above.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored, where the program executable by the processor is configured to execute the above-mentioned watchdog timeout restart live capture method.
Advantages and benefits of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention:
counting when the watchdog is started, storing the current abnormal field information of the CPU to a watchdog SRAM storage module when the counting value reaches an overtime threshold, setting the overtime identifier of the watchdog to be 1, and then resetting the CPU; and reading the watchdog timeout identification when the CPU is reset, acquiring abnormal field information from the watchdog SRAM storage module when the watchdog timeout identification is 1, sending the abnormal field information to the CPU memory for storage, setting the watchdog timeout identification to be 0, and restarting the watchdog. According to the embodiment of the invention, the abnormal field information of the CPU is immediately backed up to the watchdog SRAM module after the watchdog is overtime, then the CPU is reset, and the backed-up abnormal field information is stored to the CPU memory after the CPU is reset, so that a debugging worker can directly read the abnormal field information from the CPU memory, and the recovery of the abnormal field of the CPU and the analysis of the abnormal reason are facilitated; because the watchdog SRAM module is additionally arranged in the watchdog framework, the abnormal site can be stored when the CPU is in hardware abnormality or software abnormality, and the reliability of the system is improved.
Drawings
In order to more clearly illustrate the technical solution in the embodiment of the present invention, the drawings required to be used in the embodiment of the present invention are described below, and it should be understood that the drawings in the description below are only for convenience and clarity in describing some embodiments in the technical solution of the present invention, and it is obvious for those skilled in the art that other drawings may also be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of a structure of a watchdog timeout restart field capture system according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a working principle of a watchdog timeout restart field capture system according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a state machine of a watchdog timeout restart field capture system according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating steps of a watchdog timeout restart field capture method according to an embodiment of the present invention;
fig. 5 is a block diagram of a watchdog timeout restart field capture device according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. For the step numbers in the following embodiments, they are set for convenience of illustration only, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
In the description of the present invention, the meaning of a plurality is two or more, if there is a description to the first and the second for the purpose of distinguishing technical features, it is not understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the precedence of the indicated technical features. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.
Referring to fig. 1, an embodiment of the present invention provides a watchdog timeout restart field capture system, including:
the watchdog counting module is used for counting when the watchdog is started, and generating a first overtime signal when the counting value reaches a preset overtime threshold value;
the watchdog SRAM storage module is used for storing the abnormal field information of the CPU;
the watchdog timeout processing module is used for responding to the first timeout signal, storing the current field information of the CPU as abnormal field information to the watchdog SRAM storage module, setting the watchdog timeout identifier to be 1, and sending a first reset signal to the CPU;
the watchdog starting module is used for controlling the starting of the watchdog;
and the watchdog information acquisition module is used for reading the watchdog timeout identification when the CPU is reset, acquiring the abnormal field information from the watchdog SRAM storage module and sending the abnormal field information to the CPU memory if the watchdog timeout identification is 1, setting the watchdog timeout identification to be 0, and restarting the watchdog through the watchdog starting module.
Counting when the watchdog is started, storing the current abnormal field information of the CPU to a watchdog SRAM storage module when the counting value reaches an overtime threshold value, setting the overtime identifier of the watchdog to be 1, and then resetting the CPU; and reading the watchdog overtime identification when the CPU is reset, acquiring abnormal field information from the watchdog SRAM storage module when the watchdog overtime identification is 1, sending the abnormal field information to the CPU memory for storage, setting the watchdog overtime identification to be 0, and restarting the watchdog. According to the embodiment of the invention, the abnormal field information of the CPU is immediately backed up to the watchdog SRAM module after the watchdog is overtime, then the CPU is reset, and the backed-up abnormal field information is stored to the CPU memory after the CPU is reset, so that a debugging worker can directly read the abnormal field information from the CPU memory, and the recovery of the abnormal field of the CPU and the analysis of the abnormal reason are facilitated; because the watchdog SRAM module is additionally arranged in the watchdog framework, the abnormal site can be stored when the CPU is in hardware abnormality or software abnormality, and the reliability of the system is improved.
In some optional embodiments, the watchdog SRAM storage module is arranged in a power domain and is not controlled by system reset, so that stable backup of abnormal field information can be ensured, and the reliability of the system is further improved.
Further as an optional implementation, the exception field information includes program counter information, program status register information, and stack register information.
Specifically, after receiving the timeout signal, the watchdog timeout processing module stores the CPU internal registers in the current field of the CPU, such as a program counter, a program status register, and a stack register, in the watchdog SRAM storage module, where the information stored in the SRAM may be stored according to a predefined format, for example, the information may be sorted by incrementing according to the format of a CPU general register, a CPU special register, and current 1024-byte stack information.
As a further optional implementation manner, the watchdog information processing module is further configured to: and reading the watchdog overtime identification when the CPU is reset, and starting the watchdog through the watchdog starting module if the watchdog overtime identification is 0.
Specifically, when the watchdog timeout flag is 0, it indicates that the CPU is not restarted due to the watchdog timeout, and therefore, it is not necessary to read and dump the abnormal field information.
Further as an optional implementation, the watchdog timeout restart live capture system further includes:
and the abnormal field information viewing module is used for receiving an operation instruction of a user, acquiring the abnormal field information from the CPU register according to the operation instruction and returning the abnormal field information to the user.
Specifically, a user (a debugger) can view information on an abnormal site stored in a memory of the CPU through an instruction, and perform recovery of the abnormal site of the CPU and analysis of the cause of the abnormality based on the information on the abnormal site.
As shown in fig. 2, which is a schematic diagram of a working principle of a watchdog timeout restart field capture system according to an embodiment of the present invention, it can be understood that, when a CPU is normally reset and started (i.e., a non-watchdog is restarted overtime), a watchdog timeout flag is not 1, at this time, a watchdog is directly started, and then a watchdog counting module starts counting; if the CPU continues to feed the dog normally, the counting value of the watchdog cannot reach an overtime threshold value, and the CPU continues to operate normally; if the CPU is abnormal in hardware or software and cannot continue to feed the watchdog, the count value of the watchdog is continuously increased, when the timeout threshold is reached, the abnormal field information of the CPU is backed up to a watchdog SRAM storage module, the timeout identifier of the watchdog is set to be 1, and then a reset signal is sent to a reset port of the CPU, so that the CPU is reset and restarted; when the CPU is reset and restarted, the watchdog overtime mark is 1, the abnormal field information backed up by the watchdog SRAM storage module is transferred to the CPU memory for storage, the watchdog overtime mark is 0, then the watchdog is restarted, counting is restarted, and the process is executed circularly.
It can be appreciated that the embodiment of the invention can timely backup the abnormal field information after each timeout restart of the watchdog, and can timely transfer the abnormal field information to the CPU memory for subsequent check after the CPU is reset and restarted, so that even if multiple times of timeout restart occur within a period of time, the abnormal field information during each timeout restart can be backed up and transferred through the watchdog SRAM memory module, and cannot be covered in the watchdog SRAM memory module, thereby further improving the reliability of the system.
As shown in fig. 3, which is a schematic diagram of a state machine of a watchdog timeout restart field capture system according to an embodiment of the present invention, it can be understood that, in the embodiment of the present invention, there are 5 states, which are an initial state, an open state, a count state, a timeout state, and an SRAM read/write state, respectively, where:
the initial state is a reset pull-in state, and is related to a closing state, the system does not work, and the register cannot be read and written;
the starting state is a reset release state and can read and write a register in the system;
a counting state, wherein when a timeout threshold value is configured, the counter starts accumulation operation;
a timeout state, which is a protection operation after entering timeout, when the count value of the counter is equal to the timeout threshold value;
and the SRAM read-write state is needed to be entered, the CPU field needs to be saved after the SRAM read-write state enters the overtime state, and in addition, the system can also receive an operation instruction of a user to enter the read-write state and read the SRAM content.
The system structure and the working principle of the embodiment of the invention are explained above, and it can be understood that the embodiment of the invention immediately backs up the abnormal field information of the CPU to the watchdog SRAM module after the watchdog is overtime, then performs the CPU reset, and stores the backed-up abnormal field information to the CPU memory after the CPU reset, so that a debugger can directly read the abnormal field information from the CPU memory, thereby facilitating the recovery of the abnormal field of the CPU and the analysis of the abnormal reason; because the watchdog SRAM module is additionally arranged in the watchdog framework, the abnormal site can be stored when the CPU is in hardware abnormality or software abnormality, and the reliability of the system is improved.
The embodiment of the invention can be applied to a system-level chip, such as an ARM chip, an X86 chip, an MIPS chip and the like, and compared with the prior art, the embodiment of the invention also has the following advantages:
1) innovativeness, in the prior art, no related technology for saving an abnormal field through hardware and then resetting a system exists;
2) reliability, the embodiment of the invention can store the abnormal site when the CPU software is abnormal and the hardware is abnormal, and the prior art can not store the abnormal site when the hardware is abnormal;
3) the embodiment of the invention can be realized by hardware, and can ensure that the system can be quickly reset after abnormal timeout so as to realize fool-proofing.
Referring to fig. 4, an embodiment of the present invention provides a watchdog timeout restart field capture method, including the following steps:
s101, counting when a watchdog is started, and generating a first overtime signal when a count value reaches a preset overtime threshold;
s102, responding to the first overtime signal, storing the current field information of the CPU as abnormal field information to a watchdog SRAM storage module, setting a watchdog overtime mark to be 1, and sending a first reset signal to the CPU;
and S103, reading the watchdog timeout identification when the CPU is reset, if the watchdog timeout identification is 1, acquiring abnormal field information from the watchdog SRAM storage module, sending the abnormal field information to the CPU memory, setting the watchdog timeout identification to be 0, and restarting the watchdog.
Further as an optional implementation, the exception field information includes program counter information, program status register information, and stack register information.
As a further optional implementation manner, the watchdog timeout restart live capture method further includes the following steps:
and reading the watchdog overtime identification when the CPU is reset, and starting the watchdog through the watchdog starting module if the watchdog overtime identification is 0.
Further as an optional implementation manner, the watchdog timeout restart live capture method further includes the following steps:
and receiving an operation instruction of a user, acquiring abnormal field information from the CPU register according to the operation instruction, and returning the abnormal field information to the user.
The contents in the system embodiments are all applicable to the method embodiments, the functions specifically realized by the method embodiments are the same as the system embodiments, and the beneficial effects achieved by the method embodiments are also the same as the beneficial effects achieved by the system embodiments.
Referring to fig. 5, an embodiment of the present invention provides a watchdog timeout restart field capture device, including:
at least one processor;
at least one memory for storing at least one program;
when the at least one program is executed by the at least one processor, the at least one program causes the at least one processor to implement the watchdog timeout restart live capture method described above.
The contents in the above method embodiments are all applicable to the present apparatus embodiment, the functions specifically implemented by the present apparatus embodiment are the same as those in the above method embodiments, and the advantageous effects achieved by the present apparatus embodiment are also the same as those achieved by the above method embodiments.
An embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored, and the program executable by the processor is used for executing the above watchdog timeout restart field capture method.
The computer-readable storage medium of the embodiment of the invention can execute the watchdog timeout restart field capture method provided by the embodiment of the method of the invention, can execute any combination implementation steps of the embodiment of the method, and has corresponding functions and beneficial effects of the method.
The embodiment of the invention also discloses a computer program product or a computer program, which comprises computer instructions, and the computer instructions are stored in a computer readable storage medium. The computer instructions may be read by a processor of a computer device from a computer-readable storage medium, and executed by the processor, causing the computer device to perform the method illustrated in fig. 4.
In alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flow charts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.
Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the above-described functions and/or features may be integrated in a single physical device and/or software module, or one or more of the functions and/or features may be implemented in a separate physical device or software module. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary for an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be understood within the ordinary skill of an engineer, given the nature, function, and internal relationship of the modules. Accordingly, those skilled in the art can, using ordinary skill, practice the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative of and not intended to limit the scope of the invention, which is defined by the appended claims and their full scope of equivalents.
The above functions, if implemented in the form of software functional units and sold or used as a separate product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Further, the computer readable medium could even be paper or another suitable medium upon which the above described program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A watchdog timeout restart field capture system, comprising:
the watchdog counting module is used for counting when the watchdog is started, and generating a first overtime signal when the counting value reaches a preset overtime threshold value;
the watchdog SRAM storage module is used for storing the abnormal field information of the CPU;
the watchdog timeout processing module is used for responding to the first timeout signal, storing the current field information of the CPU as the abnormal field information to the watchdog SRAM storage module, setting a watchdog timeout identifier to be 1, and sending a first reset signal to the CPU;
the watchdog starting module is used for controlling the starting of the watchdog;
and the watchdog information acquisition module is used for reading the watchdog timeout identification when the CPU is reset, acquiring the abnormal field information from the watchdog SRAM storage module and sending the abnormal field information to the CPU memory if the watchdog timeout identification is 1, setting the watchdog timeout identification to be 0, and restarting the watchdog through the watchdog starting module.
2. The watchdog timeout restart field capture system of claim 1, wherein: the exception field information includes program counter information, program status register information, and stack register information.
3. The watchdog timeout restart field capture system of claim 1, wherein the watchdog information processing module is further configured to: and reading the watchdog timeout identification when the CPU is reset, and starting the watchdog through the watchdog starting module if the watchdog timeout identification is 0.
4. The watchdog timeout restart field capture system of claim 1, wherein the watchdog timeout restart field capture system further comprises:
and the abnormal field information viewing module is used for receiving an operation instruction of a user, acquiring the abnormal field information from the CPU register according to the operation instruction and returning the abnormal field information to the user.
5. A watchdog overtime restart field capture method is characterized by comprising the following steps:
counting when the watchdog is started, and generating a first overtime signal when the count value reaches a preset overtime threshold value;
responding to the first overtime signal, storing the current field information of the CPU as abnormal field information to a watchdog SRAM storage module, setting a watchdog overtime mark to be 1, and sending a first reset signal to the CPU;
and the watchdog timeout identifier is used for reading the watchdog timeout identifier when the CPU is reset, acquiring the abnormal field information from the watchdog SRAM storage module and sending the abnormal field information to a CPU memory if the watchdog timeout identifier is 1, setting the watchdog timeout identifier to be 0, and restarting the watchdog.
6. The watchdog timeout restart live capture method of claim 5, wherein: the exception field information includes program counter information, program status register information, and stack register information.
7. The watchdog timeout restart field capture method according to claim 5, wherein the watchdog timeout restart field capture method further comprises the following steps:
and reading the watchdog timeout identification when the CPU is reset, and starting the watchdog through the watchdog starting module if the watchdog timeout identification is 0.
8. The watchdog timeout restart field capture method of claim 5, wherein the watchdog timeout restart field capture method further comprises the steps of:
and receiving an operation instruction of a user, acquiring the abnormal field information from the CPU register according to the operation instruction, and returning the abnormal field information to the user.
9. A watchdog timeout restart field capture device, comprising:
at least one processor;
at least one memory for storing at least one program;
when executed by the at least one processor, cause the at least one processor to implement a watchdog timeout restart live capture method as claimed in any one of claims 5 to 8.
10. A computer readable storage medium having stored therein a processor executable program, wherein the processor executable program when executed by a processor is for performing a watchdog timeout restart live capture method as claimed in any one of claims 5 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210459095.8A CN114756832A (en) | 2022-04-26 | 2022-04-26 | Watchdog overtime restart field capture system, method, device and storage medium |
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| CN202210459095.8A CN114756832A (en) | 2022-04-26 | 2022-04-26 | Watchdog overtime restart field capture system, method, device and storage medium |
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