CN114756404B - Data processing method, device, electronic equipment and storage medium - Google Patents
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Abstract
The application provides a data processing method, a device, electronic equipment and a storage medium, which are applied to the technical field of electric data processing, wherein the data processing method comprises the following steps: receiving a data update request for an L2P table, wherein the data update request comprises first physical address data to be updated in the L2P table; determining a new value of a check code according to the first physical address data; updating the new value of the check code to a target memory to update the old value of the check code, and updating the first physical address data to the L2P table, wherein the target memory is not the DDR. When each piece of physical address data is updated into the L2P table, the check code corresponding to the L2P table is updated based on the physical address data, so that the solid state disk can maintain any piece of physical address data in the L2P table by using the check code, the reliability of the physical address data in the L2P table is improved, and the safety and reliability of the solid state disk in data operation are guaranteed.
Description
Technical Field
The present disclosure relates to the field of electronic data processing technologies, and in particular, to a data processing method, an apparatus, an electronic device, and a storage medium.
Background
A Solid State Disk (Solid State Disk or Solid State Drive, abbreviated as SSD) using a FLASH memory (FLASH chip) is used, and a host controller of the SSD needs to use an L2P table (Logic LBA to Physical Address, logical-to-physical address mapping table) to perform FLASH memory management, for example, when performing FLASH memory operations such as reading data from the SSD, writing data into the SSD, performing garbage collection operation on the SSD, etc., all physical addresses corresponding to the FLASH memory of the managed operation need to be obtained from the L2P table, where the L2P is usually cached in the DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory) of the Solid State Disk.
In view of the inherent characteristics of DDR, the buffered data is susceptible to bit inversion (bitflip), so that once the physical address value in the L2P table is bit-reversed, i.e. the physical address in the L2P table is mapped with errors, the read-write system does not perform effective error correction on the address value, when the system manages the data of the flash memory according to the erroneous physical address, the system must cause data errors, and even the whole disc enters an illegal state. Therefore, when the DDR cache data is bit-reversed, if the DDR cache data is not effectively corrected, user data is very easily erroneous and lost, and even serious loss results occur.
In the existing application scheme of the solid state disk, in order to ensure that the DDR data of the solid state disk is reliable, a solid state disk controller generally provides 1bit error correction and 2bit error detection functions based on an ECC technology (Error Correcting Code, error checking and correcting technology). However, the ECC can only perform 1bit error correction and 2bit error detection for the 1bit inversion condition, and the ECC is unable to perform when the DDR data has the multi-bit inversion condition.
Therefore, in the face of the possible multi-bit inversion of L2P table data stored at DDR, which requires error detection and correction of data, a new data processing scheme is needed.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a data processing method, apparatus, electronic device, and storage medium, which can improve the data reliability of the L2P table, and are beneficial to improving the security and reliability of the solid state disk when executing data operations.
The embodiment of the specification provides the following technical scheme:
the embodiment of the specification provides a data processing method, which is applied to a controller of a solid state disk, and comprises the following steps:
receiving a data update request for an L2P table, wherein the L2P table is cached in the DDR of a solid state disk, and the data update request contains first physical address data to be updated into the L2P table;
Determining a new value of a check code according to the first physical address data, wherein the new value of the check code is obtained by performing exclusive OR logic operation on an old value of the check code and the first physical address data, and the old value of the check code is a numerical value corresponding to the check code before the new value of the check code is generated;
updating the new value of the check code to a target memory to update the old value of the check code, and updating the first physical address data to the L2P table, wherein the target memory is not the DDR.
The embodiment of the specification also provides a data processing method applied to a controller of a solid state disk, the data processing method comprising the following steps:
receiving a data operation instruction initiated by a host to a solid state disk, wherein the data operation instruction comprises logic address data corresponding to an operated target flash memory;
determining target physical address data corresponding to the logic address data from an L2P table, wherein the L2P table is cached in the DDR of the solid state disk;
acquiring a current value of a check code, wherein the current value of the check code is data obtained by performing exclusive-or logic operation on all physical address data cached in the L2P table before caching in the L2P table, the current value of the check code is cached in a target memory, and the target memory is not the DDR;
Determining first address data according to the current value of the check code, wherein the first address data is obtained by performing exclusive OR logic operation on the current value of the check code and all other physical address data which are cached in the L2P table except the target physical address data;
and executing the data operation instruction on the target flash memory according to the first address data.
The embodiment of the specification also provides a data processing device, which is applied to a controller of a solid state disk, and comprises:
the data updating module is used for receiving a data updating request for an L2P table, wherein the L2P table is cached in the DDR of the solid state disk, and the data updating request comprises first physical address data to be updated into the L2P table;
the first determining module is used for determining a new value of the check code according to the first physical address data, wherein the new value of the check code is obtained by performing exclusive OR logic operation on the old value of the check code and the first physical address data, and the old value of the check code is a numerical value corresponding to the check code before the new value of the check code is generated;
a first control module that updates a new value of the check code to a target memory to update an old value of the check code, and updates the first physical address data to the L2P table, wherein the target memory is not the DDR.
The embodiment of the specification also provides a data processing device, which is applied to a controller of a solid state disk, and comprises:
the second receiving module is used for receiving a data operation instruction initiated by the host to the solid state disk, wherein the data operation instruction comprises logic address data corresponding to the operated target flash memory;
the second determining module determines target physical address data corresponding to the logic address data from an L2P table, wherein the L2P table is cached in the DDR of the solid state disk;
the first acquisition module acquires the current value of a check code, wherein the current value of the check code is data obtained by carrying out exclusive OR logic operation on all physical address data cached in the L2P table before caching in the L2P table, the current value of the check code is cached in a target memory, and the target memory is not the DDR;
the first calculation module is used for determining first address data according to the current value of the check code, wherein the first address data is obtained by performing exclusive OR logic operation on the current value of the check code and all other physical address data which are cached in the L2P table except the target physical address data;
And the second control module executes the data operation instruction on the target flash memory according to the first address data.
The embodiment of the specification also provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform: a data processing method as claimed in any one of the present specification.
The present specification embodiment also provides a computer storage medium storing computer-executable instructions that, when executed by a processor, perform the data processing method of any one of the present specification.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
when each piece of physical address data is cached in the L2P table, corresponding check codes are generated in advance according to the physical address data, so that any one piece of physical address data in the L2P table can be reliably checked according to the check codes, and multi-bit inversion error correction can be carried out on the data cached in the L2P table of the DDR through the check codes, so that the data reliability of the solid state disk is ensured. The check code is obtained by exclusive OR logic operation of the physical addresses, which occupies little data volume, and can save the miss storage, and the check code and the physical address data are stored separately, namely, the physical address data are stored in the DDR through the L2P table, and the check code is stored in other memories, so even if the L2P table data stored in the DDR are subjected to bit inversion, the correct physical address data are only needed to be calculated according to the check code, and the physical address data of the L2P table can be detected, checked, corrected and the like by utilizing the physical address data obtained by the back calculation.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional solid state disk for performing data operations based on an L2P table;
FIG. 2 is a schematic diagram of a solid state disk with optimized and improved data operation based on an L2P table;
FIG. 3 is a flow chart of a method of data processing when any one of the physical addresses in the application is updated into the L2P table;
FIG. 4 is a flow chart of the maintenance detection of any one of the physical address data in the L2P table in the present application;
FIG. 5 is a schematic diagram of a data processing apparatus when any physical address in the present application is updated into an L2P table;
FIG. 6 is a flowchart of a data processing method when a solid state disk performs data operations in the present application;
fig. 7 is a schematic structural diagram of a data processing device when the solid state disk in the present application performs a data operation.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
At present, the existing solid state disk controller has 1 bit error on DDR, can correct errors according to ECC, and has an error detection function on 2 bits. Once the L2P stored in DDR has multi-bit flip, the data will be read out, which will cause errors or invalidations.
Taking fig. 1 as an example, the flow of 8 sectors (LBA 0 to LBA 7) of the system read LBA (Logical Block Address ) is as follows:
1. first, host initiates a read operation from LBA0 to LBA 7;
2. after the firmware receives the operation command, the firmware converts (overt) the logical address of the command into a translation unit (Logic Translation Unit, LTU, wherein LTU is based on 4K), that is, into LTU0;
3. The firmware will then query the physical address of the actual NAND (Flash Physical Address, FPA) from the L2P table in DDR;
4. after the firmware gets the FPA address, a read operation to the NAND is initiated.
However, in the above 3 rd read operation, once the physical address stored in the DDR is bit-inverted, that is, the FPA corresponding to the LTU0 is bit-inverted, it is mapped to the wrong physical address, and in this case, in the 4 th step, one wrong data is read from one wrong address. For example, assuming that the value of the FPA corresponding to LTU0 is 0x1000A5, if bit0 is bit reversed, the value corresponding to FPA becomes 0x1000A4, and the data that should have been read from NAND physical location 0x1000A5, as a result, will be read from 0x1000A4, and it is apparent that the read data is erroneous.
In the prior art, the controller of the solid state disk can provide the functions of 1bit error correction and 2bit error detection through the ECC technology, for example, the value of the FPA is 0x1000A5, and the FPA is changed into 0x1000A4 after only 1bit inversion (bit 0) occurs, and the controller can correct the error of the 1bit after ECC error correction.
However, the ECC technique can only provide 1bit error correction and 2bit error detection, and when there is a multi-bit error (i.e., multi-bit inversion occurs), although the controller cannot correct the data in which the bit inversion occurs based on the ECC technique if the controller can detect that the data is in error, it is impossible to correct the data in which two bits are in error and whether the real data on the inversion bit should be 1 or 0. For example, the FPA has a value of 0x1000A5, a two bit error (bit 0, bit 1) occurs, and the value changes to 0x1000A6.
In view of this, after the inventor has conducted intensive research and improved exploration on the solid state disk and the verification manner thereof, the embodiment of the present specification proposes a data processing scheme for detecting and correcting errors of multi-bit inversion: as shown in fig. 2, in one aspect, when each new physical address (FPA) data is updated to the L2P table, a new check code corresponding to the current L2P table is first generated using the new physical address data, where the check code may be generated according to the following exclusive or logic operation formula: the new check code=old check code =new physical address ", then the new physical address is updated and stored in the L2P table, namely the new physical address data can be mapped by the LTU and then stored in the L2P table in the DDR, and the check code is stored in the target Memory, wherein the target Memory is not used for storing the DDR of the L2P table, thus the check code is stored separately from the physical address data, for example, the target Memory is a Memory (such as SRAM (Static Random-Access Memory)) which is easy to undergo bit inversion, and the check code is updated along with the continuous updating of the physical address data and is stored in the L2P table, so that a check code can be used to represent the check condition of the physical address data in the L2P table, and the check code can be used with the data with the same bit number as the physical address, thereby saving a large amount of Memory resources; on the other hand, when any physical address in the L2P table is detected, that is, when it is determined whether the physical address is bit-reversed in the L2P table, the check code corresponding to the current L2P table and all physical addresses (except the physical address to be checked) currently existing in the L2P table may be used to perform exclusive-or logic operation to obtain new physical address data, that is, form new address data corresponding to the physical address to be checked, so that specific bits of the physical address to be checked, which are bit-reversed, may be detected and corrected by using the new address data.
For example, the updating of 4byte physical address data (noted FPA) into the L2P table is illustrated as follows:
when the L2P table is updated to the first physical address (denoted as fpa_0), a 4byte storage space (i.e. a storage space storing a check code) may be opened up in the target memory (e.g. SRAM), the storage space is marked as RAID, and the RAID is assigned, for example, the RAID is initialized to 0 first, and then the original RAID and the fpa_0 to be updated to the L2P table are subjected to exclusive-or logic operation to form a new check code RAID, or the fpa_0 is directly assigned to the RAID, i.e. raid=fpa_0;
when the L2P table is updated to a second physical address (noted as FPA_1) for the second time, performing exclusive OR logic transportation on the original RAID in the SRAM and the FPA_1 which needs to be updated to the L2P table to update the check code, namely, a new check code RAID=RAID =FPA_1=FPA_0 # -FPA_1;
the third time the L2P table is updated to a third physical address (denoted as fpa_2), the original RAID in the SRAM is transported by exclusive or with the fpa_2 to be updated to the L2P table to obtain a new check code, i.e. raid=raid =fpa_2=fpa_0 °fpa_1 °fpa_2;
similarly, the nth L2P table is updated with the nth physical address data (denoted as fpa_n), and the original RAID in the SRAM is transported by exclusive or with the fpa_n to be updated in the L2P table to update the check code, i.e., the new check code raid=raid × fpa_n=fpa_0 × fpa_1 × fpa_2 × … × fpa_n.
For example, for physical address data of one 4byte in which bit inversion exists in the L2P table, detection of which bits have undergone bit inversion is schematically shown as follows:
based on the foregoing description of the example, it is assumed that the first physical address data (i.e., fpa_0) is bit-reversed, and at this time, a new physical address data fpa_0 ' may be obtained by back calculation from the check code and other physical address data, that is, fpa_0 ' =raid_1 =fpa_2 × … × fpa_n, where RAID is check code data corresponding to the current L2P table (i.e., the L2P table updated into the first to N physical address fpa_1 to N), and thus, the obtained new physical address data fpa_0 ' may be compared with the fpa_0 stored in the current L2P table according to the bits, that is, which bits stored in the current L2P table are specifically bit-reversed, and whether the corresponding values before and after the inversion on the bit-reversed bits are 1 or 0.
Taking the example of updating the stored three physical address data into the L2P table, the change of the check code, the bit inversion and the true value of the bit detected by the check code, etc. are schematically described as follows:
assume that: fpa0=0x1000 (hexadecimal data), fpa1=0x20a5, fpa2=0x2000;
When the L2P is updated into the FPA_0 for the first time, updating a check code RAID corresponding to the FPA_0 into the SRAM, namely opening up a 4byte storage space in the SRAM for storing RAID data, wherein the RAID data is the FPA_0, namely RAID=FPA_0;
when the L2P is updated into the FPA_1 for the second time, RAID data is updated after the exclusive OR logic operation is performed on RAID in the SRAM and the FPA_1, namely, new data of the RAID is as follows: raid=0x1000 #, 0x20a5=0x30a5;
when the L2P is updated into the FPA_2 for the third time, RAID data is updated after the exclusive OR logic operation is carried out on RAID in the SRAM and the FPA_2, namely, new data of the RAID is as follows: raid=0x30a5 _, 0x2000=0x1000, 0x20a5 =0x2000=0x10a5.
Therefore, the L2P table currently stores the three physical address data, and the corresponding check code is 4byte data: 0x10A5.
Now assume that bit0 and bit 1 bit inversions occur for FPA_0, i.e., FPA_0 changes from data 0x1000 to data 0x1003;
further, after the back calculation, a new physical address data fpa_0 'is obtained, wherein fpa_0=raid_fpa_1_2, that is, fpa_0' =0x10a5=0x20a2000=0x1000.
It can be seen that, from the new physical address data fpa_0 ', it is known that the bit inversion of the multiple bits occurs in fpa_0, and with the new physical address data fpa_0', it is possible to know not only which bits are specifically bit-inverted, but also the true values of the bit-inverted bits, and even to correct the physical address data in which the bit inversion occurs, for example, correct fpa_0 from the error data 0x1003 to the correct data 0x1000.
Therefore, when the physical address enters the L2P table, namely, when the physical address forms a mapping relation in the L2P table, the physical address is utilized to generate the check code at the same time, even if the physical address continuously enters the L2P table, the check code is continuously updated, all the physical addresses in the L2P table correspond to one check code, and further, any one physical address data in the L2P table can be reversely calculated through the check code to carry out bit inversion detection, check, error correction and the like, so that the problem that the data in the L2P table is unreliable due to the bit inversion characteristic of the DDR is effectively solved, and the safe and reliable data operation of the solid state disk is ensured.
The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
As shown in fig. 3, the embodiment of the present disclosure provides a data processing method, which may be applied to a controller of a solid state disk, so as to facilitate the solid state disk to maintain the reliability of the hard disk data in real time. The data processing method may include the following steps:
step S202, a data update request for an L2P table is received, wherein the L2P table is cached in the DDR of the solid state disk, and the data update request contains first physical address data to be updated into the L2P table.
In the solid state disk, an L2P table is used for storing the mapping relation between the Logical Block Address (LBA) and the physical block address, and the L2P table is stored in the DDR. Therefore, the controller (also called a main controller) of the solid state disk can effectively manage each physical block storage unit through the L2P table, for example, when the controller of the solid state disk needs to operate (for example, read data, write data, etc.) one physical block, a logical block address sent by a file system is received, then a corresponding physical block address is found from the L2P table according to the logical block address, and finally the storage unit corresponding to the physical block address is operated according to the found physical block address.
In practice, when new data is to be written into the solid state disk, the main controller writes the new data into the blank flash memory space (i.e. the erased storage space), and then correspondingly updates the data in the L2P table, at this time, the main controller generally receives a data update request, and updates the data (i.e. the mapping relationship between the logical block address and the physical block address) in the L2P table through the data update request, where the update request may be accompanied by a physical block address (e.g. denoted as first physical address data) that needs to be updated. Thus, when the controller receives an update request for updating the data of the L2P table, the controller may extract the corresponding physical address data from the request.
The physical address data in the update request may be specified data directly stored in the request, or may be data further determined according to related data in the request, and the form of the physical address data in the request is not limited here.
Step S204, determining a new value of the check code according to the first physical address data, wherein the new value of the check code is obtained by performing exclusive OR logic operation on the old value of the check code and the first physical address data, and the old value of the check code is a numerical value corresponding to the check code before the new value of the check code is generated.
As described above, each physical address to be updated into the L2P table is used to generate the check code corresponding to the L2P table before entering the L2P table, that is, the check code is generated according to the physical address entering the L2P table, specifically, the generation mode is as follows: the new physical address is exclusive-ored with the old value of the check code, so that the exclusive-ored result is the new value of the check code.
It should be noted that, the new value and the old value of the check code are only relative, that is, when the next new physical address enters the L2P table, the new value that belongs to the check code in advance is the old value used in the current calculation, and specific reference may be made to the foregoing schematic description, which is not repeated herein.
Step S206, updating the new value of the check code to a target memory to update the old value of the check code, and updating the first physical address data to the L2P table, wherein the target memory is not the DDR.
In practice, since the DDR has a bit inversion property, the check code is stored in not the DDR but another memory (which may be referred to as a target memory herein), thereby avoiding the possibility of bit inversion of the check code. Therefore, the target memory may be different from the DDR storing the L2P table, such as SRAM with high read/write speed and high reliability, such as a memory (e.g., flash memory, EEPROM, etc.) that can hold data even if the read/write speed is slightly low and power is lost.
The new value of the check code is determined by the first physical address data, and the first physical address data can be updated into the L2P table, namely, the mapping relation between the first physical address data and the logical block address in the file system is formed in the L2P table.
It should be noted that, the manner of updating the physical address data into the L2P table may be implemented according to the file system requirement of the solid state disk, for example, in the foregoing example, the LTU may be used to generate the data (i.e. the mapping relationship) of the L2P table, which is not limited herein.
Through the steps S202 to S206, when each physical address data is updated into L2P, the check code is generated by using the physical address data at the same time, and the check code is stored in other memories, so that the bit inversion condition of each physical address data stored in the L2P table can be detected, checked and even corrected by using the check code in the later period, the safety and reliability of the data of the L2P table stored in the DDR are ensured, and the reliability of the data operation of the solid state disk is improved.
In addition, since the check code is obtained by sequentially performing exclusive-or logic operation on each piece of physical address data updated into the L2P table, not only the check code occupies little storage space, for example, the byte length of the check code can be the same as that of the physical address data, for example, the physical address is 4 bytes, but also the check code corresponding to the whole L2P table only occupies 4 bytes storage space, so that the check code can be stored in any memory inside the solid state disk without additionally arranging a special memory.
And the check code can be used for back-calculating address data corresponding to any physical address in the L2P table, so that the physical address can be checked based on the address data obtained by back-calculation, such as detecting which bits are subjected to bit inversion, such as correcting errors for the bits subjected to bit inversion, and the like.
Therefore, even if there are a plurality of bits of data stored in the L2P table in the DDR, the check can be performed using the check code provided in the embodiment of the present specification.
In some embodiments, the check code may be stored in an SRAM inside the solid state disk, that is, the target memory may preferably be an SRAM inside the solid state disk, where the data processing method may further include: and creating a target storage unit in the SRAM, wherein the target storage unit is used for storing the check code.
As the foregoing illustrates, a memory cell may be opened up in the SRAM, and the space size of the memory cell may be the size of the memory space that needs to be occupied by any physical address data in the L2P table, for example, each physical address data stored in the L2P table is 4 bytes, and then a 4byte memory cell is opened up in the SRAM for storing the check code.
By storing the check code in the SRAM in the solid state disk, not only is other memories not required to be additionally designed, but also the characteristics (such as high-speed reading and writing) of the SRAM can be utilized, so that the data processing efficiency when the physical address data is updated into the L2P table is ensured, and the reliability of the check code can be ensured.
In some embodiments, after the physical address data is updated into the L2P table in the DDR, the data of the L2P table may be further detected in real time, so the data processing method may further include: detecting whether bit inversion exists in the second physical address data cached in the L2P table.
In implementation, when the physical address data stored in the L2P table is subjected to multi-bit inversion, although the ECC technology cannot detect which bits are inverted, the ECC technology can still be used for obtaining that the physical address data has errors, so that whether the physical address data in the L2P table has the bit inversion or not can still be detected based on the existing ECC technology of the solid state disk, the existing functions of the solid state disk can be fully utilized for detection, and the additional detection function is not required, thereby being beneficial to guaranteeing the efficiency of processing the data by the solid state disk.
It should be noted that, whether the physical address data in the L2P table has bit inversion or not may be detected by using the foregoing ECC technique, or may also be detected by using other detection methods, and particularly may be selected according to the application requirement of the solid state disk.
Preferably, for a physical address in the L2P table, where the detection of the bit inversion condition needs to be performed, address data corresponding to the physical address may be calculated back based on the check code provided in the present specification, and then, whether the physical address stores bit inversion may be determined by comparing the address data obtained by the back calculation with the physical address.
As shown in fig. 4, when detecting whether there is a bit reversal in the second physical address data buffered in the L2P table, the method may include the steps of:
Step S402, the current value of the check code is obtained from the target memory.
When detecting the bit inversion condition of the physical address data (herein referred to as the second physical address data for convenience of illustration) in the L2P table, the detection may be performed based on the check code corresponding to the current L2P, that is, the current value of the check code corresponding to the current L2P table needs to be obtained from the target memory, so as to perform back calculation of the physical address based on the current value.
It should be noted that, the current value of the check code is obtained from the target memory in a corresponding obtaining manner according to the application scenario of the specific solid state disk, for example, when the target memory is an SRAM, the obtaining manner corresponds to reading the check code from the SRAM, so the method for obtaining the check code is not limited.
Step S404, determining first address data according to the current value of the check code, wherein the first address data is obtained by performing exclusive OR logic operation on the current value of the check code and all other physical address data which are cached in the L2P table except the second physical address data.
When the inverse calculation of the physical address is performed based on the current value of the check code, the inverse calculation is performed on the current value of the check code and other physical address data except the physical address data to be detected in the L2P table through exclusive or logic operation, and the schematic process of the inverse calculation can refer to the related schematic description in the previous example and is not repeated.
Step S406, determining whether the second physical address data is consistent with the first address data, and executing step S408 when the second physical address data is inconsistent with the first address data, otherwise, executing step S410;
step S408, determining that the second physical address data has bit inversion;
step S410, determining that the second physical address data has no bit inversion.
In the determination of the consistency of the two data in step S406, the numerical comparison determination may be directly performed based on the two data, or the comparison determination may be performed by bit based on the two data, which is not limited herein.
Based on the check code corresponding to the L2P table and other physical address data in the L2P table, a true value (i.e., the first address data) of the physical address data to be detected before being updated into the L2P table can be accurately and reliably calculated, and whether the physical address data stored in the L2P table has a bit inversion condition can be determined based on the true value.
In some embodiments, after determining that the second physical address data has bit inversion, the data processing method provided by the embodiment of the present disclosure may further determine which bits are specifically bit-inverted, may determine a true value of the bit with the reflected bit inversion, and may further correct the bit with the bit inversion.
In one example, the data processing method may further include: and determining bit positions with bit inversion in the second physical address data according to the first address data.
As described in the foregoing example, since the first address data is a reliable real value corresponding to the second physical address data, the first address data and the second physical address data can be compared by bit, so that it can be accurately obtained which bits are bit-reversed according to the comparison result of the bits. Therefore, even if the plurality of bits of the second physical address data in the L2P table are bit-reversed, the specific bit in which the bit reversal occurs can be accurately and reliably determined.
In one example, the data processing method may further include: and correcting the error of the bit with the bit inversion in the second physical address data according to the first address data.
As described in the foregoing example, since the first address data is a reliable real value corresponding to the second physical address data, the bit of the second physical address data, in which the bit is inverted, may be corrected according to the first address data, so as to correct the second physical address data back to correct data.
In some embodiments, after determining which bits of the second physical address data have bit inversion, the method may be implemented according to an application scheme of the solid state disk, for example, statistics may be performed on the number of times of bit inversion occurring in a storage unit of the DDR, and then maintenance may be performed on the storage unit of the DDR according to the statistics, where the maintenance may include repairing, prompting, avoiding the storage units, and so on, so that the possibility of bit inversion occurring in the L2P table data stored in the DDR may be further reduced.
Based on the same inventive concept, the embodiments of the present disclosure provide an apparatus, an electronic device, and a computer storage medium corresponding to the method described in any one of the foregoing embodiments.
As shown in fig. 5, a data processing apparatus 500 provided in an embodiment of the present disclosure is applied to a controller of a solid state disk, where the data processing apparatus 500 may include: a first receiving module 501, a first determining module 503 and a first control module 505.
Specifically, the first receiving module 501 is configured to receive a data update request for an L2P table, where the L2P table is cached in a DDR of a solid state disk, and the data update request includes first physical address data to be updated in the L2P table;
The first determining module 503 is configured to determine a new value of a check code according to the first physical address data, where the new value of the check code is obtained by performing an exclusive-or logical operation on an old value of the check code and the first physical address data, and the old value of the check code is a value corresponding to the check code before the new value of the check code is generated;
the first control module 505 is configured to update a new value of the check code to a target memory to update an old value of the check code, and update the first physical address data to the L2P table, wherein the target memory is not the DDR.
When each piece of physical address data needs to be updated into the L2P table, a new value of the check code can be generated by utilizing the physical address data, so that the check code is updated along with the update of the physical address data into the L2P table, and the check code is obtained by carrying out exclusive OR logic operation on each piece of physical address data updated into the L2P table, so that the whole L2P table only needs to correspond to one check code, and the exclusive OR logic operation is convenient for obtaining a reliable true value corresponding to the original physical address data through back calculation at the later stage, thereby being beneficial to guaranteeing the reliability of the physical address data in the L2P table through the true value.
Furthermore, the check code is obtained by exclusive OR logic operation of the physical address data, so that the byte number of the check code occupying the storage space can be the same as the byte number occupied by any one physical address data, namely the check code occupies little storage space, and therefore, the check code can be stored by utilizing a memory in the solid state disk without designing other memories for the check code.
Optionally, the data processing apparatus 500 further includes: a detection module (not shown in fig. 5) that may be used to detect whether there is a bit reversal in the second physical address data buffered in the L2P table.
Optionally, the detecting module may perform the following operations when detecting whether there is bit inversion in the second physical address data buffered in the L2P table:
acquiring the current value of the check code from the target memory;
determining first address data according to the current value of the check code, wherein the first address data is obtained by exclusive OR logic operation of the current value of the check code and all other physical address data which are cached in the L2P table except the second physical address data;
determining whether the second physical address data is consistent with the first address data, and determining that the second physical address data has bit inversion when the second physical address data is inconsistent with the first address data.
Optionally, the detection module may be further configured to perform the following operations: after determining that the second physical address data has bit inversion, determining bit of the second physical address data with bit inversion according to the first address data;
and/or after determining that the second physical address data has bit inversion, correcting the bit of the second physical address data with bit inversion according to the first address data.
Optionally, when the target memory includes SRAM, the data processing apparatus 500 further includes: an SRAM operation module (not shown in fig. 5) for creating a target memory cell in the SRAM, the target memory cell for storing the check code.
Based on the same inventive concept, the embodiments of the present disclosure provide a data processing method, so as to perform reliable data processing on a physical address obtained from an L2P table when a solid state disk performs data operation, so as to ensure that the solid state disk performs safe and reliable data operation.
As shown in fig. 6, an embodiment of the present disclosure provides a data processing method, which may include:
step S602, a data operation instruction initiated by a host to a solid state disk is received, wherein the data operation instruction comprises logic address data corresponding to an operated target flash memory.
When data operation (such as reading data, writing data, erasing data, etc.) is performed on the data in the solid state disk, generally, the host computer sends out an operation instruction and gives out logical address data corresponding to the corresponding data operation, so that the controller of the solid state disk executes the data operation after passing through the L2P table according to the logical address data.
It should be noted that, the Host (Host) may be a related device that needs to initiate a data operation on data in the solid state disk, for example, a data system, a file system, a reader-writer, and other devices, where these devices may be devices inside the solid state disk or may be devices outside the solid state disk, which is not limited herein.
Step S604, determining target physical address data corresponding to the logical address data from an L2P table, where the L2P table is cached in the DDR of the solid state disk.
As described above, the L2P table is stored in the DDR inside the solid state disk, and the data of the L2P table includes the mapping relationship between the logical address and the physical address, so that after the logical address data is received, the physical address corresponding to the logical address can be obtained based on the L2P table.
However, in view of the DDR characteristics, bit inversion of physical address data in the L2P table is easily caused, that is, the data in the L2P table is easily subject to errors, and once a data operation is performed according to the erroneous physical address data, the data operation causing the solid state disk to have errors, even an illegal data operation, will be caused. Therefore, the data processing method provided in the present specification further needs to perform data operations after further data processing on the physical address data.
Step S606, obtaining the current value of the check code, wherein the current value of the check code is data obtained by performing exclusive OR logic operation on all physical address data cached in the L2P table before caching in the L2P table, the current value of the check code is cached in a target memory, and the target memory is not the DDR.
As in the foregoing example, the physical address back calculation may be performed according to the check code to obtain the reliable real value of the physical address, so that the current value of the check code, that is, the check code corresponding to all the physical address data in the current L2P table, needs to be obtained.
Step S608, determining the first address data according to the current value of the check code, that is, calculating the first address data according to the check code, where the back calculation is as follows: the first address data is obtained by exclusive OR logic operation of the current value of the check code and all other physical address data which are cached in the L2P table except the target physical address data.
And (3) calculating the corresponding reliable true value (namely the first address data) of the target physical address data before updating the target physical address data into the L2P table through the check code and all other physical address data except the target physical address data in the L2P table. It should be noted that, the back calculation process may refer to the foregoing description, and will not be repeated.
Step S610, executing the data operation instruction on the target flash memory according to the first address data.
In implementation, when the data operation instruction is executed on the target flash memory according to the first address data, the data operation instruction may be executed on the target flash memory directly according to the first address data, or after the target physical address data is determined to be correct according to the first address data, the data operation instruction may be executed according to the target physical address data, which is not limited herein.
Through the steps S602 to S610, the reliable real value corresponding to the target physical address data of the data operation is calculated based on the check code and the physical address data of the L2P table, so that the data operation can be performed according to the real value, and the safety and reliability of the solid state disk in performing the data operation are ensured.
In some embodiments, in executing the data operation, the solid state disk may further detect and maintain data correctness of the L2P table, so the data processing method may further include: and determining whether bit inversion exists in the target physical address data according to the first address data. By detecting the bit reversal condition, the physical address in the L2P table can be ensured to be correct and reliable, and the reliability and the safety of the data operation of the solid state disk based on the L2P table can be ensured.
The maintenance of the bit inversion detection may be performed when the data operation instruction is received, or may be performed during an idle period, which is not limited herein.
In some embodiments, after determining that the target physical address data has a bit reversal, a related maintenance operation may also be performed for the bit reversal case.
In one example, bits of the target physical address data in which bit inversion occurs may be determined from the first address data, i.e., it is determined which bits of the target physical address data in which bit inversion occurs. Therefore, even if a plurality of bits are bit-reversed, it is possible to accurately detect which bits are bit-reversed based on the real, reliable first address data.
In one example, the bit with the bit inversion in the target physical address data may be corrected according to the first address data, that is, the bit with the bit inversion may be accurately corrected based on the real and reliable first address data, so as to correct the target physical address to a correct address.
Based on the same inventive concept, the embodiments of the present disclosure further provide a data processing apparatus for performing data operations on a solid state disk.
As shown in fig. 7, the embodiment of the present disclosure further provides a data processing apparatus 700, which is applied to a controller of a solid state disk, where the data processing apparatus 700 includes: a second receiving module 701, a second determining module 703, a first obtaining module 705, a first calculating module 707 and a second control module 709.
Specifically, the second receiving module 701 is configured to receive a data operation instruction initiated by a host to the solid state disk, where the data operation instruction includes logical address data corresponding to the operated target flash memory;
the second determining module 703 is configured to determine target physical address data corresponding to the logical address data from an L2P table, where the L2P table is cached in the DDR of the solid state disk;
the first obtaining module 705 is configured to obtain a current value of a check code, where the current value of the check code is data obtained by performing exclusive or logic operation on all physical address data cached in the L2P table before caching in the L2P table, and the current value of the check code is cached in a target memory, where the target memory is not the DDR;
the first calculation module 707 is configured to determine first address data according to the current value of the check code, where the first address data is obtained by performing exclusive-or logic operation on the current value of the check code and all other physical address data that are already cached in the L2P table except for the target physical address data;
The second control module 709 is configured to execute the data operation instruction on the target flash memory according to the first address data.
Optionally, the data processing apparatus 700 further includes: an error correction module (not shown in fig. 7) for determining whether or not there is bit inversion of the target physical address data based on the first address data.
Optionally, the error correction module is specifically configured to perform the following operations: after determining that the target physical address data has bit inversion, determining bit with bit inversion in the target physical address data according to the first address data; and/or correcting the bit with the bit inversion in the target physical address data according to the first address data.
Based on the same inventive concept, the embodiments of the present disclosure provide an electronic device for data processing, corresponding to the data processing method of any one of the foregoing embodiments, the electronic device including at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform: a data processing method as in any of the embodiments of the present specification.
Based on the same inventive concept, the embodiments of the present specification provide a computer storage medium for data processing, the computer storage medium storing computer executable instructions that, when executed by a processor, perform the data processing method as provided in any of the embodiments of the present specification.
Note that the computer storage medium may include, but is not limited to: portable disk, hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.
In a possible implementation, the application may also provide that the data processing is implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps of the method as described in any of the preceding embodiments, when said program product is run on the terminal device.
Wherein the program code for performing the present application may be written in any combination of one or more programming languages, which program code may execute entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device, partly on the remote device or entirely on the remote device.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment focuses on differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. The data processing method is characterized by being applied to a controller of a solid state disk, and comprises the following steps of:
receiving a data update request for an L2P table, wherein the L2P table is cached in the DDR of a solid state disk, and the data update request contains first physical address data to be updated into the L2P table;
determining a new value of a check code according to the first physical address data, wherein the new value of the check code is obtained by performing exclusive OR logic operation on an old value of the check code and the first physical address data, and the old value of the check code is a numerical value corresponding to the check code before the new value of the check code is generated;
Updating a new value of the check code to a target memory to update an old value of the check code, and updating the first physical address data into the L2P table, wherein the target memory is not the DDR;
after determining that the second physical address data in the L2P table has bit inversion, determining bit positions with bit inversion in the second physical address data according to the first address data; the first address data is obtained by exclusive OR logic operation of the current value of the check code and all other physical address data which are cached in the L2P table except the second physical address data;
and/or correcting the bit with the bit inversion in the second physical address data according to the first address data;
wherein detecting whether there is bit inversion in the second physical address data cached in the L2P table includes:
acquiring the current value of the check code from the target memory;
determining first address data according to the current value of the check code;
determining whether the second physical address data is consistent with the first address data, and determining that the second physical address data has bit inversion when the second physical address data is inconsistent with the first address data.
2. The data processing method according to claim 1, wherein when the target memory includes an SRAM, the data processing method further comprises: and creating a target storage unit in the SRAM, wherein the target storage unit is used for storing the check code.
3. The data processing method is characterized by being applied to a controller of a solid state disk, and comprises the following steps of:
receiving a data operation instruction initiated by a host to a solid state disk, wherein the data operation instruction comprises logic address data corresponding to an operated target flash memory;
determining target physical address data corresponding to the logic address data from an L2P table, wherein the L2P table is cached in the DDR of the solid state disk;
acquiring a current value of a check code, wherein the current value of the check code is data obtained by performing exclusive-or logic operation on all physical address data cached in the L2P table before caching in the L2P table, the current value of the check code is cached in a target memory, and the target memory is not the DDR;
determining first address data according to the current value of the check code, wherein the first address data is obtained by performing exclusive OR logic operation on the current value of the check code and all other physical address data which are cached in the L2P table except the target physical address data;
Executing the data operation instruction on the target flash memory according to the first address data;
after determining that the second physical address data in the L2P table has bit inversion, determining bit positions with bit inversion in the second physical address data according to the first address data; the first address data is obtained by exclusive OR logic operation of the current value of the check code and all other physical address data which are cached in the L2P table except the second physical address data;
and/or correcting the bit with the bit inversion in the second physical address data according to the first address data;
wherein detecting whether there is bit inversion in the second physical address data cached in the L2P table includes:
acquiring the current value of the check code from the target memory;
determining first address data according to the current value of the check code;
determining whether the second physical address data is consistent with the first address data, and determining that the second physical address data has bit inversion when the second physical address data is inconsistent with the first address data.
4. A data processing apparatus, characterized by a controller applied to a solid state disk, the data processing apparatus comprising:
The data updating module is used for receiving a data updating request for an L2P table, wherein the L2P table is cached in the DDR of the solid state disk, and the data updating request comprises first physical address data to be updated into the L2P table;
the first determining module is used for determining a new value of the check code according to the first physical address data, wherein the new value of the check code is obtained by performing exclusive OR logic operation on the old value of the check code and the first physical address data, and the old value of the check code is a numerical value corresponding to the check code before the new value of the check code is generated;
a first control module that updates a new value of the check code to a target memory to update an old value of the check code, and updates the first physical address data to the L2P table, wherein the target memory is not the DDR; after determining that the second physical address data in the L2P table has bit inversion, determining bit positions with bit inversion in the second physical address data according to the first address data; the first address data is obtained by exclusive OR logic operation of the current value of the check code and all other physical address data which are cached in the L2P table except the second physical address data;
And/or correcting the bit with the bit inversion in the second physical address data according to the first address data;
wherein it is detected whether there is a bit reversal in the second physical address data buffered in the L2P table by: acquiring the current value of the check code from the target memory; determining first address data according to the current value of the check code; determining whether the second physical address data is consistent with the first address data, and determining that the second physical address data has bit inversion when the second physical address data is inconsistent with the first address data.
5. A data processing apparatus, characterized by a controller applied to a solid state disk, the data processing apparatus comprising:
the second receiving module is used for receiving a data operation instruction initiated by the host to the solid state disk, wherein the data operation instruction comprises logic address data corresponding to the operated target flash memory;
the second determining module determines target physical address data corresponding to the logic address data from an L2P table, wherein the L2P table is cached in the DDR of the solid state disk;
the first acquisition module acquires the current value of a check code, wherein the current value of the check code is data obtained by carrying out exclusive OR logic operation on all physical address data cached in the L2P table before caching in the L2P table, the current value of the check code is cached in a target memory, and the target memory is not the DDR;
The first calculation module is used for determining first address data according to the current value of the check code, wherein the first address data is obtained by performing exclusive OR logic operation on the current value of the check code and all other physical address data which are cached in the L2P table except the target physical address data;
the second control module executes the data operation instruction on the target flash memory according to the first address data; after determining that the second physical address data in the L2P table has bit inversion, determining bit positions with bit inversion in the second physical address data according to the first address data; the first address data is obtained by exclusive OR logic operation of the current value of the check code and all other physical address data which are cached in the L2P table except the second physical address data;
and/or correcting the bit with the bit inversion in the second physical address data according to the first address data;
wherein it is detected whether there is a bit reversal in the second physical address data buffered in the L2P table by: acquiring the current value of the check code from the target memory; determining first address data according to the current value of the check code; determining whether the second physical address data is consistent with the first address data, and determining that the second physical address data has bit inversion when the second physical address data is inconsistent with the first address data.
6. An electronic device, comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform: a data processing method as claimed in any one of claims 1 to 4.
7. A computer storage medium storing computer executable instructions which, when executed by a processor, perform the data processing method of any one of claims 1-4.
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