CN114741342A

CN114741342A - Method and related device for updating mapping relation

Info

Publication number: CN114741342A
Application number: CN202110018186.3A
Authority: CN
Inventors: 张陈旭; 罗小东
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-01-07
Filing date: 2021-01-07
Publication date: 2022-07-12

Abstract

The embodiment of the application discloses a method and a related device for updating a mapping relation, which are used in the field of communication. In the method of the embodiment of the present application, a target partition is first determined from a plurality of partitions of a global virtual address GVA, each of the plurality of partitions includes a part GVA, and then a mapping relationship between the part GVA included in the target partition and a local virtual address LVA is updated.

Description

Method and related device for updating mapping relation

Technical Field

The embodiment of the present application relates to the field of communications, and in particular, to a method for updating a mapping relationship and a related apparatus.

Background

In a distributed system supporting a Remote Direct Memory Access (RDMA) network, a node can remotely read and write the memory of other nodes through an RDMA protocol, a distributed shared memory system can be realized based on the technology, and based on the system, a user process can fully utilize the memory resources in all nodes. Specifically, in the distributed shared memory system, two layers of mappings may be established, where for a Global Virtual Address (GVA) of a segment of memory, a Local Virtual Address (LVA) of a fixed node is mapped, and for an LVA, a local Physical Address (PA) is mapped continuously. Therefore, when a user applies for a section of global memory space, the distributed system needs to apply for a physical space as a PA on a selected node, register the PA with a network card to register a memory area (MR), generate an LVA accessible from a remote end, record the mapping from the LVA to the PA in a local address mapping table, and establish the mapping from the GVA to the LVA in the global address mapping table, thereby completing the application of the whole global memory.

Based on the above mechanism, the mapping relationship from the LVA to the PA in the local address mapping table needs to be modified when the physical memory address is changed. However, in the distributed system, the local address mapping table is stored in the network card, and the network card does not support the modification of the mapping from the LVA to the PA, so that the memory address can be changed only by modifying the mapping relationship from the GVA to the LVA in the local address mapping table. Before the above modification operation is performed, all nodes need to be notified to delete the mapping cache of the cache that needs to be modified, and after all nodes are successfully deleted, the mapping from the GVA to the LVA in the local address mapping table is modified, which results in low updating efficiency of the mapping relationship.

Disclosure of Invention

The embodiment of the application provides a method and a related device for updating a mapping relation, and the mapping relation between the GVA of the target partition part and the LVA of the local virtual address is only required to be updated, and the mapping relation in other partitions is not required to be updated, so that the updating efficiency of the mapping relation is improved.

In a first aspect of the embodiments of the present application, a method for updating a mapping relationship is provided, in which a target partition is first determined from multiple partitions of a global virtual address GVA, and each of the multiple partitions contains a part GVA, and then a mapping relationship between the part GVA contained in the target partition and a local virtual address LVA is updated.

In this embodiment, only the mapping relationship between the target partition portion GVA and the local virtual address LVA needs to be updated, and the mapping relationship in other partitions does not need to be updated, so that the efficiency of updating the mapping relationship is improved.

In an alternative embodiment of the present application, the target partition is determined by comparing version numbers of the plurality of partitions, and the version number of the target partition is different from version numbers of other partitions in the plurality of partitions.

In this embodiment, by comparing the version numbers of a plurality of partitions, it is determined that a partition different from the version numbers of other partitions needs to update the mapping relationship, and therefore it is possible to determine that the partition is the target partition, thereby improving the feasibility of the scheme.

In an alternative embodiment of the present application, before updating the mapping relationship between the partial GVA and the local virtual address LVA in the target partition, the memory access to the target partition needs to be frozen.

In the embodiment, the memory access to the target partition is frozen, so that the influence on the memory access when the mapping relation is updated is reduced, and the service quality is improved.

In an optional implementation manner of the present application, specifically, the access prohibition flag is set for the target partition, so as to achieve the purpose of freezing the memory access to the target partition.

In this embodiment, the access prohibition flag is validated, and the memory access to the target partition is stopped, thereby improving the feasibility of the scheme.

In an optional embodiment of the present application, because the memory access to the target partition is frozen before the mapping relationship is updated, after the mapping relationship between the partial GVA in the target partition and the local virtual address LVA is updated, the memory access to the target partition needs to be recovered.

In the embodiment, the service of the memory access to the target memory is timely recovered after the mapping relation is updated by recovering the memory access to the target partition, so that the service quality is further improved.

In an optional implementation manner of the present application, the purpose of resuming the memory access to the target partition is achieved by specifically clearing the access prohibition flag set for the target partition.

In this embodiment, the access prohibition flag is cleared, and the memory access to the target partition is resumed, thereby improving the feasibility of the scheme.

In an optional embodiment of the present application, specifically, the mapping cache of the mapping relationship between the part GVA and the LVA in the target partition is deleted, and the updated mapping relationship between the part GVA and the LVA in the target partition is loaded to the mapping cache, so as to update the mapping relationship between the part GVA and the local virtual address LVA in the target partition.

In this embodiment, by deleting the mapping cache of the non-updated mapping relationship, it is ensured that the mapping cache is not used for determining the address through the non-updated mapping relationship when performing the memory access, and then, the mapping relationship of the part of the GVA and the LVA in the updated target partition is loaded to the mapping cache, so that when the memory access to the target partition is restored after the update, the address can be determined through the latest mapping relationship of the GVA and the LVA, and on the basis of improving the feasibility of the scheme, the accuracy and reliability of the address determination can be improved.

In an alternative embodiment of the present application, the partition is based on a scatter algorithm to scatter the GVA.

In this embodiment, the GVA is broken up to obtain a plurality of partitions, and each partition includes at least one mapping relationship between the LVA and the PA, so that when performing memory access, a required PA can be accurately determined by the plurality of partitions, thereby improving feasibility and reliability of the scheme.

A second aspect of an embodiment of the present application provides a mapping relationship updating apparatus, including:

a determining module for determining a target partition from a plurality of partitions of the global virtual address GVA, wherein each partition contains a portion GVA;

and the updating module is used for updating the mapping relation between the part GVA and the local virtual address LVA contained in the target partition.

In an optional implementation manner of the present application, the determining module is specifically configured to compare version numbers of the plurality of partitions, and determine the target partition, where the version number of the target partition is different from version numbers of other partitions in the plurality of partitions.

In another optional implementation manner of the present application, the mapping relationship updating apparatus further includes a freezing module;

and the freezing module is used for freezing the memory access to the target partition before the updating module updates the mapping relation between the part of GVA in the target partition and the local virtual address LVA.

In another optional implementation manner of the present application, the freezing module is specifically configured to set an access prohibition flag for the target partition.

In another optional implementation manner of the present application, the mapping relationship updating apparatus further includes a recovery module;

and the recovery module is used for recovering the memory access of the target partition after the update module finishes updating the mapping relation between the part GVA and the local virtual address LVA in the target partition.

In another optional embodiment of the present application, the recovery module is specifically configured to clear the prohibited-access flag.

In another optional implementation manner of the present application, the update module is specifically configured to:

deleting the mapping cache of the mapping relation of part of GVA and LVA in the target partition;

and loading the updated mapping relation of the part GVA and the part LVA in the target partition to a mapping cache.

In another alternative embodiment of the present application, the plurality of partitions are based on a scatter algorithm to scatter the GVA.

In a third aspect of the embodiments of the present application, a terminal device is provided, where the terminal device may be a mapping relationship updating apparatus designed in the foregoing method, or a chip provided in the mapping relationship updating apparatus. The terminal device includes: and a processor, coupled to the memory, and configured to execute the instructions in the memory to implement the method performed by the mapping relation updating apparatus in the first aspect and any one of the possible implementations of the first aspect. Optionally, the terminal device further comprises a memory. Optionally, the terminal device further comprises a communication interface, the processor being coupled to the communication interface.

When the terminal device is the mapping relation updating apparatus, the communication interface may be a transceiver, or an input/output interface.

When the terminal device is a chip provided in the mapping relationship updating apparatus, the communication interface may be an input/output interface.

Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input/output interface may be an input/output circuit.

A fourth aspect of the embodiments of the present application provides a node, where the node includes a processor and a network card, where the processor is in communication with the network card, and the network card executes the method in any one of the foregoing first aspect or possible implementation manners of the first aspect.

In a fifth aspect of embodiments of the present application, a program is provided, which, when being executed by a processor, is configured to perform the method in the first aspect or any one of the possible implementation manners of the first aspect.

A sixth aspect of the embodiments of the present application provides a computer program product (or computer program) storing one or more computers, and when the computer program product is executed by a processor, the processor executes the method in the first aspect or any one of the possible implementation manners of the first aspect.

A seventh aspect of the embodiments of the present application provides a network card, where the network card includes a processor and an interface, where the processor is connected to the interface, and the processor executes the method in the first aspect or any one of the possible implementation manners of the first aspect.

In an eighth aspect of embodiments of the present application, a computer-readable storage medium is provided, where the computer-readable storage medium stores a program, and the program enables a terminal device to execute any one of the methods in the first aspect and the possible implementation manners.

It should be noted that, the advantageous effects brought by the embodiments of the second aspect to the eighth aspect of the present application, and the description of the embodiments of the aspects may be understood with reference to the embodiments of the first aspect, and therefore, repeated descriptions are omitted.

Drawings

FIG. 1 is a schematic diagram of an architecture of a memory system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another architecture of a memory system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an architecture of a storage device according to an embodiment of the present application;

fig. 4 is a schematic diagram illustrating an architecture of a network card in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a distributed shared memory system according to an embodiment of the present application;

FIG. 6 is a diagram of an embodiment of a method for updating a mapping relationship in an embodiment of the present application;

fig. 7 is a schematic diagram of an embodiment of a mapping relationship updating apparatus in an embodiment of the present application.

Detailed Description

In order to make the above objects, technical solutions and advantages of the present application more comprehensible, detailed descriptions are provided below. The detailed description sets forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and/or examples. Because such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or any combination thereof. The terms "first," "second," "third," "fourth," and the like in the description and in the claims and drawings of the present application, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The architecture of the storage system provided in the embodiment of the present application is as shown in fig. 1, and fig. 1 is a schematic architecture diagram of the storage system in the embodiment of the present application, as shown in the figure, a storage node 120 is connected with a client 130 through a network 110, and the client 130 performs data transmission with the storage node 120 through the network 110. For convenience of description, the embodiment of the present application only illustrates data transmission between one client 130 and one storage node 120. In practical applications, there may be a plurality of clients 130 and a plurality of storage nodes 120, and the number of clients 130 and storage nodes 120 should not be construed as a limitation to the embodiments of the present application.

Further, fig. 2 is another schematic architecture diagram of the storage system in the embodiment of the present application, as shown in fig. 2, the storage node 120 includes a processor 121, a memory 122, a plurality of storage devices 124 and a network card 125 that are connected through a bus 123.

Processor 121 is the control center for storage node 120. Optionally, processor 121 includes one or more Central Processing Units (CPUs), which may each be a single-core or multi-core CPU. The term "processor" as used herein refers to one or more devices, circuits, and/or processing cores that process program instructions.

The memory 122 is used for storing program instructions, and the processor 121 obtains the program instructions from the memory 122 and executes the program instructions. Illustratively, the Memory 122 may be a Random Access Memory (RAM).

The bus 123 is used to transfer data between the processor 121, the storage device 124, and the network card 125. Illustratively, the bus 123 may be a Peripheral component interconnect express (PCIe) bus.

Storage device 124 is used to permanently store data from client 130. The storage device 124 may be various types of hard disks, such as a Solid State Drive (SSD) or a mechanical disk. The interface of the hard disk may be a Serial Attached SCSI (SAS) interface, a Fiber Channel (FC) interface, or a PCIe interface, where the SCSI (small Computer System interface) is a small machine System interface. The structure of the storage device 124 is shown in fig. 3.

The storage node 120 and the client 130 transmit data with the client's network card 135 via the storage node's network card 125. Alternatively, the structure of the client 130 may refer to the storage node 120, and the client 130 may also be a server, a computing device, or other devices that may serve as a host in the art.

Fig. 3 is a schematic diagram of an architecture of a storage device according to an embodiment of the present invention, and as shown in fig. 3, the storage device 124 includes a memory 302 and a persistent storage medium 303 connected to a processor 301. Processor 301 is the control center for storage device 124. The processor 301 includes registers for temporarily storing instructions, data, and addresses of the processor 301. The memory 302 is used for storing program instructions, and the processor 301 executes the program instructions in the memory 302 to implement functions corresponding to the program instructions. The persistent storage medium 303 may be a flash memory, a magnetic disk, or the like for persistently storing data. Optionally, the memory 302 of the storage device may be a part of the storage device processor 301, that is, the storage device in fig. 3 may include the processor 301 and the persistent storage medium 303, and the memory 302 in fig. 3 is implemented by a memory cache.

Fig. 4 is a schematic diagram of an architecture of a network card in an embodiment of the present application, and as shown in fig. 4, the network card 125 includes a processor 401 and an interface 402, and the processor 401 and the interface 402 are connected to each other. The processor 401 is a control center of the network, and the interface 402 is used for transmitting data received by the network card. In addition, the network card may further include a cache for storing program instructions, and the processor 401 executes the program instructions in the cache to implement the functions corresponding to the program instructions.

The storage node 120 may be an enterprise-level storage device or server or any other device having a similar structure as shown at 120 in fig. 2.

In this embodiment, the network card 125 stores a mapping relationship from global GVA to LVA and a mapping relationship from LVA to PA in the storage node, and the memory 122 of each storage device 124 stores a mapping relationship from global GVA to LVA and a mapping relationship from LVA to PA corresponding to the storage device 124.

For further understanding of the embodiments of the present application, some terms or concepts related to the embodiments of the present application are explained below to facilitate understanding by those skilled in the art.

Remote Direct Memory Access (RDMA)

RDMA is a technology that enables one computer to directly transfer data from a memory to another computer memory through a network, and first copies data to an NIC (network card) through a Direct Memory Access (DMA) mode, and then transmits the data to a remote NIC through the network, and then directly reaches the remote memory, without an operating system having to refer to copy data in a buffer and a Central Processing Unit (CPU) multiple times, thereby reducing the need for bandwidth and processor overhead and reducing latency.

Second, exchange (SWAP)

SWAP refers to exchanging data between a high-speed medium and a low-speed medium, replacing data with low access frequency into the low-speed medium, and loading the data back into the high-speed medium before accessing again to achieve the purpose of expanding the space of the high-speed medium.

Thirdly, garbage recovery (garboge collection, GC)

When partial data is invalid, more fragments exist in the storage space, and effective data in the storage space is moved to a new storage space through garbage collection, so that the purpose of releasing the fragment space is achieved.

Four, layered storage (Tier)

The storage medium is divided into different hierarchies according to performance and capacity, and data is migrated among the different hierarchies according to the access heat.

Based on the technology, in the distributed system supporting the RDMA network, a client can remotely read and write the memory of other storage nodes through the RDMA protocol, and a distributed shared memory system can be realized based on the technology, so that the distributed shared memory system is further based on the distributed shared memory system. For convenience of understanding, referring to fig. 5, fig. 5 is a schematic structural diagram of a distributed shared memory system in an embodiment of the present application, as shown in fig. 5, the distributed shared memory system may globally and uniformly address memories of all clients and storage nodes (fig. 5 only shows a case of 1 client and 2 storage nodes, actually in the distributed shared memory system, a client and a storage node are many-to-many), and all nodes (including a client and a storage node) in the distributed shared memory system may access a global memory address through RDMA to achieve the purpose of global memory sharing, so that a user process may fully utilize memory resources in all nodes in all the distributed shared memory system. The operations corresponding to the memory access include, but are not limited to, an application allocation (Alloc) operation, a release application (Free) operation, a Read application (Read) operation or a Write application (Write) operation.

In the distributed shared memory system, two layers of mapping can be established, the first layer is a global address mapping table, in the global address mapping table, the GVA is mapped to a segment of LVA of a plurality of nodes, the second layer is a local address mapping table, and the LVA of each node is mapped to a segment of local PA continuously. Therefore, when a user applies for a section of global memory space, a physical space needs to be applied on a selected node as a PA, the PA is registered to a network card, an LVA which can be accessed by a remote end is generated, then the mapping from the LVA to the PA is recorded in a local address mapping table, the mapping from the GVA to the LVA is applied and established in the global address mapping table and broadcast is carried out in the nodes of the whole network, and therefore the application of the whole global memory is completed. Secondly, when a node needs to access a certain global memory address, firstly, the mapping relation from the GVA to the LVA in the global address mapping table is inquired, then RDMA access is carried out on the accessed node through the LVA, and the mapping relation from the LVA to the PA found in the local mapping table by the network card of the accessed node is used for accessing the physical address. In order to improve the access efficiency, a global mapping table, that is, a mapping relationship from GVA to LVA, is usually cached at a node initiating a global memory access, however, in a scenario such as SWAP, GC, Tier, etc., a logical address needs to be remapped to another physical address, and at this time, validity and consistency of global mapping information need to be ensured, so as to avoid reading and writing an incorrect memory address.

In the distributed system, the address mapping table of each storage node includes a global mapping table, specifically, a mapping relationship from a global GVA to an LVA of each node and a local mapping table, specifically, a mapping relationship from an LVA of a local node to a PA, and the address mapping table is stored in a network card, while the network card does not support dynamic registration, that is, does not support modifying the mapping from the LVA to the PA in the local mapping table, so that the memory address can only be changed by modifying the mapping relationship from the GVA to the LVA in the address mapping table of the node. Further, when the global mapping relationship from the GVA to the LVA in the address mapping table needs to be modified, the mapping cache needing to be modified needs to be broadcast and deleted to all the nodes in the cluster, and after all the nodes are successfully deleted, the mapping relationship needing to be modified on all the nodes is updated, so that the efficiency of updating the mapping relationship is reduced.

In order to solve the above problem, an embodiment of the present application provides a method for updating a mapping relationship, where a GVA is broken into multiple partitions, a target partition corresponding to a mapping relationship from the GVA to the LVA needs to be modified is determined, and then only a mapping relationship from the GVA to the LVA in the target partition needs to be updated, and a mapping relationship in another partition does not need to be updated, so as to improve efficiency of updating the mapping relationship. It can be understood that the method provided by the embodiment of the present application is not limited to map updating, and the method provided by the embodiment of the present application may also be used in a scenario where global broadcast of update data is required in a distributed system, and may also improve the efficiency of updating data.

For convenience of understanding, the method for updating the mapping relationship used in the embodiment of the present application is described in detail below, please refer to fig. 6, fig. 6 is a schematic diagram of an embodiment of the method for updating the mapping relationship in the embodiment of the present application, and as shown in fig. 6, the method for updating the mapping relationship includes the following steps.

S601, the client determines a plurality of partitions of global virtual addresses GVA;

in this embodiment, the client performs unified partitioning on the global virtual address GVA to determine multiple partitions, and the process of unified partitioning may be configured by an administrator. On this basis, each partition contains a global virtual address GVA part, i.e. in the global address mapping table, each GVA partition corresponds to at least one LVA space, i.e. the GVA space and the LVA space in the GVA partition are one-to-many.

Specifically, the partitions are obtained by scattering the GVA in the global address mapping table based on a scattering algorithm.

Further, the client may also obtain a first message, and the first message may be used to indicate that the version numbers of the plurality of partitions are updated. The client is capable of determining the updated version numbers of the plurality of partitions after updating the version numbers of the plurality of partitions according to the first message. For example, the version number of the plurality of partitions before the update is "1.2.2", and the version number of the plurality of partitions after the update is "1.2.4".

S602, determining a target partition from a plurality of partitions of the global virtual address GVA by the storage node;

in this embodiment, the storage node needs to determine the target partition from the plurality of partitions of the global virtual address GVA.

Further, the storage node first needs to obtain a second message, where the second message is used to instruct the memory access to the partition to be updated in the multiple partitions. The memory access includes an application allocation (Alloc), an application release (Free), an application data Read (Read) or an application data Write (Write), and the specific type of the memory access is not limited herein. The second message may access a part of the GVA in the partition, and the specific second message carries address information of the part of the GVA, and the GVA partition corresponding to the part of the GVA is determined as the target partition by querying in the plurality of partitions.

Further, since the second message obtained by the storage node indicates to perform memory access on the partition to be updated in the plurality of partitions, in order to ensure that the memory access can be performed smoothly, the storage node needs to determine the version number of the partition to be updated. For example, the version number of the partition to be updated is "1.2.0".

Specifically, since the client can determine the version numbers of the updated partitions in step S601, the storage node further needs to obtain the version numbers of the updated partitions from the client, compare the determined version numbers of the partitions to be updated with the version numbers of the updated partitions, and determine that the partition to be updated is the target partition when the version number of the partition to be updated is different from the version number of the updated partitions. For example, if the version number of the updated plurality of partitions is "1.2.4" and the version number of the partition to be updated is "1.2.0", the storage node may determine that the partition to be updated is the target partition.

Still further, before the client updates the mapping relationship between the GVA and the LVA in the target partition, the storage node may also delete the mapping cache of the mapping relationship between the GVA and the LVA in the target partition. If the corresponding relation between the partial GVA and the partial LVA in the target partition is updated, the partial GVA and the partial LVA in the target partition can be deleted, and the updating efficiency is further improved.

S603, the client acquires update information, wherein the update information indicates that the mapping relation between the GVA and the local virtual address LVA in the target partition is updated;

in this embodiment, the client obtains the update information sent by the storage node, and the update information indicates that the client updates the mapping relationship between the GVA and the LVA in the target partition. If the storage node updates the mapping relationship between the partial GVA and the partial LVA, the client can acquire the information of the mapping relationship between the partial GVA and the partial LVA from the storage node.

It may be understood that there is no timing limitation between the step S603 and the step S602 for the storage node to delete the mapping between the GVA and the LVA in the target partition, that is, the step S603 and the step S602 for the storage node to delete the mapping between the GVA and the LVA in the target partition may be performed at the same time, and the step S603 and the step S602 for the storage node to delete the mapping between the GVA and the LVA in the target partition may also be performed in sequence, and the specific timing is not to be construed as a limitation of the present application.

Secondly, since the memory access may be affected when the mapping relationship is updated when the client performs the memory access, the storage node needs to temporarily freeze the memory access when the client updates the mapping relationship, and then resume the memory access after the client completes the updating of the mapping relationship. Specifically, in this embodiment, each GVA partition carries an access prohibition identifier, before the client updates the mapping relationship between the GVA and the LVA in the target partition, the access prohibition identifier carried by the target partition becomes valid, at this time, the storage node freezes the memory access to the target partition, and the step S604 is triggered to be executed.

S604, the client updates the mapping relation between the partial GVA and the local virtual address LVA contained in the target partition.

In this embodiment, since the client indicates to update the mapping relationship between the GVA and the LVA in the target partition through the update information acquired in step S603, the client may update the mapping relationship between the partial GVA and the local virtual address LVA included in the target partition according to the update information, so as to obtain the updated mapping relationship between the GVA and the LVA. If the client can acquire the information of the mapping relationship of the partial GVA and the partial LVA from the storage node, the client can update the target partition according to the update information. Specifically, since the address mapping table is stored in the network card, and the network card does not support the modification of the mapping from the LVA to the PA in the local mapping table, when the memory address corresponding to the memory access is changed, the mapping relationship between the GVA and the local virtual address LVA corresponding to the memory access in the address mapping table of the node needs to be updated, so that the mapping relationship is updated partially in this embodiment.

Further, in step S603, before updating the mapping relationship between the GVA and the LVA in the target partition, the storage node may delete the mapping cache of the mapping relationship between the GVA and the LVA in the target partition. Therefore, after the client obtains the updated mapping relationship between the GVA and the LVA, the storage node needs to clear the access prohibition identifier carried by the target partition to recover the memory access to the target partition. And loading the updated mapping relation between the GVA and the LVA in the target partition to a mapping cache of the storage node to ensure that the mapping cache is the latest mapping relation between the GVA and the LVA in the target partition, thereby ensuring that the memory access of the target partition is not influenced.

Further, if the method for updating the mapping relationship provided by the embodiment of the present application is applied to a copy or other redundant systems, when the mapping relationship between the GVA and the LVA is updated, the accessibility of the corresponding data of the system can be ensured by accessing other redundant addresses, so that the service provided by the system to the outside is not affected. Because only the mapping relation in the target partition needs to be updated, the mapping relations in other partitions do not need to be updated, and the updating efficiency of the mapping relations is improved.

The scheme provided by the embodiment of the application is mainly introduced in the aspect of a method. It is to be understood that the mapping relation updating apparatus includes a hardware structure and/or a software module for performing each function in order to implement the above functions. Those of skill in the art will readily appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the mapping relationship updating apparatus may be divided into the functional modules based on the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

Therefore, the following describes the mapping relationship updating apparatus in the present application in detail, please refer to fig. 7, fig. 7 is a schematic diagram of an embodiment of the mapping relationship updating apparatus in the embodiment of the present application, and as shown in fig. 7, the mapping relationship updating apparatus 700 includes:

a determining module 701, configured to determine a target partition from multiple partitions of the global virtual address GVA, where each partition includes a partial GVA;

an updating module 702, configured to update a mapping relationship between a part of the GVA included in the target partition and the local virtual address LVA.

In some optional embodiments of the present application, the determining module 701 is specifically configured to compare version numbers of the plurality of partitions, and determine the target partition, where the version number of the target partition is different from the version numbers of other partitions in the plurality of partitions.

In some optional embodiments of the present application, the mapping relationship updating apparatus 700 further includes a freezing module 703;

the freezing module 703 is configured to freeze memory access to the target partition before the updating module 702 updates the mapping relationship between the partial GVA and the local virtual address LVA in the target partition.

In some optional embodiments of the present application, the freezing module 703 is specifically configured to set an access prohibition flag for the target partition.

In some optional embodiments of the present application, the mapping relation updating apparatus 700 further includes a recovery module 704;

a recovering module 704, configured to recover memory access to the target partition after the updating module 702 completes updating the mapping relationship between the partial GVA and the local virtual address LVA in the target partition.

In some optional embodiments of the present application, the recovery module 704 is specifically configured to clear the prohibited-access flag.

In some optional embodiments of the present application, the update module 702 is specifically configured to:

In some optional embodiments of the present application, the plurality of partitions is obtained by breaking the GVA based on a breaking algorithm.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor. To avoid repetition, it is not described in detail here.

It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip having signal processing capability. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor described above may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

It will be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM, enhanced SDRAM, SLDRAM, Synchronous Link DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

According to the method provided by the embodiment of the present application, the present application further provides a network card, where the network card includes a processor and an interface, the processor is connected to the interface, and the processor is the first aspect described above or the method in any one of the possible implementation manners of the first aspect.

According to the method provided by the embodiment of the present application, the present application further provides a node, where the node includes a processor and a network card, the processor is in communication connection with the network card, and the network card executes the method executed by the client and the storage node in the embodiment shown in fig. 6.

According to the method provided by the embodiment of the present application, the present application further provides a computer program product, which includes: computer program code which, when run on a computer, causes the computer to perform the method performed by the client and storage node in the embodiment shown in fig. 6.

According to the method provided by the embodiment of the present application, the present application also provides a computer-readable storage medium storing program code, which when run on a computer, causes the computer to execute the method executed by the client and the storage node in the embodiment shown in fig. 6.

As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between 2 or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for updating mapping relationship, comprising:

determining a target partition from a plurality of partitions of a global virtual address, GVA, wherein each partition contains a portion of the GVA;

and updating the mapping relation between the partial GVA contained in the target partition and the local virtual address LVA.

2. The method according to claim 1, wherein determining the target partition from the plurality of partitions of the global virtual address GVA comprises:

comparing version numbers of the plurality of partitions and determining the target partition, wherein the version number of the target partition is different from the version numbers of other partitions in the plurality of partitions.

3. The method according to claim 1, wherein before said updating the mapping relationship between the partial GVA and the local virtual address LVA in the target partition, the method further comprises:

memory access to the target partition is frozen.

4. The method of claim 3, wherein the freezing memory access to the target partition comprises:

and setting an access prohibition identifier for the target partition.

5. The method according to claim 4, wherein after completing updating the mapping relationship between the partial GVA and the Local Virtual Address (LVA) in the target partition, the method further comprises:

and restoring the memory access of the target partition.

6. The method of claim 5, wherein the resuming memory access to the target partition comprises:

and clearing the access prohibition identification.

7. The method according to claim 1, wherein said updating the mapping relationship between the partial GVA and the local virtual address LVA in the target partition comprises:

and loading the updated mapping relation of the partial GVA and the partial LVA in the target partition to the mapping cache.

8. A method according to any of claims 1 to 7, wherein said plurality of partitions are based on a scatter algorithm to scatter said GVA.

9. A mapping relationship updating apparatus, comprising:

a determining module for determining a target partition from a plurality of partitions of a global virtual address, GVA, wherein each partition contains a portion of the GVA;

10. The mapping relationship updating apparatus according to claim 9, wherein the determining module is specifically configured to compare version numbers of the plurality of partitions to determine the target partition, wherein the version number of the target partition is different from version numbers of other partitions in the plurality of partitions.

11. The mapping relationship updating apparatus according to claim 10, further comprising a freezing module;

the freezing module is configured to freeze memory access to the target partition before the updating module updates the mapping relationship between the partial GVA and the local virtual address LVA in the target partition.

12. The mapping relationship updating apparatus according to claim 11, wherein the freezing module is specifically configured to set an access prohibition flag for the target partition.

13. The mapping relationship updating apparatus according to claim 12, wherein the mapping relationship updating apparatus further comprises a recovery module;

and the recovery module is configured to recover the memory access to the target partition after the update module completes updating the mapping relationship between the partial GVA and the local virtual address LVA in the target partition.

14. The mapping relationship updating apparatus according to claim 13, wherein the recovery module is specifically configured to clear the prohibited-access flag.

15. The mapping relationship updating apparatus according to claim 9, wherein the updating module is specifically configured to:

16. The mapping relationship updating apparatus according to any of claims 9 to 15, wherein the plurality of partitions are obtained by breaking up the GVA based on a breaking algorithm.

17. A node, comprising a processor and a network card, the processor and the network card communicatively coupled, the network card performing the method of any of claims 1 to 8.

18. A network card comprising a processor and an interface, said processor being connected to said interface, said processor performing the method of any one of claims 1 to 8.

19. A computer program product, characterized in that the computer program product, when executed on a computer, causes the computer to perform the method according to any of claims 1 to 8.

20. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the method of any of claims 1 to 8.