CN114741336A

CN114741336A - Method for adjusting Host side cache region in memory, electronic equipment and chip system

Info

Publication number: CN114741336A
Application number: CN202210645452.XA
Authority: CN
Inventors: 周小航
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-06-09
Filing date: 2022-06-09
Publication date: 2022-07-12
Anticipated expiration: 2042-06-09
Also published as: CN114741336B

Abstract

The application provides a method for adjusting a Host side cache region in a memory, electronic equipment and a chip system, and relates to the technical field of storage; the method can adjust the size of the cache region at the Host side in the system memory according to the load condition of the system, thereby realizing the dynamic adjustment of the size of the memory used by the system, and further reducing the problem that the system load is heavier due to more system memories which are pre-occupied in the electronic equipment adopting the UFS device.

Description

Method for adjusting cache region on Host side in memory, electronic equipment and chip system

Technical Field

The present application relates to the field of storage technologies, and in particular, to a method for adjusting a cache region on a Host side in a memory, an electronic device, and a chip system.

Background

With the development of storage technology, storage standards have also developed from emmc (embedded Multi Media card) to ufs (universal Flash storage). The UFS standard defines an interface between the UFS driver and the UFS host controller, and also defines data structures in the system memory for exchanging data, control, and status information.

The UFS standard can move working memory into system memory, thereby reducing system cost and improving device performance. For example, a portion of space may be pre-occupied in the system memory as a Host-side cache region for storing the L2P table of the UFS device. However, the system memory is usually pre-occupied, so that the problem of heavy system load often occurs.

Disclosure of Invention

The application provides a method for adjusting a cache region at a Host side in a memory, electronic equipment and a chip system, which can solve the problem that the system load is heavy due to more system memories occupied in the electronic equipment adopting a UFS device.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, the present application provides a method for adjusting a Host-side cache region in a memory, where the method includes:

acquiring the load pressure of the system;

and adjusting the size of a Host side cache region in a memory of the system according to the load pressure of the system, wherein the Host side cache region in the memory is used for caching the L2P data of the UFS device.

In the application, the size of the cache region on the Host side in the system memory is dynamically adjusted according to the load pressure of the system, so that the size of the memory occupied by the system is dynamically adjusted, and the problem that the system load is heavier due to more system memories which are pre-occupied in electronic equipment adopting UFS devices is solved.

As an implementation manner of the first aspect, the obtaining a load pressure of the system includes:

and acquiring the memory state and IO pressure of the system.

In the application, the load pressure of the system can be evaluated through the memory state and the IO pressure.

As another implementation manner of the first aspect, the adjusting, according to the load pressure of the system, the size of the Host-side cache region in the memory of the system includes:

and when the memory state is greater than or equal to a first threshold value or the IO pressure is greater than or equal to a second threshold value, adjusting the size of the Host-side cache region in the memory to be a first percentage of the memory, wherein the first percentage is smaller than the percentage of the memory occupied by the Host-side cache region during initialization.

In the application, the load pressure of the memory state and the IO pressure evaluation system can be adopted simultaneously, and when the memory state is large and the IO pressure is large, the space pre-occupied by the Host side cache region during initialization is smaller in comparison with the Host side cache region adjustment, so that the load pressure of the system is relieved.

As another implementation manner of the first aspect, the adjusting, according to the load pressure of the system, the size of the Host-side cache region in the memory of the system further includes:

when the memory state is smaller than the first threshold and the IO pressure is smaller than a second threshold, calculating a ratio coefficient of a Host side cache region in the memory according to the memory state and the IO pressure, wherein the ratio coefficient is used for determining the percentage of the Host side cache region in the memory;

and adjusting the size of the Host side cache region to be a second percentage of the memory according to the percentage coefficient of the Host side cache region.

The method and the device can also calculate the proportion coefficient of the Host side cache region according to the numerical value of the memory state and the numerical value of the IO pressure, so that the percentage of the Host side cache region in the memory can be more finely adjusted. And finer adjustment is realized.

As another implementation manner of the first aspect, the calculating a ratio coefficient of a Host-side cache region in the memory according to the memory state and the IO pressure includes:

calculating the ratio coefficient of the cache region at the Host side according to the formula K = MR/THMR x km + IOR/THIOR x ki;

k represents the proportion coefficient of the cache region on the Host side, MR is the memory state, THMR is the maximum threshold value of the memory state, km is the memory weight, IOR is IO pressure, THIOR is the maximum threshold value of the IO pressure, and ki is the IO weight.

As another implementation manner of the first aspect, after adjusting the size of the Host-side cache region in the memory of the system, the method further includes:

acquiring an access statistical result of each HPBRegion in the UFS device, wherein the access statistical result is used for indicating the frequency of accessing user data corresponding to L2P data in the HPBRegion;

sorting the HPBRegions from high to low based on the access statistical result;

selecting L2P data in the first N HPBRegions to be stored in the cache region at the Host side according to the adjusted size of the cache region at the Host side, wherein the adjusted size of the cache region at the Host side at most comprises the N HPBRegions.

In the application, after the size of the cache region at the Host side is adjusted, the L2P data in the hpbretion with higher access frequency can be selected to be stored in the cache region at the Host side according to the adjusted size of the cache region at the Host side, so as to improve the hit rate when accessing the data in the cache region at the Host side.

As another implementation manner of the first aspect, before obtaining the access statistics of each hpbreion, the method further includes:

after receiving an access request of user data stored in the UFS device, acquiring a cold and hot mark of the user data from a file system;

reading L2P data corresponding to the logical address of the user data;

and determining the access statistical result of the HPBRegion in which the L2P data corresponding to the user data is located according to the cold and hot characteristics of the user data.

According to the method and the device, the access frequency of the HPBRegion in which the L2P data is located can be determined according to the cold and hot characteristics of the user data corresponding to the L2P data, so that the L2P data in the HPBRegion with the higher access frequency is stored in the cache region on the Host side, and the hit rate when the data in the cache region on the Host side is accessed is improved more finely.

As another implementation manner of the first aspect, determining, according to the cold-hot characteristic of the user data, an access statistical result of an hpbreion in which L2P data corresponding to the user data is located includes:

if the cold and hot marks of the user data indicate that the user data are hot data, adding a first threshold to an access statistical result of an HPBRegion in which L2P data corresponding to the user data are located;

if the cold and hot marks of the user data indicate that the user data are temperature data, adding a second threshold to the access statistical result of the HPBRegion in which the L2P data corresponding to the user data are located;

and if the cold and hot marks of the user data indicate that the user data are cold data, adding a third threshold to the access statistical result of the HPBRegion in which the L2P data corresponding to the user data are located, wherein the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

As another implementation manner of the first aspect, the storing, in the Host-side cache region, the L2P data in the first N selected hpbregs includes:

comparing the first N HPBRegions with HPBRegions corresponding to the currently stored L2P data in the Host-side cache region to obtain HPBRegions to be activated and deactivated HPBRegions, wherein the HPBRegions to be activated are HPBRegions which exist in the first N HPBRegions and do not exist in the HPBRegions corresponding to the currently stored L2P data in the Host-side cache region, and the deactivated HPBRegions are HPBRegions which do not exist in the first N HPBRegions and exist in the HPBRegions corresponding to the currently stored L2P data in the Host-side cache region;

and storing the L2P data in the HPBRegion to be activated in the Host-side cache region, and deleting the L2P data in the deactivated HPBRegion from the Host-side cache region.

In a second aspect, an electronic device is provided, comprising a processor for executing a computer program stored in a memory, implementing the method of any of the first aspect of the present application.

In a third aspect, a chip system is provided, which includes a processor coupled to a memory, and the processor executes a computer program stored in the memory to implement the method of any one of the first aspect of the present application.

In a fourth aspect, there is provided a computer readable storage medium storing a computer program which, when executed by one or more processors, performs the method of any one of the first aspects of the present application.

In a fifth aspect, the present application provides a computer program product for causing an apparatus to perform the method of any one of the first aspect of the present application when the computer program product is run on the apparatus.

It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.

Drawings

Fig. 1 is a schematic hardware structure diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating a relationship between a UFS device, a memory, and a Host-side cache region of an electronic device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a relationship between HPBRegion and L2P data according to an embodiment of the present disclosure;

fig. 4 is a schematic flowchart illustrating a process of adjusting L2P data in a cache region on a Host side according to an embodiment of the present application;

fig. 5 is a schematic flow chart illustrating a process of adjusting the size of a Host-side cache region in a memory according to an embodiment of the present disclosure;

fig. 6 is a schematic flowchart illustrating a process of adjusting L2P data stored in a cache region on the Host side according to an embodiment of the present application;

fig. 7 is a schematic flowchart illustrating a process of adjusting a size of a Host-side cache region in a memory and adjusting L2P data in the Host-side cache region according to an embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that in the embodiments of the present application, "one or more" means one, two, or more than two; "and/or" describes the association relationship of the associated objects, indicating that three relationships may exist; for example, a and/or B, may represent: a alone, both A and B, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," "fourth," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

The method for adjusting the cache region on the Host side in the memory provided by the embodiment of the application can be applied to electronic devices such as a tablet computer, a mobile phone, a notebook computer, a super-mobile personal computer (UMPC), a netbook, a Personal Digital Assistant (PDA), and the like. The memory in these electronic devices may be UFS devices. The embodiment of the present application does not limit the specific type of the electronic device.

Fig. 1 shows a schematic structural diagram of an electronic device. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a Universal Serial Bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a key 190, a motor 191, a camera 193, a display screen 194, a Subscriber Identity Module (SIM) card interface 195, and the like. The sensor module 180 may include a pressure sensor 180A, a touch sensor 180K, and the like.

It is to be understood that the illustrated structure of the embodiment of the present application does not specifically limit the electronic device 100. In other embodiments of the present application, electronic device 100 may include more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Processor 110 may include one or more processing units, such as: the processor 110 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a memory, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. The different processing units may be separate devices or may be integrated into one or more processors.

The controller may be, among other things, a neural center and a command center of the electronic device 100. The controller can generate an operation control signal according to the instruction operation code and the timing signal to complete the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 110. If the processor 110 needs to reuse the instruction or data, it can be called directly from memory. Avoiding repeated accesses reduces the latency of the processor 110, thereby increasing the efficiency of the system.

The USB interface 130 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 130 may be used to connect a charger to charge the electronic device 100, and may also be used to transmit data between the electronic device 100 and a peripheral device.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to extend the storage capability of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music, video, etc. are saved in an external memory card.

The internal memory 121 may be used to store computer-executable program code, which includes instructions. The processor 110 executes various functional applications of the electronic device 100 and data processing by executing instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. The storage program area may store an operating system, and an application program (such as a sound playing function, an image playing function, etc.) required by at least one function.

In addition, the internal memory 121 may include a high-speed random access memory, and may further include a nonvolatile memory, such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (UFS), and the like.

The charging management module 140 is configured to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger via the USB interface 130.

The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 and provides power to the processor 110, the internal memory 121, the external memory, the display 194, the camera 193, the wireless communication module 160, and the like.

In some other embodiments, the power management module 141 may also be disposed in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be disposed in the same device.

The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed as a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution including 2G/3G/4G/5G wireless communication applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a Low Noise Amplifier (LNA), and the like. The mobile communication module 150 may receive the electromagnetic wave from the antenna 1, filter, amplify, etc. the received electromagnetic wave, and transmit the electromagnetic wave to the modem processor for demodulation. The mobile communication module 150 may also amplify the signal modulated by the modem processor, and convert the signal into electromagnetic wave through the antenna 1 to radiate the electromagnetic wave.

The wireless communication module 160 may provide a solution for wireless communication applied to the electronic device 100, including Wireless Local Area Networks (WLANs) (e.g., wireless fidelity (Wi-Fi) networks), bluetooth (bluetooth, BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), and the like. The wireless communication module 160 may be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, perform frequency modulation and amplification on the signal, and convert the signal into electromagnetic waves via the antenna 2 to radiate the electromagnetic waves.

In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150 and antenna 2 is coupled to wireless communication module 160 so that electronic device 100 can communicate with networks and other devices through wireless communication techniques.

The electronic device 100 may implement audio functions via the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone interface 170D, and the application processor. Such as music playing, recording, etc.

The audio module 170 is used to convert digital audio signals into analog audio signals for output and also to convert analog audio inputs into digital audio signals. The audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be disposed in the processor 110, or some functional modules of the audio module 170 may be disposed in the processor 110.

The speaker 170A, also called a "horn", is used to convert the audio electrical signal into an acoustic signal. The electronic apparatus 100 can listen to music through the speaker 170A or listen to a handsfree call.

The receiver 170B, also called "earpiece", is used to convert the electrical audio signal into a sound signal. When the electronic apparatus 100 receives a call or voice information, it can receive voice by placing the receiver 170B close to the ear of the person.

The microphone 170C, also referred to as a "microphone," is used to convert sound signals into electrical signals. When making a call or transmitting voice information, the user can input a voice signal to the microphone 170C by speaking the user's mouth near the microphone 170C. The electronic device 100 may be provided with at least one microphone 170C. In other embodiments, the electronic device 100 may be provided with two microphones 170C to implement noise reduction functions in addition to listening to voice information. In other embodiments, the electronic device 100 may further include three, four or more microphones 170C to collect sound signals, reduce noise, identify sound sources, and perform directional recording.

The headphone interface 170D is used to connect a wired headphone. The headset interface 170D may be the USB interface 130, or may be a 3.5mm open mobile electronic device platform (OMTP) standard interface, a cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

The pressure sensor 180A is used for sensing a pressure signal, and converting the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A may be disposed on the display screen 194. The pressure sensor 180A can be of a wide variety, such as a resistive pressure sensor, an inductive pressure sensor, a capacitive pressure sensor, and the like. The capacitive pressure sensor may be a sensor comprising at least two parallel plates having an electrically conductive material. When a force acts on the pressure sensor 180A, the capacitance between the electrodes changes. The electronic device 100 determines the strength of the pressure from the change in capacitance. When a touch operation is applied to the display screen 194, the electronic apparatus 100 detects the intensity of the touch operation according to the pressure sensor 180A. The electronic apparatus 100 may also calculate the touched position from the detection signal of the pressure sensor 180A.

The touch sensor 180K is also referred to as a "touch panel". The touch sensor 180K may be disposed on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, which is also called a "touch screen". The touch sensor 180K is used to detect a touch operation applied thereto or nearby. The touch sensor can communicate the detected touch operation to the application processor to determine the touch event type. Visual output associated with the touch operation may be provided through the display screen 194. In other embodiments, the touch sensor 180K may be disposed on the surface of the electronic device 100 at a different position than the display screen 194.

The keys 190 include a power-on key, a volume key, and the like. The keys 190 may be mechanical keys. Or may be touch keys. The electronic apparatus 100 may receive a key input, and generate a key signal input related to user setting and function control of the electronic apparatus 100.

The motor 191 may generate a vibration cue. The motor 191 may be used for incoming call vibration cues, as well as for touch vibration feedback.

The electronic device 100 implements display functions via the GPU, the display screen 194, and the application processor. The GPU is a microprocessor for image processing, and is connected to the display screen 194 and an application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or alter display information.

The display screen 194 is used to display images, video, and the like. In some embodiments, the electronic device 100 may include 1 or N display screens 194, with N being a positive integer greater than 1.

The camera 193 is used to capture still images or video. In some embodiments, the electronic device 100 may include 1 or N cameras 193, N being a positive integer greater than 1.

The SIM card interface 195 is used to connect a SIM card. The SIM card can be brought into and out of contact with the electronic apparatus 100 by being inserted into the SIM card interface 195 or being pulled out of the SIM card interface 195. The electronic device 100 may support 1 or N SIM card interfaces, N being a positive integer greater than 1.

The embodiment of the present application does not particularly limit the specific structure of the execution main body of the method for adjusting the Host-side cache region in the memory, as long as the code recorded with the method for adjusting the Host-side cache region in the memory according to the embodiment of the present application is run to perform the processing according to the method for adjusting the Host-side cache region in the memory provided by the embodiment of the present application. For example, an execution main body of the method for adjusting the Host-side cache region in the memory provided in the embodiment of the present application may be a functional module capable of calling a program and executing the program in the electronic device, or a processing device applied to the electronic device, such as a chip.

Universal Flash Storage (UFS) is a Storage standard. The memory adopting the storage standard can be used as a memory of the electronic equipment, for example, a hard disk of the electronic equipment. Wherein a portion of the storage space in the UFS device is used for storing various data (e.g., installed applications, various files of the user, etc.), and another portion of the storage space is used for storing the L2P table of the UFS device.

The L2P table is a mapping table of a solid state disk SSD (e.g., UFS device), and specifically is a mapping of a Logical Block Address (LBA) and a Physical Block Address (PBA). The logical address is an address generated by the central processing unit when the program runs and is also a virtual address. The physical address is an address in the hard disk and is also an actual address. The physical address can not be accessed or viewed directly by the user program, but the logical address can be accessed or viewed by the user program, therefore, a mapping table of the logical address and the physical address needs to be established, when the central processing unit needs to access the data in the hard disk, the L2P table needs to be accessed to inquire the physical address of the data based on the logical address of the data, and then the data is accessed from the hard disk based on the physical address.

The UFS storage standard may further include a Host Performance Boost (HPB) characteristic, which is to utilize a memory of the electronic device to cache an L2P table of the UFS device to improve the read performance.

As an example, the entire L2P table of the UFS device may be cached in the memory of the electronic device.

Referring to fig. 2, UFS devices can be divided into multiple hpbregions. The size of the HPB data area on the UFS device may be denoted as hpbregenissize. When a part of space is allocated in the memory as a cache space for the Host side to occupy, the size for the Host side to occupy is as follows: HPBREGONISze/4 kb × 8Byte, corresponding to HPBREGONISze/512. Namely, the space of the size of HPBREGIONSize/512 on the UFS device is divided in the memory to be occupied by the Host side. For convenience of description, the space occupied by the Host side in the memory is recorded as a Host side cache region. Certainly, after the cache region at the Host side is deducted from the memory of the electronic device, the remaining part of the memory is used for executing the function of the original system memory. The size of the cache region on the Host side is reduced equivalently to the system memory.

For example, if the memory of the electronic device is 8G and the UFS device is 256G, a space with a size of 256G/512=512M is divided into the memory as a Host cache region. The method is equivalent to taking 512M/8G =1/16 of the memory out as a Host cache region, and 15/16 of the remaining memory keeps the function of the original memory.

The values 8G, 256G and 1/512 are merely examples, and other values may be used in practical applications, which are not limited in the present application.

Referring to fig. 3, there are a plurality of hpbregions (spatial representation in logical address units) in the HPB data area. The HPBRegion comprises a plurality of hpbsubregions. Each HPBSubRegion in turn contains a plurality of hpbentys. Each HPBEntry may store data for logical to physical address translation (L2P data).

During initialization, the Host side pre-applies for a plurality of hpbregions (e.g., hpbregemize/512 hpbregesize) in the memory as a Host side cache region. And stores the L2P table of the UFS device stored in the UFS device in the Host-side cache area. In practical applications, all the L2P tables stored in the UFS device may be stored in the Host-side cache region.

In practical applications, the L2P data in the hpbregence with a low hit rate may be deleted from the Host-side cache region according to the flow chart shown in fig. 4, and since there is a deletion step, there may be a part of L2P data in the Host-side cache region over time, so the L2P data in the hpbregence with a high hit rate may also be stored in the Host-side cache region. The process of adjusting the L2P data in the cache region on the Host side is realized through the steps of deleting and storing. Reference may be made in particular to the description of the embodiment shown in fig. 4.

In step S101, the UFS device side determines the HPBRegion to be activated (HPBRegion with higher access frequency) and the deactivated HPBRegion (HPBRegion with lower access frequency) according to the frequency of access of each HPBRegion.

Wherein, the frequency of the HPBRegion access represents the frequency of the L2P data in the HPBRegion access. After the hpbreion to be activated is activated, the L2P data in the hpbreion can be stored in the Host side cache region, and after the deactivated hpbreion is successfully deactivated, the L2P data in the hpbreion is deleted from the Host side cache region.

In practical application, a threshold a and a threshold B may be set, the L2P data in the hpbregences with access frequencies higher than the threshold a will be stored in the Host-side cache region, the L2P data in the hpbregences with access frequencies lower than the threshold B will be deleted from the Host cache region, and the hpbregences to be activated and the hpbregences to be deactivated are determined according to the hpbregences corresponding to the L2P data currently stored in the Host cache region.

As an example, HPBRegion with a frequency of access above threshold a includes: hpbreion 1 and hpbreion 2. HPBRegion with a frequency of access below threshold B includes: hpbreion 3 and hpbreion 4. The current Host-side cache region stores L2P data as L2P data in HPBRegion1 and HPBRegion 4. The hpbreion 2 may be set to the hpbreion to be activated. Set hpbretion 4 to the deactivated hpbretion.

Certainly, in practical application, the hpbreges may also be sorted from high to low according to the accessed frequency, a larger number of hpbreges are selected as much as possible from the hpbrege with the highest accessed frequency according to the size of the Host-side cache region, then the L2P data in the selected hpbreges are used as the L2P data stored in the Host-side cache region, and then it is determined which regions are to be activated and which regions are to be deactivated based on the hpbreges currently stored in the Host-side cache region.

The recommendation information may include recommendation information of the hpbretion to be activated; recommendation information for deactivated HPBRegion may also be included; it is also possible to include recommendation information of HPBRegion to be activated and recommendation information of HPBRegion to be deactivated at the same time. The embodiment of the application takes the recommendation information of the HPBRegion to be activated and the recommendation information of the deactivated HPBRegion as an example.

And step S102, the UFS device side sends recommendation information of the HPBRegion to be activated and recommendation information of the HPBRegion of the deactivated subarea to the Host side.

Step S103, after the Host side receives the recommendation information, if the recommendation information comprises: and deleting the L2P data in the HPBRegion deactivated in the recommendation information from the Host side cache region.

Step S104, if the recommendation information comprises: and recommendation information of the HPBRegion to be activated, wherein the Host side requests to acquire L2P data in the HPBRegion to be activated from the UFS device side.

In step S105, after receiving the request, the UFS device side reads the L2P data corresponding to the hpbretion in the request.

In step S106, the UFS device side supplies the read L2P data in hpbreion to the Host side.

In step S107, the Host side stores the L2P data received from the hpbretion in the cache region on the Host side.

In practical applications, the cache region on the Host side is not fully occupied by the L2P data with high access frequency, which may cause waste of memory resources, and even if the L2P data are fully placed in the cache region on the Host side, some L2P data with low access frequency may cause waste of memory resources. Especially, the less space in the Host side cache region used by the L2P data, the more serious the waste of memory resources. Moreover, under the conditions of serious system load and short memory, the memory pressure is more serious because the cache region at the Host side occupies more memory resources.

In order to solve the problem, the size of the cache region at the Host side can be dynamically adjusted according to the system memory state and the IO state, and the situation that the memory resource is not enough due to the fact that the cache region at the Host side occupies too much memory resource is reduced.

As an example of dynamically adjusting the size of the Host-side buffer, refer to the flowchart shown in fig. 5.

Step S201, obtain the IO pressure and the memory state of the system in a preset time period.

The IO pressure of the system represents the read-write pressure of the system, and different parameters can be adopted to measure the IO pressure of the system according to actual conditions. By way of example, there may be a percentage of time per second for IO operations, a percentage of time per second for the IO queue to be in a non-empty state, or a percentage of throughput per second to a preset maximum throughput. Of course, in practical application, other parameters for measuring the IO pressure of the system may be used.

The memory state of the system represents the pressure of the system memory, and different parameters can be adopted to measure the memory state of the system according to actual conditions. For example, the percentage of the currently occupied memory may be, the maximum percentage of the currently occupied memory within a period of time may be, the average of the percentages of the currently occupied memory acquired multiple times within a period of time may be, and the like. In practical application, other parameters for measuring the system memory state may also be used.

In practical applications, the IO pressure may be further divided into a plurality of levels, for example, three levels, namely a large level, a medium level and a small level, and the memory state may also be divided into a plurality of levels, for example, three levels, namely a tense level, a normal level and an idle level.

The embodiment of the application can obtain the IO pressure and the memory state at the same time to determine the load condition of the system (which can also be understood as the load pressure). In practical applications, the load pressure of the system may also be determined according to only one of the parameters (e.g., according to IO pressure only or according to memory state only). Of course, in practical applications, other parameters or more parameters may be selected to determine the load pressure of the system. If one parameter is used to measure the load pressure of the system, the condition related to another parameter in the embodiment of the present application may be deleted.

As an example of determining the load pressure, the load pressure of the system is greater when the memory is being consumed too much. When the IO queue idle state time is small, the system load pressure is large.

Step S202, determining the system load condition according to the IO pressure and the memory state.

In the embodiment of the present application, if the IO pressure and the memory state of the system are measured in percentage, a percentage threshold may be set, so as to determine the system load condition according to the percentage threshold.

For example, if the memory status is greater than or equal to 80%, or the IO pressure is greater than or equal to 80%, it is determined that the system is busy. If the memory state is less than 80% and the IO pressure is less than 80%, the system is determined to be normal.

Wherein, 80% is only used for example, in practical application, the threshold corresponding to the memory state may be recorded as the first threshold, and the threshold corresponding to the IO pressure may be recorded as the second threshold.

Namely, when the memory state is smaller than the first threshold and the IO pressure is smaller than the second threshold, it is determined that the system is busy.

If the IO pressure and the memory state of the system are measured by the levels, the load conditions corresponding to different levels may be preset.

If the IO pressure is high and the memory state is tense, the corresponding system is busy. Otherwise, the corresponding system is normal.

In step S203, if the system load is busy, the Host-side cache area is set to the first percentage of the memory, and the remaining space is returned to the system.

Wherein the first percentage may be 10%, 5%, etc. The 5% and 10% are only used as examples, and in practical applications, the size of the Host-side buffer can be set smaller than the size of the initial Host-side buffer (hpbregenionsize/512) to cope with the situation of heavy system load.

And step S204, if the system load condition is normal, calculating the proportion coefficient of the cache region at the Host side.

In practical applications, if the load condition is normal (not busy), the size of the Host-side buffer may be set to the initial size of the Host-side buffer (hpb regionsize/512).

Of course, the size of the cache region on the Host side can be calculated as the percentage of the memory according to the percentage of the memory state and the percentage of the IO pressure.

For example, if the memory state is less than 80% and the IO pressure is less than 80%, the system is determined to be normal, and the ratio coefficient is calculated. Different fraction coefficients correspond to different percentages.

As an example of calculating the duty factor, K = MR/THMR × km + IOR/THIOR × ki.

The ratio coefficient is equal to the ratio of the memory state to the maximum threshold of the memory state multiplied by the memory weight plus the ratio of the IO pressure to the maximum threshold of the IO pressure multiplied by the IO weight.

The maximum threshold of the memory state is a preset value, and can be determined based on the condition that the memory states are different from each other in the system. As an example, when the memory state is 90%, the system is easy to be abnormal (stuck, dead, etc.) in operation, and the maximum threshold of the memory state may be set to 90%.

The IO pressure maximum threshold is also a preset value, and may be determined based on the condition that the IO pressures are different in the system. As an example, when the IO pressure is 95%, the system is likely to be abnormal in operation (e.g., an alarm is generated), and the IO pressure maximum threshold may be set to 95%.

Of course, the percentages in the above examples are only examples, and in practical applications, different percentages may be set due to different models of electronic devices and different memory devices.

The sum of the IO weight and the memory weight may be 1.

As an example, when the IO pressure is 75%, the memory state is 70%, the IO weight is 0.5, and the memory weight is 0.5, the occupancy coefficient is 75%/95%. 0.5+ 70%/90%. 0.5 ≈ 0.78. I.e. a coefficient of occupation of 0.78.

Wherein, different percentage coefficients correspond to different percentages of the memory occupied by the Host side cache region. When the IO pressure is larger and the memory state is larger, the occupation ratio coefficient is larger. The larger the IO pressure is, the larger the memory state is, the smaller the percentage of the Host side cache region in the memory should be, so that the larger the memory occupied by the system is, and therefore, the inverse relationship exists between the occupation ratio coefficient and the percentage of the Host side cache region in the memory.

Of course, in practical applications, the scaling factor may also be rounded.

As an example, the Round function may Round a number to a fixed number of bits behind the decimal point.

For example, Round (a, 1) denotes rounding the number a to one digit after the decimal point.

Round（0.256，1）=0.3。

Round（0.619，1）=0.6。

That is, Round ((MR/THMR x km + IOR/THIOR x ki), 1) can be used as the memory ratio coefficient.

Of course, in practical application, when the load condition is normal, the load condition may be divided into a plurality of levels under normal conditions.

For example, when the load condition is normal, the load condition may be divided into a plurality of levels, and the size of the Host-side cache region may be set to different percentages of the memory in different levels. Specific reference may be made to the examples shown in table 1.

Table 1 percentage of memory occupied by Host side cache region corresponding to different IO pressure levels and different memory state levels

The percentages in the memory percentages in table 1 are for illustration only and do not limit the present application in any way. In practice, more or fewer levels may be provided, and different percentages may be provided.

In step S205, the percentage of the memory occupied by the Host cache area is adjusted to a second percentage according to the percentage coefficient.

Of course, the second percentage is also only an example, and in practical applications, a plurality of specific space values (the size of the Host-side cache region) may also be set, and different proportion coefficients correspond to different space values.

In this way, the percentage of the memory occupied by the cache region at the Host side can be adjusted. When the system load is heavy, the memory occupied by the Host side cache region is small, and the memory occupied by the system (the Host side cache region subtracted from the memory of the electronic equipment) is large. When the system load is light, the memory occupied by the cache region at the Host side is large, and the memory occupied by the system is small. However, no matter how the adjustment is made, the cache region on the Host side is smaller than the memory occupied by the system. The memory ratio matched with the system load is adjusted in real time according to the system load condition, so that the system memory deducts the cache region at the Host side to reserve the memory size really used for the system to be matched with the system load.

As mentioned above, the percentage of the memory occupied by the Host side cache region can be adjusted in real time, which is equivalent to adjusting the size of the Host cache region in real time. The purpose of storing the L2P data in the Host-side cache region is to: when data access is needed, the corresponding physical address is preferentially searched from the L2P data stored in the Host-side cache region, and if the corresponding physical address is not searched from the L2P data stored in the Host-side cache region, the corresponding physical address needs to be searched from the L2P data stored in the UFS device. And accessing the data corresponding to the physical address according to the searched physical address. Therefore, when the memory occupied by the Host-side cache region is small and is not enough to store all the L2P data due to the fact that the system is busy, the L2P data cached by the Host-side cache region can be the L2P data in the hpbretion with the higher access rate.

As described earlier, the L2P data stored in the Host-side cache area can be determined according to the frequency with which each hpbreion in the UFS is accessed. In practical application, the access frequency of the address in the L2P data stored in each hpbretion can be estimated according to the cold and hot characteristics of the data corresponding to the address in the L2P data stored in each hpbretion, so that the L2P data in the hpbretion with higher access frequency is stored in the Host-side cache region, and the hit rate of the L2P data stored in the Host-side cache region is improved.

As another example, the access frequency of the hpbreion (or the address stored therein) may be estimated according to the cold and hot characteristics of the data corresponding to the address stored in the hpbreion of the UFS device, so as to store the L2P data in the hpbreion with higher access frequency in the Host-side cache region, which may be specifically referred to the flowchart shown in fig. 6.

Step S301, a module in the upper layer application or system reads file data.

In this embodiment of the present application, file data stored in the UFS device can be read by an application installed in the electronic device or by another module in the system, and the file data can be recorded as user data.

In step S302, the cold and hot flags of the file data are obtained from the file system.

In this embodiment, the cold and hot marks of the file data may be obtained from the file system, and the basis for marking the cold and hot marks of the file data in the file system is not limited.

As an example, the file system may determine the cold-hot flag of file data at the frequency that the file data is accessed, e.g., file data that is accessed more frequently is hot data and file data that is accessed less frequently is cold data. Of course, in practical applications, temperature data may also be set, and the frequency of accessing the temperature data is lower than that of accessing hot data and higher than that of accessing cold data.

As another example, the file system may also determine the cold and hot flags of the file data based on the type of file data.

It should be noted that, the references to the hot and cold marks of the file system marked file data in the embodiments of the present application are only used for examples, and do not cause any limitation.

In practical applications, the cold and hot characteristics of the data can also be set to more levels.

In step S303, the L2P data of the logical address corresponding to the file data is acquired.

Step S304, based on the cold and hot characteristics of the file data, updating the access statistical result of the HPBRegion in which the L2P data is located.

And calculating an access statistical result according to a formula NumCount [ i ] = Weights.

Wherein, NumCount [ i ] represents the access statistical result weight of the ith HPBRegion represents the accumulation of the cold and hot Weights of the file data, and i is less than or equal to the total number of the HPBRegions.

Whenever L2P data is accessed once and the L2P data is in the ith sub-region, NumCount [ i ] is added with the cold and hot weight of the file data corresponding to the L2P data.

Wherein the weight of the data of different cold and hot marks is different.

As an example, the data may be divided into cold data and hot data, the weight of the hot data being greater than the weight of the cold data, or the data may be divided into cold data, warm data, and hot data, the weight of the hot data being greater than the weight of the warm data, the weight of the warm data being greater than the weight of the cold data.

The division of the cold and hot data can be based on any existing way of dividing the cold and hot data.

Of course, in practical applications, the data may be divided into more types according to the cold and hot characteristics of the data. The embodiment of the present application does not limit this.

Taking the example of dividing data into cold data, warm data, and hot data, the cold data may be weighted 1, the warm data may be weighted 4, and the hot data may be weighted 10.

Wherein 1, 4 and 10 are only used for example, in practical application, the hot data may be weighted by a first value, the warm data may be weighted by a second value, and the cold data may be weighted by a third value. The first value is greater than the second value, which is greater than the third value.

As described above, once a file data is accessed, it is necessary to access L2P data corresponding to the file data once. Therefore, the access statistics of the hpbreion may be used to indicate the frequency with which the L2P data in the hpbreion may be accessed. If the access statistics result is large, it indicates that the frequency of accessing the L2P data in the hpbretion is high, and the L2P data in the hpbretion can be cached in the Host-side buffer.

When the initial value of the access statistics of one HPBRegion is a preset value (for example, 0), the access statistics is added with the cold and hot weight of the file data corresponding to the L2P data every time the L2P data in the HPBRegion is accessed. The access statistics result is gradually increased along with the increase of the access times.

In practical applications, the access statistics of each hpbreion may be set to an initial value every time a certain period of time (greater than or equal to the preset time period in the above embodiment) elapses, and statistics of the access statistics of each hpbreion may be restarted at this time. The embodiment of the present application does not limit this.

Step S305, sorting the HPBRegions according to the access statistical result.

The hpbregions may be ordered from large to small according to access statistics.

In step S306, the L2P data in the N hpbregs before sorting are read from the UFS device to the Host-side cache region. Wherein, N is the maximum number of HPBRegions which can be contained in the cache region at the Host side, and N is a natural number which is greater than or equal to 1.

Wherein, the determination mode of N includes:

the size of the current Host-side buffer (e.g., 5% of memory) is first determined. According to the size of the Host-side cache region (for example, N hpbregs), the L2P data in the N hpbregs before the sorting (sorting from large to small of the access statistics) can be taken and cached in the Host-side cache region. In this way, the predicted L2P data in the HPBRegion with high access frequency can be stored in the Host-side cache region, and the storage of as much L2P data as possible in the Host-side cache region is realized. Therefore, the hit rate of the cache region at the Host side is improved, and the probability that the cache region at the Host side misses the data needing to be sent to the UFS device to access L2P data is reduced.

In this way, each time the Host side accesses the Host side cache region first, the full amount of L2P data in the UFS device is accessed again to obtain the corresponding physical address in the case that the corresponding L2P data cannot be obtained by accessing the Host side cache region.

It should be noted that the access statistics result of each hpbretion can be counted by the Host side. After accessing the L2P data of the hit file data in the cache region of the Host side, the Host side can add the statistical access result of the HPBRegion corresponding to the L2P data to the weight of the cold and hot characteristics corresponding to the L2P data; after accessing the L2P data of the file data missed in the cache region on the Host side, the L2P data of the file data is accessed from the UFS device, and the Host side may add the statistical access result of the hpbrection corresponding to the L2P data to the weight of the hot and cold characteristics corresponding to the L2P data.

The L2P data of part of the HPBRegions stored in the Host side cache region all have corresponding HPBRegions in the UFS device, so that the statistical access result of each HPBRegion in the UFS device can be counted no matter the L2P data is hit in the Host side cache region or the L2P data needs to be accessed in the UFS device.

In practical applications, the embodiment shown in fig. 5 and the embodiment shown in fig. 6 may be combined, and after the memory size occupied by the Host-side cache region is determined each time, which data of L2P stored in the hpbreg is determined to be stored in the Host-side cache region according to the statistical result of access of each hpbreg in the UFS device according to the current statistics.

See the schematic flow diagram shown in fig. 7.

Step S301, a module in the upper layer application or system reads file data.

In step S302, the file system obtains the cold and hot marks of the file data.

Wherein, every time when a module in the upper layer application or system reads the file data, step S301 to step S304 are executed.

Wherein step S201 is performed every time a preset time period elapses. After execution to step S205, access statistics of the respective hpbregions are acquired, and execution of step S305 and step S306 is started.

And 305, sequencing the HPBRegion according to the access statistical result.

In step S306, the L2P data in the N hpbregs before sorting are read from the UFS device to the Host-side cache region.

Each step in the flow shown in fig. 7 may refer to the related description in the embodiments shown in fig. 5 and fig. 6, and is not repeated herein.

The process of adjusting the ratio of the cache region at the Host side is triggered in a preset time period; the access statistics of each HPBRegion are triggered when the requirement of reading the file exists; after the size of the cache region on the Host side is adjusted, obtaining the access statistical results of each HPBRegion, which is equivalent to obtaining the access statistical results of each HPBRegion once every preset time period, and only during obtaining the access statistical results of each HPBRegion twice, there may be a need to read the file data, that is, the access statistical results of the HPBRegion are updated, or there may be no need to read the file data during obtaining the access statistical results of each HPBRegion twice, that is, the access statistical results of each HPBRegion are still consistent with the previous access statistical results.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps in the foregoing method embodiments may be implemented.

Embodiments of the present application further provide a computer program product, which when run on a first device, enables the first device to implement the steps in the foregoing method embodiments.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer readable storage medium and used by a processor to implement the steps of the embodiments of the methods described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or apparatus capable of carrying computer program code to a first device, including recording media, computer Memory, Read-Only Memory (ROM), Random-Access Memory (RAM), electrical carrier signals, telecommunications signals, and software distribution media. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.

An embodiment of the present application further provides a chip system, where the chip system includes a processor, the processor is coupled to the memory, and the processor executes a computer program stored in the memory to implement the steps of any of the method embodiments of the present application. The chip system may be a single chip or a chip module composed of a plurality of chips.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A method for adjusting a Host side cache region in a memory is characterized by being applied to electronic equipment adopting a UFS device, and the method comprises the following steps:

acquiring the load pressure of the system;

2. The method of claim 1, wherein the obtaining a load pressure of a system comprises:

and acquiring the memory state and IO pressure of the system.

3. The method of claim 2, wherein the adjusting the size of the Host-side cache region in the memory of the system according to the load pressure of the system comprises:

when the memory state is larger than or equal to a first threshold value or the IO pressure is larger than or equal to a second threshold value, adjusting the size of a Host side cache region in the memory to be a first percentage of the memory, wherein the first percentage is smaller than the percentage of the Host side cache region in the memory during initialization.

4. The method of claim 3, wherein the adjusting the size of the Host-side cache region in the memory of the system according to the load pressure of the system further comprises:

when the memory state is smaller than the first threshold and the IO pressure is smaller than the second threshold, calculating a ratio coefficient of a Host side cache region in the memory according to the memory state and the IO pressure, wherein the ratio coefficient is used for determining the percentage of the Host side cache region in the memory;

5. The method of claim 4, wherein the calculating the fraction coefficient of the Host-side cache region in the memory according to the memory state and the IO pressure comprises:

k represents the occupation ratio coefficient of the cache region on the Host side, MR is the memory state, THMR is the maximum threshold value of the memory state, km is the memory weight, IOR is the IO pressure, THIOR is the maximum threshold value of the IO pressure, and ki is the IO weight.

6. The method of any of claims 1 to 5, wherein after adjusting the size of the Host-side cache in the memory of the system, the method further comprises:

sorting the HPBRegions from high to low based on the access statistical result;

7. The method of claim 6, wherein prior to obtaining the access statistics for each hpbreion, the method further comprises:

reading L2P data corresponding to the logical address of the user data;

8. The method of claim 7, wherein determining the access statistics of the hpbreion in which the L2P data corresponding to the user data is located according to the hot and cold characteristics of the user data comprises:

if the cold and hot marks of the user data indicate that the user data are hot data, adding a first value to an access statistical result of an HPBRegion in which L2P data corresponding to the user data are located;

if the cold and hot marks of the user data indicate that the user data are temperature data, adding a second value to the access statistical result of the HPBRegion in which the L2P data corresponding to the user data are located;

and if the cold and hot marks of the user data indicate that the user data are cold data, adding a third value to the access statistical result of the HPBRegion in which the L2P data corresponding to the user data are located, wherein the first value is greater than the second value, and the second value is greater than the third value.

9. The method of claim 6, wherein the storing of the L2P data in the first N selected HPBRegions in the Host-side cache region comprises:

storing L2P data in the HPBRegion to be activated in the Host-side cache region, and deleting L2P data in the deactivated HPBRegion from the Host-side cache region.

10. An electronic device, characterized in that the electronic device comprises a processor for executing a computer program stored in a memory, so that the electronic device implements the method according to any of claims 1 to 9.

11. A chip system comprising a processor coupled to a memory, the processor executing a computer program stored in the memory to implement the method of any of claims 1 to 9.