CN114740414A - Method, device and equipment for determining system error of network analyzer and storage medium - Google Patents

Method, device and equipment for determining system error of network analyzer and storage medium Download PDF

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Publication number
CN114740414A
CN114740414A CN202210362003.4A CN202210362003A CN114740414A CN 114740414 A CN114740414 A CN 114740414A CN 202210362003 A CN202210362003 A CN 202210362003A CN 114740414 A CN114740414 A CN 114740414A
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port
resistance value
error
resistance
variable resistor
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柳佰华
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Spreadtrum Communications Shanghai Co Ltd
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Spreadtrum Communications Shanghai Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Abstract

The embodiment of the application provides a method, a device and equipment for determining system errors of a network analyzer and a storage medium. The network analyzer includes a first port and a second port, and the network analyzer is connected to a calibration device, the calibration device including three variable resistors connected in series, the method comprising: when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the first port through the calibration device to obtain a plurality of first errors of the network analyzer; when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the second port through the calibration device to obtain a plurality of second errors of the network analyzer; when the resistance values of the three variable resistors are corresponding resistance values, testing the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer; and determining a plurality of system errors of the network analyzer according to the plurality of first errors, the plurality of second errors and the plurality of third errors. The system error of the network analyzer can be accurately determined.

Description

Method, device and equipment for determining system error of network analyzer and storage medium
Technical Field
The present application relates to the field of network analyzers, and in particular, to a method, an apparatus, a device, and a storage medium for determining a system error of a network analyzer.
Background
The network analyzer is a comprehensive microwave measuring instrument which can perform scanning measurement in a wide frequency band to determine network parameters. When the network analyzer measures network parameters, system errors are generated due to the imperfection of devices inside the analyzer, and the accuracy of network parameter measurement is low.
In the related art, the accuracy of network parameter measurement is improved by calibrating a network analyzer. Specifically, a network analyzer measures standard components, such as a circuit breaker, a matched load and the like, to calculate a system error, and then removes the system error from the measured network parameters to obtain real network parameters. If the standard component is damaged, the accuracy of determining the system error is low, and the accuracy of measuring the network parameters is low.
Disclosure of Invention
The application relates to a method, a device, equipment and a storage medium for determining system errors of a network analyzer, which improve the accuracy of determining the system errors of the network analyzer.
In a first aspect, an embodiment of the present application provides a method for determining a system error of a network analyzer, where the network analyzer includes a first port and a second port, the network analyzer is connected to a calibration device, the calibration device includes three variable resistors connected in series, and the method includes:
when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the first port through the calibration device to obtain a plurality of first errors of the network analyzer;
when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the second port through the calibration device to obtain a plurality of second errors of the network analyzer;
when the resistance values of the three variable resistors are corresponding resistance values, testing the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer;
determining a plurality of systematic errors of the network analyzer based on the plurality of first errors, the plurality of second errors, and the plurality of third errors.
In one possible embodiment, the calibration device further comprises a first contact point and a second contact point, the three variable resistances comprising a first variable resistance, a second variable resistance, and a third variable resistance, wherein,
one end of the first variable resistor is connected with the first contact point, and the other end of the first variable resistor is grounded;
one end of the second variable resistor is connected with the first contact point, and the other end of the second variable resistor is connected with the second contact point;
one end of the third variable resistor is connected to the second contact point, and the other end of the third variable resistor is grounded.
In a possible embodiment, the first port is connected to the first contact point; when the resistance values of the three variable resistors are respectively corresponding resistance values, the first port is tested through the calibration device to obtain a plurality of first errors of the network analyzer, and the method comprises the following steps:
when the resistance values of the three variable resistors correspond to first resistance value information, testing the first port through the calibration device to obtain a first open circuit error;
when the resistance values of the three variable resistors correspond to second resistance value information, testing the first port through the calibration device to obtain a first short circuit error;
when the resistance values of the three variable resistors correspond to third resistance value information, testing the first port through the calibration device to obtain a first load error;
wherein the plurality of first errors includes the first open error, the first short error, and the first load error.
In one possible embodiment, the first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the second resistance value information is used to indicate: the resistance value of the first variable resistor is preset 0, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the third resistance value information is used to indicate: the resistance value of the first variable resistor is a preset value, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
In a possible embodiment, the second port is connected to the second contact point; when the resistance values of the three variable resistors are respectively corresponding resistance values, the second port is tested through the calibration device to obtain a plurality of second errors of the network analyzer, and the method comprises the following steps:
when the resistance values of the three variable resistors correspond to the first resistance value information, testing the second port through the calibration device to obtain a second open circuit error;
when the resistance values of the three variable resistors correspond to fourth resistance value information, testing the second port through the calibration device to obtain a second short circuit error;
when the resistance values of the three variable resistors correspond to fifth resistance value information, testing the second port through the calibration device to obtain a second load error;
wherein the plurality of second errors includes the second open error, the second short error, and the second load error.
In one possible embodiment, the first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the fourth resistance value information is used to indicate: the resistance value of the third variable resistor is preset 0, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value;
the fifth resistance value information is used to indicate: the resistance value of the third variable resistor is a preset value, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value.
In a possible embodiment, the first port is connected to the first contact point and the second port is connected to the second contact point; when the resistance values of the three variable resistors are corresponding resistance values, the first port and the second port are tested through the calibration device to obtain a plurality of third errors of the network analyzer, including:
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the first port through the calibration device to obtain a first pass error;
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the second port through the calibration device to obtain a second straight-through error;
wherein the plurality of third errors includes the first pass through error and the second pass through error.
In one possible embodiment, the sixth resistance value information is used to indicate:
the resistance value of the first variable resistor is a preset maximum value;
the resistance value of the second variable resistor is preset 0;
and the resistance value of the third variable resistor is the preset maximum value.
In a second aspect, the present embodiments provide a system error determination apparatus for a network analyzer, the apparatus including a first port and a second port, the apparatus being connected to a calibration device, the calibration device including three variable resistors connected in series, the apparatus including a first determination module, a second determination module, a third determination module, and a fourth determination module, wherein,
the first determining module is configured to test the first port through the calibration device when the resistance values of the three variable resistors are respectively corresponding resistance values, so as to obtain a plurality of first errors of the network analyzer;
the second determining module is configured to test the second port through the calibration device when the resistance values of the three variable resistors are respectively corresponding resistance values, so as to obtain a plurality of second errors of the network analyzer;
the third determining module is configured to, when the resistance values of the three variable resistors are corresponding resistance values, test the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer;
the fourth determining module is configured to determine a plurality of systematic errors of the network analyzer according to the plurality of first errors, the plurality of second errors, and the plurality of third errors.
In one possible embodiment, the calibration device further comprises a first contact point and a second contact point, the three variable resistances comprising a first variable resistance, a second variable resistance, and a third variable resistance, wherein,
one end of the first variable resistor is connected with the first contact point, and the other end of the first variable resistor is grounded;
one end of the second variable resistor is connected with the first contact point, and the other end of the second variable resistor is connected with the second contact point;
one end of the third variable resistor is connected to the second contact point, and the other end of the third variable resistor is grounded.
In a possible embodiment, the first port is connected to the first contact point; the first determining module is specifically configured to:
when the resistance values of the three variable resistors correspond to first resistance value information, testing the first port through the calibration device to obtain a first open circuit error;
when the resistance values of the three variable resistors correspond to second resistance value information, testing the first port through the calibration device to obtain a first short circuit error;
when the resistance values of the three variable resistors correspond to third resistance value information, testing the first port through the calibration device to obtain a first load error;
wherein the plurality of first errors includes the first open error, the first short error, and the first load error.
In one possible implementation, the first determining module is specifically configured to,
the first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the second resistance value information is used to indicate: the resistance value of the first variable resistor is preset 0, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the third resistance value information is used to indicate: the resistance value of the first variable resistor is a preset value, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
In a possible embodiment, the second port is connected to the second contact point; the second determining module is specifically configured to:
when the resistance values of the three variable resistors correspond to the first resistance value information, testing the second port through the calibration device to obtain a second open circuit error;
when the resistance values of the three variable resistors correspond to fourth resistance value information, testing the second port through the calibration device to obtain a second short circuit error;
when the resistance values of the three variable resistors correspond to fifth resistance value information, testing the second port through the calibration device to obtain a second load error;
wherein the plurality of second errors includes the second open error, the second short error, and the second load error.
In one possible embodiment, the second determination module is specifically configured to,
the first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the fourth resistance value information is used to indicate: the resistance value of the third variable resistor is preset 0, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value;
the fifth resistance value information is used to indicate: the resistance value of the third variable resistor is a preset value, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value.
In a possible embodiment, the first port is connected to the first contact point, and the second port is connected to the second contact point; the third determining module is specifically configured to:
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the first port through the calibration device to obtain a first pass error;
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the second port through the calibration device to obtain a second straight-through error;
wherein the plurality of third errors includes the first pass through error and the second pass through error.
In one possible embodiment, the third determining module is specifically configured to,
the sixth resistance value information is used to indicate:
the resistance value of the first variable resistor is a preset maximum value;
the resistance value of the second variable resistor is preset 0;
and the resistance value of the third variable resistor is the preset maximum value.
In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor;
the memory is used for storing computer execution instructions;
the processor executes computer-executable instructions stored by the memory, causing the processor to perform the method of determining a systematic error of a network analyzer according to the first aspect.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the computer-readable storage medium is configured to implement the system error determination method of the network analyzer according to any one of the first aspects.
In a fifth aspect, the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the method for determining the system error of the network analyzer according to any one of the first aspect may be implemented.
The embodiment of the application provides a method, a device, equipment and a storage medium for determining system errors of a network analyzer. The network analyzer includes a first port and a second port, and the network analyzer is connected to a calibration device, the calibration device including three variable resistors connected in series, the method comprising: when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the first port through the calibration device to obtain a plurality of first errors of the network analyzer; when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the second port through the calibration device to obtain a plurality of second errors of the network analyzer; when the resistance values of the three variable resistors are corresponding resistance values, testing the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer; determining a plurality of systematic errors of the network analyzer based on the plurality of first errors, the plurality of second errors, and the plurality of third errors. The method for determining the system error can accurately determine the system error of the network analyzer, so that the accuracy of the network analyzer in measuring the network parameters is improved, and the cost is low.
Drawings
Fig. 1 is a schematic structural diagram of a network analyzer according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a calibration device of a network analyzer according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of a method for determining a system error of a network analyzer according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of another method for determining a system error of a network analyzer according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a system error determination apparatus of a network analyzer according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same or similar items having substantially the same function and action. For example, the first chip and the second chip are only used for distinguishing different chips, and the order of the chips is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
For convenience of understanding, the structure of the network analyzer according to the embodiment of the present application will be described below with reference to fig. 1.
Fig. 1 is a schematic structural diagram of a network analyzer according to an embodiment of the present application. Referring to fig. 1, the network analyzer includes an excitation signal source 101, a power divider 102, a switch 103, a receiver 104, a directional coupler 105, and two ports. The network analyzer may measure a scattering (S) parameter of the network. During testing, the excitation signal source 101 provides an incident signal, the incident signal passes through the power divider 102 and the directional coupler 105, the incident signal is separated into an incident signal R, a reflected signal a and a transmission signal B, and then the receiver tests the incident signal R, the reflected signal a and the transmission signal B of the tested network to obtain the S parameter of the network.
Due to imperfections of microwave and millimeter wave components and the like in the network analyzer, systematic errors are introduced into the measured S parameters, resulting in inaccuracy of the measurement of the S parameters. To improve the accuracy of S-parameter measurements, the network analyzer needs to be calibrated to eliminate systematic errors.
The systematic error may include the following components:
(1) because the directional coupler is not ideal, a part of the measuring signal from the signal source leaks to the coupling port between the reflection of the measured piece, and thus a measuring error, namely a directional error, is caused;
(2) because of the imperfect matching of the S parameter measuring system, the equivalent source reflection coefficient is not completely zero when the measured piece is seen towards the signal source direction, and a part of signals are reflected back and forth between the measured piece and the signal source to cause a measuring error, which is called a source mismatch error;
(3) when the tested network looks towards the load direction, the load mismatch error is caused by the load mismatch;
(4) due to the frequency response characteristics of devices such as a power divider, a directional coupler, a joint, a test cable and the like, frequency response errors of a test system can be caused, namely transmission measurement frequency response errors and reflection measurement frequency response errors exist;
(5) an error, i.e., a leakage error, is caused due to a signal leakage between the port 1 and the port 3 of the test apparatus.
For the forward and direction measurements, there are the above 6 errors, respectively.
Measurement of systematic error and S parameter S11M、S12M、S21M、S22MAnd the actual value S of the S parameter11A、S12A、S21A、S22AThe relationship between them is shown by the following four formulas:
Figure BDA0003585650300000091
Figure BDA0003585650300000092
Figure BDA0003585650300000093
Figure BDA0003585650300000094
wherein S is11When the port 2 is matched, the reflection coefficient of the port 1 is obtained; s22When port 1 is matched, the reflection coefficient of port 2 is shown; s12When port 1 is matched, the reverse transmission coefficient from port 2 to port 1 is obtained; s21Meaning the forward transmission coefficient of port 1 to port 2 when port 2 is matched.
EDIs a forward directional error; eLIs a positive load mismatch error; eSIs a positive source mismatch error; eTTIs the forward transmission frequency response error; eRTIs the forward reflection frequency response error; eXIs a positive leakage error; the band marked is the error in the reverse measurement.
If the standard component is damaged, the accuracy of determining the system error is low, and the accuracy of measuring the S parameter is low; meanwhile, the calibration part of the conventional network analyzer is a single device and is easy to lose, so that the cost for determining the system error is increased.
In view of this, the present application provides a calibration device, which includes three variable resistors connected in series; in the process of determining the system error of the network analyzer, the system error of the network analyzer can be tested by debugging the resistance values of the three variable resistors. The calibration device provided by the embodiment of the application can accurately determine the system error of the network analyzer, so that the accuracy of the network analyzer in measuring the network parameters is improved; meanwhile, the calibration device provided by the embodiment of the application is large and not easy to lose, so that the cost for determining the system error is reduced.
The technical means shown in the present application will be described in detail below with reference to specific examples. It should be noted that the following embodiments may exist independently or may be combined with each other, and the description of the same or displayed contents is not repeated in different embodiments.
Fig. 2 is a schematic structural diagram of a calibration device of a network analyzer according to an embodiment of the present application. Referring to fig. 2, the device includes a first variable resistor 201, a second variable resistor 202, a third variable resistor 203, and a first contact point 204 and a second contact point 205.
One end of the first variable resistor 201 is connected to the first contact point 204, and the other end is grounded; one end of the second variable resistor 202 is connected to the first contact point 204, and the other end is connected to the second contact point 205; one end of the third variable resistor 203 is connected to the second contact point 205, and the other end is grounded.
The method for determining the systematic error of the network analyzer is explained in detail below with reference to fig. 3-4 on the basis of the calibration device shown in fig. 2.
Fig. 3 is a schematic flowchart of a method for determining a system error of a network analyzer according to an embodiment of the present disclosure. Referring to fig. 3, the network analyzer includes a first port and a second port, and the method includes:
s301, when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the first port through the calibration device to obtain a plurality of first errors of the network analyzer.
The testing of the first port means that short circuit testing, open circuit testing and load testing are carried out on the first port; when different tests are carried out, the resistance values of the three variable resistors are different.
A first error may be obtained for each test performed on the first port.
The first error may be a systematic error; or may be a set of systematic errors.
For example: when performing a load test, the first error may be a directional error; when the open-circuit test is performed,
Figure BDA0003585650300000101
and S302, when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the second port through the calibration device to obtain a plurality of second errors of the network analyzer.
The step of testing the second port refers to the step of performing short circuit test, open circuit test and load test on the second port; when different tests are carried out, the resistance values of the three variable resistors are different.
A second error is obtained for each test performed on the second port.
The second error may be a systematic error; or may be a set of systematic errors.
And S303, when the resistance values of the three variable resistors are corresponding resistance values, testing the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer.
The testing of the first port and the second port means that: the values of the three variable resistors are set so that the first port and the second port are directly connected to test the input reflection coefficient of port 1 and the transmission coefficient of port 2.
The third error may be a set of systematic errors, e.g.,
Figure BDA0003585650300000102
s304, determining a plurality of system errors of the network analyzer according to the plurality of first errors, the plurality of second errors and the plurality of third errors.
Since the first error and the second error may be directly systematic errors or may be a set of systematic errors, a plurality of systematic errors may be determined according to relationships between the plurality of systematic errors and the plurality of first errors, the plurality of second errors, and the plurality of third errors.
In the embodiment shown in fig. 3, when the resistance values of the three variable resistors are respectively corresponding resistance values, the first port is tested by the calibration device to obtain a plurality of first errors of the network analyzer; when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the second port through the calibration device to obtain a plurality of second errors of the network analyzer; when the resistance values of the three variable resistors are corresponding resistance values, testing the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer; and determining a plurality of system errors of the network analyzer according to the plurality of first errors, the plurality of second errors and the plurality of third errors. The method for determining the system error can accurately determine the system error of the network analyzer, so that the accuracy of the network analyzer in measuring the network parameters is improved, and the cost is low.
On the basis of any of the above embodiments, the following describes the method for determining the systematic error of the network analyzer in detail with reference to the embodiment shown in fig. 4.
Fig. 4 is a schematic flowchart of another method for determining a system error of a network analyzer according to an embodiment of the present disclosure. Referring to fig. 4, the method may include:
s401, connecting the first port with the first contact point, and testing the first port through the calibration device when the resistance values of the three variable resistors correspond to the first resistance value information to obtain a first open circuit error.
The first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
When the signal source is forward energized, a first open circuit error for port 1 can be measured.
The first open circuit error may be
Figure BDA0003585650300000111
S402, connecting the first port with the first contact point, and testing the first port through the calibration device when the resistance values of the three variable resistors correspond to the second resistance value information to obtain a first short circuit error.
The second resistance value information is used to indicate: the resistance value of the first variable resistor is preset 0, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
A first short circuit error of port 1 can be measured when the signal source is forward energized.
The first short circuit error may be
Figure BDA0003585650300000112
And S403, connecting the first port with the first contact point, and testing the first port through the calibration device when the resistance values of the three variable resistors correspond to the third resistance value information to obtain a first load error.
The third resistance value information is used to indicate: the resistance value of the first variable resistor is a preset value, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
The preset value may be 50 ohms.
The first loading error includes the input reflection coefficient of port 1 and the transmission coefficient of port 2.
When the signal source is positively excited, the output reflection coefficient M of the port 1 can be measured1＝EDTransmission coefficient M of Port 24＝EX。
And S404, connecting the second port with the second contact point, and testing the second port through the calibration device when the resistance values of the three variable resistors correspond to the first resistance value information to obtain a second open circuit error.
A second open circuit error of port 2 can be measured when the signal source is back-energized.
And S405, connecting the second port with the second contact point, and testing the second port through the calibration device when the resistance values of the three variable resistors correspond to the fourth resistance value information to obtain a second short circuit error.
The fourth resistance value information is used to indicate: the resistance value of the third variable resistor is preset 0, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value.
A second short circuit error of port 2 can be measured when the signal source is back energized.
And S406, connecting the second port with the second contact point, and testing the second port through the calibration device when the resistance values of the three variable resistors correspond to the fifth resistance value information to obtain a second load error.
The fifth resistance value information is used to indicate: the resistance value of the third variable resistor is a preset value, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value.
The second load error is a value measured when the signal source is given a reverse excitation.
The second loading error includes the input reflection coefficient of port 1 and the transmission coefficient of port 2.
And S407, connecting the first port with the first contact point, connecting the second port with the second contact point, and testing the first port through the calibration device when the resistance values of the three variable resistors correspond to the sixth resistance value information to obtain a first pass error.
The sixth resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value; the resistance value of the second variable resistor is preset 0; and the resistance value of the third variable resistor is the preset maximum value.
When the signal source is positively excited, a first pass error of the port 1 can be measured; another first pass error of port 1 can be measured when the signal source is back-energized.
For example, in forward excitation, the first pass error may be
Figure BDA0003585650300000131
And S408, connecting the first port with the first contact point, connecting the second port with the second contact point, and testing the second port through the calibration device when the resistance values of the three variable resistors correspond to the sixth resistance value information to obtain a second direct connection error.
A second pass-through error at port 2 can be measured when the signal source is being forward-excited; another second pass-through error for port 2 can be measured when the signal source is back-energized.
For example, in forward excitation, the second pass-through error may be
Figure BDA0003585650300000132
S409, determining a plurality of system errors of the network analyzer according to the first open circuit error, the first short circuit error, the first load error, the second open circuit error, the second short circuit error, the second load error, the first direct connection error and the second direct connection error.
When the signal source is positively excited, M can be obtained1、M2、M3、M4、M5And M6(ii) a When the signal source is excited reversely or positively, M can be obtained1 *、M2 *、M3 *、M4 *、M5 *And M6 *(ii) a The systematic error can be calculated according to the relation between the 12 error terms and the systematic error.
And finally, determining the actual value of the S parameter according to the value of the system error and the formulas I to IV.
In the embodiment shown in fig. 4, when the first port is connected to the first contact, and when the resistances of the three variable resistors correspond to the first resistance information, the first port is tested by the calibration device to obtain a first open-circuit error; when the resistance values of the three variable resistors correspond to the second resistance value information, testing the first port through the calibration device to obtain a first short circuit error; and when the resistance values of the three variable resistors correspond to the third resistance value information, testing the first port through the calibration device to obtain a first load error. When the second port is connected with the second contact point and the resistance values of the three variable resistors correspond to the first resistance value information, the second port is tested through the calibration device to obtain a second open-circuit error; when the resistance values of the three variable resistors correspond to the fourth resistance value information, testing the second port through the calibration device to obtain a second short circuit error; and when the resistance values of the three variable resistors correspond to the fifth resistance value information, testing the second port through the calibration device to obtain a second load error. The first port is connected with the first contact point, the second port is connected with the second contact point, and when the resistance values of the three variable resistors correspond to the sixth resistance value information, the first port is tested through the calibration device to obtain a first pass error; and testing the second port through the calibration device to obtain a second pass-through error. And finally, determining a plurality of system errors of the network analyzer according to the first open circuit error, the first short circuit error, the first load error, the second open circuit error, the second short circuit error, the second load error, the first direct error and the second direct error. The method for determining the system error can accurately determine the system error of the network analyzer, so that the accuracy of the network analyzer in measuring the network parameters is improved, and the cost is low.
Fig. 5 is a schematic structural diagram of a system error determination apparatus of a network analyzer according to an embodiment of the present application. The apparatus comprises a first port and a second port, the apparatus is connected to a calibration device comprising three variable resistors in series. Referring to fig. 5, the system error determination apparatus 10 of the network analyzer includes: a first determination module 11, a second determination module 12, a third determination module 13 and a fourth determination module 14, wherein,
the first determining module 11 is configured to, when the resistance values of the three variable resistors are respectively corresponding resistance values, test the first port through the calibration device to obtain a plurality of first errors of the network analyzer;
the second determining module 12 is configured to, when the resistance values of the three variable resistors are respectively corresponding resistance values, test the second port through the calibration device to obtain a plurality of second errors of the network analyzer;
the third determining module 13 is configured to, when the resistance values of the three variable resistors are corresponding resistance values, test the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer;
the fourth determining module 14 is configured to determine a plurality of systematic errors of the network analyzer according to the plurality of first errors, the plurality of second errors, and the plurality of third errors.
In one possible embodiment, the calibration device further comprises a first contact point and a second contact point, the three variable resistances comprising a first variable resistance, a second variable resistance, and a third variable resistance, wherein,
one end of the first variable resistor is connected with the first contact point, and the other end of the first variable resistor is grounded;
one end of the second variable resistor is connected with the first contact point, and the other end of the second variable resistor is connected with the second contact point;
one end of the third variable resistor is connected to the second contact point, and the other end of the third variable resistor is grounded.
In a possible embodiment, the first port is connected to the first contact point; the first determining module 11 is specifically configured to:
when the resistance values of the three variable resistors correspond to first resistance value information, testing the first port through the calibration device to obtain a first open circuit error;
when the resistance values of the three variable resistors correspond to second resistance value information, testing the first port through the calibration device to obtain a first short circuit error;
when the resistance values of the three variable resistors correspond to third resistance value information, testing the first port through the calibration device to obtain a first load error;
wherein the plurality of first errors includes the first open error, the first short error, and the first load error.
In a possible embodiment, the first determination module 11 is specifically configured to,
the first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the second resistance value information is used to indicate: the resistance value of the first variable resistor is preset 0, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the third resistance value information is used to indicate: the resistance value of the first variable resistor is a preset value, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
In a possible embodiment, the second port is connected to the second contact point; the second determining module 12 is specifically configured to:
when the resistance values of the three variable resistors correspond to the first resistance value information, testing the second port through the calibration device to obtain a second open circuit error;
when the resistance values of the three variable resistors correspond to fourth resistance value information, testing the second port through the calibration device to obtain a second short circuit error;
when the resistance values of the three variable resistors correspond to fifth resistance value information, testing the second port through the calibration device to obtain a second load error;
wherein the plurality of second errors includes the second open error, the second short error, and the second load error.
In a possible embodiment, the second determination module 12 is specifically configured to,
the first resistance value information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the fourth resistance value information is used to indicate: the resistance value of the third variable resistor is preset 0, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value;
the fifth resistance value information is used to indicate: the resistance value of the third variable resistor is a preset value, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value.
In a possible embodiment, the first port is connected to the first contact point, and the second port is connected to the second contact point; the third determining module 13 is specifically configured to:
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the first port through the calibration device to obtain a first straight-through error;
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the second port through the calibration device to obtain a second straight-through error;
wherein the plurality of third errors includes the first pass through error and the second pass through error.
In a possible embodiment, the third determining module 13 is specifically configured to,
the sixth resistance value information is used to indicate:
the resistance value of the first variable resistor is a preset maximum value;
the resistance value of the second variable resistor is preset 0;
and the resistance value of the third variable resistor is the preset maximum value.
The system error determination apparatus 10 of the network analyzer provided in the embodiment of the present application may implement the technical solution shown in the above method embodiment, and its implementation principle and beneficial effect are similar, which are not described again here.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Referring to fig. 6, the electronic device 6 may include: memory 21, processor 22. Illustratively, the memory 21, the processor 22, and the various parts are interconnected by a bus 23.
Memory 21 is used to store program instructions;
processor 22 is configured to execute the program instructions stored in the memory to cause electronic device 20 to perform the method for determining the system error of the network analyzer described above.
The electronic device shown in the embodiment of fig. 6 may execute the technical solution shown in the above method embodiment, and the implementation principle and the beneficial effect are similar, which are not described herein again.
The embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the computer-readable storage medium is used for implementing the above-mentioned system error determination method for a network analyzer.
Embodiments of the present application may also provide a computer program product, which includes a computer program, and when the computer program is executed by a processor, the method for determining a system error of a network analyzer may be implemented.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the spirit of the disclosure. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims (11)

1. A method of determining systematic error of a network analyzer, wherein the network analyzer comprises a first port and a second port, wherein the network analyzer is coupled to a calibration device comprising three variable resistors in series, the method comprising:
when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the first port through the calibration device to obtain a plurality of first errors of the network analyzer;
when the resistance values of the three variable resistors are respectively corresponding resistance values, testing the second port through the calibration device to obtain a plurality of second errors of the network analyzer;
when the resistance values of the three variable resistors are corresponding resistance values, testing the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer;
determining a plurality of systematic errors of the network analyzer based on the plurality of first errors, the plurality of second errors, and the plurality of third errors.
2. The method of claim 1, wherein the calibration device further comprises a first contact point and a second contact point, and wherein the three variable resistances comprise a first variable resistance, a second variable resistance, and a third variable resistance, wherein,
one end of the first variable resistor is connected with the first contact point, and the other end of the first variable resistor is grounded;
one end of the second variable resistor is connected with the first contact point, and the other end of the second variable resistor is connected with the second contact point;
one end of the third variable resistor is connected to the second contact point, and the other end of the third variable resistor is grounded.
3. The method of claim 2, wherein the first port is connected to the first contact point; when the resistance values of the three variable resistors are respectively corresponding resistance values, the first port is tested through the calibration device to obtain a plurality of first errors of the network analyzer, and the method comprises the following steps:
when the resistance values of the three variable resistors correspond to first resistance value information, testing the first port through the calibration device to obtain a first open circuit error;
when the resistance values of the three variable resistors correspond to second resistance value information, testing the first port through the calibration device to obtain a first short circuit error;
when the resistance values of the three variable resistors correspond to third resistance value information, testing the first port through the calibration device to obtain a first load error;
wherein the plurality of first errors includes the first open error, the first short error, and the first load error.
4. The method of claim 3, wherein the first resistance information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the second resistance value information is used to indicate: the resistance value of the first variable resistor is preset 0, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the third resistance value information is used to indicate: the resistance value of the first variable resistor is a preset value, the resistance value of the second variable resistor is a preset maximum value, and the resistance value of the third variable resistor is the preset maximum value.
5. The method of claim 2, wherein the second port is connected to the second contact point; when the resistance values of the three variable resistors are respectively corresponding resistance values, the second port is tested through the calibration device to obtain a plurality of second errors of the network analyzer, and the method comprises the following steps:
when the resistance values of the three variable resistors correspond to first resistance value information, testing the second port through the calibration device to obtain a second open circuit error;
when the resistance values of the three variable resistors correspond to fourth resistance value information, testing the second port through the calibration device to obtain a second short circuit error;
when the resistance values of the three variable resistors correspond to fifth resistance value information, testing the second port through the calibration device to obtain a second load error;
wherein the plurality of second errors includes the second open error, the second short error, and the second load error.
6. The method of claim 5, wherein the first resistance information is used to indicate: the resistance value of the first variable resistor is a preset maximum value, the resistance value of the second variable resistor is the preset maximum value, and the resistance value of the third variable resistor is the preset maximum value;
the fourth resistance value information is used to indicate: the resistance value of the third variable resistor is preset 0, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value;
the fifth resistance value information is used to indicate: the resistance value of the third variable resistor is a preset value, the resistance value of the first variable resistor is a preset maximum value, and the resistance value of the second variable resistor is the preset maximum value.
7. The method of claim 2, wherein the first port is connected to the first contact point and the second port is connected to the second contact point; when the resistance values of the three variable resistors are corresponding resistance values, the first port and the second port are tested through the calibration device to obtain a plurality of third errors of the network analyzer, including:
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the first port through the calibration device to obtain a first pass error;
when the resistance values of the three variable resistors correspond to sixth resistance value information, testing the second port through the calibration device to obtain a second straight-through error;
wherein the plurality of third errors includes the first pass through error and the second pass through error.
8. The method of claim 7, wherein the sixth resistance information is used to indicate:
the resistance value of the first variable resistor is a preset maximum value;
the resistance value of the second variable resistor is preset 0;
and the resistance value of the third variable resistor is the preset maximum value.
9. A system error determination apparatus for a network analyzer, the apparatus comprising a first port and a second port, the apparatus being connected to a calibration device, the calibration device comprising three variable resistors in series, the apparatus comprising a first determination module, a second determination module, a third determination module, and a fourth determination module, wherein,
the first determining module is configured to, when the resistance values of the three variable resistors are respectively corresponding resistance values, test the first port through the calibration device to obtain a plurality of first errors of the network analyzer;
the second determining module is configured to test the second port through the calibration device when the resistance values of the three variable resistors are respectively corresponding resistance values, so as to obtain a plurality of second errors of the network analyzer;
the third determining module is configured to, when the resistance values of the three variable resistors are corresponding resistance values, test the first port and the second port through the calibration device to obtain a plurality of third errors of the network analyzer;
the fourth determining module is configured to determine a plurality of systematic errors of the network analyzer according to the plurality of first errors, the plurality of second errors, and the plurality of third errors.
10. An electronic device, comprising: a memory, a processor;
the memory is used for storing computer execution instructions;
the processor executing computer-executable instructions stored by the memory causes the processor to perform the method of determining a systematic error of a network analyzer of any of claims 1-8.
11. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor, implement the method for determining the system error of a network analyzer of any one of claims 1-8.
CN202210362003.4A 2022-04-07 2022-04-07 Method, device and equipment for determining system error of network analyzer and storage medium Pending CN114740414A (en)

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