CN114730701A

CN114730701A - Semiconductor die including diffusion barrier layer embedded in bond pad and method of forming the same

Info

Publication number: CN114730701A
Application number: CN202080081818.4A
Authority: CN
Inventors: 织田宪明; 翁照男
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2020-05-29
Filing date: 2020-12-29
Publication date: 2022-07-08
Also published as: WO2021242321A1

Abstract

A semiconductor device may be formed over a semiconductor substrate, and an interconnect-level dielectric material layer may be formed on the semiconductor device embedding a metal interconnect structure. In one embodiment, a pad connecting via level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad level dielectric material layer may be formed. A bond pad surrounded by a dielectric diffusion barrier portion may be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad and via level dielectric material layer may be formed. An integrated pad and via cavity may be formed through the pad and via level dielectric material layer and may be filled with a bond pad containing a dielectric diffusion barrier portion and an integrated pad and via structure.

Description

Semiconductor die including diffusion barrier layer embedded in bond pad and method of forming the same

RELATED APPLICATIONS

This application claims priority from the following patent applications: U.S. non-provisional patent application No. 16/888,055 filed on 29/5/2020; and U.S. non-provisional patent application No. 16/888,188, filed on 29/5/2020, which is hereby incorporated by reference in its entirety for all purposes.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular to a semiconductor die including a bond pad embedded in a diffusion barrier layer and a method of forming the same.

Background

A semiconductor memory device may include a memory array and a driver circuit on the same substrate. However, the driver circuitry takes up valuable space on the substrate, thereby reducing the available space for the memory array.

Disclosure of Invention

According to an aspect of the present disclosure, a structure is provided that includes a first semiconductor die. The first semiconductor die includes: a first semiconductor device over a first substrate; a first interconnect-level dielectric material layer embedding a first metal interconnect structure electrically connected to and overlying the first semiconductor device; a layer stack of a first pad connecting via level dielectric material layer and a first proximal dielectric diffusion barrier layer overlying the first interconnect level dielectric material layer and embedding the first pad connecting via structure; and a first pad-level dielectric material layer comprising first pad cavities filled with respective combinations of first bond pads and respective first dielectric diffusion barrier portions, wherein each of the first bond pads contacts a respective subset of the first pad connection via structures.

According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a layer stack of a first pad connecting via level dielectric material layer and a first proximal dielectric diffusion barrier layer over the first semiconductor device, the layer stack embedding a first metal interconnect structure; forming a first pad connecting via structure through the layer stack on a subset of the first metal interconnect structures; forming a first pad-level dielectric material layer over the layer stack; forming a first pad cavity through the first pad-level dielectric material layer; forming a first distal dielectric diffusion barrier layer in the first pad cavity and over the first pad-level dielectric material layer; forming an opening through the first distal dielectric diffusion barrier layer at a bottom portion of the first pad cavity, wherein a top surface of the first pad connecting via structure is physically exposed; and forming a first bond pad in a remaining volume of the first pad cavity directly on a top surface of the first pad connecting via structure.

According to an aspect of the present disclosure, a structure is provided that includes a first semiconductor die. The first semiconductor die includes: a first semiconductor device over a first substrate; a first interconnect-level dielectric material layer embedding a first metal interconnect structure electrically connected to and overlying the first semiconductor device; a first proximal dielectric diffusion barrier layer and a layer stack of a first pad and via level dielectric material layer overlying the first interconnect level dielectric material layer and embedding the first integrated pad and via structure; and first dielectric diffusion barrier portions embedded in the first pad and via level dielectric material layer, wherein each of the first dielectric diffusion barrier portions contacts and laterally surrounds a pad portion of a respective one of the first integrated pad and via structures.

According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a first interconnect-level dielectric layer embedding a first metal interconnect structure over the first semiconductor device; forming a first proximal dielectric diffusion barrier layer and a first pad and via level dielectric material layer over the first semiconductor device; forming a first integrated pad and a via cavity through the first pad and the via level dielectric material layer; forming a first distal dielectric diffusion barrier layer in the first integration pad and via cavity and over the first pad and via-level dielectric material layer; removing horizontal portions of the first distal dielectric diffusion barrier layer within the area of the first integration pad and the via cavity, wherein top surfaces of the subset of first metal interconnect structures are physically exposed; and forming a first integrated pad and via structure in the remaining volume of the first pad and via cavity.

Drawings

Fig. 1A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first interconnect-level dielectric material layer and a first metal interconnect structure according to a first embodiment of the present disclosure.

Fig. 1B is a schematic top view of the first semiconductor die of fig. 1A.

Fig. 1C is a schematic vertical cross-sectional view of a first configuration of a first semiconductor die along the vertical plane C-C of fig. 1B.

Fig. 1D is a schematic horizontal cross-sectional view of a first configuration of a first semiconductor die along the horizontal plane D-D' of fig. 1C. The vertical plane C-C is the plane of the vertical cross-section of fig. 1C.

Fig. 1E is a schematic horizontal cross-sectional view of a first configuration of a first semiconductor die along the horizontal plane E-E' of fig. 1C. The vertical plane C-C is the plane of the vertical cross-sectional view of fig. 1C.

Fig. 2A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming an interconnect capping dielectric diffusion barrier layer, a first pad connecting via level dielectric material layer, a first proximal dielectric diffusion barrier layer, and a first pad connecting via, according to a first embodiment of the present disclosure.

Fig. 2B is a schematic top view of the first semiconductor die of fig. 2A.

Fig. 3A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first pad connecting via structure according to a first embodiment of the present disclosure.

Fig. 3B is a schematic top view of the first semiconductor die of fig. 3A.

Fig. 4A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first pad level dielectric material layer and a first pad cavity according to a first embodiment of the present disclosure.

Fig. 4B is a schematic top view of the first semiconductor die of fig. 4A.

Fig. 5 is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

Fig. 6 is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after patterning a first distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

Figure 7 is a schematic vertical cross-sectional view of an area of a first configuration of a first semiconductor die after removal of a patterned photoresist layer according to a first embodiment of the present disclosure.

Fig. 8A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming first bond pads according to a first embodiment of the present disclosure.

Fig. 8B is a schematic top view of the first semiconductor die of fig. 8A.

Fig. 9 is a schematic vertical cross-sectional view of a region of a first configuration of a second semiconductor die after forming a second pad connecting via structure according to a first embodiment of the present disclosure.

Fig. 10 is a schematic vertical cross-sectional view of a region of a first configuration of a second semiconductor die after forming a second pad-level dielectric material layer and a second pad cavity according to a first embodiment of the present disclosure.

Fig. 11 is a schematic vertical cross-sectional view of a region of a first configuration of a second semiconductor die after forming a second distal dielectric diffusion barrier layer in accordance with a first embodiment of the present disclosure.

Fig. 12 is a schematic vertical cross-sectional view of a region of a first configuration of a second semiconductor die after patterning a second distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

Figure 13 is a schematic vertical cross-sectional view of a region of a first configuration of a second semiconductor die after removal of a patterned photoresist layer according to a first embodiment of the present disclosure.

Fig. 14 is a schematic vertical cross-sectional view of a region of a first configuration of a second semiconductor die after forming second bond pads according to a first embodiment of the present disclosure.

Fig. 15 is a schematic vertical cross-sectional view of a first example bonding structure after bonding a first configuration of a first semiconductor die to a first configuration of a second semiconductor die, according to a first embodiment of the present disclosure.

Fig. 16 is a schematic vertical cross-sectional view of a first exemplary bonding structure after thinning a first semiconductor die from the back side according to a first embodiment of the present disclosure.

Fig. 17 is a schematic vertical cross-sectional view of a first exemplary bonding structure after forming a backside insulation layer, external bonding pads, and solder material portions, according to a first embodiment of the present disclosure.

Figure 18 is a schematic vertical cross-sectional view of an alternative embodiment of a first semiconductor die according to a first embodiment of the present disclosure.

Fig. 19 is a schematic vertical cross-sectional view of an alternative embodiment of the first exemplary engagement structure according to the first embodiment of the present disclosure.

Fig. 20A is a vertical cross-sectional view of a second alternative embodiment of the first example junction assembly along the vertical plane a-a' of fig. 20E, in accordance with the first embodiment of the present disclosure.

Fig. 20B is a vertical cross-sectional view of the first exemplary junction assembly along vertical plane B-B' of fig. 20E.

Fig. 20C is a vertical cross-sectional view of the memory array region of the first exemplary bonding assembly along vertical plane C-C of fig. 20E.

FIG. 20D is a vertical cross-sectional view of a peripheral region of the first exemplary joining assembly taken along vertical plane D-D' of FIG. 20E.

Fig. 20E is a perspective plan view of the first exemplary engagement assembly shown in fig. 20A-20D.

FIG. 20F is a vertical cross-sectional view of the first exemplary junction assembly taken along vertical plane F-F' of FIG. 20E.

Fig. 20G is a vertical cross-sectional view of the first exemplary engagement assembly along vertical plane G-G' of fig. 20E.

Fig. 21A is a vertical cross-sectional view of a third alternative embodiment of the first example junction assembly, according to an embodiment of the present disclosure.

Fig. 21B is a vertical cross-section of a fourth alternative embodiment of the first example junction assembly, according to embodiments of the present disclosure.

Fig. 22 is a schematic vertical cross-sectional view of a region of a first semiconductor die in a second configuration after forming a first interconnect-level dielectric material layer, a first metal interconnect structure, a first proximal dielectric diffusion barrier layer, a first pad and via-level dielectric material layer, and a first pad cavity, according to a second embodiment of the present disclosure.

Fig. 23A is a schematic vertical cross-sectional view of a region of a first semiconductor die in a second configuration after forming a first integration pad and a via cavity according to a second embodiment of the present disclosure.

Fig. 23B is a schematic top view of the first semiconductor die of fig. 23A.

Fig. 24 is a schematic vertical cross-sectional view of a region of a first semiconductor die in a second configuration after forming a first distal dielectric diffusion barrier layer according to a second embodiment of the present disclosure.

Fig. 25 is a schematic vertical cross-sectional view of a region of a first semiconductor die in a second configuration after patterning a first distal dielectric diffusion barrier layer according to a second embodiment of the present disclosure.

Fig. 26 is a schematic vertical cross-sectional view of a region of a first semiconductor die in a second configuration after deposition of a first metal liner layer and a first metal pad fill material layer, according to a second embodiment of the present disclosure.

Fig. 27A is a schematic vertical cross-sectional view of a region of a first semiconductor die in a second configuration after forming a first integration pad and via structure according to a second embodiment of the present disclosure.

Fig. 27B is a schematic top view of the first semiconductor die of fig. 27A.

Fig. 28 is a schematic vertical cross-sectional view of a region of a second configuration of a second semiconductor die after forming a second proximal dielectric diffusion barrier layer, a second pad and via level dielectric material layer, and a second pad cavity, according to a second embodiment of the present disclosure.

Fig. 29A is a schematic vertical cross-sectional view of a region of a second configuration of a second semiconductor die after forming a second integration pad and a via cavity according to a second embodiment of the present disclosure.

Fig. 29B is a schematic top view of the second semiconductor die of fig. 29A.

Fig. 30 is a schematic vertical cross-sectional view of a region of a second configuration of a second semiconductor die after forming a second distal dielectric diffusion barrier layer in accordance with a second embodiment of the present disclosure.

Fig. 31 is a schematic vertical cross-sectional view of a region of a second configuration of a second semiconductor die after patterning a second distal dielectric diffusion barrier layer according to a second embodiment of the present disclosure.

Fig. 32 is a schematic vertical cross-sectional view of a region of a second configuration of a second semiconductor die after deposition of a second metal liner layer and a second metal pad fill material layer in accordance with a second embodiment of the present disclosure.

Fig. 33A is a schematic vertical cross-sectional view of a region of a second configuration of a second semiconductor die after forming a second integrated pad and via structure according to a second embodiment of the present disclosure.

Fig. 33B is a schematic top view of the second semiconductor die of fig. 33A.

Fig. 34 is a schematic vertical cross-sectional view of a second exemplary bonding structure after bonding a second configuration of first semiconductor dies to a second configuration of second semiconductor dies according to a second embodiment of the present disclosure.

Fig. 35 is a schematic vertical cross-sectional view of a second exemplary bonding structure after thinning a first semiconductor die from the back side according to a second embodiment of the present disclosure.

Fig. 36 is a schematic vertical cross-sectional view of a second exemplary bonding structure after forming a backside insulation layer, external bonding pads, and solder material portions according to a second embodiment of the present disclosure.

Figure 37 is a schematic vertical cross-sectional view of an alternative embodiment of a first semiconductor die according to a second embodiment of the present disclosure.

Fig. 38 is a schematic vertical cross-sectional view of an alternative embodiment of a second exemplary engagement structure according to a second embodiment of the present disclosure.

Detailed Description

In semiconductor dies configured for inter-pad bonding, the metal bond pads are provided as discrete structures without metal lines located between the bond pads, in order to reduce dishing or erosion of the metal bond pads during a chemical mechanical planarization (i.e., chemical mechanical polishing CMP) process. Thus, the bond pads in the edge seal region do not completely surround the inner portion of the die, and the edge seal structure has a lateral opening at the level of the metal bond pads. Moisture or ionic impurities may diffuse through the dielectric matrix embedding the metal bond pads and may penetrate into underlying semiconductor device components such as field effect transistors, memory cells, or metal interconnect structures and cause reliability degradation of various components in the semiconductor device. In other words, moisture or impurities may laterally diffuse through the gap between pairs of adjacent metal bond pads. Embodiments of the present disclosure relate to a semiconductor die including a diffusion barrier surrounded bond pad and methods of manufacturing the same, various aspects of which are discussed in detail below. The diffusion barrier layer reduces or prevents diffusion of moisture and/or impurities into the underlying semiconductor device components and improves the reliability of the semiconductor device.

The figures are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated to be absent repetition of the element. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The term "at least one" element is intended to mean all possibilities including single element possibilities and multiple element possibilities.

The same reference numbers indicate the same or similar elements. Elements having the same reference numerals are assumed to have the same composition and the same function unless otherwise specified. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. Two or more elements are "separated" from each other if the two or more elements are not in direct contact with each other. As used herein, a first element that is positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is "electrically connected" to a second element if there is a conductive path between the first element and the second element that is comprised of at least one conductive material. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range that is less than the range of an underlying or overlying structure. In addition, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above and/or below.

As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight in a direction that deviates from vertical by an angle of less than 5 degrees. The vertical or substantially vertical plane is straight in the vertical or substantially vertical direction and may or may not include curvature in a direction perpendicular to the vertical or substantially vertical direction.

As used herein, a "memory level" or "memory array level" refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through stack" element refers to an element that extends vertically through a memory level.

As used herein, "semiconductor material" is meant to have a chemical composition of 1.0X 10^-5S/m to 1.0X 10⁵A material having an electrical conductivity in the range of S/m. As used herein, "semiconductor material" refers to a material having a molecular weight of 1.0 x 10 in the absence of an electrical dopant therein^-5A material having an electrical conductivity in the range of S/m to 1.0S/m and capable of being produced with appropriate doping of an electrical dopant having a conductivity in the range of 1.0S/m to 1.0 x 10⁵A doping material of a conductivity in the range of S/m. As used herein, "electrical dopant" refers to a dopant that will be absentA p-type dopant where the hole adds to a valence band within the band structure, or an n-type dopant where the electron adds to a conduction band within the band structure. As used herein, "conductive material" means having a thickness of greater than 1.0 x 10⁵A material of S/m conductivity. As used herein, "insulator material" or "dielectric material" is meant to have a thickness of less than 1.0 x 10^-5A material of S/m conductivity. As used herein, "heavily doped semiconductor material" refers to a material that is doped with an electrical dopant at a sufficiently high atomic concentration to become conductive (i.e., has a concentration of greater than 1.0 x 10) when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initial amorphous state)⁵S/m conductivity). The "doped semiconductor material" may be a heavily doped semiconductor material, or may be a material including a dopant provided at 1.0 × 10^-5S/m to 1.0X 10⁵A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/m. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped semiconductor material. The doped semiconductor material may be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metallic element therein. All conductivity measurements were performed under standard conditions.

Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices, and may be fabricated employing the various embodiments described herein. The monolithic three-dimensional NAND string is positioned in a monolithic three-dimensional array of NAND strings over a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

Generally, a semiconductor package (or "package") refers to a unitary semiconductor device that may be attached to a circuit board by a set of pins or solder balls. Semiconductor packages may include one or more semiconductor chips (or "dies") that are through bonded, such as by flip chip bonding or another type of die-to-die bonding. A package or chip may include a single semiconductor die (or "die") or a plurality of semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip having multiple dies is capable of executing as many external commands simultaneously as the total number of planes therein. Each die includes one or more planes. The same concurrent operation may be performed in each plane within the same die, but there may be some limitations. Where the die is a memory die (i.e., a die including memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") that are the smallest units that can be erased by a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

Referring to fig. 1A-1E, a first semiconductor die 900 is shown in a first configuration. Fig. 1B and 1D-1E correspond to views of the entire area of the first semiconductor die 900 and the adjacent kerf areas that are subsequently removed during the die cut process. The first semiconductor die 900 includes a first substrate 908, a first semiconductor device 920 overlying the first substrate 908, a first interconnect-level dielectric material layer (290,960) overlying the first semiconductor device, and a first metal interconnect structure 980 embedded in the first interconnect-level dielectric material layer (290,960). In one embodiment, the first substrate 908 may be a first semiconductor substrate, such as a commercially available silicon wafer having a thickness in the range of 500 microns to 1 mm.

Discrete substrate recessed cavities can be formed in the upper portion of the first substrate 908 by applying a layer of photoresist over the top surface of the first substrate 908, photolithographically patterning the layer of photoresist to form an array of discrete openings, and transferring the pattern of the array of discrete openings into the upper portion of the first substrate by performing an anisotropic etch process. The photoresist layer may then be removed, for example, by ashing. The depth of each discrete substrate recess cavity may be in the range of 500nm to 10,000nm, although lesser and greater depths may also be used. A through-substrate liner 386 and a through-substrate via structure 388 may be formed within each discrete substrate recess cavity.

In general, the first semiconductor device 920 may include any semiconductor device known in the art. In one embodiment, the first semiconductor die 900 comprises a memory die and may include a memory device such as a three-dimensional NAND memory device. In an illustrative example, the first semiconductor device 920 may include a vertically alternating stack of insulating layers 32 and conductive layers 46, and a two-dimensional array of memory openings extending vertically through the vertically alternating stack (32, 46). Conductive layer 46 may comprise a word line of a three-dimensional NAND memory device.

A memory opening fill structure 58 may be formed within each memory opening. The memory opening fill structure 58 may include a memory film and a vertical semiconductor channel contacting the memory film. The memory film may include a blocking dielectric, a tunneling dielectric, and a charge storage material between the blocking dielectric and the tunneling dielectric. The charge storage material may include a charge trapping layer (such as a silicon nitride layer) or a plurality of discrete charge trapping regions (such as floating gates or discrete portions of the charge trapping layer). In this case, each memory opening fill structure 58 and adjacent portions of conductive layer 46 comprise a vertical NAND string. Alternatively, the memory opening fill structure 58 may include any type of non-volatile memory elements, such as resistive memory elements, ferroelectric memory elements, phase change memory elements, and the like. The memory device may include an optional horizontal semiconductor channel layer 10 connected to the bottom end of each vertical semiconductor channel, and an optional dielectric spacer layer 910 that provides electrical isolation between the first substrate 908 and the horizontal semiconductor channel layer 10.

The conductive layers 46 may be patterned to provide a mesa region in which each overlying conductive layer 46 has a smaller lateral extent than any underlying conductive layer 46. Contact via structures (not shown) may be formed in the land areas on conductive layer 46 to provide electrical connections to conductive layer 46. Dielectric material portions 65 may be formed around each vertically alternating stack (32,46) to provide electrical isolation between adjacent vertically alternating stacks (32, 46).

A through memory level via cavity may be formed through dielectric material portion 65, optional dielectric spacer layer 910, and horizontal semiconductor channel layer 10. An optional through-memory-level dielectric liner 486 and a through-memory-level via structure 488 can be formed within each through-memory-level via cavity. Each through memory level dielectric liner 486 comprises a dielectric material, such as silicon oxide. Each through-memory-level via structure 488 can be formed directly on a respective one of the through-substrate via structures 388.

The first interconnect-level dielectric material layer (290,960) may include a first proximal interconnect-level dielectric material layer 290 embedding contact via structures and bit lines 982, and a first distal interconnect-level dielectric material layer 960 embedding a subset of the first metal interconnect structures 980 located above the first proximal interconnect-level dielectric material layer 290. Bit lines 982 are a subset of first metal interconnect structure 980 and may electrically contact drain regions above the semiconductor channels at the top of memory opening fill structures 58. The contact via structures contact respective nodes of the first semiconductor device. Generally, the first metal interconnect structure 980 may be electrically connected to the first semiconductor device 920. A proximal subset of the first metal interconnect structures 980 may be located within a first distal interconnect level dielectric material layer 960. Interconnect metal lines and interconnect metal via structures that are a subset of the first metal interconnect structure 980 may be embedded in the first distal interconnect level dielectric material layer 960. In an illustrative example, the first metal interconnect structure 980 may include a first memory-side metal level M1 including memory-side first level metal lines and a second memory-side metal level M2 including memory-side second level metal lines.

Each of the first proximal interconnect-level dielectric material layer 290 and the first distal interconnect-level dielectric material layer 960 may comprise a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, silicon nitride, dielectric metalAn oxide, or a combination thereof. The first distal interconnect-level dielectric material layer 960 may include one or more dielectric diffusion barrier layers (not explicitly shown). In this case, each dielectric diffusion barrier layer embedded in the first distal interconnect-level dielectric material layer 960 may comprise silicon carbonitride (i.e., silicon carbonitride "SiCN," which is also referred to as silicon carbide nitride), silicon nitride (Si) (Si₃N₄) Silicon oxynitride or any other dielectric material that effectively blocks the diffusion of copper. In one embodiment, each dielectric diffusion barrier embedded in the first distal interconnect-level dielectric material layer 960 may comprise a dielectric material having a dielectric constant less than 5, such as less than 4, such as SiCN having a dielectric constant of about 3.8, to reduce the RC delay of the first metal interconnect structure 980. Each dielectric diffusion barrier layer may have a thickness in the range of 10nm to 300 nm.

At least one edge seal structure (688,984,986) shown in fig. 1B-1E may be formed around the perimeter of the first semiconductor die 900 through the dielectric material portion 65 and the first interconnect level dielectric material layer (290,960). For example, at least one moat trench may be formed extending vertically through dielectric material portion 65 and optionally through a lower level of the first interconnect-level dielectric material layer (290,960), and the at least one moat trench may then be filled with at least one dielectric material to form at least one first metal wall structure 688. Multiple nested metal wall structures 688 can be formed. Each first metal wall structure 688 extends continuously around a perimeter of the first semiconductor die 900 and completely laterally encapsulates the first semiconductor device 920. The entire bottom surface of each metal wall structure 688 can contact the top surface of the first substrate 908.

Each of the at least one edge seal structures (688,984,986) may also optionally include at least one via level ring structure 984 overlying and formed at a respective metal wall structure of the at least one metal wall structure 688. Each via level ring structure 984 is a component of the first metal interconnect structure 980. Additionally, each of the edge seal structures (688,984,986) may include at least one wire level ring structure 986. Each line level ring structure 986 is a component of the first metal interconnect structure 980. Each wire level ring structure 986 overlies and is formed at a respective metal wall structure of the at least one metal wall structure 688. In general, each edge seal structure (688,984,986) includes at least one set of continuous conductive material portions that extend vertically from the first substrate 908 to a top surface of the first interconnect-level dielectric material layer (290,960). Each edge seal structure (688,984,986) includes a set of continuous portions of conductive material that laterally surround the first semiconductor device 920 without any openings therethrough.

In one embodiment, each of the at least one edge seal structure (688,984,986) may include a metal wall structure 688 and a respective subset of first metal interconnect structures 980 providing a respective continuous barrier layer laterally surrounding the first semiconductor device 920 without any lateral openings. Each of the at least one edge sealing structures (688,984,986) extends vertically from the first substrate 908 to a topmost surface of the first distal interconnect level dielectric material layer 980.

Referring to fig. 2A and 2B, a layer stack may be formed including a first interconnect capping dielectric diffusion barrier 962, a first pad connecting via level dielectric material layer 964, and a first proximal dielectric diffusion barrier 972. The first interconnect cap dielectric diffusion barrier 962 may include a dielectric material that blocks copper diffusion. In one embodiment, the first interconnect capping dielectric diffusion barrier 962 may comprise silicon nitride, silicon carbo-nitride, silicon oxy-nitride, or a stack thereof. In one embodiment, the first interconnect cap dielectric diffusion barrier 962 may include a dielectric material having a dielectric constant less than 5, such as less than 4, such as a silicon carbon nitride having a dielectric constant of about 3.8. The thickness of the first interconnect capping dielectric diffusion barrier 962 may be in the range of 5nm to 50nm, although lesser and greater thicknesses may also be used.

The first pad connecting via-level dielectric material layer 964 may include and/or consist essentially of undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the first pad connecting via level dielectric material layer 964 may be in the range of 100nm to 3,000nm, although lesser and greater thicknesses may also be used. The first pad connecting via level dielectric material layer 964 may have a planar top surface.

The first proximal dielectric diffusion barrier 972 may comprise a dielectric material (e.g., a moisture barrier) that blocks moisture diffusion. The first proximal dielectric diffusion barrier layer 972 comprises and/or consists essentially of a dielectric material, such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the first proximal dielectric diffusion barrier layer 972 may comprise a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9. The thickness of the first proximal dielectric diffusion barrier layer 972 may be in the range of 5nm to 100nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the first proximal dielectric diffusion barrier layer 972 and may be lithographically patterned to form discrete openings in regions overlying the topmost metal interconnect structure of the first metal interconnect structure 980. An anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer through the first proximal dielectric diffusion barrier layer 972, the first pad connecting via level dielectric material layer 964, and the first interconnect capping dielectric diffusion barrier layer 962. A first pad connection via cavity 967 is formed through the first proximal dielectric diffusion barrier 972. The top surface of the topmost metal interconnect structure 980 may be physically exposed at the bottom of each first pad connection via cavity 967.

In one embodiment, the first pad connection via cavities 967 may be arranged as clusters of first pad connection via cavities 967, as shown in fig. 2B. Each cluster of first pad connection via cavities 967 may be located within an area of a respective one of bond pads to be subsequently formed. For example, each of the bonding pads may have a rectangular shape or a rounded rectangular shape having sides parallel to the first horizontal direction hd1 and the second horizontal direction hd 2. A dimension of each of the bonding pads in the first horizontal direction hd1 and a dimension of each of the bonding pads in the second horizontal direction hd2 are in a range of 2 microns to 60 microns. In this case, each cluster of first pad connection via cavities 967 may be arranged as a rectangular array. Although the figures show each cluster of first pad connection via cavities 967 as a 4 x 4 rectangular array, each cluster of first pad connection via cavities 967 may be formed as an M x N rectangular array, where M and N are independent integers. Alternatively, a single first pad connection via cavity 967 may be formed for each area of a bond pad to be subsequently formed.

Each first pad connection via cavity 967 is formed in an area of a respective topmost metal interconnect structure in the topmost metal interconnect structure 980. A cluster of first land connection via cavities 967 may be formed along each edge seal structure (688,984,986). The clusters of first pad connection via cavities 967 and gap regions may alternate over the entire area of each edge seal structure (688,984,986) along the perimeter of the first semiconductor die 900. In the presence of multiple nested edge seal structures (688,984,986), multiple laterally alternating sequences of clusters of first pad connection via cavities 967 and gap regions are disposed along the perimeter of the first semiconductor die 900.

Referring to fig. 3A and 3B, an optional pad connecting via level metallic barrier layer and pad connecting via level metallic fill material may be sequentially deposited in the first pad connecting via cavity 967. The pad connecting via level metal barrier layer comprises a conductive metal barrier material, such as TiN, TaN and/or WN. The conductive metal barrier material can block moisture and copper diffusion. The thickness of the pad connecting via-level metal barrier layer may be in the range of 4nm to 80nm, such as 8nm to 40nm, but smaller and larger thicknesses may also be used. The pad connecting via level metal fill material may comprise any suitable metal or metal alloy, such as tungsten.

Excess portions of the pad connect via level metal fill material and pad connect via level metal barrier layer overlying a horizontal plane including the top surface of the first proximal dielectric diffusion barrier layer 972 may be removed by a planarization process, such as chemical mechanical planarization. The remaining portions of the pad connect via-level metal fill material and the pad connect via-level metal barrier layer filling the first pad connect via cavity 967 constitute a first pad connect via structure 968. Each first pad connecting via structure 968 may include an optional pad connecting via level metal barrier liner 968A and a pad connecting via level metal fill material portion 968B. The pad connecting via level metal barrier liner 968A is a patterned remaining portion of the pad connecting via level metal barrier layer, and the pad connecting via level metal fill material portion 968B is a patterned remaining plug portion (e.g., tungsten plug) of the pad connecting via level metal fill material. Alternatively, the pad connection via level metal barrier liner 968A may be omitted. The top surface of the first pad connecting via structure 968 may be in the same horizontal plane as the top surface of the first proximal dielectric diffusion barrier layer 972.

Referring to fig. 4A and 4B, a first pad-level dielectric material layer 974 may be formed over the first proximal dielectric diffusion barrier layer 972. The first pad-level dielectric material layer 974 may include and/or consist essentially of undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the first pad-level dielectric material layer 974 may be in the range of 300nm to 3,000nm, although lesser and greater thicknesses may also be used. The first pad-level dielectric material layer 974 may have a planar top surface.

A photoresist layer (not shown) may be applied over the first pad-level dielectric material layer 974 and may be lithographically patterned to form discrete openings in each region of the clusters of first pad connecting via structures 968. In other words, each discrete opening in the photoresist layer overlies a respective cluster in the first pad connecting via structure 968. Each discrete opening in the photoresist layer has the shape of a bond pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape with sides parallel to the first horizontal direction hd1 and the second horizontal direction hd 2. The dimension of each opening in the first horizontal direction hd1 and the dimension of each opening in the second horizontal direction hd2 are in the range of 2 microns to 60 microns.

An etching process, such as an anisotropic etching process, may be performed to transfer the pattern of openings in the photoresist layer through the first pad-level dielectric material layer 974. A first pad cavity 979 is formed through the first pad-level dielectric material layer 974. The top surface of the array of first pad connection via structures 968 may be physically exposed at the bottom of each first pad cavity 979. Alternatively, the top surface of the single pad connection via structure 968 may be physically exposed at the bottom of each first pad cavity 979. Each first pad cavity 979 may have a horizontal cross-sectional shape that is rectangular or rounded rectangular such that a dimension of each first pad cavity 979 in the first horizontal direction hd1 is in a range of 2 microns to 60 microns, and a dimension of each first pad cavity 979 in the second horizontal direction hd2 is in a range of 2 microns to 60 microns. In one embodiment, each first pad cavity 979 may have a horizontal cross-sectional shape that is square or rounded square such that the dimension of each first pad cavity 979 in the first horizontal direction hd1 and the dimension of each first pad cavity 979 in the second horizontal direction hd2 are the same. In this case, the size of each first pad cavity 979 in the first horizontal direction hd1 and in the second horizontal direction hd2 may be in the range of 2 microns to 60 microns, such as 4 microns to 30 microns. The sidewalls of the first pad cavity 979 may be vertical, or may have a taper angle greater than 0 degrees and less than 30 degrees with respect to vertical (such as a taper angle in the range of 3 degrees to 10 degrees).

Referring to fig. 5, a first distal dielectric diffusion barrier 976 may be deposited in the first pad cavity 979 and over the first pad-level dielectric material layer 974. A first distal dielectric diffusion barrier 976 is deposited on the top surface of the first pad connecting via structure 968. The first distal dielectric diffusion barrier 976 comprises and/or consists essentially of a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the first distal dielectric diffusion barrier layer 976 comprises a moisture resistant dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The thickness of the first distal dielectric diffusion barrier 976 may be in the range of 5nm to 50nm, such as 10nm to 25nm, although lesser and greater thicknesses may also be used.

Referring to fig. 6, a photoresist layer 977 may be applied over the first distal dielectric diffusion barrier layer 976 and may be lithographically patterned to form discrete openings therethrough. Each area of discrete openings in the photoresist layer 977 may be located inside the bottom perimeter of a respective first pad cavity 979, i.e., inside the closed bottom edge of a set of sidewalls of the respective first pad cavity 979 that abut the top surface of the first proximal dielectric diffusion barrier layer 972. In other words, an opening through the photoresist layer 977 may be formed within an area of the bottom surface of the first pad cavity 979 by photolithographically patterning the photoresist layer 977.

The unmasked portions of the first distal dielectric diffusion barrier layer 976 may be anisotropically etched by performing an anisotropic etching process that employs the patterned photoresist layer 977 as an etch mask. An opening is formed through the first distal dielectric diffusion barrier 976 at a bottom portion of the first pad cavity 979. The remaining portions of the patterned first distal dielectric diffusion barrier 976 include first dielectric diffusion barrier portions 976P that laterally surround respective ones of the first pad cavities 979. A top surface of the first pad connecting via structure 968 is physically exposed under the first pad cavity 979.

Each of the first dielectric diffusion barrier portions 976P of the first distal dielectric diffusion barrier 976 that laterally surrounds a respective one of the first pad cavities 979 contacts the top surface of the first proximal dielectric diffusion barrier 972. Specifically, each of the first dielectric diffusion barrier portions 976P includes a sidewall segment that is in contact with the first pad-level dielectric material layer 974 and extends vertically from a bottom surface of the first pad-level dielectric material layer 974 and a top surface of the first pad-level dielectric material layer 974. In one embodiment, a perimeter of each opening through the first distal dielectric diffusion barrier 976 may be laterally offset inward from a bottom perimeter of a respective opening through the first pad-level dielectric material layer 974. In this case, each of the first dielectric diffusion barrier portions 976P includes a horizontal segment having a bottom surface that contacts the first proximal dielectric diffusion barrier layer 972. The bottom surface may include an outer periphery that abuts a bottom edge of the sidewall section of the respective first dielectric diffusion barrier portion 976P and an inner periphery that is laterally offset inward from the outer periphery by an offset distance osd that is greater than a thickness of the sidewall section of the first dielectric diffusion barrier portion 976P.

Referring to fig. 7, the patterned photoresist layer 977 may be removed, for example, by ashing. Referring to fig. 8A and 8B, a first bond pad liner layer and a first metal pad fill material may be sequentially deposited in the first pad cavity 979. The first bond pad liner layer includes a metal nitride material, such as TiN, TaN, and/or WN. The conductive metal barrier material can block copper diffusion. A first bond pad liner layer is formed on the top surface of the first pad connecting via structure 968 and on a portion of the top surface of the proximal dielectric diffusion barrier layer 972 within the opening through the first distal dielectric diffusion barrier layer 976 (i.e., within the first pad cavity 979). The thickness of the first bond pad liner layer may be in the range of 4nm to 80nm, such as 8nm to 40nm, although lesser and greater thicknesses may also be used. The first metal pad fill material may include copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process that fills the remaining volume of the first pad cavity 979.

Excess portions of the first metal pad fill material and the first bond pad liner layer overlying the horizontal plane including the top surface of the first distal dielectric diffusion barrier 976 may be removed by a planarization process, such as chemical mechanical planarization. The first metal pad filling material filling the first pad cavity 979 and the remaining portion of the first bond pad liner layer constitute a first bond pad 988. Each first bond pad 988 can include a first bond pad liner 988A and a first metal pad filler material portion 988B. The first bond pad liner 988A is a patterned remaining portion of the first bond pad liner layer and the first metal pad fill material portion 988B is a patterned remaining portion of the first metal pad fill material. The top surface of the first bond pad 988 may be in the same horizontal plane as the top surface of the first distal dielectric diffusion barrier 976.

Generally, the first bond pad 988 is formed in the remaining volume of the first pad cavity 979 directly on the top surface of the first pad connecting via structure 966 after patterning the first distal dielectric diffusion barrier layer 976. Each of the first bond pads 988 includes and/or consists of a first bond pad liner 988A comprising a metal nitride material and a first metal pad fill material portion 988B (e.g., a copper portion) embedded in the bond pad liner 988A.

In one implementation, the first dielectric diffusion barrier portions 976P are interconnected to one another through a first horizontally extending diffusion barrier portion overlying the first pad-level dielectric material layer 974. The top surface of the first bond pad 988 may lie in a horizontal plane that includes the top surface of the first horizontally extending diffusion barrier portion of the first distal dielectric diffusion barrier 976.

In one embodiment, each first bond pad 988 may physically and electrically contact a respective subset of the underlying first pad connecting via structures 968, which may be a respective plurality of first pad connecting via structures 968. Each of the first bond pads 988 may directly contact a portion of the top surface of the first proximal dielectric diffusion barrier layer 972 between the respective plurality of first pad connecting via structures 968. Generally, the first pad-level dielectric material layer 974 includes first pad cavities filled with respective combinations of first bond pads 988 and respective first dielectric diffusion barrier portions 976P.

A first subset of the first bond pads 988 may be located within an area surrounded by the at least one edge seal structure (688,984,986) and may be electrically connected to respective nodes of the first semiconductor device 920. A second subset of the first bond pads 988 may be located on and electrically connectable to a respective edge seal structure of the at least one edge seal structure (688,984,986).

Referring to fig. 9, a region of a second semiconductor die 700 in a first configuration is shown. The second semiconductor die 700 includes a second substrate 708, a second semiconductor device 720 overlying the second substrate 708, a second interconnect-level dielectric material layer 760 overlying the second semiconductor device 720, and a second metal interconnect structure 780 embedded in the second interconnect-level dielectric material layer 760. In one embodiment, the second semiconductor device 720 may include at least one Complementary Metal Oxide Semiconductor (CMOS) circuit including a field effect transistor. In one embodiment, the second substrate 708 may be a second semiconductor substrate, such as a commercially available silicon substrate having a thickness in the range of 500 microns to 1 mm.

In general, the second semiconductor device may include any semiconductor device that can operate in conjunction with the first semiconductor device in the first semiconductor die 900 to provide enhanced functionality. In one embodiment, the first semiconductor die 900 comprises a memory die and the second semiconductor die 700 comprises a logic die that includes support circuitry (i.e., peripheral circuitry) for operating a memory device (such as a three-dimensional array of memory elements) within the memory die. In one embodiment, the first semiconductor die 900 may include a three-dimensional memory device including a three-dimensional memory element array, word lines (which may include a subset of conductive layer 46), and bit lines 982, and the second semiconductor device 720 of the second semiconductor die 700 may include peripheral circuitry for operating the three-dimensional memory element array. The peripheral circuit may include: one or more word line driver circuits that drive word lines of a three-dimensional array of memory elements of the first semiconductor die 900; one or more bit line driver circuits that drive bit lines 982 of the first semiconductor die 900; one or more word line decoder circuits that decode addresses of word lines; one or more bit line decoder circuits that decode addresses of bit lines 982; one or more sense amplifier circuits that sense a state of memory elements within the memory opening fill structures 58 of the first semiconductor die 900; a source power supply circuit that supplies power to the horizontal semiconductor channel layer 10 in the first semiconductor die 900; data buffers and/or latches; and/or any other semiconductor circuitry that may be used to operate the three-dimensional memory device of the first semiconductor die 900.

The second interconnect-level dielectric material layer 760 may comprise a dielectric material, such as undoped silicate glass (e.g., silicon oxide), doped silicate glass, organosilicate glass, silicon nitride, a dielectric metal oxide, or a combination thereof. In an illustrative example, the second metal interconnect structure 780 may include a first logic side metal level D1 including logic side first level metal lines and a second logic side metal level D2 including logic side second level metal lines.

The second interconnect-level dielectric material layer 760 may include one or more dielectric diffusion barrier layers (not explicitly shown). In this case, each dielectric diffusion barrier embedded in the second interconnect-level dielectric material layer 760 may comprise silicon carbon nitride (SiCN), silicon nitride (Si3N4), silicon oxynitride, or any other dielectric material that effectively blocks the diffusion of copper. In one embodiment, each dielectric diffusion barrier embedded in the second interconnect-level dielectric material layer 760 may comprise a dielectric material having a dielectric constant less than 5, such as less than 4 (such as SiCN having a dielectric constant of about 3.8) to reduce the RC delay of the first metal interconnect structure 980. Each dielectric diffusion barrier layer may have a thickness in the range of 10nm to 300 nm. At least one edge seal structure (not shown) may be formed around the perimeter of the second semiconductor die 700 through the second interconnect-level dielectric material layer 760 in the same manner as the first semiconductor die 900. Each of the at least one edge seal structure in the second semiconductor die 700 may include a metal wall structure and optionally at least one via level ring structure and/or at least one line level ring structure. Each edge sealing structure in the second semiconductor die 700 includes a set of continuous conductive material portions that laterally surround the second semiconductor device 720 without any openings therethrough. Each of the at least one edge seal structure in the second semiconductor die 700 extends vertically from the second substrate 708 to a top surface of the second interconnect-level dielectric material layer 780.

A layer stack including a second interconnect cap dielectric diffusion barrier 762, a second pad connecting via level dielectric material layer 764, and a second proximal dielectric diffusion barrier 772 may be formed over the second interconnect level dielectric material layer 780. The second interconnect cap dielectric diffusion barrier 762 may comprise a dielectric material that blocks copper diffusion. In one embodiment, the second interconnect cap dielectric diffusion barrier 762 may comprise silicon nitride, silicon carbonitride, silicon oxynitride, or a stack thereof. In one embodiment, the second interconnect cap dielectric diffusion barrier 762 may comprise a dielectric material having a dielectric constant less than 5, such as less than 4, such as a silicon carbon nitride having a dielectric constant of about 3.8. The thickness of the second interconnect capping dielectric diffusion barrier 762 may be in the range of 5nm to 50nm, although lesser and greater thicknesses may also be used.

The second pad connecting via-level dielectric material layer 764 may comprise and/or consist essentially of undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the second pad connecting via level dielectric material layer 764 may be in the range of 100nm to 3,000nm, although lesser and greater thicknesses may also be used. The second pad connecting via level dielectric material layer 764 may have a planar top surface.

The second proximal dielectric diffusion barrier 772 may include a dielectric material that blocks moisture diffusion. The second proximal dielectric diffusion barrier 772 contains and/or consists essentially of a dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the second proximal dielectric diffusion barrier 772 may include a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9. The thickness of the second proximal dielectric diffusion barrier 772 may be in the range of 5nm to 100nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the second proximal dielectric diffusion barrier 772 and may be lithographically patterned to form discrete openings in the regions overlying the topmost metal interconnect structure of the second metal interconnect structure 780. An anisotropic etch process may be performed to transfer the pattern of openings in the photoresist layer through the second proximal dielectric diffusion barrier 772, the second pad connecting via-level dielectric material layer 764, and the second interconnect capping dielectric diffusion barrier 762. A second pad connecting via cavity is formed through the second proximal dielectric diffusion barrier 772. A top surface of the topmost metal interconnect structure 780 may be physically exposed at a bottom of each second pad connection via cavity.

In one embodiment, the second pad connection via cavities may be arranged as clusters of second pad connection via cavities. Each cluster of second pad connection via cavities may be located within an area of a respective one of the bond pads to be subsequently formed. For example, each bond pad may have a rectangular shape with orthogonal sides or a rounded rectangular shape. A dimension of each bond pad in a direction along a side of the rectangular or rounded rectangular shape may be in a range of 2 to 60 micrometers. In this case, each cluster of second pad connection via cavities may be arranged as a rectangular array. Each cluster of second pad connection via cavities may be formed as an M 'x N' rectangular array, where M 'and N' are independent integers. Alternatively, a single second pad connection via cavity may be formed for each area of a bond pad to be subsequently formed.

Each second pad connection via cavity is formed within a region of a respective topmost metal interconnect structure in the topmost metal interconnect structure 780. A cluster of second land connection via cavities may be formed along each edge seal structure. The clusters of second pad connection via cavities and gap regions may alternate over the entire area of each edge seal structure along the perimeter of the second semiconductor die 700. In the presence of a plurality of nested edge seal structures, a plurality of laterally alternating sequences of clusters of second pad connection via cavities and gap regions are disposed along a perimeter of the second semiconductor die 700.

An optional pad connect via level metal barrier and pad connect via level metal fill material may be sequentially deposited in the second pad connect via cavity. The pad connecting via level metal barrier layer comprises a conductive metal barrier material, such as TiN, TaN and/or WN. The conductive metal barrier material can block copper diffusion. The thickness of the pad connecting via level metal barrier layer may be in the range of 4nm to 80nm, such as 8nm to 40nm, although lesser and greater thicknesses may also be used. The pad connecting via level metal fill material may comprise any suitable metal or metal alloy, such as tungsten.

Excess portions of the pad connect via level metal fill material and the pad connect via level metal barrier layer overlying a horizontal plane including the top surface of the second proximal dielectric diffusion barrier 772 may be removed by a planarization process, such as chemical mechanical planarization. The remaining portions of the pad connecting via-level metal fill material and the pad connecting via-level metal barrier layer filling the second pad connecting via cavity constitute a second pad connecting via structure 768. Each second pad connecting via structure 768 may include an optional pad connecting via-level metal barrier liner 768A and a pad connecting via-level metal fill material portion 768B. Landing via-level metal barrier liner 768A is a patterned remaining portion of the landing via-level metal barrier layer, and landing via-level metal fill material portion 768B is a patterned remaining plug portion (e.g., a tungsten plug) of the landing via-level metal fill material. Alternatively, pad connecting via level metal barrier liner 768A may be omitted. The top surface of the second pad connection via structure 768 may be in the same horizontal plane as the top surface of the second proximal dielectric diffusion barrier 772.

Referring to fig. 10, a second pad-level dielectric material layer 774 may be formed over the second proximal dielectric diffusion barrier 772. The second pad-level dielectric material layer 774 may comprise and/or consist essentially of undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the second pad-level dielectric material layer 774 may be in the range of 300nm to 3,000nm, although lesser and greater thicknesses may also be used. The second pad-level dielectric material layer 774 may have a planar top surface.

A photoresist layer (not shown) may be applied over the second pad-level dielectric material layer 774 and may be lithographically patterned to form discrete openings in each region of the clusters of second pad connecting via structures 768. In other words, each discrete opening in the photoresist layer overlies a respective cluster in the second pad connecting via structure 768. Each discrete opening in the photoresist layer has the shape of a bond pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape with sides parallel to the second horizontal direction hd1 and the second horizontal direction hd 2. A size of each opening in the second horizontal direction hd1 and a size of each opening in the second horizontal direction hd2 are in a range of 2 microns to 60 microns.

An etching process, such as an anisotropic etching process, may be performed to transfer the pattern of openings in the photoresist layer through the second pad-level dielectric material layer 774. A second pad cavity 779 is formed through the second pad-level dielectric material layer 774. The top surface of the array of second pad connecting via structures 768 may be physically exposed at the bottom of each second pad cavity 779. Alternatively, the top surface of the single pad connecting via structure 768 may be physically exposed at the bottom of each second pad cavity 779. Each pad cavity 779 may have a horizontal cross-sectional shape that is rectangular or rounded rectangular such that a dimension of each pad cavity 779 in a horizontal direction along a side of the rectangular or rounded rectangular is in a range of 2 microns to 60 microns. In one embodiment, each pad cavity 779 may have a horizontal cross-sectional shape that is square or rounded square.

Referring to fig. 11, a second distal dielectric diffusion barrier 776 may be deposited in the second pad cavity 779 and over the second pad-level dielectric material layer 774. A second distal dielectric diffusion barrier 776 is deposited on the top surface of the second pad connection via structure 768. The second distal dielectric diffusion barrier layer 776 comprises and/or consists essentially of a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the second distal dielectric diffusion barrier 776 comprises a moisture resistant dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The thickness of the second distal dielectric diffusion barrier 776 may be in the range of 5nm to 50nm, such as 10nm to 25nm, although lesser and greater thicknesses may also be used.

Referring to fig. 12, a photoresist layer 777 may be applied over the second distal dielectric diffusion barrier 776 and may be lithographically patterned to form discrete openings therethrough. Each region of discrete openings in the photoresist layer 777 may be located inside the bottom perimeter of a respective second pad cavity 779, i.e., inside the closed bottom edge of a set of sidewalls of the respective second pad cavity 779 that abut the top surface of the second proximal dielectric diffusion barrier 772. In other words, an opening through the photoresist layer 777 may be formed within an area of the bottom surface of the second pad cavity 779 by photolithographically patterning the photoresist layer 777.

The unmasked portions of the second distal dielectric diffusion barrier layer 776 may be anisotropically etched by performing an anisotropic etching process that employs the patterned photoresist layer 777 as an etch mask. An opening is formed through the second distal dielectric diffusion barrier 776 at a bottom portion of the second pad cavity 779. The remaining portions of the patterned second distal dielectric diffusion barrier 776 include second dielectric diffusion barrier portions 776P that laterally surround respective ones of the second pad cavities 779. The top surface of the second pad connecting via structure 768 is physically exposed under the second pad cavity 779.

Each of the second dielectric diffusion barrier portions 776P of the second distal dielectric diffusion barrier 776 that laterally surrounds a respective one of the second pad cavities 779 contacts the top surface of the second proximal dielectric diffusion barrier 772. In particular, each of the second dielectric diffusion barrier portions 776P includes sidewall segments that are in contact with the second pad-level dielectric material layer 772 and extend vertically from a bottom surface of the second pad-level dielectric material layer 774 and a top surface of the second pad-level dielectric material layer 774. In one embodiment, a perimeter of each opening through the second distal dielectric diffusion barrier 776 may be laterally offset inward from a bottom perimeter of a respective opening through the second pad-level dielectric material layer 774. In this case, each of the second dielectric diffusion barrier portions 776P includes a horizontal segment having a bottom surface that contacts the second proximal dielectric diffusion barrier 772. The bottom surface may include an outer periphery that abuts a bottom edge of the sidewall section of the respective second dielectric diffusion barrier portion 776P and an inner periphery that is laterally offset inward from the outer periphery by an offset distance osd that is greater than a thickness of the sidewall section of the second dielectric diffusion barrier portion 776P.

Referring to fig. 13, patterned photoresist layer 777 can be removed, for example, by ashing.

Referring to fig. 14, a second bond pad liner layer and a second metal pad fill material may be sequentially deposited in a second pad cavity 779. The second bond pad liner layer includes a metal nitride material, such as TiN, TaN, and/or WN. The conductive metal barrier material can block copper diffusion. A second bond pad liner layer is formed on the top surface of the second pad connecting via structure 768 and on a portion of the top surface of the proximal dielectric diffusion barrier 772 within the opening through the second distal dielectric diffusion barrier 776 (i.e., within the second pad cavity 779). The thickness of the second bond pad liner layer may be in the range of 4nm to 80nm, such as 8nm to 40nm, although lesser and greater thicknesses may also be used. The second metal pad fill material may comprise copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process that fills the remaining volume of the second pad cavities 779.

Excess portions of the second metal pad fill material and the second bond pad liner layer overlying a horizontal plane including the top surface of the second distal dielectric diffusion barrier 776 may be removed by a planarization process, such as chemical mechanical planarization. The second metal pad filling material filling the second pad cavity 779 and the remaining portion of the second bond pad liner layer constitute a second bond pad 788. Each second bond pad 788 can include a second bond pad liner 788A and a second metal pad fill material portion 788B. The second bond pad liner 788A is a patterned remainder of the second bond pad liner layer and the second metal pad fill material portion 788B is a patterned remainder of the second metal pad fill material. The top surface of the second bond pad 788 may be in the same horizontal plane as the top surface of the second pad-level dielectric material layer 774.

Generally, the second bond pads 788 are formed in the remaining volume of the second pad cavities 779 directly on the top surface of the second pad connection via structure 766 after patterning the second distal dielectric diffusion barrier 776. Each of the second bond pads 788 includes and/or consists of a second bond pad liner 788A comprising a metal nitride material and a second metal pad fill material portion 788B embedded in the second bond pad liner 788A.

In one implementation, the second dielectric diffusion barrier portions 776P interconnect each other through second horizontally extending diffusion barrier portions overlying the second pad-level dielectric material layer 774. The top surface of the second bond pad 788 may lie in a horizontal plane including the top surface of the second horizontally extending diffusion barrier portion of the second distal dielectric diffusion barrier 776.

In one embodiment, each second bond pad 788 may physically and electrically contact a respective subset of the lower, which may be a respective plurality of second pad connecting via structures 768, of second pad connecting via structures 768. Each of the second bond pads 788 may directly contact a portion of the top surface of the second proximal dielectric diffusion barrier 772 located between a respective plurality of second pad connecting via structures 768. Generally, the second pad-level dielectric material layer 774 includes second pad cavities filled with respective combinations of the second bond pads 788 and respective second dielectric diffusion barrier portions 776P.

A first subset of the second bond pads 788 can be located within an area surrounded by at least one edge sealing structure in the second semiconductor die 700 and can be electrically connected to a respective node of the second semiconductor device 720. The second subset of second bond pads 788 may be located on and electrically connectable to a respective edge seal structure of the at least one edge seal structure. The pattern of the second bond pads 788 may be arranged in a mirror image pattern of the first bond pads 988.

Referring to fig. 15, the second semiconductor die 700 and the first semiconductor die 700 may be aligned such that each second bond pad 788 faces a respective one of the first bond pads 988. Each pair of facing first and second bond pads 988,788 may be aligned to maximize the area overlap between the first and

second bond pads

988, 788. If the first and second bond pads 988,788 have different areas, each overlapping area between a pair of facing first and second bond pads 988,788 may be the same as the area of the smaller bond pad between a pair of facing first and

second bond pads

988, 788. If the first and second bond pads 988,788 have the same area, the area of overlap between a pair of facing first and second bond pads 988,788 may be in the range of 90% to 100%, such as 95% to 100%, of the area of the first bond pad 988 (which is the same as the area of the second bond pad 788).

The first semiconductor die 900 and the second semiconductor die 700 can be in contact with each other such that each first bond pad 988 contacts a respective one of the second bond pads 788 with a respective area overlap therebetween. The assembly of the first semiconductor die 900 and the second semiconductor die 700 is annealed at an elevated temperature in the range of 250 degrees celsius to 400 degrees celsius to cause copper diffusion at each interface between the pair of oppositely facing respective first bond pads 988 and respective second bond pads 788. The duration of the annealing process at high temperature may be in the range of 5 minutes to 2 hours, although shorter or longer annealing durations may also be used. Each pair of facing first and second bond pads 988,788 are bonded to each other during an annealing process at high temperature. A first exemplary bonding structure including a first semiconductor die 900 and a second semiconductor die 700 can be formed.

A layer stack including a horizontally extending portion of the first distal dielectric diffusion barrier 976 and a horizontally extending portion of the second distal dielectric diffusion barrier 776 may be located between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774. The vertical separation distance between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774 may be the sum of the thickness of the first distal dielectric diffusion barrier 976 and the thickness of the second distal dielectric diffusion barrier 776.

Referring to fig. 16, the first substrate 908 can be thinned from the backside by grinding, polishing, anisotropic etching, or isotropic etching. The thinning process may continue until the horizontal portion of the through substrate liner 386 is removed and the horizontal surface of the through substrate via structure 388 is physically exposed. In general, by thinning the back side of the first substrate 908, which may be the substrate of a memory die, the end surfaces of the through substrate via structures 388 are physically exposed. The thickness of the first substrate 908 after thinning may be in the range of 1 micron to 30 microns, such as 2 microns to 15 microns, although lesser and greater thicknesses may also be used.

Referring to fig. 17, a backside insulating layer 930 may be formed on the backside of the first substrate 908. The backside insulating layer 930 comprises an insulating material, such as silicon oxide. The thickness of the backside insulating layer 930 may be in the range of 50nm to 500nm, although lesser and greater thicknesses may also be used. A photoresist layer (not shown) may be applied over the backside insulating layer 930 and may be lithographically patterned to form openings over the areas of the through-substrate via structures 388. An etching process can be performed to form a via cavity through the backside insulation layer 930 under each opening in the photoresist layer. The top surface of the through-substrate via structures 388 may be physically exposed at the bottom of each via cavity through the backside insulating layer 930.

At least one metallic material may be deposited into the openings through the backside insulating layer 930 and over the planar surface of the backside insulating layer 930 to form a metallic material layer. The at least one metallic material may include copper, aluminum, ruthenium, cobalt, molybdenum, and/or any other metallic material that may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, vacuum evaporation, or other deposition methods. For example, a metal nitride liner material (such as TiN, TaN, or WN) can be deposited directly on the physically exposed surfaces of the through-substrate via structure 388, on the sidewalls of the opening through the backside insulating layer 930, and over the physically exposed planar surfaces of the backside insulating layer 930. The thickness of the metal nitride liner material may be in the range of 10nm to 100nm, although lesser and greater thicknesses may also be used. At least one metallic fill material, such as copper or aluminum, may be deposited over the metal nitride liner material. In one embodiment, the at least one metallic fill material may include a stack of highly conductive metal layers, such as copper or aluminum layers, and an Under Bump Metallurgy (UBM) layer stack for bonding solder balls thereto. Exemplary UBM layer stacks include, but are not limited to, Al/Ni/Au stacks, Al/Ni/Cu stacks, Cu/Ni/Au stacks, Cu/Ni/Pd stacks, Ti/Ni/Au stacks, Ti/Cu/Ni/Au stacks, Ti-W/Cu stacks, Cr/Cu stacks, and Cr/Cu/Ni stacks. The thickness of the layer of metal material above the planar horizontal surface of the backside insulating layer 930 may be in the range of 0.5 to 10 microns, such as 1 to 5 microns, although lesser and greater thicknesses may also be used.

The at least one metallic fill material and the metallic material layer may then be patterned to form discrete backside bond pads 936 to contact a respective one of the through-substrate via structures 388. The backside bond pads 936 may serve as external bond pads that may be used to electrically connect various nodes within the first semiconductor die 900 and the second semiconductor die 700 to external nodes, such as bond pads on a package substrate or C4 bond pads of another semiconductor die. For example, solder material portions 938 may be formed on the backside bond pads 936, and a C4 bonding process or wire bonding process may be performed to electrically connect the backside bond pads 936 to the external electrically active node.

In general, the back side bond pads 936 can be formed on a back side surface of the first semiconductor die 900 (which can be a memory die) on an opposite side of the bonding interface between the first semiconductor die 900 and the second semiconductor die 700. The through-substrate via structure 388 may extend vertically through the first semiconductor die 900 and may provide electrical connections between the backside bond pads 936 and a subset of the bond pads (988,788).

Referring to fig. 18, an alternative embodiment of a first semiconductor die 900 is shown in accordance with a first embodiment of the present disclosure. An alternative embodiment of the first semiconductor die 900 of fig. 8A and 8B may be obtained by removing the horizontally extending portion of the first distal dielectric diffusion barrier 976 overlying the first pad-level dielectric material layer 974. For example, after removing the metal material from over the top surface of the first distal dielectric diffusion barrier 976, the horizontally extending portion of the first distal dielectric diffusion barrier 976 overlying the first pad-level dielectric material layer 974 may be removed by an additional polishing step of a chemical mechanical planarization process. In this case, a top surface of the first pad-level dielectric material layer 974 may be physically exposed after the planarization process, and a top surface of the first bond pad 988 may be formed within the same horizontal plane as the top surface of the first pad-level dielectric material layer 974. After removing the horizontally extending portion of the first distal dielectric diffusion barrier 976, the remaining portion of the first distal dielectric diffusion barrier 976 includes a first dielectric diffusion barrier portion 976'. The first dielectric diffusion barrier portions 976' are not interconnected with each other and are formed as discrete structures laterally surrounding respective first bond pads 988.

Referring to fig. 19, a second semiconductor die 700 may be provided in the same manner as described above and may be bonded with the alternative configuration of the first semiconductor die shown in fig. 18 to provide an alternative embodiment of the first bonding assembly. The processing steps of fig. 16 and 17 may be performed on the structure shown in fig. 19. In this case, the horizontally extending portion of the second distal dielectric diffusion barrier 776 may be located between the first and second pad-level dielectric material layers 974 and 774. The vertical separation distance between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774 may be the same as the thickness of the second distal dielectric diffusion barrier 776. The first dielectric diffusion barrier portions 976' are discrete material portions laterally spaced from one another by the first pad-level dielectric material layer 974. The top surface of the first bond pad 988 may lie within a horizontal plane that includes the top surface of the first pad-level dielectric material layer 974.

In another alternative embodiment of the first semiconductor die 900 according to the first embodiment of the present disclosure, the horizontally extending portion of the second distal dielectric diffusion barrier 776 overlying the second pad-level dielectric material layer 774 may be removed. In this alternative embodiment, the vertical separation distance between the first and second pad-level dielectric material layers 974,774 may be the same as the thickness of the first distal dielectric diffusion barrier layer 976 disposed between the first and second pad-level dielectric material layers 974, 774.

With reference to fig. 20A-20G, a second alternative embodiment of the first exemplary engagement assembly is shown. In this case, the horizontal semiconductor channel layer 10 and the optional dielectric spacer layer 910 may be omitted from the first semiconductor die 900 shown in fig. 17, and a three-dimensional memory element array may be formed directly on the first substrate 908. The first semiconductor die 900 may include a back side metallic material plate 906 that may serve as a conductive path through a subset of the memory level via structures 488. The back side metal material plate 906 may be embedded in the back side insulating layer 930, which may include a first back side insulating sub-layer 930A, a second back side insulating sub-layer 930B, and a third back side insulating sub-layer 930C. For example, the first backside insulating sublayer 930A may include silicon oxide, the second backside insulating sublayer 930B may include silicon oxide, and the third backside insulating sublayer 930C may include polyimide. The back-side metallic material plate 906 may be formed between the first back-side insulating sublayer 930A and the second back-side insulating sublayer 930B.

The dielectric diffusion barrier 952 may be embedded within the first distal interconnect level dielectric material layer 960. In one embodiment, the dielectric diffusion barrier 952 may comprise a copper barrier dielectric material having a dielectric constant less than 5, such as less than 4, such as silicon carbon nitride having a dielectric constant of about 3.8. Additionally, an additional dielectric diffusion barrier 752 may be embedded within the second interconnect-level dielectric material layer 760. In one embodiment, the additional dielectric diffusion barrier layer 752 may comprise a copper barrier dielectric material having a dielectric constant of less than 5, such as less than 4, such as silicon carbon nitride having a dielectric constant of about 3.8.

The combination of the first proximal dielectric diffusion barrier 972, the first distal dielectric diffusion barrier 976, the second proximal dielectric diffusion barrier 772, and the second distal dielectric diffusion barrier 776 form a continuous diffusion barrier structure that protects the first metal interconnect structure 980 embedded in the first distal interconnect-level dielectric material layer 960 and protects the second metal interconnect structure 780 embedded in the second interconnect-level dielectric material layer 760 from the diffusion of moisture and/or contaminants through the first pad-level dielectric material layer 974 or the second pad-level dielectric material layer 774. In addition, the combination of the first proximal dielectric diffusion barrier layer 972, the first distal dielectric diffusion barrier layer 976, and the pad connection via level metal barrier liner 968A form a continuous diffusion barrier structure that protects the first metal interconnect structure 980 embedded in the first distal interconnect level dielectric material layer 960 from the diffusion of moisture and/or contaminants through the first pad connection via level dielectric material layer 964. The combination of the second proximal dielectric diffusion barrier 772, the second distal dielectric diffusion barrier 776, and the pad connection via level metal barrier liner 768A forms a continuous diffusion barrier structure that protects the second metal interconnect structure 780 embedded in the second interconnect level dielectric material layer 760 from the diffusion of moisture and/or contaminants through the second pad connection via level dielectric material layer 764. Further, if the opposing copper bond pads of the first and second semiconductor dies are misaligned with each other, at least one of the first and second distal

dielectric diffusion barriers

976, 776 blocks diffusion of copper out of the edges of the misaligned copper bond pads into the opposing first or second pad-level dielectric material layer (974,774). This reduces void formation in the bond pad and possible delamination of the bonded assembly.

Referring to fig. 21A and 21B, an alternative embodiment of the first exemplary engagement assembly is shown. In the embodiment illustrated in fig. 21A, the edge seal structure of the first semiconductor die 900 including the first metal wall structure 688 is electrically grounded to the second substrate 708 of the second semiconductor die 700 through the edge seal structure of the second semiconductor die 700 including the second metal wall structure 388. In the embodiment illustrated in fig. 21B, the edge seal structure of the first semiconductor die 900 including the first metal wall structure 688 and the edge seal structure of the second semiconductor die 700 including the second metal wall structure 388 are electrically grounded to an external electrical ground through the stacked backside metal material plate 906 including the metal plate liner 906A and the metal fill material portion 906B. The back side metal material plate 906 may be formed through an opening in the back side insulating layer 930.

Referring to fig. 1A-21B and in accordance with various embodiments of the present disclosure, a structure includes a first semiconductor die 900. The first semiconductor die 900 includes: a first semiconductor device 920 located over the first substrate 908; a first interconnect-level dielectric material layer (290,960) embedded in a first metal interconnect structure 980 electrically connected to the first semiconductor device 920 and overlying the first semiconductor device 920 (i.e., the first metal interconnect structure 980 is on a side of the first substrate 908 opposite the first semiconductor device 920); a layer stack of a first pad connection via level dielectric material layer 964 and a first proximal dielectric diffusion barrier layer 972 overlying the first interconnect level dielectric material layer (290,960) and embedding the first pad connection via structure 968; and a first pad-level dielectric material layer 974 comprising first pad cavities filled with respective combinations of first bond pads 988 and respective first dielectric diffusion barrier portions (976P or 976'), wherein each of the first bond pads 988 contacts a respective subset of the first pad connection via structures 968.

In one embodiment, each of the first dielectric diffusion barrier portions (976P or 976') contacts a top surface of the first proximal dielectric diffusion barrier layer 972. In one embodiment, each of the first dielectric diffusion barrier portions (976P or 976') includes a sidewall segment that is in contact with the first pad-level dielectric material layer 974 and extends from a bottom surface of the first pad-level dielectric material layer 974 to a top surface of the first pad-level dielectric material layer 974. In one embodiment, each of the first dielectric diffusion barrier portions (976P or 976') further includes a horizontal segment having a bottom surface contacting the first proximal dielectric diffusion barrier layer 972, wherein the bottom surface includes an outer perimeter abutting a bottom edge of the sidewall segment and an inner perimeter laterally offset inward from the outer perimeter by an offset distance osd greater than a thickness of the sidewall segment of the first dielectric diffusion barrier portion (976P or 976').

In one embodiment, the respective subset of first pad connecting via structures 968 includes a plurality of first pad connecting via structures 968; and each of the first bond pads 988 directly contacts a portion of the top surface of the first proximal dielectric diffusion barrier layer 972 between the plurality of first pad connecting via structures 968. In one embodiment, the top surface of the first pad connecting via structure 968 is in the same horizontal plane as the top surface of the first proximal dielectric diffusion barrier layer 972.

In one embodiment, each of the first bond pads 988 includes: a first bond pad liner 988A comprising a metal nitride material; and copper having a first metal pad fill material portion 988B embedded in the bond pad liner 988A. In one embodiment, the first dielectric diffusion barrier portions 976P are interconnected to one another through first horizontally extending diffusion barrier portions overlying the first pad-level dielectric material layer 974 (i.e., horizontally extending portions of the first distal dielectric diffusion barrier layer 976); and a top surface of the first bond pad 988 lies in a horizontal plane that includes a top surface of the first horizontally extending diffusion barrier portion. In another embodiment, the first dielectric diffusion barrier portions 976' are discrete material portions laterally spaced from one another by the first pad-level dielectric material layer 974; and a top surface of the first bond pad 988 lies within a horizontal plane that includes a top surface of the first pad-level dielectric material layer 974.

In one embodiment, the first dielectric diffusion barrier portion (976P or 976') comprises a dielectric material selected from silicon nitride, silicon oxynitride, or a stack thereof; and the first proximal dielectric diffusion barrier layer 972 comprises a dielectric material selected from silicon nitride, silicon oxynitride, or silicon carbonitride.

In one embodiment, the structure includes a second semiconductor die 700 comprising: a second semiconductor device 720 located over the second substrate 708; a second interconnect-level dielectric material layer 760 embedding a second metal interconnect structure 780 electrically connected to the second semiconductor device 720 and overlying the second semiconductor device 720; and second bond pads 788 electrically connected to the second metal interconnect structure 780 and bonded to respective ones of the first bond pads 988. In one embodiment, each of the second bond pads 788 contacts and is laterally surrounded by a respective second dielectric diffusion barrier 776P; and the second bond pad 788 and the second dielectric diffusion barrier 776P are embedded in the second pad-level dielectric material layer 774. In one embodiment, the second semiconductor die 700 includes a layer stack of second pad connection via level dielectric material layers 764 and a second proximal dielectric diffusion barrier 772 between the second interconnect level dielectric material layers 760 and the second pad level dielectric material layers 774 and embedded within the second pad connection via structures 768, wherein each of the second bond pads 788 contacts a respective subset of the second pad connection via structures 768.

In one implementation, the first semiconductor die 900 includes: an additional planar diffusion barrier 962 (such as the first interconnect capping dielectric diffusion barrier 962) between the first interconnect-level dielectric material layer (290,960) and the first pad connecting via-level dielectric material layer 964; and at least one edge sealing structure (688,984,986) comprising a respective subset of the first metal interconnect structures 980, the at least one edge sealing structure providing a respective continuous barrier laterally surrounding the first semiconductor device 920 without any lateral openings and extending vertically from the first substrate 908 to the additional planar diffusion barrier.

In a first exemplary bonding structure according to a first embodiment of the present disclosure, the bonding pad may be formed by a single damascene process. In a second exemplary bonding structure according to a second embodiment of the present disclosure shown in fig. 22 to 38, a bonding pad may be formed through a dual damascene process. Referring to fig. 22, a region of a second configuration of a first semiconductor die 900 is shown. The second configuration of the first semiconductor die 900 may be derived from the first configuration of the first semiconductor die 900 shown in fig. 1A-1E by sequentially depositing a layer stack including a first proximal dielectric diffusion barrier layer 972 and a first pad and via level dielectric material layer 954 over the first distal interconnect level dielectric material layer 960.

The first proximal dielectric diffusion barrier layer 972 contacts a top surface of a subset of the first metal interconnect structures 980 and a topmost surface of the first interconnect-level dielectric material layer 960. The first proximal dielectric diffusion barrier 972 may comprise a dielectric material that blocks the diffusion of moisture. The first proximal dielectric diffusion barrier layer 972 comprises and/or consists essentially of a dielectric material, such as silicon nitride, silicon oxynitride, and/or silicon carbonitride. In one embodiment, the first proximal dielectric diffusion barrier layer 972 may comprise silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the first proximal dielectric diffusion barrier layer 972 may comprise a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon nitride oxide having a dielectric constant in the range of 5 to 7.9. The thickness of the first proximal dielectric diffusion barrier layer 972 may be in the range of 5nm to 100nm, although lesser and greater thicknesses may also be used.

A first pad and via level dielectric material layer 954 may be formed over the first proximal dielectric diffusion barrier layer 972. First pad and via-level dielectric material layer 954 may comprise and/or consist essentially of undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the first pad and via-level dielectric material layer 954 may be in a range of 600nm to 6,000nm, although lesser and greater thicknesses may also be used. The first pad and via level dielectric material layer 954 may have a planar top surface.

A photoresist layer (not shown) may be applied over the first pad and via level dielectric material layer 954 and may be lithographically patterned to form discrete openings in regions overlying the first metal interconnect structure 980 embedded within the topmost layer of the first distal interconnect level dielectric material layer 960. Each discrete opening in the photoresist layer has the shape of a bond pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape. The dimension of each opening in a direction along a side of the opening in the photoresist layer may be in a range of 2 microns to 60 microns.

An anisotropic etch process may be performed to transfer the pattern of openings in the photoresist layer through the first pad and upper portion of the via-level dielectric material layer 954. A first pad cavity 979 is formed partially through the first pad and via level dielectric material layer 954. The depth of the first pad cavity 979 may be in the range of 20% to 80%, such as 40% to 60%, of the thickness of the first pad and via-level dielectric material layer 954. Each first pad cavity 979 may have a horizontal cross-sectional shape that is rectangular or rounded rectangular such that a lateral dimension of each first pad cavity 979 in a direction of each side of the rectangular or rounded rectangular shape is in a range of 2 microns to 60 microns. In one embodiment, each first pad cavity 979 may have a horizontal cross-sectional shape that is square or rounded square. The sidewalls of the first pad cavity 979 may be vertical, or may have a taper angle greater than 0 degrees and less than 30 degrees with respect to vertical (such as a taper angle in the range of 3 degrees to 10 degrees).

Referring to fig. 23A and 23B, another layer of photoresist (not shown) may be applied over the first pad and via level dielectric material layer 954 and may be lithographically patterned to form discrete openings within the area of the first pad cavity 979. Specifically, at least one opening in the photoresist layer may be formed within each region of the first pad cavity 979. In one embodiment, a cluster of openings (such as an array of openings) in the photoresist layer may be formed within each pad cavity region. In another embodiment, one opening in the photoresist layer may be formed within each pad cavity region. An anisotropic etch process may be performed to transfer the pattern of openings in the photoresist layer through the first pad and lower portion of the via-level dielectric material layer 954. A first pad connection via cavity 969 is formed through a lower portion of the first pad and via level dielectric material layer 954. The top surface of the topmost metal interconnect structure 980 may be physically exposed at the bottom of each first pad connection via cavity 969. The photoresist layer may then be removed, for example, by ashing.

A first integrated line and via cavity 959 is formed through the first pad and via level dielectric material layer 954. Each first integrated line and via cavity 959 includes a respective one of first pad cavities 979 and at least one first pad connection via cavity 969. In one embodiment, the first integrated line and via cavity 959 may include a first pad cavity 979 and a plurality of first pad connection via cavities 969 (such as clusters of pad connection via cavities). Top surfaces of a subset of the first metal interconnect structures 980 are physically exposed to the first pad and via cavities 959 when the first pad and via cavities 959 are formed.

In one embodiment, the first pad connection via cavities 969 may be arranged as clusters of first pad connection via cavities. Each cluster of first pad connection via cavities 969 may be located within an area of a respective one of first pad cavities 979. For example, each first pad cavity 979 may have a rectangular shape or a rounded rectangular shape having sides parallel to the first horizontal direction hd1 and the second horizontal direction hd 2. A dimension of each first pad cavity 979 in the first horizontal direction hd1 and a dimension of each first pad cavity 979 in the second horizontal direction hd2 are in a range of 2 microns to 60 microns. In this case, each cluster of first pad connection via cavities 969 may be arranged as a rectangular array. Each cluster of first pad connection via cavities 969 may be formed as an M × N rectangular array, where M and N are independent integers. Alternatively, a single first pad connection via cavity 969 may be formed for each area of a bond pad to be subsequently formed.

Each first pad connection via cavity 969 is formed within a region of a respective topmost metal interconnect structure in topmost metal interconnect structure 980. A cluster of first land connection via cavities 969 may be formed along each edge seal structure (688,984,986). The clusters of first pad connection via cavities 969 and gap regions may alternate over the entire area of each edge seal structure (688,984,986) along the perimeter of the first semiconductor die 900. In the presence of multiple nested edge seal structures (688,984,986), multiple laterally alternating sequences of clusters of first pad connection via cavities 969 and gap regions are disposed along the perimeter of the first semiconductor die 900.

Referring to fig. 24, a first distal dielectric diffusion barrier 956L may be deposited in the first integrated line and via cavity 959 and over the first pad and via-level dielectric material layer 954. A first distal dielectric diffusion barrier 956L is deposited on the top surface of the underlying first metal interconnect structure 980 and on the physically exposed surfaces of the first pad and via-level dielectric material layer 954. The first distal dielectric diffusion barrier layer 956L comprises and/or consists essentially of a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the first distal dielectric diffusion barrier 956L comprises a moisture-resistant dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The first distal dielectric diffusion barrier 956L may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The thickness of the first distal dielectric diffusion barrier 956L may be in the range of 5nm to 50nm, such as 10nm to 25nm, although lesser and greater thicknesses may also be used.

Referring to fig. 25, a photoresist layer 977 may be applied over the first distal dielectric diffusion barrier 956L and may be lithographically patterned to form discrete openings therethrough. An opening is formed through the photoresist layer 977 in the area of the bottom surface of the first integration pad and via cavity 959 by photolithographically patterning the photoresist layer 977. Each area of discrete openings in photoresist layer 977 may be located inside a bottom perimeter of the pad cavity portion of a respective first integrated line and via cavity 959, i.e., inside a closed bottom edge of a set of sidewalls of the pad cavity portion of a respective first integrated line and via cavity 959. Each opening through the photoresist layer 977 may include an entire area of a set of at least one first pad connection via cavity 969 located below a pad cavity portion 979 of a respective first integrated line and via cavity 959.

The unmasked portions of the first distal dielectric diffusion barrier layer 956L are anisotropically etched by performing an anisotropic etching process that employs the patterned photoresist layer 977 as an etch mask. The unmasked horizontal portions of the first distal dielectric diffusion barrier 956L may be anisotropically etched by an anisotropic etching process. The horizontal portion of the first distal dielectric diffusion barrier 956L within the area of the first integration pad and via cavity 959 may be removed by an anisotropic etch process and the top surfaces of the subset of first metal interconnect structures 980 directly beneath the first proximal dielectric diffusion barrier 972 are physically exposed.

Openings are formed through the first distal dielectric diffusion barrier layer 956L along each perimeter of the openings through the patterned photoresist layer 977. The horizontally extending portion of the first distal dielectric diffusion barrier 956L at the bottom region of the pad cavity portion of the first integrated line and via cavity 959 and above the first pad connection via cavity 969 is removed. Accordingly, the horizontal portion of the first distal dielectric diffusion barrier 956L at the bottom portion of the first pad connection via cavity 969 is removed. The remaining portion of the patterned first distal dielectric diffusion barrier 956L comprises a first dielectric diffusion barrier portion 956P that laterally surrounds the respective pad cavity portion 979 of the first integrated line and via cavity 959. Portions of the top surface of the respective first metal interconnect structures 980 are physically exposed under each first integrated line and via cavity 959.

The remaining portion of the first distal dielectric diffusion barrier 956L after the anisotropic etching process includes a first dielectric diffusion barrier portion 956P formed on the sidewall of the pad cavity portion 979 of the first integrated pad and via cavity 959, and a first tubular dielectric diffusion barrier liner 955 formed on the sidewall of the first via cavity portion 969 of the first integrated pad and via cavity 959 below the pad cavity portion 979. The continuous remaining portion of the first distal dielectric diffusion barrier layer 956L, including the first dielectric diffusion barrier portion 956P, after the anisotropic etching process is referred to herein as the first distal dielectric diffusion barrier layer 956. The first distal dielectric diffusion barrier 956 comprises a first horizontally extending diffusion barrier portion overlying the first pad and via level dielectric material layer 954. The first dielectric diffusion barrier portions 956P are interconnected to each other by first horizontally extending diffusion barrier portions of the first distal dielectric diffusion barrier layer 956.

Each of the first dielectric diffusion barrier portions 956P is vertically spaced apart from the first proximal dielectric diffusion barrier layer 972. Each of the tubular dielectric diffusion barrier liners 955 laterally surrounds a first via cavity portion 969 of a respective one of the first integrated pad and via cavities 959. In one embodiment, the tubular dielectric diffusion barrier liner 955 does not contact and is laterally spaced apart from the first dielectric diffusion barrier portion 956P. Each tubular dielectric diffusion barrier liner 955 can contact the cylindrical sidewall of a respective opening in the first proximal dielectric diffusion barrier layer 972.

Each of the first dielectric diffusion barrier portions 956P of the first distal dielectric diffusion barrier 956 laterally surrounds a pad cavity portion 979 of the respective first integrated line and via cavity 959 and is vertically spaced apart from the first proximal dielectric diffusion barrier 972 by a lower portion of the first pad and via-level dielectric material layer 954. In one embodiment, the perimeter of each opening through the first distal dielectric diffusion barrier layer 956 may be laterally offset outward from a set of respective at least one tubular dielectric diffusion barrier liner 955. In this case, each of the first dielectric diffusion barrier portions 956P comprises a horizontal section having a bottom surface that contacts the horizontal surfaces of the first pad and via-level dielectric material layer 954. Patterned photoresist layer 977 may then be removed, for example, by ashing.

Referring to fig. 26, a first bond pad liner layer 958L and a first metal pad fill material layer 958F may be sequentially deposited in the first integrated line and via cavity 959. The first bond pad liner layer 958L includes a metal nitride material, such as TiN, TaN, and/or WN. The conductive metal barrier material can block copper diffusion. The first bond pad liner layer 958L is formed on the top surface of the subset of the first metal interconnect structure 980 at the topmost level of the first distal interconnect-level dielectric material layer 960, on the inner wall of the tubular dielectric diffusion barrier liner 955, on the physically exposed surface of the first distal dielectric diffusion barrier layer 956, and on the physically exposed horizontal surface of the first pad and via-level dielectric material layer 954 between the topmost surface of the first pad and via-level dielectric material layer 954 and the bottom surface of the first pad and via-level dielectric material layer 954. The thickness of the first bond pad liner layer 958L may be in the range of 4nm to 80nm, such as 8nm to 40nm, although lesser and greater thicknesses may also be used. The first metal pad fill material layer 958F may comprise copper, which may be deposited by a combination of a copper seed layer deposition process employing physical vapor deposition and a copper plating process that fills the remaining volume of the first integrated line and via cavity 959.

Referring to fig. 27A and 27B, excess portions of the first metal pad fill material layer 958F and the first bond pad liner layer 958L overlying a horizontal plane including the top surface of the first distal dielectric diffusion barrier layer 956 may be removed by a planarization process, such as chemical mechanical planarization. The remaining portions of the first metal pad fill material layer 958F and the first bond pad liner layer 958L filling the first integrated line and via cavities 959 constitute a first integrated pad and via structure 958 (e.g., a dual damascene first bond pad). Each first integrated pad and via structure 958 may comprise a first bond pad liner 958A and a first metal pad fill material portion 958B. The first bond pad liner 958A is a patterned remaining portion of the first bond pad liner layer 958L, and the first metal pad fill material portion 958B is a patterned remaining portion of the first metal pad fill material layer 958F. The top surface of the first integrated pad and via structure 958 may be in the same horizontal plane as the top surface of the first distal dielectric diffusion barrier layer 956.

Generally, first integrated pad and via structure 958 is formed in the remaining volume of first integrated line and via cavity 959. Each of the first integrated pad and via structures 958 includes and/or consists of a first bond pad liner 988A comprising a metal nitride material and a first metal pad fill material portion 988B embedded in the bond pad liner 988A.

In one implementation, the first dielectric diffusion barrier portions 956P interconnect to each other through first horizontally extending diffusion barrier portions overlying the first pad and via-level dielectric material layer 954. The top surface of the first integrated pad and via structure 958 may lie within a horizontal plane that includes the top surface of the first horizontally-extending diffusion barrier portion of the first distal dielectric diffusion barrier layer 956. Each of the first integration pad and via structures 958 may directly contact at least one sidewall of the first proximal dielectric diffusion barrier layer 972. Generally, first pad and via level dielectric material layer 954 includes first integrated wire and via cavities filled with respective combinations of first integrated pad and via structures 958 and respective first dielectric diffusion barrier portions 956P.

A first subset of the first integrated pad and via structures 958 may be located within an area of the at least one edge seal structure (688,984,986) and may be electrically connected to a respective node of the first semiconductor device 920. The second subset of the first integrated pad and via structures 958 may be located on, and may be electrically connected to, a respective edge seal structure of the at least one edge seal structure (688,984,986).

In one embodiment, the first bond pad liner 958A within each of the first integrated pad and via structures 958 extends continuously from a top surface of the respective first metal interconnect structure in the first metal interconnect structure 980 to a horizontal plane including a topmost surface of the first dielectric diffusion barrier portion 956P and directly contacts a horizontal surface of the first pad and via-level dielectric material layer 954 that is within an area of an opening through the respective first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion 956P.

Each first integrated pad and via structure 958 has at least one bottom surface that contacts first metal interconnect structure 980. In one embodiment, the via portion of the first integration pad and via structure 958 contacts a horizontal surface of the first metal interconnect structure 980 located at a topmost level of the first distal interconnect-level dielectric material layer 960. The first dielectric diffusion barrier portion 956P is embedded in the first pad and via-level dielectric material layer 954. Each of the first dielectric diffusion barrier portions 956P contacts and laterally surrounds a pad portion of a respective one of the first integrated pad and via structures 958. Each tubular dielectric diffusion barrier liner 955 laterally surrounds a via portion of a respective one of the first integrated pad and via structures 958.

Referring to fig. 28, a region of a second semiconductor die 700 in a second configuration is shown. The second configuration of the second semiconductor die 700 may be derived from the first configuration of the second semiconductor die 700 illustrated in fig. 9 by sequentially depositing a layer stack including a second proximal dielectric diffusion barrier 772 and a second pad and via level dielectric material layer 754 directly on the topmost surface of the second interconnect level dielectric material layer 760. In other words, the second interconnect cap dielectric diffusion barrier 762 and the second pad connection via level dielectric material layer 764 shown in fig. 9 are not formed, and the second proximal dielectric diffusion barrier 772 may be formed directly on the top surface of the second interconnect level dielectric material layer 760.

The second proximal dielectric diffusion barrier 772 contacts the top surfaces of the subset of second metal interconnect structures 780 and the topmost surface of the second dielectric material layer 760. The second proximal dielectric diffusion barrier 772 may include a dielectric material that blocks moisture diffusion. The second proximal dielectric diffusion barrier 772 contains and/or consists essentially of a dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the second proximal dielectric diffusion barrier 772 may include a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon nitride oxide having a dielectric constant in the range of 5 to 7.9. The thickness of the second proximal dielectric diffusion barrier 772 may be in the range of 5nm to 100nm, although lesser and greater thicknesses may also be used.

A second pad and via level dielectric material layer 754 may be formed over the second proximal dielectric diffusion barrier 772. The second pad and via-level dielectric material layer 754 may comprise and/or consist essentially of undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the second pad and via-level dielectric material layer 754 may be in the range of 600nm to 6,000nm, although lesser and greater thicknesses may also be used. The second pad and via-level dielectric material layer 754 may have a planar top surface.

A photoresist layer (not shown) may be applied over the second pad and via level dielectric material layer 754 and may be lithographically patterned to form discrete openings in regions overlying the second metal interconnect structure 780 embedded within the topmost layer of the second interconnect level dielectric material layer 760. Each discrete opening in the photoresist layer has the shape of a bond pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape. The dimension of each opening in a direction along a side of the opening in the photoresist layer may be in a range of 2 microns to 60 microns.

An anisotropic etch process may be performed to transfer the pattern of openings in the photoresist layer through the second pad and upper portion of the via-level dielectric material layer 754. A second pad cavity 779 is formed partially through the second pad and via level dielectric material layer 754. The depth of the second pad cavity 779 may be in the range of 20% to 80%, such as 40% to 60%, of the thickness of the second pad and via level dielectric material layer 754. Each second pad cavity 779 may have a horizontal cross-sectional shape that is rectangular or rounded rectangular such that a lateral dimension of each second pad cavity 779 in a direction of each side of the rectangular or rounded rectangular shape is in a range of 2 microns to 60 microns. In one embodiment, each second pad cavity 779 can have a horizontal cross-sectional shape that is square or rounded square. The sidewalls of the second pad cavity 779 may be vertical or may have a taper angle greater than 0 degrees and less than 30 degrees relative to vertical (such as a taper angle in the range of 3 degrees to 10 degrees).

Referring to fig. 29A and 29B, a layer of photoresist (not shown) may be applied over the second pad and via level dielectric material layer 754 and may be lithographically patterned to form discrete openings within the area of the second pad cavity 779. Specifically, at least one opening in the photoresist layer may be formed within each region of the second pad cavity 779. In one embodiment, a cluster of openings (such as an array of openings) in the photoresist layer may be formed within each pad cavity region. In another embodiment, one opening in the photoresist layer may be formed within each pad cavity region. An anisotropic etch process may be performed to transfer the pattern of openings in the photoresist layer through the second pad and lower portion of the via-level dielectric material layer 754. A second pad connection via cavity 769 is formed through a lower portion of the second pad and via level dielectric material layer 754. A top surface of the topmost metal interconnect structure 780 may be physically exposed at the bottom of each second pad connection via cavity 769. The photoresist layer may then be removed, for example, by ashing.

A second integrated line and via cavity 759 is formed through second pad and via level dielectric material layer 754. Each second integrated line and via cavity 759 includes a respective one of the second pad cavities 779 and at least one second pad connection via cavity 769. In one embodiment, the second integrated line and via cavity 759 can include a second pad cavity 779 and a plurality of second pad connection via cavities 769 (such as clusters of pad connection via cavities). The top surfaces of the subset of second metal interconnect structures 780 are physically exposed to second pad and via cavities 759 when the second pad and via cavities 759 are formed.

In one embodiment, the second pad connection via cavity 769 can be arranged as a cluster of second pad connection via cavities. Each cluster of second pad connection via cavities 769 can be located within an area of a respective one of the second pad cavities 779. For example, each of the second pad cavities 779 may have a rectangular shape or a rounded rectangular shape having sides parallel to the second horizontal direction hd1 and the second horizontal direction hd 2. The dimension of each second pad cavity 779 in the second horizontal direction hd1 and the dimension of each second pad cavity 779 in the second horizontal direction hd2 are in the range of 2 microns to 60 microns. In this case, each cluster of second pad connection via cavities 769 may be arranged as a rectangular array. Each cluster of second pad connection via cavities 769 can be formed as an M × N rectangular array, where M and N are independent integers. Alternatively, a single second pad connection via cavity 769 may be formed for each region of the bond pad to be subsequently formed.

Each second pad connection via cavity 769 is formed within a region of a respective one of the topmost metal interconnect structures 780. A cluster of second pad connection via cavities 769 can be formed along each edge seal structure (not shown) in the second semiconductor die 700. The clusters of second pad connection via cavities 769 and gap regions can alternate over the entire area of each edge seal structure along the perimeter of the second semiconductor die 700. Where there are multiple nested edge seal structures in the second semiconductor die 700, multiple laterally alternating sequences of clusters of second pad connection via cavities 769 and gap regions are disposed along the perimeter of the second semiconductor die 700.

Referring to fig. 30, a second distal dielectric diffusion barrier layer 756L may be deposited in the second integrated line and via cavities 759 and over the second pad and via level dielectric material layer 754. A second distal dielectric diffusion barrier layer 756L is deposited on the top surface of the underlying second metal interconnect structure 780 and on the physically exposed surfaces of the second pad and via level dielectric material layer 754. The second distal dielectric diffusion barrier layer 756L comprises and/or consists essentially of a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the second distal dielectric diffusion barrier layer 756L comprises a moisture resistant dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The second distal dielectric diffusion barrier layer 756L may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The thickness of the second distal dielectric diffusion barrier layer 756L may be in the range of 5nm to 50nm, such as 10nm to 25nm, although lesser and greater thicknesses may also be used.

Referring to fig. 31, a photoresist layer 777 may be applied over the second distal dielectric diffusion barrier layer 756L and may be lithographically patterned to form discrete openings therethrough. An opening is formed through the photoresist layer 777 in the area of the bottom surface of the second integration pad and via cavity 759 by lithographically patterning the photoresist layer 777. Each area of discrete openings in photoresist layer 777 may be located inside a bottom perimeter of the pad cavity portion of a respective second integrated line and via cavity 759, i.e., inside a closed bottom edge of a set of sidewalls of the pad cavity portion of a respective second integrated line and via cavity 759. Each opening through the photoresist layer 777 may include the entire area of a set of at least one second pad connection via cavity located below a pad cavity portion of a respective second integrated line and via cavity 759.

The unmasked portions of the second distal dielectric diffusion barrier layer 756L are anisotropically etched by performing an anisotropic etching process that employs the patterned photoresist layer 777 as an etch mask. The unmasked horizontal portion of the second distal dielectric diffusion barrier layer 756L can be anisotropically etched by an anisotropic etching process. The horizontal portion of the second distal dielectric diffusion barrier layer 756L in the area of the second integration pad and via cavity 759 may be removed by an anisotropic etch process and the top surfaces of the subset of second metal interconnect structures 780 directly beneath the second proximal dielectric diffusion barrier layer 772 are physically exposed.

Openings are formed through the second distal dielectric diffusion barrier layer 756L along each perimeter of the openings through the patterned photoresist layer 777. The horizontally extending portion of the second distal dielectric diffusion barrier layer 756L at the bottom region of the pad cavity portion 779 of the second integrated line and via cavity 759 and above the second pad connection via cavity 769 is removed. The horizontal portion of the second distal dielectric diffusion barrier layer 756L at the bottom portion of the second pad connection via cavity 769 is also removed. The remaining portions of the patterned second distal dielectric diffusion barrier layer 756L include second dielectric diffusion barrier portions 756P laterally surrounding respective pad cavity portions of the second integrated line and via cavities 759. Portions of the top surface of the respective second metal interconnect structures 780 are physically exposed under each second integrated line and via cavity 759.

The remaining portions of the second distal dielectric diffusion barrier 756L after the anisotropic etching process include a second dielectric diffusion barrier portion 756P formed on the sidewall of the pad cavity portion of the second integrated pad and via cavity 759, and a second tubular dielectric diffusion barrier liner 755 formed on the sidewall of the second via cavity portion 769 of the second integrated pad and via cavity 759 below the pad cavity portion 779. The continuous remaining portion of the second distal dielectric diffusion barrier layer 756L including the second dielectric diffusion barrier portion 756P after the anisotropic etching process is referred to herein as the second distal dielectric diffusion barrier layer 756. The second distal dielectric diffusion barrier layer 756 includes a second horizontally extending diffusion barrier portion overlying the second pad and via level dielectric material layer 754. The second dielectric diffusion barrier portions 756P are interconnected to each other by a second horizontally extending diffusion barrier portion of the second distal dielectric diffusion barrier layer 756.

Each of the second dielectric diffusion barrier portions 756P is vertically spaced apart from the second proximal dielectric diffusion barrier 772. Each of the tubular dielectric diffusion barrier liners 755 laterally surrounds a respective one of the second integrated pads and the via cavities 759 and the first via cavity portion 769 of the via cavity. The tubular dielectric diffusion barrier liner 755 does not contact and is laterally spaced apart from the second dielectric diffusion barrier portion 756P. Each tubular dielectric diffusion barrier liner 755 may contact the cylindrical sidewall of a respective opening in the second proximal dielectric diffusion barrier 772.

Each of the second dielectric diffusion barrier portions 756P of the second distal dielectric diffusion barrier layer 756 laterally surrounds a pad cavity portion of a respective second integrated line and via cavity 759 and is vertically spaced apart from the second proximal dielectric diffusion barrier layer 772 by a lower portion of the second pad and via level dielectric material layer 754. In one embodiment, the perimeter of each opening through the second distal dielectric diffusion barrier 756 may be laterally offset outward from a set of respective at least one tubular dielectric diffusion barrier liner 755. In this case, each of the second dielectric diffusion barrier portions 756P includes a horizontal segment having a bottom surface that contacts the horizontal surface of the second pad and via-level dielectric material layer 754. Patterned photoresist layer 777 can then be removed, for example, by ashing.

Referring to fig. 32, a second bond pad liner layer 758L and a second metal pad fill material layer 758F may be sequentially deposited in the second integrated line and via cavity 759. The second bond pad liner layer 758L includes a metal nitride material, such as TiN, TaN, and/or WN. The conductive metal barrier material can block moisture and copper diffusion. The second bond pad liner layer 758L is formed on the top surface of the subset of the second metal interconnect structure 780 located at the topmost level of the second distal interconnect level dielectric material layer 760, on the inner wall of the tubular dielectric diffusion barrier liner 755, on the physically exposed surface of the second distal dielectric diffusion barrier layer 756, and on the physically exposed horizontal surface of the second pad and via level dielectric material layer 754 located between the topmost surface of the second pad and via level dielectric material layer 754 and the bottom surface of the second pad and via level dielectric material layer 754. The thickness of the second bond pad liner layer 758L layer may be in the range of 4nm to 80nm, such as 8nm to 40nm, although lesser and greater thicknesses may also be used. The second metal pad fill material layer 758F may comprise copper, which may be deposited by a combination of a copper seed layer deposition process employing physical vapor deposition and a copper plating process that fills the remaining volume of the second integrated line and via cavity 759.

Referring to fig. 33A and 33B, excess portions of the second metallic pad fill material layer 758F and the second bond pad liner layer 758L overlying a horizontal plane including the top surface of the second distal dielectric diffusion barrier layer 756 may be removed by a planarization process, such as chemical mechanical planarization. The remaining portions of the second metal pad fill material layer 758F and the second bond pad liner layer 758L filling the second integrated line and via cavity 759 constitute a second integrated pad and via structure 758 (e.g., a dual damascene bond pad). Each second integrated pad and via structure 758 may include a second bond pad liner 758A and a second metal pad fill material portion 758B. The second bond pad liner 758A is a patterned remaining portion of the second bond pad liner layer 758L, and the second metal pad fill material portion 758B is a patterned remaining portion of the second metal pad fill material layer 758F. The top surface of the second integrated pad and via structure 758 may be in the same horizontal plane as the top surface of the second distal dielectric diffusion barrier 756.

Generally, second integrated pad and via structure 758 is formed in the remaining volume of second integrated line and via cavity 759. Each of the second integrated pad and via structures 758 includes and/or consists of a second bond pad liner 788A comprising a metal nitride material and a second metal pad fill material portion 788B embedded in the bond pad liner 788A.

In one implementation, the second dielectric diffusion barrier portions 756P are interconnected to each other through a second horizontally extending diffusion barrier portion overlying the second pad and via-level dielectric material layer 754. The top surface of the second integrated pad and via structure 758 may lie within a horizontal plane including the top surface of the second horizontally extending diffusion barrier portion of the second distal dielectric diffusion barrier layer 756. Each of the second integrated pad and via structures 758 may directly contact at least one sidewall of the second proximal dielectric diffusion barrier 772. In general, the second pad and via level dielectric material layer 754 includes second integrated line and via cavities filled with respective combinations of second integrated pad and via structures 788 and respective second dielectric diffusion barrier portions 756P.

A first subset of the second integrated pad and via structures 758 may be located within a region of at least one edge seal structure (not shown) in the second semiconductor die 700 and may be electrically connected to a respective node of the second semiconductor device 720. A second subset of the second integration pad and via structures 758 may be located on and electrically connected to a respective edge seal structure of the at least one edge seal structure. The pattern of the second dual damascene bond pads 758 may be arranged in a mirror image pattern of the first dual damascene bond pads 958.

In one embodiment, the second bond pad liner 758A within each of the second integrated pad and via structures 758 extends continuously from a top surface of the respective one of the second metal interconnect structures 780 to a horizontal plane that includes a topmost surface of the second dielectric diffusion barrier portion 756P and directly contacts a horizontal surface of the second pad and via-level dielectric material layer 754 that is located within a region of the opening through the respective one of the second dielectric diffusion barrier portions 756P.

Each second integration pad and via structure 758 has at least one bottom surface that contacts a second metal interconnect structure 780. In one embodiment, the via portion of the second integration pad and via structure 758 contacts a horizontal surface of the second metal interconnect structure 780 located at a topmost level of the second interconnect-level dielectric material layer 760. A second dielectric diffusion barrier portion 756P is embedded in the second pad and via level dielectric material layer 754. Each of the second dielectric diffusion barrier portions 756P contacts and laterally surrounds a pad portion of a respective one of the second integrated pad and via structures 758. Each tubular dielectric diffusion barrier liner 755 laterally surrounds a via portion of a respective one of the second integrated pad and via structures 758.

Referring to fig. 34, the second semiconductor die 700 and the first semiconductor die 700 may be aligned such that each second integrated pad and via structure 758 faces a respective one of the first integrated pad and via structures 958. Each pair of facing first and second integrated pad and via structures 958,758 may be aligned to maximize the area overlap between first and second integrated pad and via

structures

958, 758. If the first and second integrated pad and via structures 958,758 have different areas, each overlapping area between a pair of opposing first and second integrated pad and via structures 958,758 may be the same as the area of the smaller integrated pad and via structure between a pair of opposing first and second integrated pad and via

structures

958, 758. If the first and second integrated pad and via structures 958,758 have the same area, the area of overlap between a pair of opposing first and second integrated pad and via structures 958,758 may be in the range of 90% to 100%, such as 95% to 100%, of the area of the first integrated pad and via structure 958 (which is the same as the area of the second integrated pad and via structure 758).

The first and second semiconductor dies 900,700 can be in contact with each other such that each first integration pad and via structure 958 contacts a respective one of the second integration pad and via structures 758 with a respective area overlap therebetween. The assembly of the first and second semiconductor dies 900,700 is annealed at an elevated temperature in the range of 250 to 400 degrees celsius to cause copper diffusion at each interface between the pair of opposing respective first and second integrated pad and via

structures

958, 758. The duration of the annealing process at high temperature may be in the range of 5 minutes to 2 hours, although shorter or longer annealing durations may also be used. Each pair of facing first and second integrated pad and via

structures

958 and 758 are bonded to each other during an annealing process at high temperature. A first exemplary bonding structure including a first semiconductor die 900 and a second semiconductor die 700 can be formed.

A layer stack including a horizontally extending portion of the first distal dielectric diffusion barrier layer 956 and a horizontally extending portion of the second distal dielectric diffusion barrier layer 756 may be located between the first pad and via level dielectric material layer 954 and the second pad and via level dielectric material layer 754. The vertical separation distance between the first pad and via-level dielectric material layer 954 and the second pad and via-level dielectric material layer 754 may be the sum of the thickness of the first distal dielectric diffusion barrier layer 956 and the thickness of the second distal dielectric diffusion barrier layer 756.

Referring to fig. 35, the first substrate 908 can be thinned from the backside by grinding, polishing, anisotropic etching, or isotropic etching. The thinning process may continue until the horizontal portion of the through substrate liner 386 is removed and the horizontal surface of the through substrate via structure 388 is physically exposed. In general, by thinning the back side of the first substrate 908, which may be the substrate of a memory die, the end surfaces of the through substrate via structures 388 are physically exposed. The thickness of the first substrate 908 after thinning may be in the range of 1 micron to 30 microns, such as 2 microns to 15 microns, although lesser and greater thicknesses may also be used.

Referring to fig. 36, a backside insulating layer 930 may be formed on the backside of the first substrate 908. The backside insulating layer 930 comprises an insulating material, such as silicon oxide. The thickness of the backside insulating layer 930 may be in the range of 50nm to 500nm, although lesser and greater thicknesses may also be used. A photoresist layer (not shown) may be applied over the backside insulating layer 930 and may be lithographically patterned to form openings over the areas of the through-substrate via structures 388. An etching process can be performed to form a via cavity through the backside insulation layer 930 under each opening in the photoresist layer. The top surface of the through-substrate via structures 388 may be physically exposed through the backside insulation layer 930 at the bottom of each via cavity.

The at least one metallic fill material and the metallic material layer may then be patterned to form discrete backside bond pads 936 to contact a respective one of the through-substrate via structures 388. The backside bond pads 936 may be used as external integrated pad and via structures that may be used to electrically connect various nodes within the first and second semiconductor dies 900,700 to external nodes, such as an integrated pad and via structure on a package substrate or a C4 integrated pad and via structure of another semiconductor die. For example, solder material portions 938 can be formed on the backside bond pads 936 and a C4 bonding process or wire bonding process can be performed to electrically connect the backside bond pads 936 to an external electrically active node.

In general, the back side bond pads 936 can be formed on a back side surface of the first semiconductor die 900 (which can be a memory die) on an opposite side of the bonding interface between the first semiconductor die 900 and the second semiconductor die 700. The through-substrate via structures 388 may extend vertically through the first semiconductor die 900 and may provide electrical connections between the backside bond pads 936 and a subset of the integrated pad and via structures (958,758).

Referring to fig. 37, an alternative embodiment of a first semiconductor die 900 is shown according to a second embodiment of the present disclosure. An alternative embodiment of the first semiconductor die 900 from the first semiconductor die 900 of fig. 27A and 27B may be obtained by removing the horizontally extending portion of the first distal dielectric diffusion barrier 956 overlying the first pad and via-level dielectric material layer 954. For example, after removing portions of the metallic material from over the top surface of the first distal dielectric diffusion barrier 956, the horizontally extending portions of the first distal dielectric diffusion barrier 956 overlying the first pad and via-level dielectric material layer 954 may be removed by an additional polishing step of a chemical mechanical planarization process. In this case, the top surface of the first pad and via-level dielectric material layer 954 may be physically exposed after the planarization process, and the top surface of the first integrated pad and via structure 958 may be formed within the same horizontal plane as the top surface of the first pad and via-level dielectric material layer 954. After removing the horizontally extending portion of the first distal dielectric diffusion barrier layer 956, the remaining portion of the first distal dielectric diffusion barrier layer 956 comprises the first dielectric diffusion barrier portion 956'. The first dielectric diffusion barrier portions 956' are not interconnected to each other and are formed as discrete structures laterally surrounding the respective first integrated pad and via structures 958.

Referring to fig. 38, a second semiconductor die 700 can be provided in the same manner as described above and can be bonded with the alternative configuration of the first semiconductor die shown in fig. 37 to provide an alternative embodiment of a second bonding assembly. The process steps of fig. 35 and 36 may be performed on the structure shown in fig. 38. In this case, the horizontally extending portion of the second distal dielectric diffusion barrier layer 756 may be located between the first pad and via level dielectric material layer 954 and the second pad and via level dielectric material layer 754. The vertical separation distance between the first pad and via-level dielectric material layer 954 and the second pad and via-level dielectric material layer 754 may be the same as the thickness of the second distal dielectric diffusion barrier layer 756. The first dielectric diffusion barrier portion 956' is a discrete material portion laterally spaced from each other by the first pad and via-level dielectric material layer 954. The top surface of the first integrated pad and via structure 958 may lie within a horizontal plane that includes the top surface of the first pad and via-level dielectric material layer 954.

In another alternative embodiment of the first semiconductor die 900 according to the first embodiment of the present disclosure, the horizontally extending portion of the second distal dielectric diffusion barrier layer 756 overlying the layer 754 may be removed. In this alternative embodiment, the vertical separation distance between the first pad and via level dielectric material layer 954 and the second pad and via level dielectric material layer 754 may be the same as the thickness of the first distal dielectric diffusion barrier 956 disposed between the

layers

754 and 954.

In one embodiment, the combination of the first proximal dielectric diffusion barrier layer 972, the first distal dielectric diffusion barrier layer 956, the tubular dielectric diffusion barrier liner 955, the first bond pad liner 958A, the second proximal dielectric diffusion barrier layer 772, the second distal dielectric diffusion barrier layer 756, the tubular dielectric diffusion barrier liner 755, and the second bond pad liner 758A form a continuous diffusion barrier structure that protects the first metal interconnect structure 980 embedded in the first distal interconnect-level dielectric material layer 960 and the second metal interconnect structure 780 embedded in the second interconnect-level dielectric material layer 760 from the diffusion of moisture and/or contaminants through the first pad and via-level dielectric material layer 954 or the second pad and via-level dielectric material layer 754.

Although the present disclosure is described as employing embodiments in which the first semiconductor die 900 in a first configuration is bonded to the second semiconductor die 700 in a first configuration (as shown in fig. 1A-21B) and the first semiconductor die 900 in a second configuration is bonded to the second semiconductor die 700 in a second configuration (as shown in fig. 22-38), embodiments are expressly contemplated herein in which the first semiconductor die 900 in a first configuration is bonded to the second semiconductor die 700 in a second configuration and/or the first semiconductor die 900 in a second configuration is bonded to the second semiconductor die 700 in a first configuration. Accordingly, the claims of the present application should be construed to cover all possibilities for the first semiconductor die 900 and the second semiconductor die 700 to have any of the configurations described above.

Referring to fig. 22-38 and related figures and in accordance with various embodiments of the present disclosure, a structure is provided that includes a first semiconductor die 900. The first semiconductor die 900 includes: a first semiconductor device 920 located over the first substrate 908; a first layer of interconnect-level dielectric material (290,960) embedded in a first metal interconnect structure 980 electrically connected to the first semiconductor device 920 and overlying the first semiconductor device 920; a layer stack of a first proximal dielectric diffusion barrier 972 and a first pad and via level dielectric material layer 954 overlying the first interconnect level dielectric material layer (290,960) and embedding the first integrated pad and via structure 958; and first dielectric diffusion barrier portions (956P,956') embedded in the first pad and via-level dielectric material layer 954, wherein each of the first dielectric diffusion barrier portions (956P,956') contacts and laterally surrounds a pad portion of a respective one of the first integrated pad and via structures 958.

In one embodiment, each of the first dielectric diffusion barrier portions (956P,956') is vertically spaced apart from the first proximal dielectric diffusion barrier layer 972. In one embodiment, the tubular dielectric diffusion barrier liner 955 may laterally surround the via portion of the respective first integrated pad and via structure in the first integrated pad and via structure 958. In one embodiment, the tubular dielectric diffusion barrier liner 955 does not contact and is laterally spaced apart from the first dielectric diffusion barrier portion (956P, 956'). In one embodiment, the tubular dielectric diffusion barrier liner 955 contacts sidewalls of the corresponding opening in the first proximal dielectric diffusion barrier layer 972.

In one embodiment, the first proximal dielectric diffusion barrier layer 972 contacts top surfaces of a subset of the first metal interconnect structures 980 and a topmost surface of the first interconnect-level dielectric material layer (290,960); and the via portions of the first integrated pad and via structure 958 contact horizontal surfaces of a subset of the first metal interconnect structure 980.

In one embodiment, each of the first integrated pad and via structures 958 includes: a first bond pad liner 958A comprising a metal nitride material; and copper, which contains a first metal pad fill material portion 958B embedded partially in the first bond pad liner 958A. In one embodiment, the first dielectric diffusion barrier portions 956P interconnect to each other through first horizontally extending diffusion barrier portions overlying the first pad and via-level dielectric material layer 954; and the top surface of the first integrated pad and via structure 958 lies in a horizontal plane that includes the top surface of the first horizontally extending diffusion barrier portion. Alternatively, the first dielectric diffusion barrier portion 956' is a discrete material portion laterally spaced from each other by the first pad and via-level dielectric material layer 954; and a top surface of the first integrated pad and via structure 958 lies within a horizontal plane that includes a top surface of the first pad and via-level dielectric material layer 954.

In one embodiment, the first bond pad liner 958A within each of the first integrated pad and via structures 958 extends continuously from the top surface of the respective one of the first metal interconnect structures 980 to a horizontal plane including the topmost surface of the first dielectric diffusion barrier portion (956P,956') without any openings therein, and directly contacts the horizontal surface of the first pad and via-level dielectric material layer 954 in the region of the opening through the respective one of the first dielectric diffusion barrier portions (956P, 956').

In one embodiment, the first dielectric diffusion barrier portion (956P,956') comprises a dielectric material selected from silicon nitride, silicon oxynitride or a stack thereof; and first proximal dielectric diffusion barrier layer 972 comprises a dielectric material selected from silicon nitride, silicon oxynitride, and/or silicon carbonitride.

In one embodiment, the structure includes a second semiconductor die 700 comprising: a second semiconductor device 720 located over the second substrate 708; a second interconnect-level dielectric material layer 760 embedding a second metal interconnect structure 780 electrically connected to the second semiconductor device 720 and located under the second semiconductor device 720 (in a bonded state); and a second bond pad (which may be provided as a second bond pad 788 in the first configuration of the second semiconductor die 700 or as a pad portion of a second integrated pad and via structure 758 in the second configuration of the second semiconductor die 700) that is electrically connected to the second metal interconnect structure 780 and bonded to a respective one of the first integrated pad and via structures 958.

In one embodiment, each of the second bond pads contacts and is laterally surrounded by a respective second dielectric diffusion barrier portion (776P, 756'); a second dielectric diffusion barrier portion (776P, 756') and a second bond pad (788,758) are embedded in the pad-level dielectric material layer (which may be an upper portion of the second pad-level dielectric material layer 774 or the second pad and via-level dielectric material layer 754); and the first pad and via-level dielectric material layer 954 and the pad-level dielectric material layer (774,754) are not in contact with each other and are vertically spaced from each other by at least one horizontally extending diffusion barrier portion laterally connecting the first dielectric diffusion barrier portion 956P or laterally connecting the second dielectric diffusion barrier portion 756P. The at least one horizontally extending diffusion barrier portion may comprise a horizontally extending portion of the first distal dielectric diffusion barrier layer 956 and/or a horizontally extending portion of the second distal dielectric diffusion barrier layer 756. In one embodiment, the first semiconductor device 920 may include a three-dimensional memory device, and the second semiconductor device 720 may include a driver circuit device (e.g., a CMOS device) for the three-dimensional memory device 920.

In one embodiment, the first semiconductor die 900 includes at least one edge seal structure (688,984,986) that includes a respective subset of the first metal interconnect structures 980 that provides a respective continuous barrier laterally surrounding the first semiconductor device 920 without any lateral openings and extends vertically from the first substrate 908 to the first proximal dielectric diffusion barrier 972.

Generally, various embodiments of the present disclosure provide a moisture diffusion barrier structure at the level of the bond pad. The formation of a continuous metal structure at the intermetallic bonding interface is detrimental to the formation of a high quality bonding surface because the continuous metal structure causes local variations in the metal to dielectric area ratio, changes the microscopic recess depth of the metal relative to the dielectric surface, and degrades the bonding strength due to the local variations in the recess depth of the metal structure. The methods and structures of embodiments of the present disclosure provide a continuous diffusion barrier structure that can block moisture and impurities from diffusing into an interconnect-level dielectric material layer (290,960,760) even if moisture and/or impurities enter through openings at the level of the metal pad and the connection via structures, and thereby, improve reliability of a bonded assembly of an individual semiconductor die (900,700) and/or a plurality of semiconductor dies (900,700).

Furthermore, embodiments of the present disclosure provide compatibility of the inter-wafer bond pad structure and block moisture permeation from outside the bond die. The uppermost bond pad of the semiconductor die (900,700) preferably has a square horizontal shape to provide high bond strength. The square shape of the bond pads may allow moisture to penetrate the space between the bond pads. However, dielectric diffusion barriers prevent moisture from penetrating into memory and CMOS devices. Thus, embodiments provide a combination of high bond strength and moisture barrier.

Moisture is blocked by a seal ring conductive layer surrounding the semiconductor die (900,700) under the bond pad, and moisture is blocked by a dielectric diffusion barrier layer in the level of the bond pad. Furthermore, in some embodiments, the dielectric diffusion barrier layer may prevent or reduce out-diffusion of copper from the bond pad into the silicon oxide dielectric layer when the bond pad is partially misaligned.

In some embodiments, the bottom and sides of the bond pad (e.g., copper bond pad) are surrounded by a diffusion barrier metal or metal nitride and by a dielectric diffusion barrier to reduce or prevent moisture diffusion into the bond pad, which can lead to copper ionization and out-diffusion. Furthermore, delamination of the bonded semiconductor die may be avoided or reduced, since out-diffusion of copper from the bond pads is avoided or reduced. Furthermore, since the dielectric diffusion barrier layer is located outside the barrier metal in the bond pad level, the dielectric diffusion barrier layer blocks the diffusion of moisture into the copper bond pad. In some embodiments, malfunctions in circuit operation caused by high frequency noise may also be reduced or avoided.

In some embodiments, capacitance between adjacent metal or metal alloy layers in an interconnect layer is reduced by using a low dielectric constant dielectric layer such as SiCN or other dielectric materials described above.

The device of the first embodiment illustrated in fig. 1A-21B avoids or reduces degradation in circuit operating speed because wiring capacitance is not increased with a dielectric layer having a high dielectric constant of at least 5 placed at the bottom of the bond pad level without having to place this layer above the top layer of the underlying circuit. The device of the second embodiment shown in fig. 22-38 is formed by a dual damascene process, which provides reduced process costs. In a second embodiment, a dielectric layer with a high dielectric constant may be placed over the top layer of the bottom layer circuitry.

While specific embodiments have been mentioned above, it should be understood that the disclosure is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the word "comprise" or "comprises" contemplates all embodiments in which the word "consists essentially of or the word" consists of replaces the word "comprises" or "comprises. Embodiments using specific structures and/or configurations are shown in the present disclosure, it being understood that the present disclosure may be practiced in any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise deemed to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A structure comprising a first semiconductor die, wherein the first semiconductor die comprises:

a first semiconductor device over a first substrate;

a first interconnect-level dielectric material layer embedding a first metal interconnect structure electrically connected to and overlying the first semiconductor device;

a layer stack of a first pad connecting via level dielectric material layer and a first proximal dielectric diffusion barrier layer overlying the first interconnect level dielectric material layer and embedding a first pad connecting via structure; and

a first pad-level dielectric material layer comprising first pad cavities filled with respective combinations of first bond pads and respective first dielectric diffusion barrier portions, wherein each of the first bond pads contacts a respective subset of the first pad connection via structures.

2. The structure of claim 1, wherein each of the first dielectric diffusion barrier portions contacts a top surface of the first proximal dielectric diffusion barrier layer.

3. The structure of claim 1, wherein each of the first dielectric diffusion barrier portions comprises a sidewall segment in contact with the first pad level dielectric material layer and extending from a bottom surface of the first pad level dielectric material layer to a top surface of the first pad level dielectric material layer.

4. The structure of claim 3, wherein each of the first dielectric diffusion barrier portions further comprises a horizontal segment having a bottom surface that contacts the first proximal dielectric diffusion barrier layer, wherein the bottom surface comprises an outer perimeter abutting a bottom edge of the side wall segment and an inner perimeter laterally offset inward from the outer perimeter by an offset distance that is greater than a thickness of the side wall segment of the first dielectric diffusion barrier portion.

5. The structure of claim 1, wherein:

the respective subset of the first pad connection via structures comprises a plurality of first pad connection via structures; and is

Each of the first bond pads directly contacts a portion of the top surface of the first proximal dielectric diffusion barrier layer between the plurality of first pad connecting via structures.

6. The structure of claim 1, wherein a top surface of the first pad connection via structure is in the same horizontal plane as a top surface of the first proximal dielectric diffusion barrier layer.

7. The structure of claim 1, wherein each of the first bond pads comprises:

a first bond pad liner comprising a metal nitride material; and

copper containing a first metal pad fill material portion embedded in the bond pad liner.

8. The structure of claim 7, wherein:

the first dielectric diffusion barrier portions are interconnected to each other through first horizontally extending diffusion barrier portions overlying the first pad-level dielectric material layer; and is

A top surface of the first bond pad lies within a horizontal plane that includes a top surface of the first horizontally extending diffusion barrier portion.

9. The structure of claim 7, wherein:

the first dielectric diffusion barrier portions are discrete material portions laterally spaced from one another by the first pad-level dielectric material layer; and is provided with

A top surface of the first bond pad lies within a horizontal plane that includes a top surface of the first pad-level dielectric material layer.

10. The structure of claim 1, wherein:

the first dielectric diffusion barrier portion comprises a dielectric material selected from silicon nitride, silicon oxynitride, or a stack thereof; and is

The first proximal dielectric diffusion barrier layer comprises a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, or silicon carbonitride.

11. The structure of claim 1, further comprising a second semiconductor die, the second semiconductor die comprising:

a second semiconductor device over a second substrate;

a second interconnect-level dielectric material layer embedding a second metal interconnect structure electrically connected to the second semiconductor device; and

second bond pads electrically connected to the second metal interconnect structure and bonded to respective ones of the first bond pads.

12. The structure of claim 11, wherein:

the first semiconductor device comprises a three-dimensional memory device or a driver circuit device for the three-dimensional memory device;

the second semiconductor device comprises the other of the three-dimensional memory device or the driver circuit device for the three-dimensional memory device;

each of the second bond pads contacts and is laterally surrounded by a respective second dielectric diffusion barrier portion;

the second bond pad and the second dielectric diffusion barrier portion are embedded in a second pad-level dielectric material layer;

the second semiconductor die includes a layer stack of a second pad connection via level dielectric material layer and a second proximal dielectric diffusion barrier layer, the layer stack being between the second interconnect level dielectric material layer and the second pad level dielectric material layer and embedding a second pad connection via structure, and

each of the second bond pads contacts a respective subset of the second pad connecting via structures.

13. The structure of claim 1, wherein the first semiconductor die comprises:

an additional planar diffusion barrier layer between the first interconnect-level dielectric material layer and the first pad connecting via-level dielectric material layer; and

at least one edge sealing structure comprising a respective subset of the first metal interconnect structures, the at least one edge sealing structure providing a respective continuous barrier layer laterally surrounding the first semiconductor device without any lateral openings and extending vertically from the first substrate to the additional planar diffusion barrier layer.

14. The structure of claim 13, wherein the at least one edge seal structure is electrically grounded.

15. A method of forming a semiconductor structure, the method comprising forming a first semiconductor die by:

forming a first semiconductor device over a first substrate;

forming a layer stack of a first pad connecting via level dielectric material layer and a first proximal dielectric diffusion barrier layer over the first semiconductor device, the layer stack embedding a first metal interconnect structure;

forming a first pad connection via structure through the layer stack on a subset of the first metal interconnect structures;

forming a first pad-level dielectric material layer over the layer stack;

forming a first pad cavity through the first pad-level dielectric material layer;

forming a first distal dielectric diffusion barrier layer in the first pad cavity and over the first pad-level dielectric material layer;

forming an opening through the first distal dielectric diffusion barrier layer at a bottom portion of the first pad cavity, wherein a top surface of the first pad connection via structure is physically exposed; and

forming a first bond pad in a remaining volume of the first pad cavity directly on the top surface of the first pad connecting via structure.

16. The method of claim 15, further comprising:

forming a photoresist layer over the first distal dielectric diffusion barrier layer;

forming an opening through the photoresist layer in the region of the bottom surface of the first pad cavity by lithographically patterning the photoresist layer; and is

Anisotropically etching unmasked portions of the first distal dielectric diffusion barrier layer, wherein remaining portions of the first distal dielectric diffusion barrier layer comprise first dielectric diffusion barrier portions.

17. The method of claim 15, wherein

A top surface of the first pad connecting via structure is physically exposed in the first pad cavity when the first pad cavity is formed; and is

The first distal dielectric diffusion barrier layer is deposited on the first pad-level dielectric material layer and on the top surface of the first pad connecting via structure.

18. The method of claim 15, further comprising:

after forming the opening through the first distal dielectric diffusion barrier layer, depositing a first bond pad liner layer comprising a metal nitride material on the first pad connecting via structure and on the first distal dielectric diffusion barrier layer;

depositing a first metal pad fill material layer on the first bond pad liner layer; and is

Removing portions of the first metal pad fill material layer and the first bond pad liner layer overlying a horizontal plane including a top surface of the first dielectric diffusion barrier liner, wherein remaining portions of the first metal pad fill material layer and the first bond pad liner layer constitute the first bond pad.

19. The method of claim 15, further comprising: forming a first interconnect-level dielectric material layer over the first semiconductor device, the first interconnect-level dielectric material layer embedding a first metal interconnect structure, wherein the first metal interconnect structure is electrically connected to the first semiconductor device, wherein the layer stack is formed over the first interconnect-level dielectric material layer.

20. The method of claim 15, further comprising:

providing a second semiconductor die comprising a second semiconductor device on a second substrate and a second pad-level dielectric material layer embedding a second bond pad electrically connected to the second semiconductor device; and is

Bonding the second bond pad to the first bond pad.

21. A structure comprising a first semiconductor die, wherein the first semiconductor die comprises:

a first semiconductor device over a first substrate;

a first proximal dielectric diffusion barrier layer and a layer stack of a first pad and via level dielectric material layer overlying the first interconnect level dielectric material layer and embedding a first integrated pad and via structure; and

first dielectric diffusion barrier portions embedded in the first pad and via level dielectric material layer, wherein each of the first dielectric diffusion barrier portions contacts and laterally surrounds a pad portion of a respective one of the first integrated pad and via structures.

22. The structure of claim 21 wherein each of the first dielectric diffusion barrier portions is vertically spaced apart from the first proximal dielectric diffusion barrier layer.

23. The structure of claim 21, further comprising a tubular dielectric diffusion barrier liner laterally surrounding a via portion of respective ones of the first integrated pad and via structures.

24. The structure of claim 23, wherein the tubular dielectric diffusion barrier liner does not contact and is laterally spaced apart from the first dielectric diffusion barrier portion.

25. The structure of claim 24, wherein the tubular dielectric diffusion barrier liner contacts sidewalls of respective openings in the first proximal dielectric diffusion barrier layer.

26. The structure of claim 24, wherein:

the first proximal dielectric diffusion barrier layer contacts top surfaces of the subset of first metal interconnect structures and a topmost surface of the first interconnect-level dielectric material layer; and is

The via portions of the first integration pad and via structures contact horizontal surfaces of the subset of the first metal interconnect structures.

27. The structure of claim 21, wherein each of the first integrated pad and via structures comprises:

a first bond pad liner comprising a metal nitride material; and

copper containing a first metal pad fill material portion that partially embeds in the first bond pad liner.

28. The structure of claim 27, wherein:

the first dielectric diffusion barrier portions are interconnected to each other through first horizontally extending diffusion barrier portions overlying the first pad and via-level dielectric material layers; and is

A top surface of the first integration pad and via structure is located within a horizontal plane that includes a top surface of the first horizontally extending diffusion barrier portion.

29. The structure of claim 27, wherein:

the first dielectric diffusion barrier portion is a discrete material portion laterally spaced from one another by the first pad and via-level dielectric material layer; and is provided with

A top surface of the first via and integration structure is located within a horizontal plane that includes a top surface of the first pad and via-level dielectric material layer.

30. The structure of claim 21, wherein a first bond pad liner within each of the first integration pad and via structures extends continuously from a top surface of a respective one of the first metal interconnect structures to a horizontal plane that includes a topmost surface of the first dielectric diffusion barrier portion and directly contacts a horizontal surface of the first pad and via-level dielectric material layer that is located within a region of an opening through the respective one of the first dielectric diffusion barrier portions.

31. The structure of claim 21, wherein:

32. The structure of claim 21, further comprising a second semiconductor die, the second semiconductor die comprising:

a second semiconductor device over a second substrate;

a second bond pad electrically connected to the second metal interconnect structure and bonded to a respective one of the first integration pad and via structure.

33. The structure of claim 32, wherein:

the second dielectric diffusion barrier portion and the second bond pad are embedded in a pad-level dielectric material layer; and is

The first pad and via level dielectric material layer and the pad level dielectric material layer are not in contact with each other and are vertically spaced from each other by at least one horizontally extending diffusion barrier portion laterally connecting the first dielectric diffusion barrier portion or laterally connecting the second dielectric diffusion barrier portion.

34. The structure of claim 21, wherein the first semiconductor die comprises at least one edge sealing structure comprising a respective subset of the first metal interconnect structures, the at least one edge sealing structure providing a respective continuous barrier layer laterally surrounding the first semiconductor device without any lateral openings and extending vertically from the first substrate to the first proximal dielectric diffusion barrier layer.

35. A method of forming a semiconductor structure, the method comprising forming a first semiconductor die by:

forming a first semiconductor device over a first substrate;

forming a first interconnect-level dielectric layer embedding a first metal interconnect structure over the first semiconductor device;

forming a first proximal dielectric diffusion barrier layer and a first pad and via level dielectric material layer over the first semiconductor device;

forming a first integration pad and a via cavity through the first pad and via level dielectric material layer;

forming a first distal dielectric diffusion barrier layer in the first integrated pad and via cavity and over the first pad and via level dielectric material layer;

removing horizontal portions of the first distal dielectric diffusion barrier layer within regions of the first integration pad and via cavity, wherein top surfaces of a subset of the first metal interconnect structures are physically exposed; and is

A first integrated pad and via structure is formed in a remaining volume of the first pad and via cavity.

36. The method of claim 35, further comprising:

forming an opening through the photoresist layer in an area of the bottom surface of the first integration pad and via cavity by photolithographically patterning the photoresist layer; and is provided with

The unmasked portions of the first distal dielectric diffusion barrier layer are anisotropically etched by performing an anisotropic etch process.

37. The method of claim 36, wherein a remaining portion of the first distal dielectric diffusion barrier layer after the anisotropic etching process comprises:

a first dielectric diffusion barrier portion formed on a sidewall of a pad cavity portion of the first integration pad and via cavity; and

a first tubular dielectric diffusion barrier liner formed on a sidewall of the first integrated pad and via cavity portion of the via cavity beneath the pad cavity portion.

38. The method of claim 35, wherein

Top surfaces of the subset of the first metal interconnect structures are physically exposed to the first pad and via cavities when the first pad and via cavities are formed; and is

The first distal dielectric diffusion barrier layer is deposited on the first pad and via level dielectric material layer and on the top surfaces of the subset of the first metal interconnect structures.

39. The method of claim 35, further comprising:

after removing the horizontal portion of the first distal dielectric diffusion barrier layer, depositing a first metal liner layer comprising a metal nitride material on the subset of first metal interconnect structures and on a remaining portion of the first distal dielectric diffusion barrier layer;

depositing a first metal pad fill material layer on the first metal liner layer; and is

Removing portions of the first metal pad fill material layer and the first metal liner layer overlying a horizontal plane including a top surface of the first distal dielectric diffusion barrier layer, wherein remaining portions of the first metal pad fill material layer and the first metal liner layer constitute the first integrated pad and via structure.

40. The method of claim 35, further comprising:

providing a second semiconductor die comprising a second semiconductor device on a second substrate and a second pad-level dielectric material layer embedding a second bond pad electrically connected to the second semiconductor device; and

bonding the second bond pad to the first bond pad.